1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pm_runtime.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_gem_framebuffer_helper.h> 39 #include <drm/drm_fb_helper.h> 40 41 static void amdgpu_display_flip_callback(struct dma_fence *f, 42 struct dma_fence_cb *cb) 43 { 44 struct amdgpu_flip_work *work = 45 container_of(cb, struct amdgpu_flip_work, cb); 46 47 dma_fence_put(f); 48 schedule_work(&work->flip_work.work); 49 } 50 51 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 52 struct dma_fence **f) 53 { 54 struct dma_fence *fence= *f; 55 56 if (fence == NULL) 57 return false; 58 59 *f = NULL; 60 61 if (!dma_fence_add_callback(fence, &work->cb, 62 amdgpu_display_flip_callback)) 63 return true; 64 65 dma_fence_put(fence); 66 return false; 67 } 68 69 static void amdgpu_display_flip_work_func(struct work_struct *__work) 70 { 71 struct delayed_work *delayed_work = 72 container_of(__work, struct delayed_work, work); 73 struct amdgpu_flip_work *work = 74 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 75 struct amdgpu_device *adev = work->adev; 76 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 77 78 struct drm_crtc *crtc = &amdgpu_crtc->base; 79 unsigned long flags; 80 unsigned i; 81 int vpos, hpos; 82 83 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 84 return; 85 86 for (i = 0; i < work->shared_count; ++i) 87 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 88 return; 89 90 /* Wait until we're out of the vertical blank period before the one 91 * targeted by the flip 92 */ 93 if (amdgpu_crtc->enabled && 94 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, 95 &vpos, &hpos, NULL, NULL, 96 &crtc->hwmode) 97 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 98 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 99 (int)(work->target_vblank - 100 amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { 101 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 102 return; 103 } 104 105 /* We borrow the event spin lock for protecting flip_status */ 106 spin_lock_irqsave(&crtc->dev->event_lock, flags); 107 108 /* Do the flip (mmio) */ 109 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 110 111 /* Set the flip status */ 112 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 113 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 114 115 116 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 117 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 118 119 } 120 121 /* 122 * Handle unpin events outside the interrupt handler proper. 123 */ 124 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 125 { 126 struct amdgpu_flip_work *work = 127 container_of(__work, struct amdgpu_flip_work, unpin_work); 128 int r; 129 130 /* unpin of the old buffer */ 131 r = amdgpu_bo_reserve(work->old_abo, true); 132 if (likely(r == 0)) { 133 r = amdgpu_bo_unpin(work->old_abo); 134 if (unlikely(r != 0)) { 135 DRM_ERROR("failed to unpin buffer after flip\n"); 136 } 137 amdgpu_bo_unreserve(work->old_abo); 138 } else 139 DRM_ERROR("failed to reserve buffer after flip\n"); 140 141 amdgpu_bo_unref(&work->old_abo); 142 kfree(work->shared); 143 kfree(work); 144 } 145 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 147 struct drm_framebuffer *fb, 148 struct drm_pending_vblank_event *event, 149 uint32_t page_flip_flags, uint32_t target, 150 struct drm_modeset_acquire_ctx *ctx) 151 { 152 struct drm_device *dev = crtc->dev; 153 struct amdgpu_device *adev = dev->dev_private; 154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 155 struct drm_gem_object *obj; 156 struct amdgpu_flip_work *work; 157 struct amdgpu_bo *new_abo; 158 unsigned long flags; 159 u64 tiling_flags; 160 u64 base; 161 int i, r; 162 163 work = kzalloc(sizeof *work, GFP_KERNEL); 164 if (work == NULL) 165 return -ENOMEM; 166 167 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 168 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 169 170 work->event = event; 171 work->adev = adev; 172 work->crtc_id = amdgpu_crtc->crtc_id; 173 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 174 175 /* schedule unpin of the old buffer */ 176 obj = crtc->primary->fb->obj[0]; 177 178 /* take a reference to the old object */ 179 work->old_abo = gem_to_amdgpu_bo(obj); 180 amdgpu_bo_ref(work->old_abo); 181 182 obj = fb->obj[0]; 183 new_abo = gem_to_amdgpu_bo(obj); 184 185 /* pin the new buffer */ 186 r = amdgpu_bo_reserve(new_abo, false); 187 if (unlikely(r != 0)) { 188 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 189 goto cleanup; 190 } 191 192 r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev), &base); 193 if (unlikely(r != 0)) { 194 DRM_ERROR("failed to pin new abo buffer before flip\n"); 195 goto unreserve; 196 } 197 198 r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, 199 &work->shared_count, 200 &work->shared); 201 if (unlikely(r != 0)) { 202 DRM_ERROR("failed to get fences for buffer\n"); 203 goto unpin; 204 } 205 206 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 207 amdgpu_bo_unreserve(new_abo); 208 209 work->base = base; 210 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 211 amdgpu_get_vblank_counter_kms(dev, work->crtc_id); 212 213 /* we borrow the event spin lock for protecting flip_wrok */ 214 spin_lock_irqsave(&crtc->dev->event_lock, flags); 215 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 216 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 217 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 218 r = -EBUSY; 219 goto pflip_cleanup; 220 } 221 222 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 223 amdgpu_crtc->pflip_works = work; 224 225 226 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 227 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 228 /* update crtc fb */ 229 crtc->primary->fb = fb; 230 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 231 amdgpu_display_flip_work_func(&work->flip_work.work); 232 return 0; 233 234 pflip_cleanup: 235 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 236 DRM_ERROR("failed to reserve new abo in error path\n"); 237 goto cleanup; 238 } 239 unpin: 240 if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { 241 DRM_ERROR("failed to unpin new abo in error path\n"); 242 } 243 unreserve: 244 amdgpu_bo_unreserve(new_abo); 245 246 cleanup: 247 amdgpu_bo_unref(&work->old_abo); 248 dma_fence_put(work->excl); 249 for (i = 0; i < work->shared_count; ++i) 250 dma_fence_put(work->shared[i]); 251 kfree(work->shared); 252 kfree(work); 253 254 return r; 255 } 256 257 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 258 struct drm_modeset_acquire_ctx *ctx) 259 { 260 struct drm_device *dev; 261 struct amdgpu_device *adev; 262 struct drm_crtc *crtc; 263 bool active = false; 264 int ret; 265 266 if (!set || !set->crtc) 267 return -EINVAL; 268 269 dev = set->crtc->dev; 270 271 ret = pm_runtime_get_sync(dev->dev); 272 if (ret < 0) 273 return ret; 274 275 ret = drm_crtc_helper_set_config(set, ctx); 276 277 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 278 if (crtc->enabled) 279 active = true; 280 281 pm_runtime_mark_last_busy(dev->dev); 282 283 adev = dev->dev_private; 284 /* if we have active crtcs and we don't have a power ref, 285 take the current one */ 286 if (active && !adev->have_disp_power_ref) { 287 adev->have_disp_power_ref = true; 288 return ret; 289 } 290 /* if we have no active crtcs, then drop the power ref 291 we got before */ 292 if (!active && adev->have_disp_power_ref) { 293 pm_runtime_put_autosuspend(dev->dev); 294 adev->have_disp_power_ref = false; 295 } 296 297 /* drop the power reference we got coming in here */ 298 pm_runtime_put_autosuspend(dev->dev); 299 return ret; 300 } 301 302 static const char *encoder_names[41] = { 303 "NONE", 304 "INTERNAL_LVDS", 305 "INTERNAL_TMDS1", 306 "INTERNAL_TMDS2", 307 "INTERNAL_DAC1", 308 "INTERNAL_DAC2", 309 "INTERNAL_SDVOA", 310 "INTERNAL_SDVOB", 311 "SI170B", 312 "CH7303", 313 "CH7301", 314 "INTERNAL_DVO1", 315 "EXTERNAL_SDVOA", 316 "EXTERNAL_SDVOB", 317 "TITFP513", 318 "INTERNAL_LVTM1", 319 "VT1623", 320 "HDMI_SI1930", 321 "HDMI_INTERNAL", 322 "INTERNAL_KLDSCP_TMDS1", 323 "INTERNAL_KLDSCP_DVO1", 324 "INTERNAL_KLDSCP_DAC1", 325 "INTERNAL_KLDSCP_DAC2", 326 "SI178", 327 "MVPU_FPGA", 328 "INTERNAL_DDI", 329 "VT1625", 330 "HDMI_SI1932", 331 "DP_AN9801", 332 "DP_DP501", 333 "INTERNAL_UNIPHY", 334 "INTERNAL_KLDSCP_LVTMA", 335 "INTERNAL_UNIPHY1", 336 "INTERNAL_UNIPHY2", 337 "NUTMEG", 338 "TRAVIS", 339 "INTERNAL_VCE", 340 "INTERNAL_UNIPHY3", 341 "HDMI_ANX9805", 342 "INTERNAL_AMCLK", 343 "VIRTUAL", 344 }; 345 346 static const char *hpd_names[6] = { 347 "HPD1", 348 "HPD2", 349 "HPD3", 350 "HPD4", 351 "HPD5", 352 "HPD6", 353 }; 354 355 void amdgpu_display_print_display_setup(struct drm_device *dev) 356 { 357 struct drm_connector *connector; 358 struct amdgpu_connector *amdgpu_connector; 359 struct drm_encoder *encoder; 360 struct amdgpu_encoder *amdgpu_encoder; 361 uint32_t devices; 362 int i = 0; 363 364 DRM_INFO("AMDGPU Display Connectors\n"); 365 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 366 amdgpu_connector = to_amdgpu_connector(connector); 367 DRM_INFO("Connector %d:\n", i); 368 DRM_INFO(" %s\n", connector->name); 369 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 370 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 371 if (amdgpu_connector->ddc_bus) { 372 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 373 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 374 amdgpu_connector->ddc_bus->rec.mask_data_reg, 375 amdgpu_connector->ddc_bus->rec.a_clk_reg, 376 amdgpu_connector->ddc_bus->rec.a_data_reg, 377 amdgpu_connector->ddc_bus->rec.en_clk_reg, 378 amdgpu_connector->ddc_bus->rec.en_data_reg, 379 amdgpu_connector->ddc_bus->rec.y_clk_reg, 380 amdgpu_connector->ddc_bus->rec.y_data_reg); 381 if (amdgpu_connector->router.ddc_valid) 382 DRM_INFO(" DDC Router 0x%x/0x%x\n", 383 amdgpu_connector->router.ddc_mux_control_pin, 384 amdgpu_connector->router.ddc_mux_state); 385 if (amdgpu_connector->router.cd_valid) 386 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 387 amdgpu_connector->router.cd_mux_control_pin, 388 amdgpu_connector->router.cd_mux_state); 389 } else { 390 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 391 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 392 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 393 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 394 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 395 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 396 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 397 } 398 DRM_INFO(" Encoders:\n"); 399 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 400 amdgpu_encoder = to_amdgpu_encoder(encoder); 401 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 402 if (devices) { 403 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 404 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 405 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 406 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 407 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 408 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 409 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 410 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 411 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 412 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 413 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 414 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 415 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 416 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 417 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 418 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 419 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 420 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 421 if (devices & ATOM_DEVICE_TV1_SUPPORT) 422 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 423 if (devices & ATOM_DEVICE_CV_SUPPORT) 424 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 425 } 426 } 427 i++; 428 } 429 } 430 431 /** 432 * amdgpu_display_ddc_probe 433 * 434 */ 435 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 436 bool use_aux) 437 { 438 u8 out = 0x0; 439 u8 buf[8]; 440 int ret; 441 struct i2c_msg msgs[] = { 442 { 443 .addr = DDC_ADDR, 444 .flags = 0, 445 .len = 1, 446 .buf = &out, 447 }, 448 { 449 .addr = DDC_ADDR, 450 .flags = I2C_M_RD, 451 .len = 8, 452 .buf = buf, 453 } 454 }; 455 456 /* on hw with routers, select right port */ 457 if (amdgpu_connector->router.ddc_valid) 458 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 459 460 if (use_aux) { 461 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 462 } else { 463 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 464 } 465 466 if (ret != 2) 467 /* Couldn't find an accessible DDC on this connector */ 468 return false; 469 /* Probe also for valid EDID header 470 * EDID header starts with: 471 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 472 * Only the first 6 bytes must be valid as 473 * drm_edid_block_valid() can fix the last 2 bytes */ 474 if (drm_edid_header_is_valid(buf) < 6) { 475 /* Couldn't find an accessible EDID on this 476 * connector */ 477 return false; 478 } 479 return true; 480 } 481 482 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 483 .destroy = drm_gem_fb_destroy, 484 .create_handle = drm_gem_fb_create_handle, 485 }; 486 487 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) 488 { 489 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 490 491 #if defined(CONFIG_DRM_AMD_DC) 492 if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && 493 adev->flags & AMD_IS_APU && 494 amdgpu_device_asic_has_dc_support(adev->asic_type)) 495 domain |= AMDGPU_GEM_DOMAIN_GTT; 496 #endif 497 498 return domain; 499 } 500 501 int amdgpu_display_framebuffer_init(struct drm_device *dev, 502 struct amdgpu_framebuffer *rfb, 503 const struct drm_mode_fb_cmd2 *mode_cmd, 504 struct drm_gem_object *obj) 505 { 506 int ret; 507 rfb->base.obj[0] = obj; 508 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 509 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 510 if (ret) { 511 rfb->base.obj[0] = NULL; 512 return ret; 513 } 514 return 0; 515 } 516 517 struct drm_framebuffer * 518 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 519 struct drm_file *file_priv, 520 const struct drm_mode_fb_cmd2 *mode_cmd) 521 { 522 struct drm_gem_object *obj; 523 struct amdgpu_framebuffer *amdgpu_fb; 524 int ret; 525 526 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 527 if (obj == NULL) { 528 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 529 "can't create framebuffer\n", mode_cmd->handles[0]); 530 return ERR_PTR(-ENOENT); 531 } 532 533 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 534 if (obj->import_attach) { 535 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 536 return ERR_PTR(-EINVAL); 537 } 538 539 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 540 if (amdgpu_fb == NULL) { 541 drm_gem_object_put_unlocked(obj); 542 return ERR_PTR(-ENOMEM); 543 } 544 545 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 546 if (ret) { 547 kfree(amdgpu_fb); 548 drm_gem_object_put_unlocked(obj); 549 return ERR_PTR(ret); 550 } 551 552 return &amdgpu_fb->base; 553 } 554 555 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 556 .fb_create = amdgpu_display_user_framebuffer_create, 557 .output_poll_changed = drm_fb_helper_output_poll_changed, 558 }; 559 560 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 561 { { UNDERSCAN_OFF, "off" }, 562 { UNDERSCAN_ON, "on" }, 563 { UNDERSCAN_AUTO, "auto" }, 564 }; 565 566 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 567 { { AMDGPU_AUDIO_DISABLE, "off" }, 568 { AMDGPU_AUDIO_ENABLE, "on" }, 569 { AMDGPU_AUDIO_AUTO, "auto" }, 570 }; 571 572 /* XXX support different dither options? spatial, temporal, both, etc. */ 573 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 574 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 575 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 576 }; 577 578 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 579 { 580 int sz; 581 582 adev->mode_info.coherent_mode_property = 583 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 584 if (!adev->mode_info.coherent_mode_property) 585 return -ENOMEM; 586 587 adev->mode_info.load_detect_property = 588 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 589 if (!adev->mode_info.load_detect_property) 590 return -ENOMEM; 591 592 drm_mode_create_scaling_mode_property(adev->ddev); 593 594 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 595 adev->mode_info.underscan_property = 596 drm_property_create_enum(adev->ddev, 0, 597 "underscan", 598 amdgpu_underscan_enum_list, sz); 599 600 adev->mode_info.underscan_hborder_property = 601 drm_property_create_range(adev->ddev, 0, 602 "underscan hborder", 0, 128); 603 if (!adev->mode_info.underscan_hborder_property) 604 return -ENOMEM; 605 606 adev->mode_info.underscan_vborder_property = 607 drm_property_create_range(adev->ddev, 0, 608 "underscan vborder", 0, 128); 609 if (!adev->mode_info.underscan_vborder_property) 610 return -ENOMEM; 611 612 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 613 adev->mode_info.audio_property = 614 drm_property_create_enum(adev->ddev, 0, 615 "audio", 616 amdgpu_audio_enum_list, sz); 617 618 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 619 adev->mode_info.dither_property = 620 drm_property_create_enum(adev->ddev, 0, 621 "dither", 622 amdgpu_dither_enum_list, sz); 623 624 return 0; 625 } 626 627 void amdgpu_display_update_priority(struct amdgpu_device *adev) 628 { 629 /* adjustment options for the display watermarks */ 630 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 631 adev->mode_info.disp_priority = 0; 632 else 633 adev->mode_info.disp_priority = amdgpu_disp_priority; 634 635 } 636 637 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 638 { 639 /* try and guess if this is a tv or a monitor */ 640 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 641 (mode->vdisplay == 576) || /* 576p */ 642 (mode->vdisplay == 720) || /* 720p */ 643 (mode->vdisplay == 1080)) /* 1080p */ 644 return true; 645 else 646 return false; 647 } 648 649 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 650 const struct drm_display_mode *mode, 651 struct drm_display_mode *adjusted_mode) 652 { 653 struct drm_device *dev = crtc->dev; 654 struct drm_encoder *encoder; 655 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 656 struct amdgpu_encoder *amdgpu_encoder; 657 struct drm_connector *connector; 658 struct amdgpu_connector *amdgpu_connector; 659 u32 src_v = 1, dst_v = 1; 660 u32 src_h = 1, dst_h = 1; 661 662 amdgpu_crtc->h_border = 0; 663 amdgpu_crtc->v_border = 0; 664 665 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 666 if (encoder->crtc != crtc) 667 continue; 668 amdgpu_encoder = to_amdgpu_encoder(encoder); 669 connector = amdgpu_get_connector_for_encoder(encoder); 670 amdgpu_connector = to_amdgpu_connector(connector); 671 672 /* set scaling */ 673 if (amdgpu_encoder->rmx_type == RMX_OFF) 674 amdgpu_crtc->rmx_type = RMX_OFF; 675 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 676 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 677 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 678 else 679 amdgpu_crtc->rmx_type = RMX_OFF; 680 /* copy native mode */ 681 memcpy(&amdgpu_crtc->native_mode, 682 &amdgpu_encoder->native_mode, 683 sizeof(struct drm_display_mode)); 684 src_v = crtc->mode.vdisplay; 685 dst_v = amdgpu_crtc->native_mode.vdisplay; 686 src_h = crtc->mode.hdisplay; 687 dst_h = amdgpu_crtc->native_mode.hdisplay; 688 689 /* fix up for overscan on hdmi */ 690 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 691 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 692 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 693 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 694 amdgpu_display_is_hdtv_mode(mode)))) { 695 if (amdgpu_encoder->underscan_hborder != 0) 696 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 697 else 698 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 699 if (amdgpu_encoder->underscan_vborder != 0) 700 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 701 else 702 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 703 amdgpu_crtc->rmx_type = RMX_FULL; 704 src_v = crtc->mode.vdisplay; 705 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 706 src_h = crtc->mode.hdisplay; 707 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 708 } 709 } 710 if (amdgpu_crtc->rmx_type != RMX_OFF) { 711 fixed20_12 a, b; 712 a.full = dfixed_const(src_v); 713 b.full = dfixed_const(dst_v); 714 amdgpu_crtc->vsc.full = dfixed_div(a, b); 715 a.full = dfixed_const(src_h); 716 b.full = dfixed_const(dst_h); 717 amdgpu_crtc->hsc.full = dfixed_div(a, b); 718 } else { 719 amdgpu_crtc->vsc.full = dfixed_const(1); 720 amdgpu_crtc->hsc.full = dfixed_const(1); 721 } 722 return true; 723 } 724 725 /* 726 * Retrieve current video scanout position of crtc on a given gpu, and 727 * an optional accurate timestamp of when query happened. 728 * 729 * \param dev Device to query. 730 * \param pipe Crtc to query. 731 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 732 * For driver internal use only also supports these flags: 733 * 734 * USE_REAL_VBLANKSTART to use the real start of vblank instead 735 * of a fudged earlier start of vblank. 736 * 737 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 738 * fudged earlier start of vblank in *vpos and the distance 739 * to true start of vblank in *hpos. 740 * 741 * \param *vpos Location where vertical scanout position should be stored. 742 * \param *hpos Location where horizontal scanout position should go. 743 * \param *stime Target location for timestamp taken immediately before 744 * scanout position query. Can be NULL to skip timestamp. 745 * \param *etime Target location for timestamp taken immediately after 746 * scanout position query. Can be NULL to skip timestamp. 747 * 748 * Returns vpos as a positive number while in active scanout area. 749 * Returns vpos as a negative number inside vblank, counting the number 750 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 751 * until start of active scanout / end of vblank." 752 * 753 * \return Flags, or'ed together as follows: 754 * 755 * DRM_SCANOUTPOS_VALID = Query successful. 756 * DRM_SCANOUTPOS_INVBL = Inside vblank. 757 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 758 * this flag means that returned position may be offset by a constant but 759 * unknown small number of scanlines wrt. real scanout position. 760 * 761 */ 762 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 763 unsigned int pipe, unsigned int flags, int *vpos, 764 int *hpos, ktime_t *stime, ktime_t *etime, 765 const struct drm_display_mode *mode) 766 { 767 u32 vbl = 0, position = 0; 768 int vbl_start, vbl_end, vtotal, ret = 0; 769 bool in_vbl = true; 770 771 struct amdgpu_device *adev = dev->dev_private; 772 773 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 774 775 /* Get optional system timestamp before query. */ 776 if (stime) 777 *stime = ktime_get(); 778 779 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 780 ret |= DRM_SCANOUTPOS_VALID; 781 782 /* Get optional system timestamp after query. */ 783 if (etime) 784 *etime = ktime_get(); 785 786 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 787 788 /* Decode into vertical and horizontal scanout position. */ 789 *vpos = position & 0x1fff; 790 *hpos = (position >> 16) & 0x1fff; 791 792 /* Valid vblank area boundaries from gpu retrieved? */ 793 if (vbl > 0) { 794 /* Yes: Decode. */ 795 ret |= DRM_SCANOUTPOS_ACCURATE; 796 vbl_start = vbl & 0x1fff; 797 vbl_end = (vbl >> 16) & 0x1fff; 798 } 799 else { 800 /* No: Fake something reasonable which gives at least ok results. */ 801 vbl_start = mode->crtc_vdisplay; 802 vbl_end = 0; 803 } 804 805 /* Called from driver internal vblank counter query code? */ 806 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 807 /* Caller wants distance from real vbl_start in *hpos */ 808 *hpos = *vpos - vbl_start; 809 } 810 811 /* Fudge vblank to start a few scanlines earlier to handle the 812 * problem that vblank irqs fire a few scanlines before start 813 * of vblank. Some driver internal callers need the true vblank 814 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 815 * 816 * The cause of the "early" vblank irq is that the irq is triggered 817 * by the line buffer logic when the line buffer read position enters 818 * the vblank, whereas our crtc scanout position naturally lags the 819 * line buffer read position. 820 */ 821 if (!(flags & USE_REAL_VBLANKSTART)) 822 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 823 824 /* Test scanout position against vblank region. */ 825 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 826 in_vbl = false; 827 828 /* In vblank? */ 829 if (in_vbl) 830 ret |= DRM_SCANOUTPOS_IN_VBLANK; 831 832 /* Called from driver internal vblank counter query code? */ 833 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 834 /* Caller wants distance from fudged earlier vbl_start */ 835 *vpos -= vbl_start; 836 return ret; 837 } 838 839 /* Check if inside vblank area and apply corrective offsets: 840 * vpos will then be >=0 in video scanout area, but negative 841 * within vblank area, counting down the number of lines until 842 * start of scanout. 843 */ 844 845 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 846 if (in_vbl && (*vpos >= vbl_start)) { 847 vtotal = mode->crtc_vtotal; 848 *vpos = *vpos - vtotal; 849 } 850 851 /* Correct for shifted end of vbl at vbl_end. */ 852 *vpos = *vpos - vbl_end; 853 854 return ret; 855 } 856 857 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 858 { 859 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 860 return AMDGPU_CRTC_IRQ_NONE; 861 862 switch (crtc) { 863 case 0: 864 return AMDGPU_CRTC_IRQ_VBLANK1; 865 case 1: 866 return AMDGPU_CRTC_IRQ_VBLANK2; 867 case 2: 868 return AMDGPU_CRTC_IRQ_VBLANK3; 869 case 3: 870 return AMDGPU_CRTC_IRQ_VBLANK4; 871 case 4: 872 return AMDGPU_CRTC_IRQ_VBLANK5; 873 case 5: 874 return AMDGPU_CRTC_IRQ_VBLANK6; 875 default: 876 return AMDGPU_CRTC_IRQ_NONE; 877 } 878 } 879