1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include <asm/div64.h> 33 34 #include <linux/pm_runtime.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_edid.h> 37 38 static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb) 39 { 40 struct amdgpu_flip_work *work = 41 container_of(cb, struct amdgpu_flip_work, cb); 42 43 fence_put(f); 44 schedule_work(&work->flip_work); 45 } 46 47 static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work, 48 struct fence **f) 49 { 50 struct fence *fence= *f; 51 52 if (fence == NULL) 53 return false; 54 55 *f = NULL; 56 57 if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) 58 return true; 59 60 fence_put(fence); 61 return false; 62 } 63 64 static void amdgpu_flip_work_func(struct work_struct *__work) 65 { 66 struct amdgpu_flip_work *work = 67 container_of(__work, struct amdgpu_flip_work, flip_work); 68 struct amdgpu_device *adev = work->adev; 69 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; 70 71 struct drm_crtc *crtc = &amdgpuCrtc->base; 72 unsigned long flags; 73 unsigned i, repcnt = 4; 74 int vpos, hpos, stat, min_udelay = 0; 75 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 76 77 if (amdgpu_flip_handle_fence(work, &work->excl)) 78 return; 79 80 for (i = 0; i < work->shared_count; ++i) 81 if (amdgpu_flip_handle_fence(work, &work->shared[i])) 82 return; 83 84 /* We borrow the event spin lock for protecting flip_status */ 85 spin_lock_irqsave(&crtc->dev->event_lock, flags); 86 87 /* If this happens to execute within the "virtually extended" vblank 88 * interval before the start of the real vblank interval then it needs 89 * to delay programming the mmio flip until the real vblank is entered. 90 * This prevents completing a flip too early due to the way we fudge 91 * our vblank counter and vblank timestamps in order to work around the 92 * problem that the hw fires vblank interrupts before actual start of 93 * vblank (when line buffer refilling is done for a frame). It 94 * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for 95 * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. 96 * 97 * In practice this won't execute very often unless on very fast 98 * machines because the time window for this to happen is very small. 99 */ 100 while (amdgpuCrtc->enabled && --repcnt) { 101 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 102 * start in hpos, and to the "fudged earlier" vblank start in 103 * vpos. 104 */ 105 stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 106 GET_DISTANCE_TO_VBLANKSTART, 107 &vpos, &hpos, NULL, NULL, 108 &crtc->hwmode); 109 110 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 111 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 112 !(vpos >= 0 && hpos <= 0)) 113 break; 114 115 /* Sleep at least until estimated real start of hw vblank */ 116 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 117 if (min_udelay > vblank->framedur_ns / 2000) { 118 /* Don't wait ridiculously long - something is wrong */ 119 repcnt = 0; 120 break; 121 } 122 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 123 usleep_range(min_udelay, 2 * min_udelay); 124 spin_lock_irqsave(&crtc->dev->event_lock, flags); 125 }; 126 127 if (!repcnt) 128 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 129 "framedur %d, linedur %d, stat %d, vpos %d, " 130 "hpos %d\n", work->crtc_id, min_udelay, 131 vblank->framedur_ns / 1000, 132 vblank->linedur_ns / 1000, stat, vpos, hpos); 133 134 /* set the flip status */ 135 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 136 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 137 138 /* Do the flip (mmio) */ 139 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); 140 } 141 142 /* 143 * Handle unpin events outside the interrupt handler proper. 144 */ 145 static void amdgpu_unpin_work_func(struct work_struct *__work) 146 { 147 struct amdgpu_flip_work *work = 148 container_of(__work, struct amdgpu_flip_work, unpin_work); 149 int r; 150 151 /* unpin of the old buffer */ 152 r = amdgpu_bo_reserve(work->old_rbo, false); 153 if (likely(r == 0)) { 154 r = amdgpu_bo_unpin(work->old_rbo); 155 if (unlikely(r != 0)) { 156 DRM_ERROR("failed to unpin buffer after flip\n"); 157 } 158 amdgpu_bo_unreserve(work->old_rbo); 159 } else 160 DRM_ERROR("failed to reserve buffer after flip\n"); 161 162 amdgpu_bo_unref(&work->old_rbo); 163 kfree(work->shared); 164 kfree(work); 165 } 166 167 int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 168 struct drm_framebuffer *fb, 169 struct drm_pending_vblank_event *event, 170 uint32_t page_flip_flags) 171 { 172 struct drm_device *dev = crtc->dev; 173 struct amdgpu_device *adev = dev->dev_private; 174 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 175 struct amdgpu_framebuffer *old_amdgpu_fb; 176 struct amdgpu_framebuffer *new_amdgpu_fb; 177 struct drm_gem_object *obj; 178 struct amdgpu_flip_work *work; 179 struct amdgpu_bo *new_rbo; 180 unsigned long flags; 181 u64 tiling_flags; 182 u64 base; 183 int i, r; 184 185 work = kzalloc(sizeof *work, GFP_KERNEL); 186 if (work == NULL) 187 return -ENOMEM; 188 189 INIT_WORK(&work->flip_work, amdgpu_flip_work_func); 190 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); 191 192 work->event = event; 193 work->adev = adev; 194 work->crtc_id = amdgpu_crtc->crtc_id; 195 196 /* schedule unpin of the old buffer */ 197 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 198 obj = old_amdgpu_fb->obj; 199 200 /* take a reference to the old object */ 201 work->old_rbo = gem_to_amdgpu_bo(obj); 202 amdgpu_bo_ref(work->old_rbo); 203 204 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 205 obj = new_amdgpu_fb->obj; 206 new_rbo = gem_to_amdgpu_bo(obj); 207 208 /* pin the new buffer */ 209 r = amdgpu_bo_reserve(new_rbo, false); 210 if (unlikely(r != 0)) { 211 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 212 goto cleanup; 213 } 214 215 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 216 if (unlikely(r != 0)) { 217 amdgpu_bo_unreserve(new_rbo); 218 r = -EINVAL; 219 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 220 goto cleanup; 221 } 222 223 r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, 224 &work->shared_count, 225 &work->shared); 226 if (unlikely(r != 0)) { 227 amdgpu_bo_unreserve(new_rbo); 228 DRM_ERROR("failed to get fences for buffer\n"); 229 goto cleanup; 230 } 231 232 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); 233 amdgpu_bo_unreserve(new_rbo); 234 235 work->base = base; 236 237 r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); 238 if (r) { 239 DRM_ERROR("failed to get vblank before flip\n"); 240 goto pflip_cleanup; 241 } 242 243 /* we borrow the event spin lock for protecting flip_wrok */ 244 spin_lock_irqsave(&crtc->dev->event_lock, flags); 245 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 246 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 247 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 248 r = -EBUSY; 249 goto vblank_cleanup; 250 } 251 252 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 253 amdgpu_crtc->pflip_works = work; 254 255 /* update crtc fb */ 256 crtc->primary->fb = fb; 257 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 258 amdgpu_flip_work_func(&work->flip_work); 259 return 0; 260 261 vblank_cleanup: 262 drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); 263 264 pflip_cleanup: 265 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { 266 DRM_ERROR("failed to reserve new rbo in error path\n"); 267 goto cleanup; 268 } 269 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { 270 DRM_ERROR("failed to unpin new rbo in error path\n"); 271 } 272 amdgpu_bo_unreserve(new_rbo); 273 274 cleanup: 275 amdgpu_bo_unref(&work->old_rbo); 276 fence_put(work->excl); 277 for (i = 0; i < work->shared_count; ++i) 278 fence_put(work->shared[i]); 279 kfree(work->shared); 280 kfree(work); 281 282 return r; 283 } 284 285 int amdgpu_crtc_set_config(struct drm_mode_set *set) 286 { 287 struct drm_device *dev; 288 struct amdgpu_device *adev; 289 struct drm_crtc *crtc; 290 bool active = false; 291 int ret; 292 293 if (!set || !set->crtc) 294 return -EINVAL; 295 296 dev = set->crtc->dev; 297 298 ret = pm_runtime_get_sync(dev->dev); 299 if (ret < 0) 300 return ret; 301 302 ret = drm_crtc_helper_set_config(set); 303 304 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 305 if (crtc->enabled) 306 active = true; 307 308 pm_runtime_mark_last_busy(dev->dev); 309 310 adev = dev->dev_private; 311 /* if we have active crtcs and we don't have a power ref, 312 take the current one */ 313 if (active && !adev->have_disp_power_ref) { 314 adev->have_disp_power_ref = true; 315 return ret; 316 } 317 /* if we have no active crtcs, then drop the power ref 318 we got before */ 319 if (!active && adev->have_disp_power_ref) { 320 pm_runtime_put_autosuspend(dev->dev); 321 adev->have_disp_power_ref = false; 322 } 323 324 /* drop the power reference we got coming in here */ 325 pm_runtime_put_autosuspend(dev->dev); 326 return ret; 327 } 328 329 static const char *encoder_names[38] = { 330 "NONE", 331 "INTERNAL_LVDS", 332 "INTERNAL_TMDS1", 333 "INTERNAL_TMDS2", 334 "INTERNAL_DAC1", 335 "INTERNAL_DAC2", 336 "INTERNAL_SDVOA", 337 "INTERNAL_SDVOB", 338 "SI170B", 339 "CH7303", 340 "CH7301", 341 "INTERNAL_DVO1", 342 "EXTERNAL_SDVOA", 343 "EXTERNAL_SDVOB", 344 "TITFP513", 345 "INTERNAL_LVTM1", 346 "VT1623", 347 "HDMI_SI1930", 348 "HDMI_INTERNAL", 349 "INTERNAL_KLDSCP_TMDS1", 350 "INTERNAL_KLDSCP_DVO1", 351 "INTERNAL_KLDSCP_DAC1", 352 "INTERNAL_KLDSCP_DAC2", 353 "SI178", 354 "MVPU_FPGA", 355 "INTERNAL_DDI", 356 "VT1625", 357 "HDMI_SI1932", 358 "DP_AN9801", 359 "DP_DP501", 360 "INTERNAL_UNIPHY", 361 "INTERNAL_KLDSCP_LVTMA", 362 "INTERNAL_UNIPHY1", 363 "INTERNAL_UNIPHY2", 364 "NUTMEG", 365 "TRAVIS", 366 "INTERNAL_VCE", 367 "INTERNAL_UNIPHY3", 368 }; 369 370 static const char *hpd_names[6] = { 371 "HPD1", 372 "HPD2", 373 "HPD3", 374 "HPD4", 375 "HPD5", 376 "HPD6", 377 }; 378 379 void amdgpu_print_display_setup(struct drm_device *dev) 380 { 381 struct drm_connector *connector; 382 struct amdgpu_connector *amdgpu_connector; 383 struct drm_encoder *encoder; 384 struct amdgpu_encoder *amdgpu_encoder; 385 uint32_t devices; 386 int i = 0; 387 388 DRM_INFO("AMDGPU Display Connectors\n"); 389 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 390 amdgpu_connector = to_amdgpu_connector(connector); 391 DRM_INFO("Connector %d:\n", i); 392 DRM_INFO(" %s\n", connector->name); 393 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 394 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 395 if (amdgpu_connector->ddc_bus) { 396 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 397 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 398 amdgpu_connector->ddc_bus->rec.mask_data_reg, 399 amdgpu_connector->ddc_bus->rec.a_clk_reg, 400 amdgpu_connector->ddc_bus->rec.a_data_reg, 401 amdgpu_connector->ddc_bus->rec.en_clk_reg, 402 amdgpu_connector->ddc_bus->rec.en_data_reg, 403 amdgpu_connector->ddc_bus->rec.y_clk_reg, 404 amdgpu_connector->ddc_bus->rec.y_data_reg); 405 if (amdgpu_connector->router.ddc_valid) 406 DRM_INFO(" DDC Router 0x%x/0x%x\n", 407 amdgpu_connector->router.ddc_mux_control_pin, 408 amdgpu_connector->router.ddc_mux_state); 409 if (amdgpu_connector->router.cd_valid) 410 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 411 amdgpu_connector->router.cd_mux_control_pin, 412 amdgpu_connector->router.cd_mux_state); 413 } else { 414 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 415 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 416 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 417 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 418 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 419 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 420 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 421 } 422 DRM_INFO(" Encoders:\n"); 423 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 424 amdgpu_encoder = to_amdgpu_encoder(encoder); 425 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 426 if (devices) { 427 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 428 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 429 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 430 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 431 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 432 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 433 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 434 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 435 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 436 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 437 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 438 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 439 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 440 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 441 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 442 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 443 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 444 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 445 if (devices & ATOM_DEVICE_TV1_SUPPORT) 446 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 447 if (devices & ATOM_DEVICE_CV_SUPPORT) 448 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 449 } 450 } 451 i++; 452 } 453 } 454 455 /** 456 * amdgpu_ddc_probe 457 * 458 */ 459 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, 460 bool use_aux) 461 { 462 u8 out = 0x0; 463 u8 buf[8]; 464 int ret; 465 struct i2c_msg msgs[] = { 466 { 467 .addr = DDC_ADDR, 468 .flags = 0, 469 .len = 1, 470 .buf = &out, 471 }, 472 { 473 .addr = DDC_ADDR, 474 .flags = I2C_M_RD, 475 .len = 8, 476 .buf = buf, 477 } 478 }; 479 480 /* on hw with routers, select right port */ 481 if (amdgpu_connector->router.ddc_valid) 482 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 483 484 if (use_aux) { 485 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 486 } else { 487 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 488 } 489 490 if (ret != 2) 491 /* Couldn't find an accessible DDC on this connector */ 492 return false; 493 /* Probe also for valid EDID header 494 * EDID header starts with: 495 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 496 * Only the first 6 bytes must be valid as 497 * drm_edid_block_valid() can fix the last 2 bytes */ 498 if (drm_edid_header_is_valid(buf) < 6) { 499 /* Couldn't find an accessible EDID on this 500 * connector */ 501 return false; 502 } 503 return true; 504 } 505 506 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) 507 { 508 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 509 510 if (amdgpu_fb->obj) { 511 drm_gem_object_unreference_unlocked(amdgpu_fb->obj); 512 } 513 drm_framebuffer_cleanup(fb); 514 kfree(amdgpu_fb); 515 } 516 517 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, 518 struct drm_file *file_priv, 519 unsigned int *handle) 520 { 521 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 522 523 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); 524 } 525 526 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 527 .destroy = amdgpu_user_framebuffer_destroy, 528 .create_handle = amdgpu_user_framebuffer_create_handle, 529 }; 530 531 int 532 amdgpu_framebuffer_init(struct drm_device *dev, 533 struct amdgpu_framebuffer *rfb, 534 const struct drm_mode_fb_cmd2 *mode_cmd, 535 struct drm_gem_object *obj) 536 { 537 int ret; 538 rfb->obj = obj; 539 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 540 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 541 if (ret) { 542 rfb->obj = NULL; 543 return ret; 544 } 545 return 0; 546 } 547 548 static struct drm_framebuffer * 549 amdgpu_user_framebuffer_create(struct drm_device *dev, 550 struct drm_file *file_priv, 551 const struct drm_mode_fb_cmd2 *mode_cmd) 552 { 553 struct drm_gem_object *obj; 554 struct amdgpu_framebuffer *amdgpu_fb; 555 int ret; 556 557 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 558 if (obj == NULL) { 559 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 560 "can't create framebuffer\n", mode_cmd->handles[0]); 561 return ERR_PTR(-ENOENT); 562 } 563 564 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 565 if (amdgpu_fb == NULL) { 566 drm_gem_object_unreference_unlocked(obj); 567 return ERR_PTR(-ENOMEM); 568 } 569 570 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 571 if (ret) { 572 kfree(amdgpu_fb); 573 drm_gem_object_unreference_unlocked(obj); 574 return ERR_PTR(ret); 575 } 576 577 return &amdgpu_fb->base; 578 } 579 580 static void amdgpu_output_poll_changed(struct drm_device *dev) 581 { 582 struct amdgpu_device *adev = dev->dev_private; 583 amdgpu_fb_output_poll_changed(adev); 584 } 585 586 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 587 .fb_create = amdgpu_user_framebuffer_create, 588 .output_poll_changed = amdgpu_output_poll_changed 589 }; 590 591 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 592 { { UNDERSCAN_OFF, "off" }, 593 { UNDERSCAN_ON, "on" }, 594 { UNDERSCAN_AUTO, "auto" }, 595 }; 596 597 static struct drm_prop_enum_list amdgpu_audio_enum_list[] = 598 { { AMDGPU_AUDIO_DISABLE, "off" }, 599 { AMDGPU_AUDIO_ENABLE, "on" }, 600 { AMDGPU_AUDIO_AUTO, "auto" }, 601 }; 602 603 /* XXX support different dither options? spatial, temporal, both, etc. */ 604 static struct drm_prop_enum_list amdgpu_dither_enum_list[] = 605 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 606 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 607 }; 608 609 int amdgpu_modeset_create_props(struct amdgpu_device *adev) 610 { 611 int sz; 612 613 if (adev->is_atom_bios) { 614 adev->mode_info.coherent_mode_property = 615 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 616 if (!adev->mode_info.coherent_mode_property) 617 return -ENOMEM; 618 } 619 620 adev->mode_info.load_detect_property = 621 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 622 if (!adev->mode_info.load_detect_property) 623 return -ENOMEM; 624 625 drm_mode_create_scaling_mode_property(adev->ddev); 626 627 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 628 adev->mode_info.underscan_property = 629 drm_property_create_enum(adev->ddev, 0, 630 "underscan", 631 amdgpu_underscan_enum_list, sz); 632 633 adev->mode_info.underscan_hborder_property = 634 drm_property_create_range(adev->ddev, 0, 635 "underscan hborder", 0, 128); 636 if (!adev->mode_info.underscan_hborder_property) 637 return -ENOMEM; 638 639 adev->mode_info.underscan_vborder_property = 640 drm_property_create_range(adev->ddev, 0, 641 "underscan vborder", 0, 128); 642 if (!adev->mode_info.underscan_vborder_property) 643 return -ENOMEM; 644 645 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 646 adev->mode_info.audio_property = 647 drm_property_create_enum(adev->ddev, 0, 648 "audio", 649 amdgpu_audio_enum_list, sz); 650 651 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 652 adev->mode_info.dither_property = 653 drm_property_create_enum(adev->ddev, 0, 654 "dither", 655 amdgpu_dither_enum_list, sz); 656 657 return 0; 658 } 659 660 void amdgpu_update_display_priority(struct amdgpu_device *adev) 661 { 662 /* adjustment options for the display watermarks */ 663 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 664 adev->mode_info.disp_priority = 0; 665 else 666 adev->mode_info.disp_priority = amdgpu_disp_priority; 667 668 } 669 670 static bool is_hdtv_mode(const struct drm_display_mode *mode) 671 { 672 /* try and guess if this is a tv or a monitor */ 673 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 674 (mode->vdisplay == 576) || /* 576p */ 675 (mode->vdisplay == 720) || /* 720p */ 676 (mode->vdisplay == 1080)) /* 1080p */ 677 return true; 678 else 679 return false; 680 } 681 682 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 683 const struct drm_display_mode *mode, 684 struct drm_display_mode *adjusted_mode) 685 { 686 struct drm_device *dev = crtc->dev; 687 struct drm_encoder *encoder; 688 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 689 struct amdgpu_encoder *amdgpu_encoder; 690 struct drm_connector *connector; 691 struct amdgpu_connector *amdgpu_connector; 692 u32 src_v = 1, dst_v = 1; 693 u32 src_h = 1, dst_h = 1; 694 695 amdgpu_crtc->h_border = 0; 696 amdgpu_crtc->v_border = 0; 697 698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 699 if (encoder->crtc != crtc) 700 continue; 701 amdgpu_encoder = to_amdgpu_encoder(encoder); 702 connector = amdgpu_get_connector_for_encoder(encoder); 703 amdgpu_connector = to_amdgpu_connector(connector); 704 705 /* set scaling */ 706 if (amdgpu_encoder->rmx_type == RMX_OFF) 707 amdgpu_crtc->rmx_type = RMX_OFF; 708 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 709 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 710 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 711 else 712 amdgpu_crtc->rmx_type = RMX_OFF; 713 /* copy native mode */ 714 memcpy(&amdgpu_crtc->native_mode, 715 &amdgpu_encoder->native_mode, 716 sizeof(struct drm_display_mode)); 717 src_v = crtc->mode.vdisplay; 718 dst_v = amdgpu_crtc->native_mode.vdisplay; 719 src_h = crtc->mode.hdisplay; 720 dst_h = amdgpu_crtc->native_mode.hdisplay; 721 722 /* fix up for overscan on hdmi */ 723 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 724 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 725 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 726 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 727 is_hdtv_mode(mode)))) { 728 if (amdgpu_encoder->underscan_hborder != 0) 729 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 730 else 731 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 732 if (amdgpu_encoder->underscan_vborder != 0) 733 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 734 else 735 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 736 amdgpu_crtc->rmx_type = RMX_FULL; 737 src_v = crtc->mode.vdisplay; 738 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 739 src_h = crtc->mode.hdisplay; 740 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 741 } 742 } 743 if (amdgpu_crtc->rmx_type != RMX_OFF) { 744 fixed20_12 a, b; 745 a.full = dfixed_const(src_v); 746 b.full = dfixed_const(dst_v); 747 amdgpu_crtc->vsc.full = dfixed_div(a, b); 748 a.full = dfixed_const(src_h); 749 b.full = dfixed_const(dst_h); 750 amdgpu_crtc->hsc.full = dfixed_div(a, b); 751 } else { 752 amdgpu_crtc->vsc.full = dfixed_const(1); 753 amdgpu_crtc->hsc.full = dfixed_const(1); 754 } 755 return true; 756 } 757 758 /* 759 * Retrieve current video scanout position of crtc on a given gpu, and 760 * an optional accurate timestamp of when query happened. 761 * 762 * \param dev Device to query. 763 * \param pipe Crtc to query. 764 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 765 * For driver internal use only also supports these flags: 766 * 767 * USE_REAL_VBLANKSTART to use the real start of vblank instead 768 * of a fudged earlier start of vblank. 769 * 770 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 771 * fudged earlier start of vblank in *vpos and the distance 772 * to true start of vblank in *hpos. 773 * 774 * \param *vpos Location where vertical scanout position should be stored. 775 * \param *hpos Location where horizontal scanout position should go. 776 * \param *stime Target location for timestamp taken immediately before 777 * scanout position query. Can be NULL to skip timestamp. 778 * \param *etime Target location for timestamp taken immediately after 779 * scanout position query. Can be NULL to skip timestamp. 780 * 781 * Returns vpos as a positive number while in active scanout area. 782 * Returns vpos as a negative number inside vblank, counting the number 783 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 784 * until start of active scanout / end of vblank." 785 * 786 * \return Flags, or'ed together as follows: 787 * 788 * DRM_SCANOUTPOS_VALID = Query successful. 789 * DRM_SCANOUTPOS_INVBL = Inside vblank. 790 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 791 * this flag means that returned position may be offset by a constant but 792 * unknown small number of scanlines wrt. real scanout position. 793 * 794 */ 795 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 796 unsigned int flags, int *vpos, int *hpos, 797 ktime_t *stime, ktime_t *etime, 798 const struct drm_display_mode *mode) 799 { 800 u32 vbl = 0, position = 0; 801 int vbl_start, vbl_end, vtotal, ret = 0; 802 bool in_vbl = true; 803 804 struct amdgpu_device *adev = dev->dev_private; 805 806 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 807 808 /* Get optional system timestamp before query. */ 809 if (stime) 810 *stime = ktime_get(); 811 812 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 813 ret |= DRM_SCANOUTPOS_VALID; 814 815 /* Get optional system timestamp after query. */ 816 if (etime) 817 *etime = ktime_get(); 818 819 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 820 821 /* Decode into vertical and horizontal scanout position. */ 822 *vpos = position & 0x1fff; 823 *hpos = (position >> 16) & 0x1fff; 824 825 /* Valid vblank area boundaries from gpu retrieved? */ 826 if (vbl > 0) { 827 /* Yes: Decode. */ 828 ret |= DRM_SCANOUTPOS_ACCURATE; 829 vbl_start = vbl & 0x1fff; 830 vbl_end = (vbl >> 16) & 0x1fff; 831 } 832 else { 833 /* No: Fake something reasonable which gives at least ok results. */ 834 vbl_start = mode->crtc_vdisplay; 835 vbl_end = 0; 836 } 837 838 /* Called from driver internal vblank counter query code? */ 839 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 840 /* Caller wants distance from real vbl_start in *hpos */ 841 *hpos = *vpos - vbl_start; 842 } 843 844 /* Fudge vblank to start a few scanlines earlier to handle the 845 * problem that vblank irqs fire a few scanlines before start 846 * of vblank. Some driver internal callers need the true vblank 847 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 848 * 849 * The cause of the "early" vblank irq is that the irq is triggered 850 * by the line buffer logic when the line buffer read position enters 851 * the vblank, whereas our crtc scanout position naturally lags the 852 * line buffer read position. 853 */ 854 if (!(flags & USE_REAL_VBLANKSTART)) 855 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 856 857 /* Test scanout position against vblank region. */ 858 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 859 in_vbl = false; 860 861 /* In vblank? */ 862 if (in_vbl) 863 ret |= DRM_SCANOUTPOS_IN_VBLANK; 864 865 /* Called from driver internal vblank counter query code? */ 866 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 867 /* Caller wants distance from fudged earlier vbl_start */ 868 *vpos -= vbl_start; 869 return ret; 870 } 871 872 /* Check if inside vblank area and apply corrective offsets: 873 * vpos will then be >=0 in video scanout area, but negative 874 * within vblank area, counting down the number of lines until 875 * start of scanout. 876 */ 877 878 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 879 if (in_vbl && (*vpos >= vbl_start)) { 880 vtotal = mode->crtc_vtotal; 881 *vpos = *vpos - vtotal; 882 } 883 884 /* Correct for shifted end of vbl at vbl_end. */ 885 *vpos = *vpos - vbl_end; 886 887 return ret; 888 } 889 890 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 891 { 892 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 893 return AMDGPU_CRTC_IRQ_NONE; 894 895 switch (crtc) { 896 case 0: 897 return AMDGPU_CRTC_IRQ_VBLANK1; 898 case 1: 899 return AMDGPU_CRTC_IRQ_VBLANK2; 900 case 2: 901 return AMDGPU_CRTC_IRQ_VBLANK3; 902 case 3: 903 return AMDGPU_CRTC_IRQ_VBLANK4; 904 case 4: 905 return AMDGPU_CRTC_IRQ_VBLANK5; 906 case 5: 907 return AMDGPU_CRTC_IRQ_VBLANK6; 908 default: 909 return AMDGPU_CRTC_IRQ_NONE; 910 } 911 } 912