1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include "soc15_common.h"
34 #include "gc/gc_11_0_0_offset.h"
35 #include "gc/gc_11_0_0_sh_mask.h"
36 #include <asm/div64.h>
37 
38 #include <linux/pci.h>
39 #include <linux/pm_runtime.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_gem_framebuffer_helper.h>
43 #include <drm/drm_fb_helper.h>
44 #include <drm/drm_fourcc.h>
45 #include <drm/drm_vblank.h>
46 
47 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
48 					   struct amdgpu_framebuffer *rfb,
49 					   const struct drm_mode_fb_cmd2 *mode_cmd,
50 					   struct drm_gem_object *obj);
51 
52 static void amdgpu_display_flip_callback(struct dma_fence *f,
53 					 struct dma_fence_cb *cb)
54 {
55 	struct amdgpu_flip_work *work =
56 		container_of(cb, struct amdgpu_flip_work, cb);
57 
58 	dma_fence_put(f);
59 	schedule_work(&work->flip_work.work);
60 }
61 
62 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
63 					     struct dma_fence **f)
64 {
65 	struct dma_fence *fence= *f;
66 
67 	if (fence == NULL)
68 		return false;
69 
70 	*f = NULL;
71 
72 	if (!dma_fence_add_callback(fence, &work->cb,
73 				    amdgpu_display_flip_callback))
74 		return true;
75 
76 	dma_fence_put(fence);
77 	return false;
78 }
79 
80 static void amdgpu_display_flip_work_func(struct work_struct *__work)
81 {
82 	struct delayed_work *delayed_work =
83 		container_of(__work, struct delayed_work, work);
84 	struct amdgpu_flip_work *work =
85 		container_of(delayed_work, struct amdgpu_flip_work, flip_work);
86 	struct amdgpu_device *adev = work->adev;
87 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
88 
89 	struct drm_crtc *crtc = &amdgpu_crtc->base;
90 	unsigned long flags;
91 	unsigned i;
92 	int vpos, hpos;
93 
94 	for (i = 0; i < work->shared_count; ++i)
95 		if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
96 			return;
97 
98 	/* Wait until we're out of the vertical blank period before the one
99 	 * targeted by the flip
100 	 */
101 	if (amdgpu_crtc->enabled &&
102 	    (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
103 						&vpos, &hpos, NULL, NULL,
104 						&crtc->hwmode)
105 	     & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
106 	    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
107 	    (int)(work->target_vblank -
108 		  amdgpu_get_vblank_counter_kms(crtc)) > 0) {
109 		schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
110 		return;
111 	}
112 
113 	/* We borrow the event spin lock for protecting flip_status */
114 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
115 
116 	/* Do the flip (mmio) */
117 	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
118 
119 	/* Set the flip status */
120 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
121 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
122 
123 
124 	drm_dbg_vbl(adev_to_drm(adev),
125 		    "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
126 		    amdgpu_crtc->crtc_id, amdgpu_crtc, work);
127 
128 }
129 
130 /*
131  * Handle unpin events outside the interrupt handler proper.
132  */
133 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
134 {
135 	struct amdgpu_flip_work *work =
136 		container_of(__work, struct amdgpu_flip_work, unpin_work);
137 	int r;
138 
139 	/* unpin of the old buffer */
140 	r = amdgpu_bo_reserve(work->old_abo, true);
141 	if (likely(r == 0)) {
142 		amdgpu_bo_unpin(work->old_abo);
143 		amdgpu_bo_unreserve(work->old_abo);
144 	} else
145 		DRM_ERROR("failed to reserve buffer after flip\n");
146 
147 	amdgpu_bo_unref(&work->old_abo);
148 	kfree(work->shared);
149 	kfree(work);
150 }
151 
152 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
153 				struct drm_framebuffer *fb,
154 				struct drm_pending_vblank_event *event,
155 				uint32_t page_flip_flags, uint32_t target,
156 				struct drm_modeset_acquire_ctx *ctx)
157 {
158 	struct drm_device *dev = crtc->dev;
159 	struct amdgpu_device *adev = drm_to_adev(dev);
160 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
161 	struct drm_gem_object *obj;
162 	struct amdgpu_flip_work *work;
163 	struct amdgpu_bo *new_abo;
164 	unsigned long flags;
165 	u64 tiling_flags;
166 	int i, r;
167 
168 	work = kzalloc(sizeof *work, GFP_KERNEL);
169 	if (work == NULL)
170 		return -ENOMEM;
171 
172 	INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
173 	INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
174 
175 	work->event = event;
176 	work->adev = adev;
177 	work->crtc_id = amdgpu_crtc->crtc_id;
178 	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
179 
180 	/* schedule unpin of the old buffer */
181 	obj = crtc->primary->fb->obj[0];
182 
183 	/* take a reference to the old object */
184 	work->old_abo = gem_to_amdgpu_bo(obj);
185 	amdgpu_bo_ref(work->old_abo);
186 
187 	obj = fb->obj[0];
188 	new_abo = gem_to_amdgpu_bo(obj);
189 
190 	/* pin the new buffer */
191 	r = amdgpu_bo_reserve(new_abo, false);
192 	if (unlikely(r != 0)) {
193 		DRM_ERROR("failed to reserve new abo buffer before flip\n");
194 		goto cleanup;
195 	}
196 
197 	if (!adev->enable_virtual_display) {
198 		r = amdgpu_bo_pin(new_abo,
199 				  amdgpu_display_supported_domains(adev, new_abo->flags));
200 		if (unlikely(r != 0)) {
201 			DRM_ERROR("failed to pin new abo buffer before flip\n");
202 			goto unreserve;
203 		}
204 	}
205 
206 	r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
207 	if (unlikely(r != 0)) {
208 		DRM_ERROR("%p bind failed\n", new_abo);
209 		goto unpin;
210 	}
211 
212 	r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
213 				&work->shared_count,
214 				&work->shared);
215 	if (unlikely(r != 0)) {
216 		DRM_ERROR("failed to get fences for buffer\n");
217 		goto unpin;
218 	}
219 
220 	amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
221 	amdgpu_bo_unreserve(new_abo);
222 
223 	if (!adev->enable_virtual_display)
224 		work->base = amdgpu_bo_gpu_offset(new_abo);
225 	work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
226 		amdgpu_get_vblank_counter_kms(crtc);
227 
228 	/* we borrow the event spin lock for protecting flip_wrok */
229 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
230 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
231 		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
232 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
233 		r = -EBUSY;
234 		goto pflip_cleanup;
235 	}
236 
237 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
238 	amdgpu_crtc->pflip_works = work;
239 
240 
241 	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
242 					 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
243 	/* update crtc fb */
244 	crtc->primary->fb = fb;
245 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
246 	amdgpu_display_flip_work_func(&work->flip_work.work);
247 	return 0;
248 
249 pflip_cleanup:
250 	if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
251 		DRM_ERROR("failed to reserve new abo in error path\n");
252 		goto cleanup;
253 	}
254 unpin:
255 	if (!adev->enable_virtual_display)
256 		amdgpu_bo_unpin(new_abo);
257 
258 unreserve:
259 	amdgpu_bo_unreserve(new_abo);
260 
261 cleanup:
262 	amdgpu_bo_unref(&work->old_abo);
263 	for (i = 0; i < work->shared_count; ++i)
264 		dma_fence_put(work->shared[i]);
265 	kfree(work->shared);
266 	kfree(work);
267 
268 	return r;
269 }
270 
271 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
272 				   struct drm_modeset_acquire_ctx *ctx)
273 {
274 	struct drm_device *dev;
275 	struct amdgpu_device *adev;
276 	struct drm_crtc *crtc;
277 	bool active = false;
278 	int ret;
279 
280 	if (!set || !set->crtc)
281 		return -EINVAL;
282 
283 	dev = set->crtc->dev;
284 
285 	ret = pm_runtime_get_sync(dev->dev);
286 	if (ret < 0)
287 		goto out;
288 
289 	ret = drm_crtc_helper_set_config(set, ctx);
290 
291 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
292 		if (crtc->enabled)
293 			active = true;
294 
295 	pm_runtime_mark_last_busy(dev->dev);
296 
297 	adev = drm_to_adev(dev);
298 	/* if we have active crtcs and we don't have a power ref,
299 	   take the current one */
300 	if (active && !adev->have_disp_power_ref) {
301 		adev->have_disp_power_ref = true;
302 		return ret;
303 	}
304 	/* if we have no active crtcs, then drop the power ref
305 	   we got before */
306 	if (!active && adev->have_disp_power_ref) {
307 		pm_runtime_put_autosuspend(dev->dev);
308 		adev->have_disp_power_ref = false;
309 	}
310 
311 out:
312 	/* drop the power reference we got coming in here */
313 	pm_runtime_put_autosuspend(dev->dev);
314 	return ret;
315 }
316 
317 static const char *encoder_names[41] = {
318 	"NONE",
319 	"INTERNAL_LVDS",
320 	"INTERNAL_TMDS1",
321 	"INTERNAL_TMDS2",
322 	"INTERNAL_DAC1",
323 	"INTERNAL_DAC2",
324 	"INTERNAL_SDVOA",
325 	"INTERNAL_SDVOB",
326 	"SI170B",
327 	"CH7303",
328 	"CH7301",
329 	"INTERNAL_DVO1",
330 	"EXTERNAL_SDVOA",
331 	"EXTERNAL_SDVOB",
332 	"TITFP513",
333 	"INTERNAL_LVTM1",
334 	"VT1623",
335 	"HDMI_SI1930",
336 	"HDMI_INTERNAL",
337 	"INTERNAL_KLDSCP_TMDS1",
338 	"INTERNAL_KLDSCP_DVO1",
339 	"INTERNAL_KLDSCP_DAC1",
340 	"INTERNAL_KLDSCP_DAC2",
341 	"SI178",
342 	"MVPU_FPGA",
343 	"INTERNAL_DDI",
344 	"VT1625",
345 	"HDMI_SI1932",
346 	"DP_AN9801",
347 	"DP_DP501",
348 	"INTERNAL_UNIPHY",
349 	"INTERNAL_KLDSCP_LVTMA",
350 	"INTERNAL_UNIPHY1",
351 	"INTERNAL_UNIPHY2",
352 	"NUTMEG",
353 	"TRAVIS",
354 	"INTERNAL_VCE",
355 	"INTERNAL_UNIPHY3",
356 	"HDMI_ANX9805",
357 	"INTERNAL_AMCLK",
358 	"VIRTUAL",
359 };
360 
361 static const char *hpd_names[6] = {
362 	"HPD1",
363 	"HPD2",
364 	"HPD3",
365 	"HPD4",
366 	"HPD5",
367 	"HPD6",
368 };
369 
370 void amdgpu_display_print_display_setup(struct drm_device *dev)
371 {
372 	struct drm_connector *connector;
373 	struct amdgpu_connector *amdgpu_connector;
374 	struct drm_encoder *encoder;
375 	struct amdgpu_encoder *amdgpu_encoder;
376 	struct drm_connector_list_iter iter;
377 	uint32_t devices;
378 	int i = 0;
379 
380 	drm_connector_list_iter_begin(dev, &iter);
381 	DRM_INFO("AMDGPU Display Connectors\n");
382 	drm_for_each_connector_iter(connector, &iter) {
383 		amdgpu_connector = to_amdgpu_connector(connector);
384 		DRM_INFO("Connector %d:\n", i);
385 		DRM_INFO("  %s\n", connector->name);
386 		if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
387 			DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
388 		if (amdgpu_connector->ddc_bus) {
389 			DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
390 				 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
391 				 amdgpu_connector->ddc_bus->rec.mask_data_reg,
392 				 amdgpu_connector->ddc_bus->rec.a_clk_reg,
393 				 amdgpu_connector->ddc_bus->rec.a_data_reg,
394 				 amdgpu_connector->ddc_bus->rec.en_clk_reg,
395 				 amdgpu_connector->ddc_bus->rec.en_data_reg,
396 				 amdgpu_connector->ddc_bus->rec.y_clk_reg,
397 				 amdgpu_connector->ddc_bus->rec.y_data_reg);
398 			if (amdgpu_connector->router.ddc_valid)
399 				DRM_INFO("  DDC Router 0x%x/0x%x\n",
400 					 amdgpu_connector->router.ddc_mux_control_pin,
401 					 amdgpu_connector->router.ddc_mux_state);
402 			if (amdgpu_connector->router.cd_valid)
403 				DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
404 					 amdgpu_connector->router.cd_mux_control_pin,
405 					 amdgpu_connector->router.cd_mux_state);
406 		} else {
407 			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
408 			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
409 			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
410 			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
411 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
412 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
413 				DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
414 		}
415 		DRM_INFO("  Encoders:\n");
416 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
417 			amdgpu_encoder = to_amdgpu_encoder(encoder);
418 			devices = amdgpu_encoder->devices & amdgpu_connector->devices;
419 			if (devices) {
420 				if (devices & ATOM_DEVICE_CRT1_SUPPORT)
421 					DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
422 				if (devices & ATOM_DEVICE_CRT2_SUPPORT)
423 					DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
424 				if (devices & ATOM_DEVICE_LCD1_SUPPORT)
425 					DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
426 				if (devices & ATOM_DEVICE_DFP1_SUPPORT)
427 					DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
428 				if (devices & ATOM_DEVICE_DFP2_SUPPORT)
429 					DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
430 				if (devices & ATOM_DEVICE_DFP3_SUPPORT)
431 					DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
432 				if (devices & ATOM_DEVICE_DFP4_SUPPORT)
433 					DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
434 				if (devices & ATOM_DEVICE_DFP5_SUPPORT)
435 					DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
436 				if (devices & ATOM_DEVICE_DFP6_SUPPORT)
437 					DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
438 				if (devices & ATOM_DEVICE_TV1_SUPPORT)
439 					DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
440 				if (devices & ATOM_DEVICE_CV_SUPPORT)
441 					DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
442 			}
443 		}
444 		i++;
445 	}
446 	drm_connector_list_iter_end(&iter);
447 }
448 
449 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
450 			      bool use_aux)
451 {
452 	u8 out = 0x0;
453 	u8 buf[8];
454 	int ret;
455 	struct i2c_msg msgs[] = {
456 		{
457 			.addr = DDC_ADDR,
458 			.flags = 0,
459 			.len = 1,
460 			.buf = &out,
461 		},
462 		{
463 			.addr = DDC_ADDR,
464 			.flags = I2C_M_RD,
465 			.len = 8,
466 			.buf = buf,
467 		}
468 	};
469 
470 	/* on hw with routers, select right port */
471 	if (amdgpu_connector->router.ddc_valid)
472 		amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
473 
474 	if (use_aux) {
475 		ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
476 	} else {
477 		ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
478 	}
479 
480 	if (ret != 2)
481 		/* Couldn't find an accessible DDC on this connector */
482 		return false;
483 	/* Probe also for valid EDID header
484 	 * EDID header starts with:
485 	 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
486 	 * Only the first 6 bytes must be valid as
487 	 * drm_edid_block_valid() can fix the last 2 bytes */
488 	if (drm_edid_header_is_valid(buf) < 6) {
489 		/* Couldn't find an accessible EDID on this
490 		 * connector */
491 		return false;
492 	}
493 	return true;
494 }
495 
496 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
497 	.destroy = drm_gem_fb_destroy,
498 	.create_handle = drm_gem_fb_create_handle,
499 };
500 
501 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
502 					  uint64_t bo_flags)
503 {
504 	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
505 
506 #if defined(CONFIG_DRM_AMD_DC)
507 	/*
508 	 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
509 	 * is not supported for this board. But this mapping is required
510 	 * to avoid hang caused by placement of scanout BO in GTT on certain
511 	 * APUs. So force the BO placement to VRAM in case this architecture
512 	 * will not allow USWC mappings.
513 	 * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
514 	 */
515 	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
516 	    amdgpu_bo_support_uswc(bo_flags) &&
517 	    amdgpu_device_asic_has_dc_support(adev->asic_type) &&
518 	    adev->mode_info.gpu_vm_support)
519 		domain |= AMDGPU_GEM_DOMAIN_GTT;
520 #endif
521 
522 	return domain;
523 }
524 
525 static const struct drm_format_info dcc_formats[] = {
526 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
527 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
528 	 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
529 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
530 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
531 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
532 	   .has_alpha = true, },
533 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
534 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
535 	  .has_alpha = true, },
536 	{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
537 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
538 	  .has_alpha = true, },
539 	{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
540 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
541 	{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
542 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
543 	{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
544 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
545 	  .has_alpha = true, },
546 	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
547 	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
548 	  .has_alpha = true, },
549 	{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
550 	  .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
551 };
552 
553 static const struct drm_format_info dcc_retile_formats[] = {
554 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
555 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
556 	 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
557 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
558 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
559 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
560 	   .has_alpha = true, },
561 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
562 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
563 	  .has_alpha = true, },
564 	{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
565 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
566 	  .has_alpha = true, },
567 	{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
568 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
569 	{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
570 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
571 	{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
572 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
573 	  .has_alpha = true, },
574 	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
575 	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
576 	  .has_alpha = true, },
577 	{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
578 	  .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
579 };
580 
581 static const struct drm_format_info *
582 lookup_format_info(const struct drm_format_info formats[],
583 		  int num_formats, u32 format)
584 {
585 	int i;
586 
587 	for (i = 0; i < num_formats; i++) {
588 		if (formats[i].format == format)
589 			return &formats[i];
590 	}
591 
592 	return NULL;
593 }
594 
595 const struct drm_format_info *
596 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
597 {
598 	if (!IS_AMD_FMT_MOD(modifier))
599 		return NULL;
600 
601 	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
602 		return lookup_format_info(dcc_retile_formats,
603 					  ARRAY_SIZE(dcc_retile_formats),
604 					  format);
605 
606 	if (AMD_FMT_MOD_GET(DCC, modifier))
607 		return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
608 					  format);
609 
610 	/* returning NULL will cause the default format structs to be used. */
611 	return NULL;
612 }
613 
614 
615 /*
616  * Tries to extract the renderable DCC offset from the opaque metadata attached
617  * to the buffer.
618  */
619 static int
620 extract_render_dcc_offset(struct amdgpu_device *adev,
621 			  struct drm_gem_object *obj,
622 			  uint64_t *offset)
623 {
624 	struct amdgpu_bo *rbo;
625 	int r = 0;
626 	uint32_t metadata[10]; /* Something that fits a descriptor + header. */
627 	uint32_t size;
628 
629 	rbo = gem_to_amdgpu_bo(obj);
630 	r = amdgpu_bo_reserve(rbo, false);
631 
632 	if (unlikely(r)) {
633 		/* Don't show error message when returning -ERESTARTSYS */
634 		if (r != -ERESTARTSYS)
635 			DRM_ERROR("Unable to reserve buffer: %d\n", r);
636 		return r;
637 	}
638 
639 	r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
640 	amdgpu_bo_unreserve(rbo);
641 
642 	if (r)
643 		return r;
644 
645 	/*
646 	 * The first word is the metadata version, and we need space for at least
647 	 * the version + pci vendor+device id + 8 words for a descriptor.
648 	 */
649 	if (size < 40  || metadata[0] != 1)
650 		return -EINVAL;
651 
652 	if (adev->family >= AMDGPU_FAMILY_NV) {
653 		/* resource word 6/7 META_DATA_ADDRESS{_LO} */
654 		*offset = ((u64)metadata[9] << 16u) |
655 			  ((metadata[8] & 0xFF000000u) >> 16);
656 	} else {
657 		/* resource word 5/7 META_DATA_ADDRESS */
658 		*offset = ((u64)metadata[9] << 8u) |
659 			  ((u64)(metadata[7] & 0x1FE0000u) << 23);
660 	}
661 
662 	return 0;
663 }
664 
665 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
666 {
667 	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
668 	uint64_t modifier = 0;
669 	int num_pipes = 0;
670 	int num_pkrs = 0;
671 
672 	num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
673 	num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
674 
675 	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
676 		modifier = DRM_FORMAT_MOD_LINEAR;
677 	} else {
678 		int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
679 		bool has_xor = swizzle >= 16;
680 		int block_size_bits;
681 		int version;
682 		int pipe_xor_bits = 0;
683 		int bank_xor_bits = 0;
684 		int packers = 0;
685 		int rb = 0;
686 		int pipes = ilog2(num_pipes);
687 		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
688 
689 		switch (swizzle >> 2) {
690 		case 0: /* 256B */
691 			block_size_bits = 8;
692 			break;
693 		case 1: /* 4KiB */
694 		case 5: /* 4KiB _X */
695 			block_size_bits = 12;
696 			break;
697 		case 2: /* 64KiB */
698 		case 4: /* 64 KiB _T */
699 		case 6: /* 64 KiB _X */
700 			block_size_bits = 16;
701 			break;
702 		case 7: /* 256 KiB */
703 			block_size_bits = 18;
704 			break;
705 		default:
706 			/* RESERVED or VAR */
707 			return -EINVAL;
708 		}
709 
710 		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
711 			version = AMD_FMT_MOD_TILE_VER_GFX11;
712 		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
713 			version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
714 		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
715 			version = AMD_FMT_MOD_TILE_VER_GFX10;
716 		else
717 			version = AMD_FMT_MOD_TILE_VER_GFX9;
718 
719 		switch (swizzle & 3) {
720 		case 0: /* Z microtiling */
721 			return -EINVAL;
722 		case 1: /* S microtiling */
723 			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
724 				if (!has_xor)
725 					version = AMD_FMT_MOD_TILE_VER_GFX9;
726 			}
727 			break;
728 		case 2:
729 			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
730 				if (!has_xor && afb->base.format->cpp[0] != 4)
731 					version = AMD_FMT_MOD_TILE_VER_GFX9;
732 			}
733 			break;
734 		case 3:
735 			break;
736 		}
737 
738 		if (has_xor) {
739 			if (num_pipes == num_pkrs && num_pkrs == 0) {
740 				DRM_ERROR("invalid number of pipes and packers\n");
741 				return -EINVAL;
742 			}
743 
744 			switch (version) {
745 			case AMD_FMT_MOD_TILE_VER_GFX11:
746 				pipe_xor_bits = min(block_size_bits - 8, pipes);
747 				packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
748 				break;
749 			case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
750 				pipe_xor_bits = min(block_size_bits - 8, pipes);
751 				packers = min(block_size_bits - 8 - pipe_xor_bits,
752 					      ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
753 				break;
754 			case AMD_FMT_MOD_TILE_VER_GFX10:
755 				pipe_xor_bits = min(block_size_bits - 8, pipes);
756 				break;
757 			case AMD_FMT_MOD_TILE_VER_GFX9:
758 				rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
759 				     ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
760 				pipe_xor_bits = min(block_size_bits - 8, pipes +
761 						    ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
762 				bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
763 						    ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
764 				break;
765 			}
766 		}
767 
768 		modifier = AMD_FMT_MOD |
769 			   AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
770 			   AMD_FMT_MOD_SET(TILE_VERSION, version) |
771 			   AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
772 			   AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
773 			   AMD_FMT_MOD_SET(PACKERS, packers);
774 
775 		if (dcc_offset != 0) {
776 			bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
777 			bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
778 			const struct drm_format_info *format_info;
779 			u64 render_dcc_offset;
780 
781 			/* Enable constant encode on RAVEN2 and later. */
782 			bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
783 						   (adev->asic_type == CHIP_RAVEN &&
784 						    adev->external_rev_id >= 0x81)) &&
785 						    adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
786 
787 			int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
788 					      dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
789 					      AMD_FMT_MOD_DCC_BLOCK_256B;
790 
791 			modifier |= AMD_FMT_MOD_SET(DCC, 1) |
792 				    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
793 				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
794 				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
795 				    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
796 
797 			afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
798 			afb->base.pitches[1] =
799 				AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
800 
801 			/*
802 			 * If the userspace driver uses retiling the tiling flags do not contain
803 			 * info on the renderable DCC buffer. Luckily the opaque metadata contains
804 			 * the info so we can try to extract it. The kernel does not use this info
805 			 * but we should convert it to a modifier plane for getfb2, so the
806 			 * userspace driver that gets it doesn't have to juggle around another DCC
807 			 * plane internally.
808 			 */
809 			if (extract_render_dcc_offset(adev, afb->base.obj[0],
810 						      &render_dcc_offset) == 0 &&
811 			    render_dcc_offset != 0 &&
812 			    render_dcc_offset != afb->base.offsets[1] &&
813 			    render_dcc_offset < UINT_MAX) {
814 				uint32_t dcc_block_bits;  /* of base surface data */
815 
816 				modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
817 				afb->base.offsets[2] = render_dcc_offset;
818 
819 				if (adev->family >= AMDGPU_FAMILY_NV) {
820 					int extra_pipe = 0;
821 
822 					if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
823 					    pipes == packers && pipes > 1)
824 						extra_pipe = 1;
825 
826 					dcc_block_bits = max(20, 16 + pipes + extra_pipe);
827 				} else {
828 					modifier |= AMD_FMT_MOD_SET(RB, rb) |
829 						    AMD_FMT_MOD_SET(PIPE, pipes);
830 					dcc_block_bits = max(20, 18 + rb);
831 				}
832 
833 				dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
834 				afb->base.pitches[2] = ALIGN(afb->base.width,
835 							     1u << ((dcc_block_bits + 1) / 2));
836 			}
837 			format_info = amdgpu_lookup_format_info(afb->base.format->format,
838 								modifier);
839 			if (!format_info)
840 				return -EINVAL;
841 
842 			afb->base.format = format_info;
843 		}
844 	}
845 
846 	afb->base.modifier = modifier;
847 	afb->base.flags |= DRM_MODE_FB_MODIFIERS;
848 	return 0;
849 }
850 
851 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
852 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
853 {
854 	u64 micro_tile_mode;
855 
856 	/* Zero swizzle mode means linear */
857 	if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
858 		return 0;
859 
860 	micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
861 	switch (micro_tile_mode) {
862 	case 0: /* DISPLAY */
863 	case 3: /* RENDER */
864 		return 0;
865 	default:
866 		drm_dbg_kms(afb->base.dev,
867 			    "Micro tile mode %llu not supported for scanout\n",
868 			    micro_tile_mode);
869 		return -EINVAL;
870 	}
871 }
872 
873 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
874 				 unsigned int *width, unsigned int *height)
875 {
876 	unsigned int cpp_log2 = ilog2(cpp);
877 	unsigned int pixel_log2 = block_log2 - cpp_log2;
878 	unsigned int width_log2 = (pixel_log2 + 1) / 2;
879 	unsigned int height_log2 = pixel_log2 - width_log2;
880 
881 	*width = 1 << width_log2;
882 	*height = 1 << height_log2;
883 }
884 
885 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
886 				       bool pipe_aligned)
887 {
888 	unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
889 
890 	switch (ver) {
891 	case AMD_FMT_MOD_TILE_VER_GFX9: {
892 		/*
893 		 * TODO: for pipe aligned we may need to check the alignment of the
894 		 * total size of the surface, which may need to be bigger than the
895 		 * natural alignment due to some HW workarounds
896 		 */
897 		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
898 	}
899 	case AMD_FMT_MOD_TILE_VER_GFX10:
900 	case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
901 	case AMD_FMT_MOD_TILE_VER_GFX11: {
902 		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
903 
904 		if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
905 		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
906 			++pipes_log2;
907 
908 		return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
909 	}
910 	default:
911 		return 0;
912 	}
913 }
914 
915 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
916 				       const struct drm_format_info *format,
917 				       unsigned int block_width, unsigned int block_height,
918 				       unsigned int block_size_log2)
919 {
920 	unsigned int width = rfb->base.width /
921 		((plane && plane < format->num_planes) ? format->hsub : 1);
922 	unsigned int height = rfb->base.height /
923 		((plane && plane < format->num_planes) ? format->vsub : 1);
924 	unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
925 	unsigned int block_pitch = block_width * cpp;
926 	unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
927 	unsigned int block_size = 1 << block_size_log2;
928 	uint64_t size;
929 
930 	if (rfb->base.pitches[plane] % block_pitch) {
931 		drm_dbg_kms(rfb->base.dev,
932 			    "pitch %d for plane %d is not a multiple of block pitch %d\n",
933 			    rfb->base.pitches[plane], plane, block_pitch);
934 		return -EINVAL;
935 	}
936 	if (rfb->base.pitches[plane] < min_pitch) {
937 		drm_dbg_kms(rfb->base.dev,
938 			    "pitch %d for plane %d is less than minimum pitch %d\n",
939 			    rfb->base.pitches[plane], plane, min_pitch);
940 		return -EINVAL;
941 	}
942 
943 	/* Force at least natural alignment. */
944 	if (rfb->base.offsets[plane] % block_size) {
945 		drm_dbg_kms(rfb->base.dev,
946 			    "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
947 			    rfb->base.offsets[plane], plane, block_size);
948 		return -EINVAL;
949 	}
950 
951 	size = rfb->base.offsets[plane] +
952 		(uint64_t)rfb->base.pitches[plane] / block_pitch *
953 		block_size * DIV_ROUND_UP(height, block_height);
954 
955 	if (rfb->base.obj[0]->size < size) {
956 		drm_dbg_kms(rfb->base.dev,
957 			    "BO size 0x%zx is less than 0x%llx required for plane %d\n",
958 			    rfb->base.obj[0]->size, size, plane);
959 		return -EINVAL;
960 	}
961 
962 	return 0;
963 }
964 
965 
966 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
967 {
968 	const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
969 	uint64_t modifier = rfb->base.modifier;
970 	int ret;
971 	unsigned int i, block_width, block_height, block_size_log2;
972 
973 	if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
974 		return 0;
975 
976 	for (i = 0; i < format_info->num_planes; ++i) {
977 		if (modifier == DRM_FORMAT_MOD_LINEAR) {
978 			block_width = 256 / format_info->cpp[i];
979 			block_height = 1;
980 			block_size_log2 = 8;
981 		} else {
982 			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
983 
984 			switch ((swizzle & ~3) + 1) {
985 			case DC_SW_256B_S:
986 				block_size_log2 = 8;
987 				break;
988 			case DC_SW_4KB_S:
989 			case DC_SW_4KB_S_X:
990 				block_size_log2 = 12;
991 				break;
992 			case DC_SW_64KB_S:
993 			case DC_SW_64KB_S_T:
994 			case DC_SW_64KB_S_X:
995 				block_size_log2 = 16;
996 				break;
997 			case DC_SW_VAR_S_X:
998 				block_size_log2 = 18;
999 				break;
1000 			default:
1001 				drm_dbg_kms(rfb->base.dev,
1002 					    "Swizzle mode with unknown block size: %d\n", swizzle);
1003 				return -EINVAL;
1004 			}
1005 
1006 			get_block_dimensions(block_size_log2, format_info->cpp[i],
1007 					     &block_width, &block_height);
1008 		}
1009 
1010 		ret = amdgpu_display_verify_plane(rfb, i, format_info,
1011 						  block_width, block_height, block_size_log2);
1012 		if (ret)
1013 			return ret;
1014 	}
1015 
1016 	if (AMD_FMT_MOD_GET(DCC, modifier)) {
1017 		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1018 			block_size_log2 = get_dcc_block_size(modifier, false, false);
1019 			get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1020 					     &block_width, &block_height);
1021 			ret = amdgpu_display_verify_plane(rfb, i, format_info,
1022 							  block_width, block_height,
1023 							  block_size_log2);
1024 			if (ret)
1025 				return ret;
1026 
1027 			++i;
1028 			block_size_log2 = get_dcc_block_size(modifier, true, true);
1029 		} else {
1030 			bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1031 
1032 			block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1033 		}
1034 		get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1035 				     &block_width, &block_height);
1036 		ret = amdgpu_display_verify_plane(rfb, i, format_info,
1037 						  block_width, block_height, block_size_log2);
1038 		if (ret)
1039 			return ret;
1040 	}
1041 
1042 	return 0;
1043 }
1044 
1045 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1046 				      uint64_t *tiling_flags, bool *tmz_surface)
1047 {
1048 	struct amdgpu_bo *rbo;
1049 	int r;
1050 
1051 	if (!amdgpu_fb) {
1052 		*tiling_flags = 0;
1053 		*tmz_surface = false;
1054 		return 0;
1055 	}
1056 
1057 	rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1058 	r = amdgpu_bo_reserve(rbo, false);
1059 
1060 	if (unlikely(r)) {
1061 		/* Don't show error message when returning -ERESTARTSYS */
1062 		if (r != -ERESTARTSYS)
1063 			DRM_ERROR("Unable to reserve buffer: %d\n", r);
1064 		return r;
1065 	}
1066 
1067 	if (tiling_flags)
1068 		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1069 
1070 	if (tmz_surface)
1071 		*tmz_surface = amdgpu_bo_encrypted(rbo);
1072 
1073 	amdgpu_bo_unreserve(rbo);
1074 
1075 	return r;
1076 }
1077 
1078 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1079 						 struct amdgpu_framebuffer *rfb,
1080 						 struct drm_file *file_priv,
1081 						 const struct drm_mode_fb_cmd2 *mode_cmd,
1082 						 struct drm_gem_object *obj)
1083 {
1084 	int ret;
1085 
1086 	rfb->base.obj[0] = obj;
1087 	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1088 	/* Verify that the modifier is supported. */
1089 	if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1090 				      mode_cmd->modifier[0])) {
1091 		drm_dbg_kms(dev,
1092 			    "unsupported pixel format %p4cc / modifier 0x%llx\n",
1093 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1094 
1095 		ret = -EINVAL;
1096 		goto err;
1097 	}
1098 
1099 	ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1100 	if (ret)
1101 		goto err;
1102 
1103 	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1104 	if (ret)
1105 		goto err;
1106 
1107 	return 0;
1108 err:
1109 	drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1110 	rfb->base.obj[0] = NULL;
1111 	return ret;
1112 }
1113 
1114 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1115 					   struct amdgpu_framebuffer *rfb,
1116 					   const struct drm_mode_fb_cmd2 *mode_cmd,
1117 					   struct drm_gem_object *obj)
1118 {
1119 	struct amdgpu_device *adev = drm_to_adev(dev);
1120 	int ret, i;
1121 
1122 	/*
1123 	 * This needs to happen before modifier conversion as that might change
1124 	 * the number of planes.
1125 	 */
1126 	for (i = 1; i < rfb->base.format->num_planes; ++i) {
1127 		if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1128 			drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1129 				    i, mode_cmd->handles[0], mode_cmd->handles[i]);
1130 			ret = -EINVAL;
1131 			return ret;
1132 		}
1133 	}
1134 
1135 	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1136 	if (ret)
1137 		return ret;
1138 
1139 	if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1140 		drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1141 			      "GFX9+ requires FB check based on format modifier\n");
1142 		ret = check_tiling_flags_gfx6(rfb);
1143 		if (ret)
1144 			return ret;
1145 	}
1146 
1147 	if (!dev->mode_config.fb_modifiers_not_supported &&
1148 	    !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1149 		ret = convert_tiling_flags_to_modifier(rfb);
1150 		if (ret) {
1151 			drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1152 				    rfb->tiling_flags);
1153 			return ret;
1154 		}
1155 	}
1156 
1157 	ret = amdgpu_display_verify_sizes(rfb);
1158 	if (ret)
1159 		return ret;
1160 
1161 	for (i = 0; i < rfb->base.format->num_planes; ++i) {
1162 		drm_gem_object_get(rfb->base.obj[0]);
1163 		rfb->base.obj[i] = rfb->base.obj[0];
1164 	}
1165 
1166 	return 0;
1167 }
1168 
1169 struct drm_framebuffer *
1170 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1171 				       struct drm_file *file_priv,
1172 				       const struct drm_mode_fb_cmd2 *mode_cmd)
1173 {
1174 	struct amdgpu_framebuffer *amdgpu_fb;
1175 	struct drm_gem_object *obj;
1176 	struct amdgpu_bo *bo;
1177 	uint32_t domains;
1178 	int ret;
1179 
1180 	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1181 	if (obj ==  NULL) {
1182 		drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1183 			    "can't create framebuffer\n", mode_cmd->handles[0]);
1184 		return ERR_PTR(-ENOENT);
1185 	}
1186 
1187 	/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1188 	bo = gem_to_amdgpu_bo(obj);
1189 	domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1190 	if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1191 		drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1192 		drm_gem_object_put(obj);
1193 		return ERR_PTR(-EINVAL);
1194 	}
1195 
1196 	amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1197 	if (amdgpu_fb == NULL) {
1198 		drm_gem_object_put(obj);
1199 		return ERR_PTR(-ENOMEM);
1200 	}
1201 
1202 	ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1203 						    mode_cmd, obj);
1204 	if (ret) {
1205 		kfree(amdgpu_fb);
1206 		drm_gem_object_put(obj);
1207 		return ERR_PTR(ret);
1208 	}
1209 
1210 	drm_gem_object_put(obj);
1211 	return &amdgpu_fb->base;
1212 }
1213 
1214 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1215 	.fb_create = amdgpu_display_user_framebuffer_create,
1216 	.output_poll_changed = drm_fb_helper_output_poll_changed,
1217 };
1218 
1219 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1220 {	{ UNDERSCAN_OFF, "off" },
1221 	{ UNDERSCAN_ON, "on" },
1222 	{ UNDERSCAN_AUTO, "auto" },
1223 };
1224 
1225 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1226 {	{ AMDGPU_AUDIO_DISABLE, "off" },
1227 	{ AMDGPU_AUDIO_ENABLE, "on" },
1228 	{ AMDGPU_AUDIO_AUTO, "auto" },
1229 };
1230 
1231 /* XXX support different dither options? spatial, temporal, both, etc. */
1232 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1233 {	{ AMDGPU_FMT_DITHER_DISABLE, "off" },
1234 	{ AMDGPU_FMT_DITHER_ENABLE, "on" },
1235 };
1236 
1237 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1238 {
1239 	int sz;
1240 
1241 	adev->mode_info.coherent_mode_property =
1242 		drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1243 	if (!adev->mode_info.coherent_mode_property)
1244 		return -ENOMEM;
1245 
1246 	adev->mode_info.load_detect_property =
1247 		drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1248 	if (!adev->mode_info.load_detect_property)
1249 		return -ENOMEM;
1250 
1251 	drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1252 
1253 	sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1254 	adev->mode_info.underscan_property =
1255 		drm_property_create_enum(adev_to_drm(adev), 0,
1256 					 "underscan",
1257 					 amdgpu_underscan_enum_list, sz);
1258 
1259 	adev->mode_info.underscan_hborder_property =
1260 		drm_property_create_range(adev_to_drm(adev), 0,
1261 					  "underscan hborder", 0, 128);
1262 	if (!adev->mode_info.underscan_hborder_property)
1263 		return -ENOMEM;
1264 
1265 	adev->mode_info.underscan_vborder_property =
1266 		drm_property_create_range(adev_to_drm(adev), 0,
1267 					  "underscan vborder", 0, 128);
1268 	if (!adev->mode_info.underscan_vborder_property)
1269 		return -ENOMEM;
1270 
1271 	sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1272 	adev->mode_info.audio_property =
1273 		drm_property_create_enum(adev_to_drm(adev), 0,
1274 					 "audio",
1275 					 amdgpu_audio_enum_list, sz);
1276 
1277 	sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1278 	adev->mode_info.dither_property =
1279 		drm_property_create_enum(adev_to_drm(adev), 0,
1280 					 "dither",
1281 					 amdgpu_dither_enum_list, sz);
1282 
1283 	if (amdgpu_device_has_dc_support(adev)) {
1284 		adev->mode_info.abm_level_property =
1285 			drm_property_create_range(adev_to_drm(adev), 0,
1286 						  "abm level", 0, 4);
1287 		if (!adev->mode_info.abm_level_property)
1288 			return -ENOMEM;
1289 	}
1290 
1291 	return 0;
1292 }
1293 
1294 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1295 {
1296 	/* adjustment options for the display watermarks */
1297 	if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1298 		adev->mode_info.disp_priority = 0;
1299 	else
1300 		adev->mode_info.disp_priority = amdgpu_disp_priority;
1301 
1302 }
1303 
1304 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1305 {
1306 	/* try and guess if this is a tv or a monitor */
1307 	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1308 	    (mode->vdisplay == 576) || /* 576p */
1309 	    (mode->vdisplay == 720) || /* 720p */
1310 	    (mode->vdisplay == 1080)) /* 1080p */
1311 		return true;
1312 	else
1313 		return false;
1314 }
1315 
1316 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1317 					const struct drm_display_mode *mode,
1318 					struct drm_display_mode *adjusted_mode)
1319 {
1320 	struct drm_device *dev = crtc->dev;
1321 	struct drm_encoder *encoder;
1322 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1323 	struct amdgpu_encoder *amdgpu_encoder;
1324 	struct drm_connector *connector;
1325 	u32 src_v = 1, dst_v = 1;
1326 	u32 src_h = 1, dst_h = 1;
1327 
1328 	amdgpu_crtc->h_border = 0;
1329 	amdgpu_crtc->v_border = 0;
1330 
1331 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1332 		if (encoder->crtc != crtc)
1333 			continue;
1334 		amdgpu_encoder = to_amdgpu_encoder(encoder);
1335 		connector = amdgpu_get_connector_for_encoder(encoder);
1336 
1337 		/* set scaling */
1338 		if (amdgpu_encoder->rmx_type == RMX_OFF)
1339 			amdgpu_crtc->rmx_type = RMX_OFF;
1340 		else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1341 			 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1342 			amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1343 		else
1344 			amdgpu_crtc->rmx_type = RMX_OFF;
1345 		/* copy native mode */
1346 		memcpy(&amdgpu_crtc->native_mode,
1347 		       &amdgpu_encoder->native_mode,
1348 		       sizeof(struct drm_display_mode));
1349 		src_v = crtc->mode.vdisplay;
1350 		dst_v = amdgpu_crtc->native_mode.vdisplay;
1351 		src_h = crtc->mode.hdisplay;
1352 		dst_h = amdgpu_crtc->native_mode.hdisplay;
1353 
1354 		/* fix up for overscan on hdmi */
1355 		if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1356 		    ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1357 		     ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1358 		      connector->display_info.is_hdmi &&
1359 		      amdgpu_display_is_hdtv_mode(mode)))) {
1360 			if (amdgpu_encoder->underscan_hborder != 0)
1361 				amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1362 			else
1363 				amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1364 			if (amdgpu_encoder->underscan_vborder != 0)
1365 				amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1366 			else
1367 				amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1368 			amdgpu_crtc->rmx_type = RMX_FULL;
1369 			src_v = crtc->mode.vdisplay;
1370 			dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1371 			src_h = crtc->mode.hdisplay;
1372 			dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1373 		}
1374 	}
1375 	if (amdgpu_crtc->rmx_type != RMX_OFF) {
1376 		fixed20_12 a, b;
1377 		a.full = dfixed_const(src_v);
1378 		b.full = dfixed_const(dst_v);
1379 		amdgpu_crtc->vsc.full = dfixed_div(a, b);
1380 		a.full = dfixed_const(src_h);
1381 		b.full = dfixed_const(dst_h);
1382 		amdgpu_crtc->hsc.full = dfixed_div(a, b);
1383 	} else {
1384 		amdgpu_crtc->vsc.full = dfixed_const(1);
1385 		amdgpu_crtc->hsc.full = dfixed_const(1);
1386 	}
1387 	return true;
1388 }
1389 
1390 /*
1391  * Retrieve current video scanout position of crtc on a given gpu, and
1392  * an optional accurate timestamp of when query happened.
1393  *
1394  * \param dev Device to query.
1395  * \param pipe Crtc to query.
1396  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1397  *              For driver internal use only also supports these flags:
1398  *
1399  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1400  *              of a fudged earlier start of vblank.
1401  *
1402  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1403  *              fudged earlier start of vblank in *vpos and the distance
1404  *              to true start of vblank in *hpos.
1405  *
1406  * \param *vpos Location where vertical scanout position should be stored.
1407  * \param *hpos Location where horizontal scanout position should go.
1408  * \param *stime Target location for timestamp taken immediately before
1409  *               scanout position query. Can be NULL to skip timestamp.
1410  * \param *etime Target location for timestamp taken immediately after
1411  *               scanout position query. Can be NULL to skip timestamp.
1412  *
1413  * Returns vpos as a positive number while in active scanout area.
1414  * Returns vpos as a negative number inside vblank, counting the number
1415  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1416  * until start of active scanout / end of vblank."
1417  *
1418  * \return Flags, or'ed together as follows:
1419  *
1420  * DRM_SCANOUTPOS_VALID = Query successful.
1421  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1422  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1423  * this flag means that returned position may be offset by a constant but
1424  * unknown small number of scanlines wrt. real scanout position.
1425  *
1426  */
1427 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1428 			unsigned int pipe, unsigned int flags, int *vpos,
1429 			int *hpos, ktime_t *stime, ktime_t *etime,
1430 			const struct drm_display_mode *mode)
1431 {
1432 	u32 vbl = 0, position = 0;
1433 	int vbl_start, vbl_end, vtotal, ret = 0;
1434 	bool in_vbl = true;
1435 
1436 	struct amdgpu_device *adev = drm_to_adev(dev);
1437 
1438 	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1439 
1440 	/* Get optional system timestamp before query. */
1441 	if (stime)
1442 		*stime = ktime_get();
1443 
1444 	if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1445 		ret |= DRM_SCANOUTPOS_VALID;
1446 
1447 	/* Get optional system timestamp after query. */
1448 	if (etime)
1449 		*etime = ktime_get();
1450 
1451 	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1452 
1453 	/* Decode into vertical and horizontal scanout position. */
1454 	*vpos = position & 0x1fff;
1455 	*hpos = (position >> 16) & 0x1fff;
1456 
1457 	/* Valid vblank area boundaries from gpu retrieved? */
1458 	if (vbl > 0) {
1459 		/* Yes: Decode. */
1460 		ret |= DRM_SCANOUTPOS_ACCURATE;
1461 		vbl_start = vbl & 0x1fff;
1462 		vbl_end = (vbl >> 16) & 0x1fff;
1463 	}
1464 	else {
1465 		/* No: Fake something reasonable which gives at least ok results. */
1466 		vbl_start = mode->crtc_vdisplay;
1467 		vbl_end = 0;
1468 	}
1469 
1470 	/* Called from driver internal vblank counter query code? */
1471 	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1472 	    /* Caller wants distance from real vbl_start in *hpos */
1473 	    *hpos = *vpos - vbl_start;
1474 	}
1475 
1476 	/* Fudge vblank to start a few scanlines earlier to handle the
1477 	 * problem that vblank irqs fire a few scanlines before start
1478 	 * of vblank. Some driver internal callers need the true vblank
1479 	 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1480 	 *
1481 	 * The cause of the "early" vblank irq is that the irq is triggered
1482 	 * by the line buffer logic when the line buffer read position enters
1483 	 * the vblank, whereas our crtc scanout position naturally lags the
1484 	 * line buffer read position.
1485 	 */
1486 	if (!(flags & USE_REAL_VBLANKSTART))
1487 		vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1488 
1489 	/* Test scanout position against vblank region. */
1490 	if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1491 		in_vbl = false;
1492 
1493 	/* In vblank? */
1494 	if (in_vbl)
1495 	    ret |= DRM_SCANOUTPOS_IN_VBLANK;
1496 
1497 	/* Called from driver internal vblank counter query code? */
1498 	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1499 		/* Caller wants distance from fudged earlier vbl_start */
1500 		*vpos -= vbl_start;
1501 		return ret;
1502 	}
1503 
1504 	/* Check if inside vblank area and apply corrective offsets:
1505 	 * vpos will then be >=0 in video scanout area, but negative
1506 	 * within vblank area, counting down the number of lines until
1507 	 * start of scanout.
1508 	 */
1509 
1510 	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
1511 	if (in_vbl && (*vpos >= vbl_start)) {
1512 		vtotal = mode->crtc_vtotal;
1513 
1514 		/* With variable refresh rate displays the vpos can exceed
1515 		 * the vtotal value. Clamp to 0 to return -vbl_end instead
1516 		 * of guessing the remaining number of lines until scanout.
1517 		 */
1518 		*vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1519 	}
1520 
1521 	/* Correct for shifted end of vbl at vbl_end. */
1522 	*vpos = *vpos - vbl_end;
1523 
1524 	return ret;
1525 }
1526 
1527 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1528 {
1529 	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1530 		return AMDGPU_CRTC_IRQ_NONE;
1531 
1532 	switch (crtc) {
1533 	case 0:
1534 		return AMDGPU_CRTC_IRQ_VBLANK1;
1535 	case 1:
1536 		return AMDGPU_CRTC_IRQ_VBLANK2;
1537 	case 2:
1538 		return AMDGPU_CRTC_IRQ_VBLANK3;
1539 	case 3:
1540 		return AMDGPU_CRTC_IRQ_VBLANK4;
1541 	case 4:
1542 		return AMDGPU_CRTC_IRQ_VBLANK5;
1543 	case 5:
1544 		return AMDGPU_CRTC_IRQ_VBLANK6;
1545 	default:
1546 		return AMDGPU_CRTC_IRQ_NONE;
1547 	}
1548 }
1549 
1550 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1551 			bool in_vblank_irq, int *vpos,
1552 			int *hpos, ktime_t *stime, ktime_t *etime,
1553 			const struct drm_display_mode *mode)
1554 {
1555 	struct drm_device *dev = crtc->dev;
1556 	unsigned int pipe = crtc->index;
1557 
1558 	return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1559 						  stime, etime, mode);
1560 }
1561 
1562 static bool
1563 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1564 {
1565 	struct drm_device *dev = adev_to_drm(adev);
1566 	struct drm_fb_helper *fb_helper = dev->fb_helper;
1567 
1568 	if (!fb_helper || !fb_helper->buffer)
1569 		return false;
1570 
1571 	if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1572 		return false;
1573 
1574 	return true;
1575 }
1576 
1577 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1578 {
1579 	struct drm_device *dev = adev_to_drm(adev);
1580 	struct drm_crtc *crtc;
1581 	struct drm_connector *connector;
1582 	struct drm_connector_list_iter iter;
1583 	int r;
1584 
1585 	/* turn off display hw */
1586 	drm_modeset_lock_all(dev);
1587 	drm_connector_list_iter_begin(dev, &iter);
1588 	drm_for_each_connector_iter(connector, &iter)
1589 		drm_helper_connector_dpms(connector,
1590 					  DRM_MODE_DPMS_OFF);
1591 	drm_connector_list_iter_end(&iter);
1592 	drm_modeset_unlock_all(dev);
1593 	/* unpin the front buffers and cursors */
1594 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1595 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1596 		struct drm_framebuffer *fb = crtc->primary->fb;
1597 		struct amdgpu_bo *robj;
1598 
1599 		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1600 			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1601 			r = amdgpu_bo_reserve(aobj, true);
1602 			if (r == 0) {
1603 				amdgpu_bo_unpin(aobj);
1604 				amdgpu_bo_unreserve(aobj);
1605 			}
1606 		}
1607 
1608 		if (fb == NULL || fb->obj[0] == NULL) {
1609 			continue;
1610 		}
1611 		robj = gem_to_amdgpu_bo(fb->obj[0]);
1612 		if (!amdgpu_display_robj_is_fb(adev, robj)) {
1613 			r = amdgpu_bo_reserve(robj, true);
1614 			if (r == 0) {
1615 				amdgpu_bo_unpin(robj);
1616 				amdgpu_bo_unreserve(robj);
1617 			}
1618 		}
1619 	}
1620 	return 0;
1621 }
1622 
1623 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1624 {
1625 	struct drm_device *dev = adev_to_drm(adev);
1626 	struct drm_connector *connector;
1627 	struct drm_connector_list_iter iter;
1628 	struct drm_crtc *crtc;
1629 	int r;
1630 
1631 	/* pin cursors */
1632 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1633 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1634 
1635 		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1636 			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1637 			r = amdgpu_bo_reserve(aobj, true);
1638 			if (r == 0) {
1639 				r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1640 				if (r != 0)
1641 					dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1642 				amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1643 				amdgpu_bo_unreserve(aobj);
1644 			}
1645 		}
1646 	}
1647 
1648 	drm_helper_resume_force_mode(dev);
1649 
1650 	/* turn on display hw */
1651 	drm_modeset_lock_all(dev);
1652 
1653 	drm_connector_list_iter_begin(dev, &iter);
1654 	drm_for_each_connector_iter(connector, &iter)
1655 		drm_helper_connector_dpms(connector,
1656 					  DRM_MODE_DPMS_ON);
1657 	drm_connector_list_iter_end(&iter);
1658 
1659 	drm_modeset_unlock_all(dev);
1660 
1661 	return 0;
1662 }
1663 
1664