1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_runtime.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_vblank.h> 43 44 static void amdgpu_display_flip_callback(struct dma_fence *f, 45 struct dma_fence_cb *cb) 46 { 47 struct amdgpu_flip_work *work = 48 container_of(cb, struct amdgpu_flip_work, cb); 49 50 dma_fence_put(f); 51 schedule_work(&work->flip_work.work); 52 } 53 54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 55 struct dma_fence **f) 56 { 57 struct dma_fence *fence= *f; 58 59 if (fence == NULL) 60 return false; 61 62 *f = NULL; 63 64 if (!dma_fence_add_callback(fence, &work->cb, 65 amdgpu_display_flip_callback)) 66 return true; 67 68 dma_fence_put(fence); 69 return false; 70 } 71 72 static void amdgpu_display_flip_work_func(struct work_struct *__work) 73 { 74 struct delayed_work *delayed_work = 75 container_of(__work, struct delayed_work, work); 76 struct amdgpu_flip_work *work = 77 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 78 struct amdgpu_device *adev = work->adev; 79 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 80 81 struct drm_crtc *crtc = &amdgpu_crtc->base; 82 unsigned long flags; 83 unsigned i; 84 int vpos, hpos; 85 86 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 87 return; 88 89 for (i = 0; i < work->shared_count; ++i) 90 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 91 return; 92 93 /* Wait until we're out of the vertical blank period before the one 94 * targeted by the flip 95 */ 96 if (amdgpu_crtc->enabled && 97 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 98 &vpos, &hpos, NULL, NULL, 99 &crtc->hwmode) 100 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 101 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 102 (int)(work->target_vblank - 103 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 104 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 105 return; 106 } 107 108 /* We borrow the event spin lock for protecting flip_status */ 109 spin_lock_irqsave(&crtc->dev->event_lock, flags); 110 111 /* Do the flip (mmio) */ 112 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 113 114 /* Set the flip status */ 115 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 116 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 117 118 119 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 120 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 121 122 } 123 124 /* 125 * Handle unpin events outside the interrupt handler proper. 126 */ 127 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 128 { 129 struct amdgpu_flip_work *work = 130 container_of(__work, struct amdgpu_flip_work, unpin_work); 131 int r; 132 133 /* unpin of the old buffer */ 134 r = amdgpu_bo_reserve(work->old_abo, true); 135 if (likely(r == 0)) { 136 amdgpu_bo_unpin(work->old_abo); 137 amdgpu_bo_unreserve(work->old_abo); 138 } else 139 DRM_ERROR("failed to reserve buffer after flip\n"); 140 141 amdgpu_bo_unref(&work->old_abo); 142 kfree(work->shared); 143 kfree(work); 144 } 145 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 147 struct drm_framebuffer *fb, 148 struct drm_pending_vblank_event *event, 149 uint32_t page_flip_flags, uint32_t target, 150 struct drm_modeset_acquire_ctx *ctx) 151 { 152 struct drm_device *dev = crtc->dev; 153 struct amdgpu_device *adev = drm_to_adev(dev); 154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 155 struct drm_gem_object *obj; 156 struct amdgpu_flip_work *work; 157 struct amdgpu_bo *new_abo; 158 unsigned long flags; 159 u64 tiling_flags; 160 int i, r; 161 162 work = kzalloc(sizeof *work, GFP_KERNEL); 163 if (work == NULL) 164 return -ENOMEM; 165 166 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 167 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 168 169 work->event = event; 170 work->adev = adev; 171 work->crtc_id = amdgpu_crtc->crtc_id; 172 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 173 174 /* schedule unpin of the old buffer */ 175 obj = crtc->primary->fb->obj[0]; 176 177 /* take a reference to the old object */ 178 work->old_abo = gem_to_amdgpu_bo(obj); 179 amdgpu_bo_ref(work->old_abo); 180 181 obj = fb->obj[0]; 182 new_abo = gem_to_amdgpu_bo(obj); 183 184 /* pin the new buffer */ 185 r = amdgpu_bo_reserve(new_abo, false); 186 if (unlikely(r != 0)) { 187 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 188 goto cleanup; 189 } 190 191 if (!adev->enable_virtual_display) { 192 r = amdgpu_bo_pin(new_abo, 193 amdgpu_display_supported_domains(adev, new_abo->flags)); 194 if (unlikely(r != 0)) { 195 DRM_ERROR("failed to pin new abo buffer before flip\n"); 196 goto unreserve; 197 } 198 } 199 200 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 201 if (unlikely(r != 0)) { 202 DRM_ERROR("%p bind failed\n", new_abo); 203 goto unpin; 204 } 205 206 r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, 207 &work->shared_count, 208 &work->shared); 209 if (unlikely(r != 0)) { 210 DRM_ERROR("failed to get fences for buffer\n"); 211 goto unpin; 212 } 213 214 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 215 amdgpu_bo_unreserve(new_abo); 216 217 if (!adev->enable_virtual_display) 218 work->base = amdgpu_bo_gpu_offset(new_abo); 219 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 220 amdgpu_get_vblank_counter_kms(crtc); 221 222 /* we borrow the event spin lock for protecting flip_wrok */ 223 spin_lock_irqsave(&crtc->dev->event_lock, flags); 224 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 225 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 226 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 227 r = -EBUSY; 228 goto pflip_cleanup; 229 } 230 231 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 232 amdgpu_crtc->pflip_works = work; 233 234 235 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 236 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 237 /* update crtc fb */ 238 crtc->primary->fb = fb; 239 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 240 amdgpu_display_flip_work_func(&work->flip_work.work); 241 return 0; 242 243 pflip_cleanup: 244 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 245 DRM_ERROR("failed to reserve new abo in error path\n"); 246 goto cleanup; 247 } 248 unpin: 249 if (!adev->enable_virtual_display) 250 amdgpu_bo_unpin(new_abo); 251 252 unreserve: 253 amdgpu_bo_unreserve(new_abo); 254 255 cleanup: 256 amdgpu_bo_unref(&work->old_abo); 257 dma_fence_put(work->excl); 258 for (i = 0; i < work->shared_count; ++i) 259 dma_fence_put(work->shared[i]); 260 kfree(work->shared); 261 kfree(work); 262 263 return r; 264 } 265 266 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 267 struct drm_modeset_acquire_ctx *ctx) 268 { 269 struct drm_device *dev; 270 struct amdgpu_device *adev; 271 struct drm_crtc *crtc; 272 bool active = false; 273 int ret; 274 275 if (!set || !set->crtc) 276 return -EINVAL; 277 278 dev = set->crtc->dev; 279 280 ret = pm_runtime_get_sync(dev->dev); 281 if (ret < 0) 282 goto out; 283 284 ret = drm_crtc_helper_set_config(set, ctx); 285 286 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 287 if (crtc->enabled) 288 active = true; 289 290 pm_runtime_mark_last_busy(dev->dev); 291 292 adev = drm_to_adev(dev); 293 /* if we have active crtcs and we don't have a power ref, 294 take the current one */ 295 if (active && !adev->have_disp_power_ref) { 296 adev->have_disp_power_ref = true; 297 return ret; 298 } 299 /* if we have no active crtcs, then drop the power ref 300 we got before */ 301 if (!active && adev->have_disp_power_ref) { 302 pm_runtime_put_autosuspend(dev->dev); 303 adev->have_disp_power_ref = false; 304 } 305 306 out: 307 /* drop the power reference we got coming in here */ 308 pm_runtime_put_autosuspend(dev->dev); 309 return ret; 310 } 311 312 static const char *encoder_names[41] = { 313 "NONE", 314 "INTERNAL_LVDS", 315 "INTERNAL_TMDS1", 316 "INTERNAL_TMDS2", 317 "INTERNAL_DAC1", 318 "INTERNAL_DAC2", 319 "INTERNAL_SDVOA", 320 "INTERNAL_SDVOB", 321 "SI170B", 322 "CH7303", 323 "CH7301", 324 "INTERNAL_DVO1", 325 "EXTERNAL_SDVOA", 326 "EXTERNAL_SDVOB", 327 "TITFP513", 328 "INTERNAL_LVTM1", 329 "VT1623", 330 "HDMI_SI1930", 331 "HDMI_INTERNAL", 332 "INTERNAL_KLDSCP_TMDS1", 333 "INTERNAL_KLDSCP_DVO1", 334 "INTERNAL_KLDSCP_DAC1", 335 "INTERNAL_KLDSCP_DAC2", 336 "SI178", 337 "MVPU_FPGA", 338 "INTERNAL_DDI", 339 "VT1625", 340 "HDMI_SI1932", 341 "DP_AN9801", 342 "DP_DP501", 343 "INTERNAL_UNIPHY", 344 "INTERNAL_KLDSCP_LVTMA", 345 "INTERNAL_UNIPHY1", 346 "INTERNAL_UNIPHY2", 347 "NUTMEG", 348 "TRAVIS", 349 "INTERNAL_VCE", 350 "INTERNAL_UNIPHY3", 351 "HDMI_ANX9805", 352 "INTERNAL_AMCLK", 353 "VIRTUAL", 354 }; 355 356 static const char *hpd_names[6] = { 357 "HPD1", 358 "HPD2", 359 "HPD3", 360 "HPD4", 361 "HPD5", 362 "HPD6", 363 }; 364 365 void amdgpu_display_print_display_setup(struct drm_device *dev) 366 { 367 struct drm_connector *connector; 368 struct amdgpu_connector *amdgpu_connector; 369 struct drm_encoder *encoder; 370 struct amdgpu_encoder *amdgpu_encoder; 371 struct drm_connector_list_iter iter; 372 uint32_t devices; 373 int i = 0; 374 375 drm_connector_list_iter_begin(dev, &iter); 376 DRM_INFO("AMDGPU Display Connectors\n"); 377 drm_for_each_connector_iter(connector, &iter) { 378 amdgpu_connector = to_amdgpu_connector(connector); 379 DRM_INFO("Connector %d:\n", i); 380 DRM_INFO(" %s\n", connector->name); 381 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 382 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 383 if (amdgpu_connector->ddc_bus) { 384 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 385 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 386 amdgpu_connector->ddc_bus->rec.mask_data_reg, 387 amdgpu_connector->ddc_bus->rec.a_clk_reg, 388 amdgpu_connector->ddc_bus->rec.a_data_reg, 389 amdgpu_connector->ddc_bus->rec.en_clk_reg, 390 amdgpu_connector->ddc_bus->rec.en_data_reg, 391 amdgpu_connector->ddc_bus->rec.y_clk_reg, 392 amdgpu_connector->ddc_bus->rec.y_data_reg); 393 if (amdgpu_connector->router.ddc_valid) 394 DRM_INFO(" DDC Router 0x%x/0x%x\n", 395 amdgpu_connector->router.ddc_mux_control_pin, 396 amdgpu_connector->router.ddc_mux_state); 397 if (amdgpu_connector->router.cd_valid) 398 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 399 amdgpu_connector->router.cd_mux_control_pin, 400 amdgpu_connector->router.cd_mux_state); 401 } else { 402 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 403 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 404 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 405 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 406 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 407 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 408 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 409 } 410 DRM_INFO(" Encoders:\n"); 411 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 412 amdgpu_encoder = to_amdgpu_encoder(encoder); 413 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 414 if (devices) { 415 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 416 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 417 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 418 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 419 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 420 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 421 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 422 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 423 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 424 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 425 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 426 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 427 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 428 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 429 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 430 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 431 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 432 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 433 if (devices & ATOM_DEVICE_TV1_SUPPORT) 434 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 435 if (devices & ATOM_DEVICE_CV_SUPPORT) 436 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 437 } 438 } 439 i++; 440 } 441 drm_connector_list_iter_end(&iter); 442 } 443 444 /** 445 * amdgpu_display_ddc_probe 446 * 447 */ 448 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 449 bool use_aux) 450 { 451 u8 out = 0x0; 452 u8 buf[8]; 453 int ret; 454 struct i2c_msg msgs[] = { 455 { 456 .addr = DDC_ADDR, 457 .flags = 0, 458 .len = 1, 459 .buf = &out, 460 }, 461 { 462 .addr = DDC_ADDR, 463 .flags = I2C_M_RD, 464 .len = 8, 465 .buf = buf, 466 } 467 }; 468 469 /* on hw with routers, select right port */ 470 if (amdgpu_connector->router.ddc_valid) 471 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 472 473 if (use_aux) { 474 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 475 } else { 476 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 477 } 478 479 if (ret != 2) 480 /* Couldn't find an accessible DDC on this connector */ 481 return false; 482 /* Probe also for valid EDID header 483 * EDID header starts with: 484 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 485 * Only the first 6 bytes must be valid as 486 * drm_edid_block_valid() can fix the last 2 bytes */ 487 if (drm_edid_header_is_valid(buf) < 6) { 488 /* Couldn't find an accessible EDID on this 489 * connector */ 490 return false; 491 } 492 return true; 493 } 494 495 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 496 .destroy = drm_gem_fb_destroy, 497 .create_handle = drm_gem_fb_create_handle, 498 }; 499 500 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 501 uint64_t bo_flags) 502 { 503 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 504 505 #if defined(CONFIG_DRM_AMD_DC) 506 /* 507 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 508 * is not supported for this board. But this mapping is required 509 * to avoid hang caused by placement of scanout BO in GTT on certain 510 * APUs. So force the BO placement to VRAM in case this architecture 511 * will not allow USWC mappings. 512 * Also, don't allow GTT domain if the BO doens't have USWC falg set. 513 */ 514 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 515 amdgpu_bo_support_uswc(bo_flags) && 516 amdgpu_device_asic_has_dc_support(adev->asic_type)) { 517 switch (adev->asic_type) { 518 case CHIP_CARRIZO: 519 case CHIP_STONEY: 520 domain |= AMDGPU_GEM_DOMAIN_GTT; 521 break; 522 case CHIP_RAVEN: 523 /* enable S/G on PCO and RV2 */ 524 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 525 (adev->apu_flags & AMD_APU_IS_PICASSO)) 526 domain |= AMDGPU_GEM_DOMAIN_GTT; 527 break; 528 case CHIP_RENOIR: 529 domain |= AMDGPU_GEM_DOMAIN_GTT; 530 break; 531 532 default: 533 break; 534 } 535 } 536 #endif 537 538 return domain; 539 } 540 541 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 542 { 543 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); 544 uint64_t modifier = 0; 545 546 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 547 modifier = DRM_FORMAT_MOD_LINEAR; 548 } else { 549 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 550 bool has_xor = swizzle >= 16; 551 int block_size_bits; 552 int version; 553 int pipe_xor_bits = 0; 554 int bank_xor_bits = 0; 555 int packers = 0; 556 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 557 558 switch (swizzle >> 2) { 559 case 0: /* 256B */ 560 block_size_bits = 8; 561 break; 562 case 1: /* 4KiB */ 563 case 5: /* 4KiB _X */ 564 block_size_bits = 12; 565 break; 566 case 2: /* 64KiB */ 567 case 4: /* 64 KiB _T */ 568 case 6: /* 64 KiB _X */ 569 block_size_bits = 16; 570 break; 571 default: 572 /* RESERVED or VAR */ 573 return -EINVAL; 574 } 575 576 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 577 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 578 else if (adev->family == AMDGPU_FAMILY_NV) 579 version = AMD_FMT_MOD_TILE_VER_GFX10; 580 else 581 version = AMD_FMT_MOD_TILE_VER_GFX9; 582 583 switch (swizzle & 3) { 584 case 0: /* Z microtiling */ 585 return -EINVAL; 586 case 1: /* S microtiling */ 587 if (!has_xor) 588 version = AMD_FMT_MOD_TILE_VER_GFX9; 589 break; 590 case 2: 591 if (!has_xor && afb->base.format->cpp[0] != 4) 592 version = AMD_FMT_MOD_TILE_VER_GFX9; 593 break; 594 case 3: 595 break; 596 } 597 598 if (has_xor) { 599 switch (version) { 600 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 601 pipe_xor_bits = min(block_size_bits - 8, 602 ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes)); 603 packers = min(block_size_bits - 8 - pipe_xor_bits, 604 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); 605 break; 606 case AMD_FMT_MOD_TILE_VER_GFX10: 607 pipe_xor_bits = min(block_size_bits - 8, 608 ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes)); 609 break; 610 case AMD_FMT_MOD_TILE_VER_GFX9: 611 pipe_xor_bits = min(block_size_bits - 8, 612 ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes) + 613 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 614 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, 615 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 616 break; 617 } 618 } 619 620 modifier = AMD_FMT_MOD | 621 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 622 AMD_FMT_MOD_SET(TILE_VERSION, version) | 623 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 624 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 625 AMD_FMT_MOD_SET(PACKERS, packers); 626 627 if (dcc_offset != 0) { 628 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 629 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 630 631 /* Enable constant encode on RAVEN2 and later. */ 632 bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN || 633 (adev->asic_type == CHIP_RAVEN && 634 adev->external_rev_id >= 0x81); 635 636 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : 637 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : 638 AMD_FMT_MOD_DCC_BLOCK_256B; 639 640 modifier |= AMD_FMT_MOD_SET(DCC, 1) | 641 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) | 642 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) | 643 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) | 644 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size); 645 646 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; 647 afb->base.pitches[1] = AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 648 } 649 } 650 651 afb->base.modifier = modifier; 652 afb->base.flags |= DRM_MODE_FB_MODIFIERS; 653 return 0; 654 } 655 656 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 657 uint64_t *tiling_flags, bool *tmz_surface) 658 { 659 struct amdgpu_bo *rbo; 660 int r; 661 662 if (!amdgpu_fb) { 663 *tiling_flags = 0; 664 *tmz_surface = false; 665 return 0; 666 } 667 668 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 669 r = amdgpu_bo_reserve(rbo, false); 670 671 if (unlikely(r)) { 672 /* Don't show error message when returning -ERESTARTSYS */ 673 if (r != -ERESTARTSYS) 674 DRM_ERROR("Unable to reserve buffer: %d\n", r); 675 return r; 676 } 677 678 if (tiling_flags) 679 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 680 681 if (tmz_surface) 682 *tmz_surface = amdgpu_bo_encrypted(rbo); 683 684 amdgpu_bo_unreserve(rbo); 685 686 return r; 687 } 688 689 int amdgpu_display_framebuffer_init(struct drm_device *dev, 690 struct amdgpu_framebuffer *rfb, 691 const struct drm_mode_fb_cmd2 *mode_cmd, 692 struct drm_gem_object *obj) 693 { 694 int ret; 695 rfb->base.obj[0] = obj; 696 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 697 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 698 if (ret) 699 goto fail; 700 701 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 702 if (ret) 703 goto fail; 704 705 if (dev->mode_config.allow_fb_modifiers && 706 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { 707 ret = convert_tiling_flags_to_modifier(rfb); 708 if (ret) 709 goto fail; 710 } 711 712 return 0; 713 714 fail: 715 rfb->base.obj[0] = NULL; 716 return ret; 717 } 718 719 struct drm_framebuffer * 720 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 721 struct drm_file *file_priv, 722 const struct drm_mode_fb_cmd2 *mode_cmd) 723 { 724 struct drm_gem_object *obj; 725 struct amdgpu_framebuffer *amdgpu_fb; 726 int ret; 727 728 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 729 if (obj == NULL) { 730 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 731 "can't create framebuffer\n", mode_cmd->handles[0]); 732 return ERR_PTR(-ENOENT); 733 } 734 735 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 736 if (obj->import_attach) { 737 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 738 return ERR_PTR(-EINVAL); 739 } 740 741 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 742 if (amdgpu_fb == NULL) { 743 drm_gem_object_put(obj); 744 return ERR_PTR(-ENOMEM); 745 } 746 747 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 748 if (ret) { 749 kfree(amdgpu_fb); 750 drm_gem_object_put(obj); 751 return ERR_PTR(ret); 752 } 753 754 return &amdgpu_fb->base; 755 } 756 757 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 758 .fb_create = amdgpu_display_user_framebuffer_create, 759 .output_poll_changed = drm_fb_helper_output_poll_changed, 760 }; 761 762 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 763 { { UNDERSCAN_OFF, "off" }, 764 { UNDERSCAN_ON, "on" }, 765 { UNDERSCAN_AUTO, "auto" }, 766 }; 767 768 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 769 { { AMDGPU_AUDIO_DISABLE, "off" }, 770 { AMDGPU_AUDIO_ENABLE, "on" }, 771 { AMDGPU_AUDIO_AUTO, "auto" }, 772 }; 773 774 /* XXX support different dither options? spatial, temporal, both, etc. */ 775 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 776 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 777 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 778 }; 779 780 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 781 { 782 int sz; 783 784 adev->mode_info.coherent_mode_property = 785 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 786 if (!adev->mode_info.coherent_mode_property) 787 return -ENOMEM; 788 789 adev->mode_info.load_detect_property = 790 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 791 if (!adev->mode_info.load_detect_property) 792 return -ENOMEM; 793 794 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 795 796 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 797 adev->mode_info.underscan_property = 798 drm_property_create_enum(adev_to_drm(adev), 0, 799 "underscan", 800 amdgpu_underscan_enum_list, sz); 801 802 adev->mode_info.underscan_hborder_property = 803 drm_property_create_range(adev_to_drm(adev), 0, 804 "underscan hborder", 0, 128); 805 if (!adev->mode_info.underscan_hborder_property) 806 return -ENOMEM; 807 808 adev->mode_info.underscan_vborder_property = 809 drm_property_create_range(adev_to_drm(adev), 0, 810 "underscan vborder", 0, 128); 811 if (!adev->mode_info.underscan_vborder_property) 812 return -ENOMEM; 813 814 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 815 adev->mode_info.audio_property = 816 drm_property_create_enum(adev_to_drm(adev), 0, 817 "audio", 818 amdgpu_audio_enum_list, sz); 819 820 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 821 adev->mode_info.dither_property = 822 drm_property_create_enum(adev_to_drm(adev), 0, 823 "dither", 824 amdgpu_dither_enum_list, sz); 825 826 if (amdgpu_device_has_dc_support(adev)) { 827 adev->mode_info.abm_level_property = 828 drm_property_create_range(adev_to_drm(adev), 0, 829 "abm level", 0, 4); 830 if (!adev->mode_info.abm_level_property) 831 return -ENOMEM; 832 } 833 834 return 0; 835 } 836 837 void amdgpu_display_update_priority(struct amdgpu_device *adev) 838 { 839 /* adjustment options for the display watermarks */ 840 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 841 adev->mode_info.disp_priority = 0; 842 else 843 adev->mode_info.disp_priority = amdgpu_disp_priority; 844 845 } 846 847 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 848 { 849 /* try and guess if this is a tv or a monitor */ 850 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 851 (mode->vdisplay == 576) || /* 576p */ 852 (mode->vdisplay == 720) || /* 720p */ 853 (mode->vdisplay == 1080)) /* 1080p */ 854 return true; 855 else 856 return false; 857 } 858 859 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 860 const struct drm_display_mode *mode, 861 struct drm_display_mode *adjusted_mode) 862 { 863 struct drm_device *dev = crtc->dev; 864 struct drm_encoder *encoder; 865 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 866 struct amdgpu_encoder *amdgpu_encoder; 867 struct drm_connector *connector; 868 u32 src_v = 1, dst_v = 1; 869 u32 src_h = 1, dst_h = 1; 870 871 amdgpu_crtc->h_border = 0; 872 amdgpu_crtc->v_border = 0; 873 874 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 875 if (encoder->crtc != crtc) 876 continue; 877 amdgpu_encoder = to_amdgpu_encoder(encoder); 878 connector = amdgpu_get_connector_for_encoder(encoder); 879 880 /* set scaling */ 881 if (amdgpu_encoder->rmx_type == RMX_OFF) 882 amdgpu_crtc->rmx_type = RMX_OFF; 883 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 884 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 885 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 886 else 887 amdgpu_crtc->rmx_type = RMX_OFF; 888 /* copy native mode */ 889 memcpy(&amdgpu_crtc->native_mode, 890 &amdgpu_encoder->native_mode, 891 sizeof(struct drm_display_mode)); 892 src_v = crtc->mode.vdisplay; 893 dst_v = amdgpu_crtc->native_mode.vdisplay; 894 src_h = crtc->mode.hdisplay; 895 dst_h = amdgpu_crtc->native_mode.hdisplay; 896 897 /* fix up for overscan on hdmi */ 898 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 899 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 900 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 901 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 902 amdgpu_display_is_hdtv_mode(mode)))) { 903 if (amdgpu_encoder->underscan_hborder != 0) 904 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 905 else 906 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 907 if (amdgpu_encoder->underscan_vborder != 0) 908 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 909 else 910 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 911 amdgpu_crtc->rmx_type = RMX_FULL; 912 src_v = crtc->mode.vdisplay; 913 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 914 src_h = crtc->mode.hdisplay; 915 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 916 } 917 } 918 if (amdgpu_crtc->rmx_type != RMX_OFF) { 919 fixed20_12 a, b; 920 a.full = dfixed_const(src_v); 921 b.full = dfixed_const(dst_v); 922 amdgpu_crtc->vsc.full = dfixed_div(a, b); 923 a.full = dfixed_const(src_h); 924 b.full = dfixed_const(dst_h); 925 amdgpu_crtc->hsc.full = dfixed_div(a, b); 926 } else { 927 amdgpu_crtc->vsc.full = dfixed_const(1); 928 amdgpu_crtc->hsc.full = dfixed_const(1); 929 } 930 return true; 931 } 932 933 /* 934 * Retrieve current video scanout position of crtc on a given gpu, and 935 * an optional accurate timestamp of when query happened. 936 * 937 * \param dev Device to query. 938 * \param pipe Crtc to query. 939 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 940 * For driver internal use only also supports these flags: 941 * 942 * USE_REAL_VBLANKSTART to use the real start of vblank instead 943 * of a fudged earlier start of vblank. 944 * 945 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 946 * fudged earlier start of vblank in *vpos and the distance 947 * to true start of vblank in *hpos. 948 * 949 * \param *vpos Location where vertical scanout position should be stored. 950 * \param *hpos Location where horizontal scanout position should go. 951 * \param *stime Target location for timestamp taken immediately before 952 * scanout position query. Can be NULL to skip timestamp. 953 * \param *etime Target location for timestamp taken immediately after 954 * scanout position query. Can be NULL to skip timestamp. 955 * 956 * Returns vpos as a positive number while in active scanout area. 957 * Returns vpos as a negative number inside vblank, counting the number 958 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 959 * until start of active scanout / end of vblank." 960 * 961 * \return Flags, or'ed together as follows: 962 * 963 * DRM_SCANOUTPOS_VALID = Query successful. 964 * DRM_SCANOUTPOS_INVBL = Inside vblank. 965 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 966 * this flag means that returned position may be offset by a constant but 967 * unknown small number of scanlines wrt. real scanout position. 968 * 969 */ 970 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 971 unsigned int pipe, unsigned int flags, int *vpos, 972 int *hpos, ktime_t *stime, ktime_t *etime, 973 const struct drm_display_mode *mode) 974 { 975 u32 vbl = 0, position = 0; 976 int vbl_start, vbl_end, vtotal, ret = 0; 977 bool in_vbl = true; 978 979 struct amdgpu_device *adev = drm_to_adev(dev); 980 981 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 982 983 /* Get optional system timestamp before query. */ 984 if (stime) 985 *stime = ktime_get(); 986 987 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 988 ret |= DRM_SCANOUTPOS_VALID; 989 990 /* Get optional system timestamp after query. */ 991 if (etime) 992 *etime = ktime_get(); 993 994 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 995 996 /* Decode into vertical and horizontal scanout position. */ 997 *vpos = position & 0x1fff; 998 *hpos = (position >> 16) & 0x1fff; 999 1000 /* Valid vblank area boundaries from gpu retrieved? */ 1001 if (vbl > 0) { 1002 /* Yes: Decode. */ 1003 ret |= DRM_SCANOUTPOS_ACCURATE; 1004 vbl_start = vbl & 0x1fff; 1005 vbl_end = (vbl >> 16) & 0x1fff; 1006 } 1007 else { 1008 /* No: Fake something reasonable which gives at least ok results. */ 1009 vbl_start = mode->crtc_vdisplay; 1010 vbl_end = 0; 1011 } 1012 1013 /* Called from driver internal vblank counter query code? */ 1014 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1015 /* Caller wants distance from real vbl_start in *hpos */ 1016 *hpos = *vpos - vbl_start; 1017 } 1018 1019 /* Fudge vblank to start a few scanlines earlier to handle the 1020 * problem that vblank irqs fire a few scanlines before start 1021 * of vblank. Some driver internal callers need the true vblank 1022 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1023 * 1024 * The cause of the "early" vblank irq is that the irq is triggered 1025 * by the line buffer logic when the line buffer read position enters 1026 * the vblank, whereas our crtc scanout position naturally lags the 1027 * line buffer read position. 1028 */ 1029 if (!(flags & USE_REAL_VBLANKSTART)) 1030 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1031 1032 /* Test scanout position against vblank region. */ 1033 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1034 in_vbl = false; 1035 1036 /* In vblank? */ 1037 if (in_vbl) 1038 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1039 1040 /* Called from driver internal vblank counter query code? */ 1041 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1042 /* Caller wants distance from fudged earlier vbl_start */ 1043 *vpos -= vbl_start; 1044 return ret; 1045 } 1046 1047 /* Check if inside vblank area and apply corrective offsets: 1048 * vpos will then be >=0 in video scanout area, but negative 1049 * within vblank area, counting down the number of lines until 1050 * start of scanout. 1051 */ 1052 1053 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1054 if (in_vbl && (*vpos >= vbl_start)) { 1055 vtotal = mode->crtc_vtotal; 1056 1057 /* With variable refresh rate displays the vpos can exceed 1058 * the vtotal value. Clamp to 0 to return -vbl_end instead 1059 * of guessing the remaining number of lines until scanout. 1060 */ 1061 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 1062 } 1063 1064 /* Correct for shifted end of vbl at vbl_end. */ 1065 *vpos = *vpos - vbl_end; 1066 1067 return ret; 1068 } 1069 1070 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 1071 { 1072 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 1073 return AMDGPU_CRTC_IRQ_NONE; 1074 1075 switch (crtc) { 1076 case 0: 1077 return AMDGPU_CRTC_IRQ_VBLANK1; 1078 case 1: 1079 return AMDGPU_CRTC_IRQ_VBLANK2; 1080 case 2: 1081 return AMDGPU_CRTC_IRQ_VBLANK3; 1082 case 3: 1083 return AMDGPU_CRTC_IRQ_VBLANK4; 1084 case 4: 1085 return AMDGPU_CRTC_IRQ_VBLANK5; 1086 case 5: 1087 return AMDGPU_CRTC_IRQ_VBLANK6; 1088 default: 1089 return AMDGPU_CRTC_IRQ_NONE; 1090 } 1091 } 1092 1093 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 1094 bool in_vblank_irq, int *vpos, 1095 int *hpos, ktime_t *stime, ktime_t *etime, 1096 const struct drm_display_mode *mode) 1097 { 1098 struct drm_device *dev = crtc->dev; 1099 unsigned int pipe = crtc->index; 1100 1101 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1102 stime, etime, mode); 1103 } 1104