1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include "soc15_common.h" 34 #include "gc/gc_11_0_0_offset.h" 35 #include "gc/gc_11_0_0_sh_mask.h" 36 #include <asm/div64.h> 37 38 #include <linux/pci.h> 39 #include <linux/pm_runtime.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_fb_helper.h> 43 #include <drm/drm_gem_framebuffer_helper.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_modeset_helper.h> 46 #include <drm/drm_vblank.h> 47 48 /** 49 * amdgpu_display_hotplug_work_func - work handler for display hotplug event 50 * 51 * @work: work struct pointer 52 * 53 * This is the hotplug event work handler (all ASICs). 54 * The work gets scheduled from the IRQ handler if there 55 * was a hotplug interrupt. It walks through the connector table 56 * and calls hotplug handler for each connector. After this, it sends 57 * a DRM hotplug event to alert userspace. 58 * 59 * This design approach is required in order to defer hotplug event handling 60 * from the IRQ handler to a work handler because hotplug handler has to use 61 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 62 * sleep). 63 */ 64 void amdgpu_display_hotplug_work_func(struct work_struct *work) 65 { 66 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 67 hotplug_work.work); 68 struct drm_device *dev = adev_to_drm(adev); 69 struct drm_mode_config *mode_config = &dev->mode_config; 70 struct drm_connector *connector; 71 struct drm_connector_list_iter iter; 72 73 mutex_lock(&mode_config->mutex); 74 drm_connector_list_iter_begin(dev, &iter); 75 drm_for_each_connector_iter(connector, &iter) 76 amdgpu_connector_hotplug(connector); 77 drm_connector_list_iter_end(&iter); 78 mutex_unlock(&mode_config->mutex); 79 /* Just fire off a uevent and let userspace tell us what to do */ 80 drm_helper_hpd_irq_event(dev); 81 } 82 83 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 84 struct amdgpu_framebuffer *rfb, 85 const struct drm_mode_fb_cmd2 *mode_cmd, 86 struct drm_gem_object *obj); 87 88 static void amdgpu_display_flip_callback(struct dma_fence *f, 89 struct dma_fence_cb *cb) 90 { 91 struct amdgpu_flip_work *work = 92 container_of(cb, struct amdgpu_flip_work, cb); 93 94 dma_fence_put(f); 95 schedule_work(&work->flip_work.work); 96 } 97 98 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 99 struct dma_fence **f) 100 { 101 struct dma_fence *fence= *f; 102 103 if (fence == NULL) 104 return false; 105 106 *f = NULL; 107 108 if (!dma_fence_add_callback(fence, &work->cb, 109 amdgpu_display_flip_callback)) 110 return true; 111 112 dma_fence_put(fence); 113 return false; 114 } 115 116 static void amdgpu_display_flip_work_func(struct work_struct *__work) 117 { 118 struct delayed_work *delayed_work = 119 container_of(__work, struct delayed_work, work); 120 struct amdgpu_flip_work *work = 121 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 122 struct amdgpu_device *adev = work->adev; 123 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 124 125 struct drm_crtc *crtc = &amdgpu_crtc->base; 126 unsigned long flags; 127 unsigned i; 128 int vpos, hpos; 129 130 for (i = 0; i < work->shared_count; ++i) 131 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 132 return; 133 134 /* Wait until we're out of the vertical blank period before the one 135 * targeted by the flip 136 */ 137 if (amdgpu_crtc->enabled && 138 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 139 &vpos, &hpos, NULL, NULL, 140 &crtc->hwmode) 141 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 142 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 143 (int)(work->target_vblank - 144 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 145 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 146 return; 147 } 148 149 /* We borrow the event spin lock for protecting flip_status */ 150 spin_lock_irqsave(&crtc->dev->event_lock, flags); 151 152 /* Do the flip (mmio) */ 153 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 154 155 /* Set the flip status */ 156 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 157 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 158 159 160 drm_dbg_vbl(adev_to_drm(adev), 161 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 162 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 163 164 } 165 166 /* 167 * Handle unpin events outside the interrupt handler proper. 168 */ 169 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 170 { 171 struct amdgpu_flip_work *work = 172 container_of(__work, struct amdgpu_flip_work, unpin_work); 173 int r; 174 175 /* unpin of the old buffer */ 176 r = amdgpu_bo_reserve(work->old_abo, true); 177 if (likely(r == 0)) { 178 amdgpu_bo_unpin(work->old_abo); 179 amdgpu_bo_unreserve(work->old_abo); 180 } else 181 DRM_ERROR("failed to reserve buffer after flip\n"); 182 183 amdgpu_bo_unref(&work->old_abo); 184 kfree(work->shared); 185 kfree(work); 186 } 187 188 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 189 struct drm_framebuffer *fb, 190 struct drm_pending_vblank_event *event, 191 uint32_t page_flip_flags, uint32_t target, 192 struct drm_modeset_acquire_ctx *ctx) 193 { 194 struct drm_device *dev = crtc->dev; 195 struct amdgpu_device *adev = drm_to_adev(dev); 196 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 197 struct drm_gem_object *obj; 198 struct amdgpu_flip_work *work; 199 struct amdgpu_bo *new_abo; 200 unsigned long flags; 201 u64 tiling_flags; 202 int i, r; 203 204 work = kzalloc(sizeof *work, GFP_KERNEL); 205 if (work == NULL) 206 return -ENOMEM; 207 208 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 209 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 210 211 work->event = event; 212 work->adev = adev; 213 work->crtc_id = amdgpu_crtc->crtc_id; 214 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 215 216 /* schedule unpin of the old buffer */ 217 obj = crtc->primary->fb->obj[0]; 218 219 /* take a reference to the old object */ 220 work->old_abo = gem_to_amdgpu_bo(obj); 221 amdgpu_bo_ref(work->old_abo); 222 223 obj = fb->obj[0]; 224 new_abo = gem_to_amdgpu_bo(obj); 225 226 /* pin the new buffer */ 227 r = amdgpu_bo_reserve(new_abo, false); 228 if (unlikely(r != 0)) { 229 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 230 goto cleanup; 231 } 232 233 if (!adev->enable_virtual_display) { 234 r = amdgpu_bo_pin(new_abo, 235 amdgpu_display_supported_domains(adev, new_abo->flags)); 236 if (unlikely(r != 0)) { 237 DRM_ERROR("failed to pin new abo buffer before flip\n"); 238 goto unreserve; 239 } 240 } 241 242 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 243 if (unlikely(r != 0)) { 244 DRM_ERROR("%p bind failed\n", new_abo); 245 goto unpin; 246 } 247 248 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, 249 &work->shared_count, 250 &work->shared); 251 if (unlikely(r != 0)) { 252 DRM_ERROR("failed to get fences for buffer\n"); 253 goto unpin; 254 } 255 256 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 257 amdgpu_bo_unreserve(new_abo); 258 259 if (!adev->enable_virtual_display) 260 work->base = amdgpu_bo_gpu_offset(new_abo); 261 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 262 amdgpu_get_vblank_counter_kms(crtc); 263 264 /* we borrow the event spin lock for protecting flip_wrok */ 265 spin_lock_irqsave(&crtc->dev->event_lock, flags); 266 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 267 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 268 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 269 r = -EBUSY; 270 goto pflip_cleanup; 271 } 272 273 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 274 amdgpu_crtc->pflip_works = work; 275 276 277 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 278 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 279 /* update crtc fb */ 280 crtc->primary->fb = fb; 281 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 282 amdgpu_display_flip_work_func(&work->flip_work.work); 283 return 0; 284 285 pflip_cleanup: 286 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 287 DRM_ERROR("failed to reserve new abo in error path\n"); 288 goto cleanup; 289 } 290 unpin: 291 if (!adev->enable_virtual_display) 292 amdgpu_bo_unpin(new_abo); 293 294 unreserve: 295 amdgpu_bo_unreserve(new_abo); 296 297 cleanup: 298 amdgpu_bo_unref(&work->old_abo); 299 for (i = 0; i < work->shared_count; ++i) 300 dma_fence_put(work->shared[i]); 301 kfree(work->shared); 302 kfree(work); 303 304 return r; 305 } 306 307 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 308 struct drm_modeset_acquire_ctx *ctx) 309 { 310 struct drm_device *dev; 311 struct amdgpu_device *adev; 312 struct drm_crtc *crtc; 313 bool active = false; 314 int ret; 315 316 if (!set || !set->crtc) 317 return -EINVAL; 318 319 dev = set->crtc->dev; 320 321 ret = pm_runtime_get_sync(dev->dev); 322 if (ret < 0) 323 goto out; 324 325 ret = drm_crtc_helper_set_config(set, ctx); 326 327 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 328 if (crtc->enabled) 329 active = true; 330 331 pm_runtime_mark_last_busy(dev->dev); 332 333 adev = drm_to_adev(dev); 334 /* if we have active crtcs and we don't have a power ref, 335 take the current one */ 336 if (active && !adev->have_disp_power_ref) { 337 adev->have_disp_power_ref = true; 338 return ret; 339 } 340 /* if we have no active crtcs, then drop the power ref 341 we got before */ 342 if (!active && adev->have_disp_power_ref) { 343 pm_runtime_put_autosuspend(dev->dev); 344 adev->have_disp_power_ref = false; 345 } 346 347 out: 348 /* drop the power reference we got coming in here */ 349 pm_runtime_put_autosuspend(dev->dev); 350 return ret; 351 } 352 353 static const char *encoder_names[41] = { 354 "NONE", 355 "INTERNAL_LVDS", 356 "INTERNAL_TMDS1", 357 "INTERNAL_TMDS2", 358 "INTERNAL_DAC1", 359 "INTERNAL_DAC2", 360 "INTERNAL_SDVOA", 361 "INTERNAL_SDVOB", 362 "SI170B", 363 "CH7303", 364 "CH7301", 365 "INTERNAL_DVO1", 366 "EXTERNAL_SDVOA", 367 "EXTERNAL_SDVOB", 368 "TITFP513", 369 "INTERNAL_LVTM1", 370 "VT1623", 371 "HDMI_SI1930", 372 "HDMI_INTERNAL", 373 "INTERNAL_KLDSCP_TMDS1", 374 "INTERNAL_KLDSCP_DVO1", 375 "INTERNAL_KLDSCP_DAC1", 376 "INTERNAL_KLDSCP_DAC2", 377 "SI178", 378 "MVPU_FPGA", 379 "INTERNAL_DDI", 380 "VT1625", 381 "HDMI_SI1932", 382 "DP_AN9801", 383 "DP_DP501", 384 "INTERNAL_UNIPHY", 385 "INTERNAL_KLDSCP_LVTMA", 386 "INTERNAL_UNIPHY1", 387 "INTERNAL_UNIPHY2", 388 "NUTMEG", 389 "TRAVIS", 390 "INTERNAL_VCE", 391 "INTERNAL_UNIPHY3", 392 "HDMI_ANX9805", 393 "INTERNAL_AMCLK", 394 "VIRTUAL", 395 }; 396 397 static const char *hpd_names[6] = { 398 "HPD1", 399 "HPD2", 400 "HPD3", 401 "HPD4", 402 "HPD5", 403 "HPD6", 404 }; 405 406 void amdgpu_display_print_display_setup(struct drm_device *dev) 407 { 408 struct drm_connector *connector; 409 struct amdgpu_connector *amdgpu_connector; 410 struct drm_encoder *encoder; 411 struct amdgpu_encoder *amdgpu_encoder; 412 struct drm_connector_list_iter iter; 413 uint32_t devices; 414 int i = 0; 415 416 drm_connector_list_iter_begin(dev, &iter); 417 DRM_INFO("AMDGPU Display Connectors\n"); 418 drm_for_each_connector_iter(connector, &iter) { 419 amdgpu_connector = to_amdgpu_connector(connector); 420 DRM_INFO("Connector %d:\n", i); 421 DRM_INFO(" %s\n", connector->name); 422 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 423 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 424 if (amdgpu_connector->ddc_bus) { 425 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 426 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 427 amdgpu_connector->ddc_bus->rec.mask_data_reg, 428 amdgpu_connector->ddc_bus->rec.a_clk_reg, 429 amdgpu_connector->ddc_bus->rec.a_data_reg, 430 amdgpu_connector->ddc_bus->rec.en_clk_reg, 431 amdgpu_connector->ddc_bus->rec.en_data_reg, 432 amdgpu_connector->ddc_bus->rec.y_clk_reg, 433 amdgpu_connector->ddc_bus->rec.y_data_reg); 434 if (amdgpu_connector->router.ddc_valid) 435 DRM_INFO(" DDC Router 0x%x/0x%x\n", 436 amdgpu_connector->router.ddc_mux_control_pin, 437 amdgpu_connector->router.ddc_mux_state); 438 if (amdgpu_connector->router.cd_valid) 439 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 440 amdgpu_connector->router.cd_mux_control_pin, 441 amdgpu_connector->router.cd_mux_state); 442 } else { 443 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 444 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 445 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 446 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 447 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 448 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 449 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 450 } 451 DRM_INFO(" Encoders:\n"); 452 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 453 amdgpu_encoder = to_amdgpu_encoder(encoder); 454 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 455 if (devices) { 456 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 457 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 458 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 459 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 460 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 461 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 462 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 463 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 464 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 465 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 466 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 467 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 468 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 469 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 470 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 471 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 472 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 473 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 474 if (devices & ATOM_DEVICE_TV1_SUPPORT) 475 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 476 if (devices & ATOM_DEVICE_CV_SUPPORT) 477 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 478 } 479 } 480 i++; 481 } 482 drm_connector_list_iter_end(&iter); 483 } 484 485 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 486 bool use_aux) 487 { 488 u8 out = 0x0; 489 u8 buf[8]; 490 int ret; 491 struct i2c_msg msgs[] = { 492 { 493 .addr = DDC_ADDR, 494 .flags = 0, 495 .len = 1, 496 .buf = &out, 497 }, 498 { 499 .addr = DDC_ADDR, 500 .flags = I2C_M_RD, 501 .len = 8, 502 .buf = buf, 503 } 504 }; 505 506 /* on hw with routers, select right port */ 507 if (amdgpu_connector->router.ddc_valid) 508 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 509 510 if (use_aux) { 511 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 512 } else { 513 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 514 } 515 516 if (ret != 2) 517 /* Couldn't find an accessible DDC on this connector */ 518 return false; 519 /* Probe also for valid EDID header 520 * EDID header starts with: 521 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 522 * Only the first 6 bytes must be valid as 523 * drm_edid_block_valid() can fix the last 2 bytes */ 524 if (drm_edid_header_is_valid(buf) < 6) { 525 /* Couldn't find an accessible EDID on this 526 * connector */ 527 return false; 528 } 529 return true; 530 } 531 532 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 533 .destroy = drm_gem_fb_destroy, 534 .create_handle = drm_gem_fb_create_handle, 535 }; 536 537 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 538 uint64_t bo_flags) 539 { 540 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 541 542 #if defined(CONFIG_DRM_AMD_DC) 543 /* 544 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 545 * is not supported for this board. But this mapping is required 546 * to avoid hang caused by placement of scanout BO in GTT on certain 547 * APUs. So force the BO placement to VRAM in case this architecture 548 * will not allow USWC mappings. 549 * Also, don't allow GTT domain if the BO doesn't have USWC flag set. 550 */ 551 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 552 amdgpu_bo_support_uswc(bo_flags) && 553 adev->dc_enabled && 554 adev->mode_info.gpu_vm_support) 555 domain |= AMDGPU_GEM_DOMAIN_GTT; 556 #endif 557 558 return domain; 559 } 560 561 static const struct drm_format_info dcc_formats[] = { 562 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 563 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 564 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 565 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 566 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 567 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 568 .has_alpha = true, }, 569 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 570 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 571 .has_alpha = true, }, 572 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2, 573 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 574 .has_alpha = true, }, 575 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 576 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 577 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 578 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 579 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 580 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 581 .has_alpha = true, }, 582 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 583 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 584 .has_alpha = true, }, 585 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2, 586 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 587 }; 588 589 static const struct drm_format_info dcc_retile_formats[] = { 590 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 591 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 592 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 593 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 594 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 595 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 596 .has_alpha = true, }, 597 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 598 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 599 .has_alpha = true, }, 600 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3, 601 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 602 .has_alpha = true, }, 603 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 604 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 605 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 606 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 607 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 608 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 609 .has_alpha = true, }, 610 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 611 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 612 .has_alpha = true, }, 613 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3, 614 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 615 }; 616 617 static const struct drm_format_info * 618 lookup_format_info(const struct drm_format_info formats[], 619 int num_formats, u32 format) 620 { 621 int i; 622 623 for (i = 0; i < num_formats; i++) { 624 if (formats[i].format == format) 625 return &formats[i]; 626 } 627 628 return NULL; 629 } 630 631 const struct drm_format_info * 632 amdgpu_lookup_format_info(u32 format, uint64_t modifier) 633 { 634 if (!IS_AMD_FMT_MOD(modifier)) 635 return NULL; 636 637 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) 638 return lookup_format_info(dcc_retile_formats, 639 ARRAY_SIZE(dcc_retile_formats), 640 format); 641 642 if (AMD_FMT_MOD_GET(DCC, modifier)) 643 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats), 644 format); 645 646 /* returning NULL will cause the default format structs to be used. */ 647 return NULL; 648 } 649 650 651 /* 652 * Tries to extract the renderable DCC offset from the opaque metadata attached 653 * to the buffer. 654 */ 655 static int 656 extract_render_dcc_offset(struct amdgpu_device *adev, 657 struct drm_gem_object *obj, 658 uint64_t *offset) 659 { 660 struct amdgpu_bo *rbo; 661 int r = 0; 662 uint32_t metadata[10]; /* Something that fits a descriptor + header. */ 663 uint32_t size; 664 665 rbo = gem_to_amdgpu_bo(obj); 666 r = amdgpu_bo_reserve(rbo, false); 667 668 if (unlikely(r)) { 669 /* Don't show error message when returning -ERESTARTSYS */ 670 if (r != -ERESTARTSYS) 671 DRM_ERROR("Unable to reserve buffer: %d\n", r); 672 return r; 673 } 674 675 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL); 676 amdgpu_bo_unreserve(rbo); 677 678 if (r) 679 return r; 680 681 /* 682 * The first word is the metadata version, and we need space for at least 683 * the version + pci vendor+device id + 8 words for a descriptor. 684 */ 685 if (size < 40 || metadata[0] != 1) 686 return -EINVAL; 687 688 if (adev->family >= AMDGPU_FAMILY_NV) { 689 /* resource word 6/7 META_DATA_ADDRESS{_LO} */ 690 *offset = ((u64)metadata[9] << 16u) | 691 ((metadata[8] & 0xFF000000u) >> 16); 692 } else { 693 /* resource word 5/7 META_DATA_ADDRESS */ 694 *offset = ((u64)metadata[9] << 8u) | 695 ((u64)(metadata[7] & 0x1FE0000u) << 23); 696 } 697 698 return 0; 699 } 700 701 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 702 { 703 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); 704 uint64_t modifier = 0; 705 int num_pipes = 0; 706 int num_pkrs = 0; 707 708 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 709 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; 710 711 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 712 modifier = DRM_FORMAT_MOD_LINEAR; 713 } else { 714 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 715 bool has_xor = swizzle >= 16; 716 int block_size_bits; 717 int version; 718 int pipe_xor_bits = 0; 719 int bank_xor_bits = 0; 720 int packers = 0; 721 int rb = 0; 722 int pipes = ilog2(num_pipes); 723 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 724 725 switch (swizzle >> 2) { 726 case 0: /* 256B */ 727 block_size_bits = 8; 728 break; 729 case 1: /* 4KiB */ 730 case 5: /* 4KiB _X */ 731 block_size_bits = 12; 732 break; 733 case 2: /* 64KiB */ 734 case 4: /* 64 KiB _T */ 735 case 6: /* 64 KiB _X */ 736 block_size_bits = 16; 737 break; 738 case 7: /* 256 KiB */ 739 block_size_bits = 18; 740 break; 741 default: 742 /* RESERVED or VAR */ 743 return -EINVAL; 744 } 745 746 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) 747 version = AMD_FMT_MOD_TILE_VER_GFX11; 748 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 749 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 750 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) 751 version = AMD_FMT_MOD_TILE_VER_GFX10; 752 else 753 version = AMD_FMT_MOD_TILE_VER_GFX9; 754 755 switch (swizzle & 3) { 756 case 0: /* Z microtiling */ 757 return -EINVAL; 758 case 1: /* S microtiling */ 759 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { 760 if (!has_xor) 761 version = AMD_FMT_MOD_TILE_VER_GFX9; 762 } 763 break; 764 case 2: 765 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { 766 if (!has_xor && afb->base.format->cpp[0] != 4) 767 version = AMD_FMT_MOD_TILE_VER_GFX9; 768 } 769 break; 770 case 3: 771 break; 772 } 773 774 if (has_xor) { 775 if (num_pipes == num_pkrs && num_pkrs == 0) { 776 DRM_ERROR("invalid number of pipes and packers\n"); 777 return -EINVAL; 778 } 779 780 switch (version) { 781 case AMD_FMT_MOD_TILE_VER_GFX11: 782 pipe_xor_bits = min(block_size_bits - 8, pipes); 783 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 784 break; 785 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 786 pipe_xor_bits = min(block_size_bits - 8, pipes); 787 packers = min(block_size_bits - 8 - pipe_xor_bits, 788 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); 789 break; 790 case AMD_FMT_MOD_TILE_VER_GFX10: 791 pipe_xor_bits = min(block_size_bits - 8, pipes); 792 break; 793 case AMD_FMT_MOD_TILE_VER_GFX9: 794 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 795 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 796 pipe_xor_bits = min(block_size_bits - 8, pipes + 797 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 798 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, 799 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 800 break; 801 } 802 } 803 804 modifier = AMD_FMT_MOD | 805 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 806 AMD_FMT_MOD_SET(TILE_VERSION, version) | 807 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 808 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 809 AMD_FMT_MOD_SET(PACKERS, packers); 810 811 if (dcc_offset != 0) { 812 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 813 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 814 const struct drm_format_info *format_info; 815 u64 render_dcc_offset; 816 817 /* Enable constant encode on RAVEN2 and later. */ 818 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN || 819 (adev->asic_type == CHIP_RAVEN && 820 adev->external_rev_id >= 0x81)) && 821 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); 822 823 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : 824 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : 825 AMD_FMT_MOD_DCC_BLOCK_256B; 826 827 modifier |= AMD_FMT_MOD_SET(DCC, 1) | 828 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) | 829 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) | 830 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) | 831 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size); 832 833 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; 834 afb->base.pitches[1] = 835 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 836 837 /* 838 * If the userspace driver uses retiling the tiling flags do not contain 839 * info on the renderable DCC buffer. Luckily the opaque metadata contains 840 * the info so we can try to extract it. The kernel does not use this info 841 * but we should convert it to a modifier plane for getfb2, so the 842 * userspace driver that gets it doesn't have to juggle around another DCC 843 * plane internally. 844 */ 845 if (extract_render_dcc_offset(adev, afb->base.obj[0], 846 &render_dcc_offset) == 0 && 847 render_dcc_offset != 0 && 848 render_dcc_offset != afb->base.offsets[1] && 849 render_dcc_offset < UINT_MAX) { 850 uint32_t dcc_block_bits; /* of base surface data */ 851 852 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); 853 afb->base.offsets[2] = render_dcc_offset; 854 855 if (adev->family >= AMDGPU_FAMILY_NV) { 856 int extra_pipe = 0; 857 858 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && 859 pipes == packers && pipes > 1) 860 extra_pipe = 1; 861 862 dcc_block_bits = max(20, 16 + pipes + extra_pipe); 863 } else { 864 modifier |= AMD_FMT_MOD_SET(RB, rb) | 865 AMD_FMT_MOD_SET(PIPE, pipes); 866 dcc_block_bits = max(20, 18 + rb); 867 } 868 869 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); 870 afb->base.pitches[2] = ALIGN(afb->base.width, 871 1u << ((dcc_block_bits + 1) / 2)); 872 } 873 format_info = amdgpu_lookup_format_info(afb->base.format->format, 874 modifier); 875 if (!format_info) 876 return -EINVAL; 877 878 afb->base.format = format_info; 879 } 880 } 881 882 afb->base.modifier = modifier; 883 afb->base.flags |= DRM_MODE_FB_MODIFIERS; 884 return 0; 885 } 886 887 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ 888 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) 889 { 890 u64 micro_tile_mode; 891 892 /* Zero swizzle mode means linear */ 893 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) 894 return 0; 895 896 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); 897 switch (micro_tile_mode) { 898 case 0: /* DISPLAY */ 899 case 3: /* RENDER */ 900 return 0; 901 default: 902 drm_dbg_kms(afb->base.dev, 903 "Micro tile mode %llu not supported for scanout\n", 904 micro_tile_mode); 905 return -EINVAL; 906 } 907 } 908 909 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, 910 unsigned int *width, unsigned int *height) 911 { 912 unsigned int cpp_log2 = ilog2(cpp); 913 unsigned int pixel_log2 = block_log2 - cpp_log2; 914 unsigned int width_log2 = (pixel_log2 + 1) / 2; 915 unsigned int height_log2 = pixel_log2 - width_log2; 916 917 *width = 1 << width_log2; 918 *height = 1 << height_log2; 919 } 920 921 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, 922 bool pipe_aligned) 923 { 924 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); 925 926 switch (ver) { 927 case AMD_FMT_MOD_TILE_VER_GFX9: { 928 /* 929 * TODO: for pipe aligned we may need to check the alignment of the 930 * total size of the surface, which may need to be bigger than the 931 * natural alignment due to some HW workarounds 932 */ 933 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); 934 } 935 case AMD_FMT_MOD_TILE_VER_GFX10: 936 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 937 case AMD_FMT_MOD_TILE_VER_GFX11: { 938 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 939 940 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && 941 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) 942 ++pipes_log2; 943 944 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12); 945 } 946 default: 947 return 0; 948 } 949 } 950 951 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane, 952 const struct drm_format_info *format, 953 unsigned int block_width, unsigned int block_height, 954 unsigned int block_size_log2) 955 { 956 unsigned int width = rfb->base.width / 957 ((plane && plane < format->num_planes) ? format->hsub : 1); 958 unsigned int height = rfb->base.height / 959 ((plane && plane < format->num_planes) ? format->vsub : 1); 960 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; 961 unsigned int block_pitch = block_width * cpp; 962 unsigned int min_pitch = ALIGN(width * cpp, block_pitch); 963 unsigned int block_size = 1 << block_size_log2; 964 uint64_t size; 965 966 if (rfb->base.pitches[plane] % block_pitch) { 967 drm_dbg_kms(rfb->base.dev, 968 "pitch %d for plane %d is not a multiple of block pitch %d\n", 969 rfb->base.pitches[plane], plane, block_pitch); 970 return -EINVAL; 971 } 972 if (rfb->base.pitches[plane] < min_pitch) { 973 drm_dbg_kms(rfb->base.dev, 974 "pitch %d for plane %d is less than minimum pitch %d\n", 975 rfb->base.pitches[plane], plane, min_pitch); 976 return -EINVAL; 977 } 978 979 /* Force at least natural alignment. */ 980 if (rfb->base.offsets[plane] % block_size) { 981 drm_dbg_kms(rfb->base.dev, 982 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n", 983 rfb->base.offsets[plane], plane, block_size); 984 return -EINVAL; 985 } 986 987 size = rfb->base.offsets[plane] + 988 (uint64_t)rfb->base.pitches[plane] / block_pitch * 989 block_size * DIV_ROUND_UP(height, block_height); 990 991 if (rfb->base.obj[0]->size < size) { 992 drm_dbg_kms(rfb->base.dev, 993 "BO size 0x%zx is less than 0x%llx required for plane %d\n", 994 rfb->base.obj[0]->size, size, plane); 995 return -EINVAL; 996 } 997 998 return 0; 999 } 1000 1001 1002 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 1003 { 1004 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); 1005 uint64_t modifier = rfb->base.modifier; 1006 int ret; 1007 unsigned int i, block_width, block_height, block_size_log2; 1008 1009 if (rfb->base.dev->mode_config.fb_modifiers_not_supported) 1010 return 0; 1011 1012 for (i = 0; i < format_info->num_planes; ++i) { 1013 if (modifier == DRM_FORMAT_MOD_LINEAR) { 1014 block_width = 256 / format_info->cpp[i]; 1015 block_height = 1; 1016 block_size_log2 = 8; 1017 } else { 1018 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); 1019 1020 switch ((swizzle & ~3) + 1) { 1021 case DC_SW_256B_S: 1022 block_size_log2 = 8; 1023 break; 1024 case DC_SW_4KB_S: 1025 case DC_SW_4KB_S_X: 1026 block_size_log2 = 12; 1027 break; 1028 case DC_SW_64KB_S: 1029 case DC_SW_64KB_S_T: 1030 case DC_SW_64KB_S_X: 1031 block_size_log2 = 16; 1032 break; 1033 case DC_SW_VAR_S_X: 1034 block_size_log2 = 18; 1035 break; 1036 default: 1037 drm_dbg_kms(rfb->base.dev, 1038 "Swizzle mode with unknown block size: %d\n", swizzle); 1039 return -EINVAL; 1040 } 1041 1042 get_block_dimensions(block_size_log2, format_info->cpp[i], 1043 &block_width, &block_height); 1044 } 1045 1046 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1047 block_width, block_height, block_size_log2); 1048 if (ret) 1049 return ret; 1050 } 1051 1052 if (AMD_FMT_MOD_GET(DCC, modifier)) { 1053 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { 1054 block_size_log2 = get_dcc_block_size(modifier, false, false); 1055 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1056 &block_width, &block_height); 1057 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1058 block_width, block_height, 1059 block_size_log2); 1060 if (ret) 1061 return ret; 1062 1063 ++i; 1064 block_size_log2 = get_dcc_block_size(modifier, true, true); 1065 } else { 1066 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); 1067 1068 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); 1069 } 1070 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1071 &block_width, &block_height); 1072 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1073 block_width, block_height, block_size_log2); 1074 if (ret) 1075 return ret; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1082 uint64_t *tiling_flags, bool *tmz_surface) 1083 { 1084 struct amdgpu_bo *rbo; 1085 int r; 1086 1087 if (!amdgpu_fb) { 1088 *tiling_flags = 0; 1089 *tmz_surface = false; 1090 return 0; 1091 } 1092 1093 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1094 r = amdgpu_bo_reserve(rbo, false); 1095 1096 if (unlikely(r)) { 1097 /* Don't show error message when returning -ERESTARTSYS */ 1098 if (r != -ERESTARTSYS) 1099 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1100 return r; 1101 } 1102 1103 if (tiling_flags) 1104 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1105 1106 if (tmz_surface) 1107 *tmz_surface = amdgpu_bo_encrypted(rbo); 1108 1109 amdgpu_bo_unreserve(rbo); 1110 1111 return r; 1112 } 1113 1114 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, 1115 struct amdgpu_framebuffer *rfb, 1116 struct drm_file *file_priv, 1117 const struct drm_mode_fb_cmd2 *mode_cmd, 1118 struct drm_gem_object *obj) 1119 { 1120 int ret; 1121 1122 rfb->base.obj[0] = obj; 1123 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1124 /* Verify that the modifier is supported. */ 1125 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, 1126 mode_cmd->modifier[0])) { 1127 drm_dbg_kms(dev, 1128 "unsupported pixel format %p4cc / modifier 0x%llx\n", 1129 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 1130 1131 ret = -EINVAL; 1132 goto err; 1133 } 1134 1135 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); 1136 if (ret) 1137 goto err; 1138 1139 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 1140 1141 if (ret) 1142 goto err; 1143 1144 return 0; 1145 err: 1146 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); 1147 rfb->base.obj[0] = NULL; 1148 return ret; 1149 } 1150 1151 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 1152 struct amdgpu_framebuffer *rfb, 1153 const struct drm_mode_fb_cmd2 *mode_cmd, 1154 struct drm_gem_object *obj) 1155 { 1156 struct amdgpu_device *adev = drm_to_adev(dev); 1157 int ret, i; 1158 1159 /* 1160 * This needs to happen before modifier conversion as that might change 1161 * the number of planes. 1162 */ 1163 for (i = 1; i < rfb->base.format->num_planes; ++i) { 1164 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 1165 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", 1166 i, mode_cmd->handles[0], mode_cmd->handles[i]); 1167 ret = -EINVAL; 1168 return ret; 1169 } 1170 } 1171 1172 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 1173 if (ret) 1174 return ret; 1175 1176 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { 1177 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, 1178 "GFX9+ requires FB check based on format modifier\n"); 1179 ret = check_tiling_flags_gfx6(rfb); 1180 if (ret) 1181 return ret; 1182 } 1183 1184 if (!dev->mode_config.fb_modifiers_not_supported && 1185 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { 1186 ret = convert_tiling_flags_to_modifier(rfb); 1187 if (ret) { 1188 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier", 1189 rfb->tiling_flags); 1190 return ret; 1191 } 1192 } 1193 1194 ret = amdgpu_display_verify_sizes(rfb); 1195 if (ret) 1196 return ret; 1197 1198 for (i = 0; i < rfb->base.format->num_planes; ++i) { 1199 drm_gem_object_get(rfb->base.obj[0]); 1200 rfb->base.obj[i] = rfb->base.obj[0]; 1201 } 1202 1203 return 0; 1204 } 1205 1206 struct drm_framebuffer * 1207 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 1208 struct drm_file *file_priv, 1209 const struct drm_mode_fb_cmd2 *mode_cmd) 1210 { 1211 struct amdgpu_framebuffer *amdgpu_fb; 1212 struct drm_gem_object *obj; 1213 struct amdgpu_bo *bo; 1214 uint32_t domains; 1215 int ret; 1216 1217 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1218 if (obj == NULL) { 1219 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " 1220 "can't create framebuffer\n", mode_cmd->handles[0]); 1221 return ERR_PTR(-ENOENT); 1222 } 1223 1224 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1225 bo = gem_to_amdgpu_bo(obj); 1226 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); 1227 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { 1228 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); 1229 drm_gem_object_put(obj); 1230 return ERR_PTR(-EINVAL); 1231 } 1232 1233 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 1234 if (amdgpu_fb == NULL) { 1235 drm_gem_object_put(obj); 1236 return ERR_PTR(-ENOMEM); 1237 } 1238 1239 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, 1240 mode_cmd, obj); 1241 if (ret) { 1242 kfree(amdgpu_fb); 1243 drm_gem_object_put(obj); 1244 return ERR_PTR(ret); 1245 } 1246 1247 drm_gem_object_put(obj); 1248 return &amdgpu_fb->base; 1249 } 1250 1251 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 1252 .fb_create = amdgpu_display_user_framebuffer_create, 1253 }; 1254 1255 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 1256 { { UNDERSCAN_OFF, "off" }, 1257 { UNDERSCAN_ON, "on" }, 1258 { UNDERSCAN_AUTO, "auto" }, 1259 }; 1260 1261 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 1262 { { AMDGPU_AUDIO_DISABLE, "off" }, 1263 { AMDGPU_AUDIO_ENABLE, "on" }, 1264 { AMDGPU_AUDIO_AUTO, "auto" }, 1265 }; 1266 1267 /* XXX support different dither options? spatial, temporal, both, etc. */ 1268 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 1269 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 1270 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 1271 }; 1272 1273 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 1274 { 1275 int sz; 1276 1277 adev->mode_info.coherent_mode_property = 1278 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 1279 if (!adev->mode_info.coherent_mode_property) 1280 return -ENOMEM; 1281 1282 adev->mode_info.load_detect_property = 1283 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 1284 if (!adev->mode_info.load_detect_property) 1285 return -ENOMEM; 1286 1287 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 1288 1289 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 1290 adev->mode_info.underscan_property = 1291 drm_property_create_enum(adev_to_drm(adev), 0, 1292 "underscan", 1293 amdgpu_underscan_enum_list, sz); 1294 1295 adev->mode_info.underscan_hborder_property = 1296 drm_property_create_range(adev_to_drm(adev), 0, 1297 "underscan hborder", 0, 128); 1298 if (!adev->mode_info.underscan_hborder_property) 1299 return -ENOMEM; 1300 1301 adev->mode_info.underscan_vborder_property = 1302 drm_property_create_range(adev_to_drm(adev), 0, 1303 "underscan vborder", 0, 128); 1304 if (!adev->mode_info.underscan_vborder_property) 1305 return -ENOMEM; 1306 1307 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 1308 adev->mode_info.audio_property = 1309 drm_property_create_enum(adev_to_drm(adev), 0, 1310 "audio", 1311 amdgpu_audio_enum_list, sz); 1312 1313 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 1314 adev->mode_info.dither_property = 1315 drm_property_create_enum(adev_to_drm(adev), 0, 1316 "dither", 1317 amdgpu_dither_enum_list, sz); 1318 1319 if (adev->dc_enabled) { 1320 adev->mode_info.abm_level_property = 1321 drm_property_create_range(adev_to_drm(adev), 0, 1322 "abm level", 0, 4); 1323 if (!adev->mode_info.abm_level_property) 1324 return -ENOMEM; 1325 } 1326 1327 return 0; 1328 } 1329 1330 void amdgpu_display_update_priority(struct amdgpu_device *adev) 1331 { 1332 /* adjustment options for the display watermarks */ 1333 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 1334 adev->mode_info.disp_priority = 0; 1335 else 1336 adev->mode_info.disp_priority = amdgpu_disp_priority; 1337 1338 } 1339 1340 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 1341 { 1342 /* try and guess if this is a tv or a monitor */ 1343 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1344 (mode->vdisplay == 576) || /* 576p */ 1345 (mode->vdisplay == 720) || /* 720p */ 1346 (mode->vdisplay == 1080)) /* 1080p */ 1347 return true; 1348 else 1349 return false; 1350 } 1351 1352 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1353 const struct drm_display_mode *mode, 1354 struct drm_display_mode *adjusted_mode) 1355 { 1356 struct drm_device *dev = crtc->dev; 1357 struct drm_encoder *encoder; 1358 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1359 struct amdgpu_encoder *amdgpu_encoder; 1360 struct drm_connector *connector; 1361 u32 src_v = 1, dst_v = 1; 1362 u32 src_h = 1, dst_h = 1; 1363 1364 amdgpu_crtc->h_border = 0; 1365 amdgpu_crtc->v_border = 0; 1366 1367 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1368 if (encoder->crtc != crtc) 1369 continue; 1370 amdgpu_encoder = to_amdgpu_encoder(encoder); 1371 connector = amdgpu_get_connector_for_encoder(encoder); 1372 1373 /* set scaling */ 1374 if (amdgpu_encoder->rmx_type == RMX_OFF) 1375 amdgpu_crtc->rmx_type = RMX_OFF; 1376 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 1377 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 1378 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 1379 else 1380 amdgpu_crtc->rmx_type = RMX_OFF; 1381 /* copy native mode */ 1382 memcpy(&amdgpu_crtc->native_mode, 1383 &amdgpu_encoder->native_mode, 1384 sizeof(struct drm_display_mode)); 1385 src_v = crtc->mode.vdisplay; 1386 dst_v = amdgpu_crtc->native_mode.vdisplay; 1387 src_h = crtc->mode.hdisplay; 1388 dst_h = amdgpu_crtc->native_mode.hdisplay; 1389 1390 /* fix up for overscan on hdmi */ 1391 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1392 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 1393 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 1394 connector->display_info.is_hdmi && 1395 amdgpu_display_is_hdtv_mode(mode)))) { 1396 if (amdgpu_encoder->underscan_hborder != 0) 1397 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 1398 else 1399 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 1400 if (amdgpu_encoder->underscan_vborder != 0) 1401 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 1402 else 1403 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 1404 amdgpu_crtc->rmx_type = RMX_FULL; 1405 src_v = crtc->mode.vdisplay; 1406 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 1407 src_h = crtc->mode.hdisplay; 1408 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 1409 } 1410 } 1411 if (amdgpu_crtc->rmx_type != RMX_OFF) { 1412 fixed20_12 a, b; 1413 a.full = dfixed_const(src_v); 1414 b.full = dfixed_const(dst_v); 1415 amdgpu_crtc->vsc.full = dfixed_div(a, b); 1416 a.full = dfixed_const(src_h); 1417 b.full = dfixed_const(dst_h); 1418 amdgpu_crtc->hsc.full = dfixed_div(a, b); 1419 } else { 1420 amdgpu_crtc->vsc.full = dfixed_const(1); 1421 amdgpu_crtc->hsc.full = dfixed_const(1); 1422 } 1423 return true; 1424 } 1425 1426 /* 1427 * Retrieve current video scanout position of crtc on a given gpu, and 1428 * an optional accurate timestamp of when query happened. 1429 * 1430 * \param dev Device to query. 1431 * \param pipe Crtc to query. 1432 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1433 * For driver internal use only also supports these flags: 1434 * 1435 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1436 * of a fudged earlier start of vblank. 1437 * 1438 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1439 * fudged earlier start of vblank in *vpos and the distance 1440 * to true start of vblank in *hpos. 1441 * 1442 * \param *vpos Location where vertical scanout position should be stored. 1443 * \param *hpos Location where horizontal scanout position should go. 1444 * \param *stime Target location for timestamp taken immediately before 1445 * scanout position query. Can be NULL to skip timestamp. 1446 * \param *etime Target location for timestamp taken immediately after 1447 * scanout position query. Can be NULL to skip timestamp. 1448 * 1449 * Returns vpos as a positive number while in active scanout area. 1450 * Returns vpos as a negative number inside vblank, counting the number 1451 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1452 * until start of active scanout / end of vblank." 1453 * 1454 * \return Flags, or'ed together as follows: 1455 * 1456 * DRM_SCANOUTPOS_VALID = Query successful. 1457 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1458 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1459 * this flag means that returned position may be offset by a constant but 1460 * unknown small number of scanlines wrt. real scanout position. 1461 * 1462 */ 1463 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 1464 unsigned int pipe, unsigned int flags, int *vpos, 1465 int *hpos, ktime_t *stime, ktime_t *etime, 1466 const struct drm_display_mode *mode) 1467 { 1468 u32 vbl = 0, position = 0; 1469 int vbl_start, vbl_end, vtotal, ret = 0; 1470 bool in_vbl = true; 1471 1472 struct amdgpu_device *adev = drm_to_adev(dev); 1473 1474 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1475 1476 /* Get optional system timestamp before query. */ 1477 if (stime) 1478 *stime = ktime_get(); 1479 1480 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 1481 ret |= DRM_SCANOUTPOS_VALID; 1482 1483 /* Get optional system timestamp after query. */ 1484 if (etime) 1485 *etime = ktime_get(); 1486 1487 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1488 1489 /* Decode into vertical and horizontal scanout position. */ 1490 *vpos = position & 0x1fff; 1491 *hpos = (position >> 16) & 0x1fff; 1492 1493 /* Valid vblank area boundaries from gpu retrieved? */ 1494 if (vbl > 0) { 1495 /* Yes: Decode. */ 1496 ret |= DRM_SCANOUTPOS_ACCURATE; 1497 vbl_start = vbl & 0x1fff; 1498 vbl_end = (vbl >> 16) & 0x1fff; 1499 } 1500 else { 1501 /* No: Fake something reasonable which gives at least ok results. */ 1502 vbl_start = mode->crtc_vdisplay; 1503 vbl_end = 0; 1504 } 1505 1506 /* Called from driver internal vblank counter query code? */ 1507 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1508 /* Caller wants distance from real vbl_start in *hpos */ 1509 *hpos = *vpos - vbl_start; 1510 } 1511 1512 /* Fudge vblank to start a few scanlines earlier to handle the 1513 * problem that vblank irqs fire a few scanlines before start 1514 * of vblank. Some driver internal callers need the true vblank 1515 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1516 * 1517 * The cause of the "early" vblank irq is that the irq is triggered 1518 * by the line buffer logic when the line buffer read position enters 1519 * the vblank, whereas our crtc scanout position naturally lags the 1520 * line buffer read position. 1521 */ 1522 if (!(flags & USE_REAL_VBLANKSTART)) 1523 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1524 1525 /* Test scanout position against vblank region. */ 1526 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1527 in_vbl = false; 1528 1529 /* In vblank? */ 1530 if (in_vbl) 1531 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1532 1533 /* Called from driver internal vblank counter query code? */ 1534 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1535 /* Caller wants distance from fudged earlier vbl_start */ 1536 *vpos -= vbl_start; 1537 return ret; 1538 } 1539 1540 /* Check if inside vblank area and apply corrective offsets: 1541 * vpos will then be >=0 in video scanout area, but negative 1542 * within vblank area, counting down the number of lines until 1543 * start of scanout. 1544 */ 1545 1546 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1547 if (in_vbl && (*vpos >= vbl_start)) { 1548 vtotal = mode->crtc_vtotal; 1549 1550 /* With variable refresh rate displays the vpos can exceed 1551 * the vtotal value. Clamp to 0 to return -vbl_end instead 1552 * of guessing the remaining number of lines until scanout. 1553 */ 1554 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 1555 } 1556 1557 /* Correct for shifted end of vbl at vbl_end. */ 1558 *vpos = *vpos - vbl_end; 1559 1560 return ret; 1561 } 1562 1563 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 1564 { 1565 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 1566 return AMDGPU_CRTC_IRQ_NONE; 1567 1568 switch (crtc) { 1569 case 0: 1570 return AMDGPU_CRTC_IRQ_VBLANK1; 1571 case 1: 1572 return AMDGPU_CRTC_IRQ_VBLANK2; 1573 case 2: 1574 return AMDGPU_CRTC_IRQ_VBLANK3; 1575 case 3: 1576 return AMDGPU_CRTC_IRQ_VBLANK4; 1577 case 4: 1578 return AMDGPU_CRTC_IRQ_VBLANK5; 1579 case 5: 1580 return AMDGPU_CRTC_IRQ_VBLANK6; 1581 default: 1582 return AMDGPU_CRTC_IRQ_NONE; 1583 } 1584 } 1585 1586 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 1587 bool in_vblank_irq, int *vpos, 1588 int *hpos, ktime_t *stime, ktime_t *etime, 1589 const struct drm_display_mode *mode) 1590 { 1591 struct drm_device *dev = crtc->dev; 1592 unsigned int pipe = crtc->index; 1593 1594 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1595 stime, etime, mode); 1596 } 1597 1598 static bool 1599 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) 1600 { 1601 struct drm_device *dev = adev_to_drm(adev); 1602 struct drm_fb_helper *fb_helper = dev->fb_helper; 1603 1604 if (!fb_helper || !fb_helper->buffer) 1605 return false; 1606 1607 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj) 1608 return false; 1609 1610 return true; 1611 } 1612 1613 int amdgpu_display_suspend_helper(struct amdgpu_device *adev) 1614 { 1615 struct drm_device *dev = adev_to_drm(adev); 1616 struct drm_crtc *crtc; 1617 struct drm_connector *connector; 1618 struct drm_connector_list_iter iter; 1619 int r; 1620 1621 drm_kms_helper_poll_disable(dev); 1622 1623 /* turn off display hw */ 1624 drm_modeset_lock_all(dev); 1625 drm_connector_list_iter_begin(dev, &iter); 1626 drm_for_each_connector_iter(connector, &iter) 1627 drm_helper_connector_dpms(connector, 1628 DRM_MODE_DPMS_OFF); 1629 drm_connector_list_iter_end(&iter); 1630 drm_modeset_unlock_all(dev); 1631 /* unpin the front buffers and cursors */ 1632 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1634 struct drm_framebuffer *fb = crtc->primary->fb; 1635 struct amdgpu_bo *robj; 1636 1637 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1638 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1639 r = amdgpu_bo_reserve(aobj, true); 1640 if (r == 0) { 1641 amdgpu_bo_unpin(aobj); 1642 amdgpu_bo_unreserve(aobj); 1643 } 1644 } 1645 1646 if (fb == NULL || fb->obj[0] == NULL) { 1647 continue; 1648 } 1649 robj = gem_to_amdgpu_bo(fb->obj[0]); 1650 if (!amdgpu_display_robj_is_fb(adev, robj)) { 1651 r = amdgpu_bo_reserve(robj, true); 1652 if (r == 0) { 1653 amdgpu_bo_unpin(robj); 1654 amdgpu_bo_unreserve(robj); 1655 } 1656 } 1657 } 1658 return 0; 1659 } 1660 1661 int amdgpu_display_resume_helper(struct amdgpu_device *adev) 1662 { 1663 struct drm_device *dev = adev_to_drm(adev); 1664 struct drm_connector *connector; 1665 struct drm_connector_list_iter iter; 1666 struct drm_crtc *crtc; 1667 int r; 1668 1669 /* pin cursors */ 1670 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1671 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1672 1673 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1674 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1675 r = amdgpu_bo_reserve(aobj, true); 1676 if (r == 0) { 1677 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 1678 if (r != 0) 1679 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 1680 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 1681 amdgpu_bo_unreserve(aobj); 1682 } 1683 } 1684 } 1685 1686 drm_helper_resume_force_mode(dev); 1687 1688 /* turn on display hw */ 1689 drm_modeset_lock_all(dev); 1690 1691 drm_connector_list_iter_begin(dev, &iter); 1692 drm_for_each_connector_iter(connector, &iter) 1693 drm_helper_connector_dpms(connector, 1694 DRM_MODE_DPMS_ON); 1695 drm_connector_list_iter_end(&iter); 1696 1697 drm_modeset_unlock_all(dev); 1698 1699 drm_kms_helper_poll_enable(dev); 1700 1701 return 0; 1702 } 1703 1704