1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include <asm/div64.h> 33 34 #include <linux/pm_runtime.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_edid.h> 37 38 static void amdgpu_flip_wait_fence(struct amdgpu_device *adev, 39 struct fence **f) 40 { 41 struct amdgpu_fence *fence; 42 long r; 43 44 if (*f == NULL) 45 return; 46 47 fence = to_amdgpu_fence(*f); 48 if (fence) { 49 r = fence_wait(&fence->base, false); 50 if (r == -EDEADLK) 51 r = amdgpu_gpu_reset(adev); 52 } else 53 r = fence_wait(*f, false); 54 55 if (r) 56 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r); 57 58 /* We continue with the page flip even if we failed to wait on 59 * the fence, otherwise the DRM core and userspace will be 60 * confused about which BO the CRTC is scanning out 61 */ 62 fence_put(*f); 63 *f = NULL; 64 } 65 66 static void amdgpu_flip_work_func(struct work_struct *__work) 67 { 68 struct amdgpu_flip_work *work = 69 container_of(__work, struct amdgpu_flip_work, flip_work); 70 struct amdgpu_device *adev = work->adev; 71 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; 72 73 struct drm_crtc *crtc = &amdgpuCrtc->base; 74 unsigned long flags; 75 unsigned i; 76 int vpos, hpos, stat, min_udelay; 77 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 78 79 amdgpu_flip_wait_fence(adev, &work->excl); 80 for (i = 0; i < work->shared_count; ++i) 81 amdgpu_flip_wait_fence(adev, &work->shared[i]); 82 83 /* We borrow the event spin lock for protecting flip_status */ 84 spin_lock_irqsave(&crtc->dev->event_lock, flags); 85 86 /* If this happens to execute within the "virtually extended" vblank 87 * interval before the start of the real vblank interval then it needs 88 * to delay programming the mmio flip until the real vblank is entered. 89 * This prevents completing a flip too early due to the way we fudge 90 * our vblank counter and vblank timestamps in order to work around the 91 * problem that the hw fires vblank interrupts before actual start of 92 * vblank (when line buffer refilling is done for a frame). It 93 * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for 94 * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. 95 * 96 * In practice this won't execute very often unless on very fast 97 * machines because the time window for this to happen is very small. 98 */ 99 for (;;) { 100 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 101 * start in hpos, and to the "fudged earlier" vblank start in 102 * vpos. 103 */ 104 stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 105 GET_DISTANCE_TO_VBLANKSTART, 106 &vpos, &hpos, NULL, NULL, 107 &crtc->hwmode); 108 109 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 110 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 111 !(vpos >= 0 && hpos <= 0)) 112 break; 113 114 /* Sleep at least until estimated real start of hw vblank */ 115 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 116 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 117 usleep_range(min_udelay, 2 * min_udelay); 118 spin_lock_irqsave(&crtc->dev->event_lock, flags); 119 }; 120 121 /* do the flip (mmio) */ 122 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); 123 /* set the flip status */ 124 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 125 126 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 127 } 128 129 /* 130 * Handle unpin events outside the interrupt handler proper. 131 */ 132 static void amdgpu_unpin_work_func(struct work_struct *__work) 133 { 134 struct amdgpu_flip_work *work = 135 container_of(__work, struct amdgpu_flip_work, unpin_work); 136 int r; 137 138 /* unpin of the old buffer */ 139 r = amdgpu_bo_reserve(work->old_rbo, false); 140 if (likely(r == 0)) { 141 r = amdgpu_bo_unpin(work->old_rbo); 142 if (unlikely(r != 0)) { 143 DRM_ERROR("failed to unpin buffer after flip\n"); 144 } 145 amdgpu_bo_unreserve(work->old_rbo); 146 } else 147 DRM_ERROR("failed to reserve buffer after flip\n"); 148 149 amdgpu_bo_unref(&work->old_rbo); 150 kfree(work->shared); 151 kfree(work); 152 } 153 154 int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 155 struct drm_framebuffer *fb, 156 struct drm_pending_vblank_event *event, 157 uint32_t page_flip_flags) 158 { 159 struct drm_device *dev = crtc->dev; 160 struct amdgpu_device *adev = dev->dev_private; 161 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 162 struct amdgpu_framebuffer *old_amdgpu_fb; 163 struct amdgpu_framebuffer *new_amdgpu_fb; 164 struct drm_gem_object *obj; 165 struct amdgpu_flip_work *work; 166 struct amdgpu_bo *new_rbo; 167 unsigned long flags; 168 u64 tiling_flags; 169 u64 base; 170 int i, r; 171 172 work = kzalloc(sizeof *work, GFP_KERNEL); 173 if (work == NULL) 174 return -ENOMEM; 175 176 INIT_WORK(&work->flip_work, amdgpu_flip_work_func); 177 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); 178 179 work->event = event; 180 work->adev = adev; 181 work->crtc_id = amdgpu_crtc->crtc_id; 182 183 /* schedule unpin of the old buffer */ 184 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 185 obj = old_amdgpu_fb->obj; 186 187 /* take a reference to the old object */ 188 work->old_rbo = gem_to_amdgpu_bo(obj); 189 amdgpu_bo_ref(work->old_rbo); 190 191 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 192 obj = new_amdgpu_fb->obj; 193 new_rbo = gem_to_amdgpu_bo(obj); 194 195 /* pin the new buffer */ 196 r = amdgpu_bo_reserve(new_rbo, false); 197 if (unlikely(r != 0)) { 198 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 199 goto cleanup; 200 } 201 202 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 203 if (unlikely(r != 0)) { 204 amdgpu_bo_unreserve(new_rbo); 205 r = -EINVAL; 206 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 207 goto cleanup; 208 } 209 210 r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, 211 &work->shared_count, 212 &work->shared); 213 if (unlikely(r != 0)) { 214 amdgpu_bo_unreserve(new_rbo); 215 DRM_ERROR("failed to get fences for buffer\n"); 216 goto cleanup; 217 } 218 219 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); 220 amdgpu_bo_unreserve(new_rbo); 221 222 work->base = base; 223 224 r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); 225 if (r) { 226 DRM_ERROR("failed to get vblank before flip\n"); 227 goto pflip_cleanup; 228 } 229 230 /* we borrow the event spin lock for protecting flip_wrok */ 231 spin_lock_irqsave(&crtc->dev->event_lock, flags); 232 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 233 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 234 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 235 r = -EBUSY; 236 goto vblank_cleanup; 237 } 238 239 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 240 amdgpu_crtc->pflip_works = work; 241 242 /* update crtc fb */ 243 crtc->primary->fb = fb; 244 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 245 queue_work(amdgpu_crtc->pflip_queue, &work->flip_work); 246 return 0; 247 248 vblank_cleanup: 249 drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); 250 251 pflip_cleanup: 252 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { 253 DRM_ERROR("failed to reserve new rbo in error path\n"); 254 goto cleanup; 255 } 256 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { 257 DRM_ERROR("failed to unpin new rbo in error path\n"); 258 } 259 amdgpu_bo_unreserve(new_rbo); 260 261 cleanup: 262 amdgpu_bo_unref(&work->old_rbo); 263 fence_put(work->excl); 264 for (i = 0; i < work->shared_count; ++i) 265 fence_put(work->shared[i]); 266 kfree(work->shared); 267 kfree(work); 268 269 return r; 270 } 271 272 int amdgpu_crtc_set_config(struct drm_mode_set *set) 273 { 274 struct drm_device *dev; 275 struct amdgpu_device *adev; 276 struct drm_crtc *crtc; 277 bool active = false; 278 int ret; 279 280 if (!set || !set->crtc) 281 return -EINVAL; 282 283 dev = set->crtc->dev; 284 285 ret = pm_runtime_get_sync(dev->dev); 286 if (ret < 0) 287 return ret; 288 289 ret = drm_crtc_helper_set_config(set); 290 291 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 292 if (crtc->enabled) 293 active = true; 294 295 pm_runtime_mark_last_busy(dev->dev); 296 297 adev = dev->dev_private; 298 /* if we have active crtcs and we don't have a power ref, 299 take the current one */ 300 if (active && !adev->have_disp_power_ref) { 301 adev->have_disp_power_ref = true; 302 return ret; 303 } 304 /* if we have no active crtcs, then drop the power ref 305 we got before */ 306 if (!active && adev->have_disp_power_ref) { 307 pm_runtime_put_autosuspend(dev->dev); 308 adev->have_disp_power_ref = false; 309 } 310 311 /* drop the power reference we got coming in here */ 312 pm_runtime_put_autosuspend(dev->dev); 313 return ret; 314 } 315 316 static const char *encoder_names[38] = { 317 "NONE", 318 "INTERNAL_LVDS", 319 "INTERNAL_TMDS1", 320 "INTERNAL_TMDS2", 321 "INTERNAL_DAC1", 322 "INTERNAL_DAC2", 323 "INTERNAL_SDVOA", 324 "INTERNAL_SDVOB", 325 "SI170B", 326 "CH7303", 327 "CH7301", 328 "INTERNAL_DVO1", 329 "EXTERNAL_SDVOA", 330 "EXTERNAL_SDVOB", 331 "TITFP513", 332 "INTERNAL_LVTM1", 333 "VT1623", 334 "HDMI_SI1930", 335 "HDMI_INTERNAL", 336 "INTERNAL_KLDSCP_TMDS1", 337 "INTERNAL_KLDSCP_DVO1", 338 "INTERNAL_KLDSCP_DAC1", 339 "INTERNAL_KLDSCP_DAC2", 340 "SI178", 341 "MVPU_FPGA", 342 "INTERNAL_DDI", 343 "VT1625", 344 "HDMI_SI1932", 345 "DP_AN9801", 346 "DP_DP501", 347 "INTERNAL_UNIPHY", 348 "INTERNAL_KLDSCP_LVTMA", 349 "INTERNAL_UNIPHY1", 350 "INTERNAL_UNIPHY2", 351 "NUTMEG", 352 "TRAVIS", 353 "INTERNAL_VCE", 354 "INTERNAL_UNIPHY3", 355 }; 356 357 static const char *hpd_names[6] = { 358 "HPD1", 359 "HPD2", 360 "HPD3", 361 "HPD4", 362 "HPD5", 363 "HPD6", 364 }; 365 366 void amdgpu_print_display_setup(struct drm_device *dev) 367 { 368 struct drm_connector *connector; 369 struct amdgpu_connector *amdgpu_connector; 370 struct drm_encoder *encoder; 371 struct amdgpu_encoder *amdgpu_encoder; 372 uint32_t devices; 373 int i = 0; 374 375 DRM_INFO("AMDGPU Display Connectors\n"); 376 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 377 amdgpu_connector = to_amdgpu_connector(connector); 378 DRM_INFO("Connector %d:\n", i); 379 DRM_INFO(" %s\n", connector->name); 380 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 381 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 382 if (amdgpu_connector->ddc_bus) { 383 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 384 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 385 amdgpu_connector->ddc_bus->rec.mask_data_reg, 386 amdgpu_connector->ddc_bus->rec.a_clk_reg, 387 amdgpu_connector->ddc_bus->rec.a_data_reg, 388 amdgpu_connector->ddc_bus->rec.en_clk_reg, 389 amdgpu_connector->ddc_bus->rec.en_data_reg, 390 amdgpu_connector->ddc_bus->rec.y_clk_reg, 391 amdgpu_connector->ddc_bus->rec.y_data_reg); 392 if (amdgpu_connector->router.ddc_valid) 393 DRM_INFO(" DDC Router 0x%x/0x%x\n", 394 amdgpu_connector->router.ddc_mux_control_pin, 395 amdgpu_connector->router.ddc_mux_state); 396 if (amdgpu_connector->router.cd_valid) 397 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 398 amdgpu_connector->router.cd_mux_control_pin, 399 amdgpu_connector->router.cd_mux_state); 400 } else { 401 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 402 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 403 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 404 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 405 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 406 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 407 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 408 } 409 DRM_INFO(" Encoders:\n"); 410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 411 amdgpu_encoder = to_amdgpu_encoder(encoder); 412 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 413 if (devices) { 414 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 415 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 416 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 417 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 418 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 419 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 420 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 421 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 422 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 423 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 424 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 425 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 426 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 427 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 428 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 429 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 430 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 431 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 432 if (devices & ATOM_DEVICE_TV1_SUPPORT) 433 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 434 if (devices & ATOM_DEVICE_CV_SUPPORT) 435 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 436 } 437 } 438 i++; 439 } 440 } 441 442 /** 443 * amdgpu_ddc_probe 444 * 445 */ 446 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, 447 bool use_aux) 448 { 449 u8 out = 0x0; 450 u8 buf[8]; 451 int ret; 452 struct i2c_msg msgs[] = { 453 { 454 .addr = DDC_ADDR, 455 .flags = 0, 456 .len = 1, 457 .buf = &out, 458 }, 459 { 460 .addr = DDC_ADDR, 461 .flags = I2C_M_RD, 462 .len = 8, 463 .buf = buf, 464 } 465 }; 466 467 /* on hw with routers, select right port */ 468 if (amdgpu_connector->router.ddc_valid) 469 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 470 471 if (use_aux) { 472 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 473 } else { 474 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 475 } 476 477 if (ret != 2) 478 /* Couldn't find an accessible DDC on this connector */ 479 return false; 480 /* Probe also for valid EDID header 481 * EDID header starts with: 482 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 483 * Only the first 6 bytes must be valid as 484 * drm_edid_block_valid() can fix the last 2 bytes */ 485 if (drm_edid_header_is_valid(buf) < 6) { 486 /* Couldn't find an accessible EDID on this 487 * connector */ 488 return false; 489 } 490 return true; 491 } 492 493 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) 494 { 495 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 496 497 if (amdgpu_fb->obj) { 498 drm_gem_object_unreference_unlocked(amdgpu_fb->obj); 499 } 500 drm_framebuffer_cleanup(fb); 501 kfree(amdgpu_fb); 502 } 503 504 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, 505 struct drm_file *file_priv, 506 unsigned int *handle) 507 { 508 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 509 510 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); 511 } 512 513 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 514 .destroy = amdgpu_user_framebuffer_destroy, 515 .create_handle = amdgpu_user_framebuffer_create_handle, 516 }; 517 518 int 519 amdgpu_framebuffer_init(struct drm_device *dev, 520 struct amdgpu_framebuffer *rfb, 521 struct drm_mode_fb_cmd2 *mode_cmd, 522 struct drm_gem_object *obj) 523 { 524 int ret; 525 rfb->obj = obj; 526 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 527 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 528 if (ret) { 529 rfb->obj = NULL; 530 return ret; 531 } 532 return 0; 533 } 534 535 static struct drm_framebuffer * 536 amdgpu_user_framebuffer_create(struct drm_device *dev, 537 struct drm_file *file_priv, 538 struct drm_mode_fb_cmd2 *mode_cmd) 539 { 540 struct drm_gem_object *obj; 541 struct amdgpu_framebuffer *amdgpu_fb; 542 int ret; 543 544 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 545 if (obj == NULL) { 546 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 547 "can't create framebuffer\n", mode_cmd->handles[0]); 548 return ERR_PTR(-ENOENT); 549 } 550 551 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 552 if (amdgpu_fb == NULL) { 553 drm_gem_object_unreference_unlocked(obj); 554 return ERR_PTR(-ENOMEM); 555 } 556 557 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 558 if (ret) { 559 kfree(amdgpu_fb); 560 drm_gem_object_unreference_unlocked(obj); 561 return ERR_PTR(ret); 562 } 563 564 return &amdgpu_fb->base; 565 } 566 567 static void amdgpu_output_poll_changed(struct drm_device *dev) 568 { 569 struct amdgpu_device *adev = dev->dev_private; 570 amdgpu_fb_output_poll_changed(adev); 571 } 572 573 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 574 .fb_create = amdgpu_user_framebuffer_create, 575 .output_poll_changed = amdgpu_output_poll_changed 576 }; 577 578 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 579 { { UNDERSCAN_OFF, "off" }, 580 { UNDERSCAN_ON, "on" }, 581 { UNDERSCAN_AUTO, "auto" }, 582 }; 583 584 static struct drm_prop_enum_list amdgpu_audio_enum_list[] = 585 { { AMDGPU_AUDIO_DISABLE, "off" }, 586 { AMDGPU_AUDIO_ENABLE, "on" }, 587 { AMDGPU_AUDIO_AUTO, "auto" }, 588 }; 589 590 /* XXX support different dither options? spatial, temporal, both, etc. */ 591 static struct drm_prop_enum_list amdgpu_dither_enum_list[] = 592 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 593 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 594 }; 595 596 int amdgpu_modeset_create_props(struct amdgpu_device *adev) 597 { 598 int sz; 599 600 if (adev->is_atom_bios) { 601 adev->mode_info.coherent_mode_property = 602 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 603 if (!adev->mode_info.coherent_mode_property) 604 return -ENOMEM; 605 } 606 607 adev->mode_info.load_detect_property = 608 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 609 if (!adev->mode_info.load_detect_property) 610 return -ENOMEM; 611 612 drm_mode_create_scaling_mode_property(adev->ddev); 613 614 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 615 adev->mode_info.underscan_property = 616 drm_property_create_enum(adev->ddev, 0, 617 "underscan", 618 amdgpu_underscan_enum_list, sz); 619 620 adev->mode_info.underscan_hborder_property = 621 drm_property_create_range(adev->ddev, 0, 622 "underscan hborder", 0, 128); 623 if (!adev->mode_info.underscan_hborder_property) 624 return -ENOMEM; 625 626 adev->mode_info.underscan_vborder_property = 627 drm_property_create_range(adev->ddev, 0, 628 "underscan vborder", 0, 128); 629 if (!adev->mode_info.underscan_vborder_property) 630 return -ENOMEM; 631 632 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 633 adev->mode_info.audio_property = 634 drm_property_create_enum(adev->ddev, 0, 635 "audio", 636 amdgpu_audio_enum_list, sz); 637 638 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 639 adev->mode_info.dither_property = 640 drm_property_create_enum(adev->ddev, 0, 641 "dither", 642 amdgpu_dither_enum_list, sz); 643 644 return 0; 645 } 646 647 void amdgpu_update_display_priority(struct amdgpu_device *adev) 648 { 649 /* adjustment options for the display watermarks */ 650 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 651 adev->mode_info.disp_priority = 0; 652 else 653 adev->mode_info.disp_priority = amdgpu_disp_priority; 654 655 } 656 657 static bool is_hdtv_mode(const struct drm_display_mode *mode) 658 { 659 /* try and guess if this is a tv or a monitor */ 660 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 661 (mode->vdisplay == 576) || /* 576p */ 662 (mode->vdisplay == 720) || /* 720p */ 663 (mode->vdisplay == 1080)) /* 1080p */ 664 return true; 665 else 666 return false; 667 } 668 669 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 670 const struct drm_display_mode *mode, 671 struct drm_display_mode *adjusted_mode) 672 { 673 struct drm_device *dev = crtc->dev; 674 struct drm_encoder *encoder; 675 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 676 struct amdgpu_encoder *amdgpu_encoder; 677 struct drm_connector *connector; 678 struct amdgpu_connector *amdgpu_connector; 679 u32 src_v = 1, dst_v = 1; 680 u32 src_h = 1, dst_h = 1; 681 682 amdgpu_crtc->h_border = 0; 683 amdgpu_crtc->v_border = 0; 684 685 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 686 if (encoder->crtc != crtc) 687 continue; 688 amdgpu_encoder = to_amdgpu_encoder(encoder); 689 connector = amdgpu_get_connector_for_encoder(encoder); 690 amdgpu_connector = to_amdgpu_connector(connector); 691 692 /* set scaling */ 693 if (amdgpu_encoder->rmx_type == RMX_OFF) 694 amdgpu_crtc->rmx_type = RMX_OFF; 695 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 696 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 697 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 698 else 699 amdgpu_crtc->rmx_type = RMX_OFF; 700 /* copy native mode */ 701 memcpy(&amdgpu_crtc->native_mode, 702 &amdgpu_encoder->native_mode, 703 sizeof(struct drm_display_mode)); 704 src_v = crtc->mode.vdisplay; 705 dst_v = amdgpu_crtc->native_mode.vdisplay; 706 src_h = crtc->mode.hdisplay; 707 dst_h = amdgpu_crtc->native_mode.hdisplay; 708 709 /* fix up for overscan on hdmi */ 710 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 711 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 712 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 713 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 714 is_hdtv_mode(mode)))) { 715 if (amdgpu_encoder->underscan_hborder != 0) 716 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 717 else 718 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 719 if (amdgpu_encoder->underscan_vborder != 0) 720 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 721 else 722 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 723 amdgpu_crtc->rmx_type = RMX_FULL; 724 src_v = crtc->mode.vdisplay; 725 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 726 src_h = crtc->mode.hdisplay; 727 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 728 } 729 } 730 if (amdgpu_crtc->rmx_type != RMX_OFF) { 731 fixed20_12 a, b; 732 a.full = dfixed_const(src_v); 733 b.full = dfixed_const(dst_v); 734 amdgpu_crtc->vsc.full = dfixed_div(a, b); 735 a.full = dfixed_const(src_h); 736 b.full = dfixed_const(dst_h); 737 amdgpu_crtc->hsc.full = dfixed_div(a, b); 738 } else { 739 amdgpu_crtc->vsc.full = dfixed_const(1); 740 amdgpu_crtc->hsc.full = dfixed_const(1); 741 } 742 return true; 743 } 744 745 /* 746 * Retrieve current video scanout position of crtc on a given gpu, and 747 * an optional accurate timestamp of when query happened. 748 * 749 * \param dev Device to query. 750 * \param pipe Crtc to query. 751 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 752 * For driver internal use only also supports these flags: 753 * 754 * USE_REAL_VBLANKSTART to use the real start of vblank instead 755 * of a fudged earlier start of vblank. 756 * 757 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 758 * fudged earlier start of vblank in *vpos and the distance 759 * to true start of vblank in *hpos. 760 * 761 * \param *vpos Location where vertical scanout position should be stored. 762 * \param *hpos Location where horizontal scanout position should go. 763 * \param *stime Target location for timestamp taken immediately before 764 * scanout position query. Can be NULL to skip timestamp. 765 * \param *etime Target location for timestamp taken immediately after 766 * scanout position query. Can be NULL to skip timestamp. 767 * 768 * Returns vpos as a positive number while in active scanout area. 769 * Returns vpos as a negative number inside vblank, counting the number 770 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 771 * until start of active scanout / end of vblank." 772 * 773 * \return Flags, or'ed together as follows: 774 * 775 * DRM_SCANOUTPOS_VALID = Query successful. 776 * DRM_SCANOUTPOS_INVBL = Inside vblank. 777 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 778 * this flag means that returned position may be offset by a constant but 779 * unknown small number of scanlines wrt. real scanout position. 780 * 781 */ 782 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 783 unsigned int flags, int *vpos, int *hpos, 784 ktime_t *stime, ktime_t *etime, 785 const struct drm_display_mode *mode) 786 { 787 u32 vbl = 0, position = 0; 788 int vbl_start, vbl_end, vtotal, ret = 0; 789 bool in_vbl = true; 790 791 struct amdgpu_device *adev = dev->dev_private; 792 793 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 794 795 /* Get optional system timestamp before query. */ 796 if (stime) 797 *stime = ktime_get(); 798 799 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 800 ret |= DRM_SCANOUTPOS_VALID; 801 802 /* Get optional system timestamp after query. */ 803 if (etime) 804 *etime = ktime_get(); 805 806 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 807 808 /* Decode into vertical and horizontal scanout position. */ 809 *vpos = position & 0x1fff; 810 *hpos = (position >> 16) & 0x1fff; 811 812 /* Valid vblank area boundaries from gpu retrieved? */ 813 if (vbl > 0) { 814 /* Yes: Decode. */ 815 ret |= DRM_SCANOUTPOS_ACCURATE; 816 vbl_start = vbl & 0x1fff; 817 vbl_end = (vbl >> 16) & 0x1fff; 818 } 819 else { 820 /* No: Fake something reasonable which gives at least ok results. */ 821 vbl_start = mode->crtc_vdisplay; 822 vbl_end = 0; 823 } 824 825 /* Called from driver internal vblank counter query code? */ 826 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 827 /* Caller wants distance from real vbl_start in *hpos */ 828 *hpos = *vpos - vbl_start; 829 } 830 831 /* Fudge vblank to start a few scanlines earlier to handle the 832 * problem that vblank irqs fire a few scanlines before start 833 * of vblank. Some driver internal callers need the true vblank 834 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 835 * 836 * The cause of the "early" vblank irq is that the irq is triggered 837 * by the line buffer logic when the line buffer read position enters 838 * the vblank, whereas our crtc scanout position naturally lags the 839 * line buffer read position. 840 */ 841 if (!(flags & USE_REAL_VBLANKSTART)) 842 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 843 844 /* Test scanout position against vblank region. */ 845 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 846 in_vbl = false; 847 848 /* In vblank? */ 849 if (in_vbl) 850 ret |= DRM_SCANOUTPOS_IN_VBLANK; 851 852 /* Called from driver internal vblank counter query code? */ 853 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 854 /* Caller wants distance from fudged earlier vbl_start */ 855 *vpos -= vbl_start; 856 return ret; 857 } 858 859 /* Check if inside vblank area and apply corrective offsets: 860 * vpos will then be >=0 in video scanout area, but negative 861 * within vblank area, counting down the number of lines until 862 * start of scanout. 863 */ 864 865 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 866 if (in_vbl && (*vpos >= vbl_start)) { 867 vtotal = mode->crtc_vtotal; 868 *vpos = *vpos - vtotal; 869 } 870 871 /* Correct for shifted end of vbl at vbl_end. */ 872 *vpos = *vpos - vbl_end; 873 874 return ret; 875 } 876 877 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 878 { 879 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 880 return AMDGPU_CRTC_IRQ_NONE; 881 882 switch (crtc) { 883 case 0: 884 return AMDGPU_CRTC_IRQ_VBLANK1; 885 case 1: 886 return AMDGPU_CRTC_IRQ_VBLANK2; 887 case 2: 888 return AMDGPU_CRTC_IRQ_VBLANK3; 889 case 3: 890 return AMDGPU_CRTC_IRQ_VBLANK4; 891 case 4: 892 return AMDGPU_CRTC_IRQ_VBLANK5; 893 case 5: 894 return AMDGPU_CRTC_IRQ_VBLANK6; 895 default: 896 return AMDGPU_CRTC_IRQ_NONE; 897 } 898 } 899