1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include <asm/div64.h> 33 34 #include <linux/pm_runtime.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_edid.h> 37 38 static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb) 39 { 40 struct amdgpu_flip_work *work = 41 container_of(cb, struct amdgpu_flip_work, cb); 42 43 fence_put(f); 44 schedule_work(&work->flip_work); 45 } 46 47 static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work, 48 struct fence **f) 49 { 50 struct fence *fence= *f; 51 52 if (fence == NULL) 53 return false; 54 55 *f = NULL; 56 57 if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) 58 return true; 59 60 fence_put(fence); 61 return false; 62 } 63 64 static void amdgpu_flip_work_func(struct work_struct *__work) 65 { 66 struct amdgpu_flip_work *work = 67 container_of(__work, struct amdgpu_flip_work, flip_work); 68 struct amdgpu_device *adev = work->adev; 69 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; 70 71 struct drm_crtc *crtc = &amdgpuCrtc->base; 72 unsigned long flags; 73 unsigned i, repcnt = 4; 74 int vpos, hpos, stat, min_udelay = 0; 75 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 76 77 if (amdgpu_flip_handle_fence(work, &work->excl)) 78 return; 79 80 for (i = 0; i < work->shared_count; ++i) 81 if (amdgpu_flip_handle_fence(work, &work->shared[i])) 82 return; 83 84 /* We borrow the event spin lock for protecting flip_status */ 85 spin_lock_irqsave(&crtc->dev->event_lock, flags); 86 87 /* If this happens to execute within the "virtually extended" vblank 88 * interval before the start of the real vblank interval then it needs 89 * to delay programming the mmio flip until the real vblank is entered. 90 * This prevents completing a flip too early due to the way we fudge 91 * our vblank counter and vblank timestamps in order to work around the 92 * problem that the hw fires vblank interrupts before actual start of 93 * vblank (when line buffer refilling is done for a frame). It 94 * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for 95 * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. 96 * 97 * In practice this won't execute very often unless on very fast 98 * machines because the time window for this to happen is very small. 99 */ 100 while (amdgpuCrtc->enabled && --repcnt) { 101 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 102 * start in hpos, and to the "fudged earlier" vblank start in 103 * vpos. 104 */ 105 stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 106 GET_DISTANCE_TO_VBLANKSTART, 107 &vpos, &hpos, NULL, NULL, 108 &crtc->hwmode); 109 110 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 111 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 112 !(vpos >= 0 && hpos <= 0)) 113 break; 114 115 /* Sleep at least until estimated real start of hw vblank */ 116 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 117 if (min_udelay > vblank->framedur_ns / 2000) { 118 /* Don't wait ridiculously long - something is wrong */ 119 repcnt = 0; 120 break; 121 } 122 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 123 usleep_range(min_udelay, 2 * min_udelay); 124 spin_lock_irqsave(&crtc->dev->event_lock, flags); 125 } 126 127 if (!repcnt) 128 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 129 "framedur %d, linedur %d, stat %d, vpos %d, " 130 "hpos %d\n", work->crtc_id, min_udelay, 131 vblank->framedur_ns / 1000, 132 vblank->linedur_ns / 1000, stat, vpos, hpos); 133 134 /* Do the flip (mmio) */ 135 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 136 137 /* Set the flip status */ 138 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 139 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 140 141 142 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 143 amdgpuCrtc->crtc_id, amdgpuCrtc, work); 144 145 } 146 147 /* 148 * Handle unpin events outside the interrupt handler proper. 149 */ 150 static void amdgpu_unpin_work_func(struct work_struct *__work) 151 { 152 struct amdgpu_flip_work *work = 153 container_of(__work, struct amdgpu_flip_work, unpin_work); 154 int r; 155 156 /* unpin of the old buffer */ 157 r = amdgpu_bo_reserve(work->old_rbo, false); 158 if (likely(r == 0)) { 159 r = amdgpu_bo_unpin(work->old_rbo); 160 if (unlikely(r != 0)) { 161 DRM_ERROR("failed to unpin buffer after flip\n"); 162 } 163 amdgpu_bo_unreserve(work->old_rbo); 164 } else 165 DRM_ERROR("failed to reserve buffer after flip\n"); 166 167 amdgpu_bo_unref(&work->old_rbo); 168 kfree(work->shared); 169 kfree(work); 170 } 171 172 int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 173 struct drm_framebuffer *fb, 174 struct drm_pending_vblank_event *event, 175 uint32_t page_flip_flags) 176 { 177 struct drm_device *dev = crtc->dev; 178 struct amdgpu_device *adev = dev->dev_private; 179 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 180 struct amdgpu_framebuffer *old_amdgpu_fb; 181 struct amdgpu_framebuffer *new_amdgpu_fb; 182 struct drm_gem_object *obj; 183 struct amdgpu_flip_work *work; 184 struct amdgpu_bo *new_rbo; 185 unsigned long flags; 186 u64 tiling_flags; 187 u64 base; 188 int i, r; 189 190 work = kzalloc(sizeof *work, GFP_KERNEL); 191 if (work == NULL) 192 return -ENOMEM; 193 194 INIT_WORK(&work->flip_work, amdgpu_flip_work_func); 195 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); 196 197 work->event = event; 198 work->adev = adev; 199 work->crtc_id = amdgpu_crtc->crtc_id; 200 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 201 202 /* schedule unpin of the old buffer */ 203 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 204 obj = old_amdgpu_fb->obj; 205 206 /* take a reference to the old object */ 207 work->old_rbo = gem_to_amdgpu_bo(obj); 208 amdgpu_bo_ref(work->old_rbo); 209 210 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 211 obj = new_amdgpu_fb->obj; 212 new_rbo = gem_to_amdgpu_bo(obj); 213 214 /* pin the new buffer */ 215 r = amdgpu_bo_reserve(new_rbo, false); 216 if (unlikely(r != 0)) { 217 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 218 goto cleanup; 219 } 220 221 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 222 if (unlikely(r != 0)) { 223 r = -EINVAL; 224 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 225 goto unreserve; 226 } 227 228 r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, 229 &work->shared_count, 230 &work->shared); 231 if (unlikely(r != 0)) { 232 DRM_ERROR("failed to get fences for buffer\n"); 233 goto unpin; 234 } 235 236 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); 237 amdgpu_bo_unreserve(new_rbo); 238 239 work->base = base; 240 241 r = drm_crtc_vblank_get(crtc); 242 if (r) { 243 DRM_ERROR("failed to get vblank before flip\n"); 244 goto pflip_cleanup; 245 } 246 247 /* we borrow the event spin lock for protecting flip_wrok */ 248 spin_lock_irqsave(&crtc->dev->event_lock, flags); 249 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 250 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 251 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 252 r = -EBUSY; 253 goto vblank_cleanup; 254 } 255 256 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 257 amdgpu_crtc->pflip_works = work; 258 259 260 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 261 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 262 /* update crtc fb */ 263 crtc->primary->fb = fb; 264 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 265 amdgpu_flip_work_func(&work->flip_work); 266 return 0; 267 268 vblank_cleanup: 269 drm_crtc_vblank_put(crtc); 270 271 pflip_cleanup: 272 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { 273 DRM_ERROR("failed to reserve new rbo in error path\n"); 274 goto cleanup; 275 } 276 unpin: 277 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { 278 DRM_ERROR("failed to unpin new rbo in error path\n"); 279 } 280 unreserve: 281 amdgpu_bo_unreserve(new_rbo); 282 283 cleanup: 284 amdgpu_bo_unref(&work->old_rbo); 285 fence_put(work->excl); 286 for (i = 0; i < work->shared_count; ++i) 287 fence_put(work->shared[i]); 288 kfree(work->shared); 289 kfree(work); 290 291 return r; 292 } 293 294 int amdgpu_crtc_set_config(struct drm_mode_set *set) 295 { 296 struct drm_device *dev; 297 struct amdgpu_device *adev; 298 struct drm_crtc *crtc; 299 bool active = false; 300 int ret; 301 302 if (!set || !set->crtc) 303 return -EINVAL; 304 305 dev = set->crtc->dev; 306 307 ret = pm_runtime_get_sync(dev->dev); 308 if (ret < 0) 309 return ret; 310 311 ret = drm_crtc_helper_set_config(set); 312 313 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 314 if (crtc->enabled) 315 active = true; 316 317 pm_runtime_mark_last_busy(dev->dev); 318 319 adev = dev->dev_private; 320 /* if we have active crtcs and we don't have a power ref, 321 take the current one */ 322 if (active && !adev->have_disp_power_ref) { 323 adev->have_disp_power_ref = true; 324 return ret; 325 } 326 /* if we have no active crtcs, then drop the power ref 327 we got before */ 328 if (!active && adev->have_disp_power_ref) { 329 pm_runtime_put_autosuspend(dev->dev); 330 adev->have_disp_power_ref = false; 331 } 332 333 /* drop the power reference we got coming in here */ 334 pm_runtime_put_autosuspend(dev->dev); 335 return ret; 336 } 337 338 static const char *encoder_names[38] = { 339 "NONE", 340 "INTERNAL_LVDS", 341 "INTERNAL_TMDS1", 342 "INTERNAL_TMDS2", 343 "INTERNAL_DAC1", 344 "INTERNAL_DAC2", 345 "INTERNAL_SDVOA", 346 "INTERNAL_SDVOB", 347 "SI170B", 348 "CH7303", 349 "CH7301", 350 "INTERNAL_DVO1", 351 "EXTERNAL_SDVOA", 352 "EXTERNAL_SDVOB", 353 "TITFP513", 354 "INTERNAL_LVTM1", 355 "VT1623", 356 "HDMI_SI1930", 357 "HDMI_INTERNAL", 358 "INTERNAL_KLDSCP_TMDS1", 359 "INTERNAL_KLDSCP_DVO1", 360 "INTERNAL_KLDSCP_DAC1", 361 "INTERNAL_KLDSCP_DAC2", 362 "SI178", 363 "MVPU_FPGA", 364 "INTERNAL_DDI", 365 "VT1625", 366 "HDMI_SI1932", 367 "DP_AN9801", 368 "DP_DP501", 369 "INTERNAL_UNIPHY", 370 "INTERNAL_KLDSCP_LVTMA", 371 "INTERNAL_UNIPHY1", 372 "INTERNAL_UNIPHY2", 373 "NUTMEG", 374 "TRAVIS", 375 "INTERNAL_VCE", 376 "INTERNAL_UNIPHY3", 377 }; 378 379 static const char *hpd_names[6] = { 380 "HPD1", 381 "HPD2", 382 "HPD3", 383 "HPD4", 384 "HPD5", 385 "HPD6", 386 }; 387 388 void amdgpu_print_display_setup(struct drm_device *dev) 389 { 390 struct drm_connector *connector; 391 struct amdgpu_connector *amdgpu_connector; 392 struct drm_encoder *encoder; 393 struct amdgpu_encoder *amdgpu_encoder; 394 uint32_t devices; 395 int i = 0; 396 397 DRM_INFO("AMDGPU Display Connectors\n"); 398 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 399 amdgpu_connector = to_amdgpu_connector(connector); 400 DRM_INFO("Connector %d:\n", i); 401 DRM_INFO(" %s\n", connector->name); 402 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 403 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 404 if (amdgpu_connector->ddc_bus) { 405 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 406 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 407 amdgpu_connector->ddc_bus->rec.mask_data_reg, 408 amdgpu_connector->ddc_bus->rec.a_clk_reg, 409 amdgpu_connector->ddc_bus->rec.a_data_reg, 410 amdgpu_connector->ddc_bus->rec.en_clk_reg, 411 amdgpu_connector->ddc_bus->rec.en_data_reg, 412 amdgpu_connector->ddc_bus->rec.y_clk_reg, 413 amdgpu_connector->ddc_bus->rec.y_data_reg); 414 if (amdgpu_connector->router.ddc_valid) 415 DRM_INFO(" DDC Router 0x%x/0x%x\n", 416 amdgpu_connector->router.ddc_mux_control_pin, 417 amdgpu_connector->router.ddc_mux_state); 418 if (amdgpu_connector->router.cd_valid) 419 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 420 amdgpu_connector->router.cd_mux_control_pin, 421 amdgpu_connector->router.cd_mux_state); 422 } else { 423 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 424 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 425 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 426 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 427 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 428 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 429 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 430 } 431 DRM_INFO(" Encoders:\n"); 432 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 433 amdgpu_encoder = to_amdgpu_encoder(encoder); 434 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 435 if (devices) { 436 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 437 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 438 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 439 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 440 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 441 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 442 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 443 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 444 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 445 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 446 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 447 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 448 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 449 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 450 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 451 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 452 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 453 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 454 if (devices & ATOM_DEVICE_TV1_SUPPORT) 455 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 456 if (devices & ATOM_DEVICE_CV_SUPPORT) 457 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 458 } 459 } 460 i++; 461 } 462 } 463 464 /** 465 * amdgpu_ddc_probe 466 * 467 */ 468 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, 469 bool use_aux) 470 { 471 u8 out = 0x0; 472 u8 buf[8]; 473 int ret; 474 struct i2c_msg msgs[] = { 475 { 476 .addr = DDC_ADDR, 477 .flags = 0, 478 .len = 1, 479 .buf = &out, 480 }, 481 { 482 .addr = DDC_ADDR, 483 .flags = I2C_M_RD, 484 .len = 8, 485 .buf = buf, 486 } 487 }; 488 489 /* on hw with routers, select right port */ 490 if (amdgpu_connector->router.ddc_valid) 491 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 492 493 if (use_aux) { 494 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 495 } else { 496 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 497 } 498 499 if (ret != 2) 500 /* Couldn't find an accessible DDC on this connector */ 501 return false; 502 /* Probe also for valid EDID header 503 * EDID header starts with: 504 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 505 * Only the first 6 bytes must be valid as 506 * drm_edid_block_valid() can fix the last 2 bytes */ 507 if (drm_edid_header_is_valid(buf) < 6) { 508 /* Couldn't find an accessible EDID on this 509 * connector */ 510 return false; 511 } 512 return true; 513 } 514 515 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) 516 { 517 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 518 519 drm_gem_object_unreference_unlocked(amdgpu_fb->obj); 520 drm_framebuffer_cleanup(fb); 521 kfree(amdgpu_fb); 522 } 523 524 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, 525 struct drm_file *file_priv, 526 unsigned int *handle) 527 { 528 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 529 530 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); 531 } 532 533 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 534 .destroy = amdgpu_user_framebuffer_destroy, 535 .create_handle = amdgpu_user_framebuffer_create_handle, 536 }; 537 538 int 539 amdgpu_framebuffer_init(struct drm_device *dev, 540 struct amdgpu_framebuffer *rfb, 541 const struct drm_mode_fb_cmd2 *mode_cmd, 542 struct drm_gem_object *obj) 543 { 544 int ret; 545 rfb->obj = obj; 546 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 547 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 548 if (ret) { 549 rfb->obj = NULL; 550 return ret; 551 } 552 return 0; 553 } 554 555 static struct drm_framebuffer * 556 amdgpu_user_framebuffer_create(struct drm_device *dev, 557 struct drm_file *file_priv, 558 const struct drm_mode_fb_cmd2 *mode_cmd) 559 { 560 struct drm_gem_object *obj; 561 struct amdgpu_framebuffer *amdgpu_fb; 562 int ret; 563 564 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 565 if (obj == NULL) { 566 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 567 "can't create framebuffer\n", mode_cmd->handles[0]); 568 return ERR_PTR(-ENOENT); 569 } 570 571 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 572 if (amdgpu_fb == NULL) { 573 drm_gem_object_unreference_unlocked(obj); 574 return ERR_PTR(-ENOMEM); 575 } 576 577 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 578 if (ret) { 579 kfree(amdgpu_fb); 580 drm_gem_object_unreference_unlocked(obj); 581 return ERR_PTR(ret); 582 } 583 584 return &amdgpu_fb->base; 585 } 586 587 static void amdgpu_output_poll_changed(struct drm_device *dev) 588 { 589 struct amdgpu_device *adev = dev->dev_private; 590 amdgpu_fb_output_poll_changed(adev); 591 } 592 593 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 594 .fb_create = amdgpu_user_framebuffer_create, 595 .output_poll_changed = amdgpu_output_poll_changed 596 }; 597 598 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 599 { { UNDERSCAN_OFF, "off" }, 600 { UNDERSCAN_ON, "on" }, 601 { UNDERSCAN_AUTO, "auto" }, 602 }; 603 604 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 605 { { AMDGPU_AUDIO_DISABLE, "off" }, 606 { AMDGPU_AUDIO_ENABLE, "on" }, 607 { AMDGPU_AUDIO_AUTO, "auto" }, 608 }; 609 610 /* XXX support different dither options? spatial, temporal, both, etc. */ 611 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 612 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 613 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 614 }; 615 616 int amdgpu_modeset_create_props(struct amdgpu_device *adev) 617 { 618 int sz; 619 620 if (adev->is_atom_bios) { 621 adev->mode_info.coherent_mode_property = 622 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 623 if (!adev->mode_info.coherent_mode_property) 624 return -ENOMEM; 625 } 626 627 adev->mode_info.load_detect_property = 628 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 629 if (!adev->mode_info.load_detect_property) 630 return -ENOMEM; 631 632 drm_mode_create_scaling_mode_property(adev->ddev); 633 634 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 635 adev->mode_info.underscan_property = 636 drm_property_create_enum(adev->ddev, 0, 637 "underscan", 638 amdgpu_underscan_enum_list, sz); 639 640 adev->mode_info.underscan_hborder_property = 641 drm_property_create_range(adev->ddev, 0, 642 "underscan hborder", 0, 128); 643 if (!adev->mode_info.underscan_hborder_property) 644 return -ENOMEM; 645 646 adev->mode_info.underscan_vborder_property = 647 drm_property_create_range(adev->ddev, 0, 648 "underscan vborder", 0, 128); 649 if (!adev->mode_info.underscan_vborder_property) 650 return -ENOMEM; 651 652 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 653 adev->mode_info.audio_property = 654 drm_property_create_enum(adev->ddev, 0, 655 "audio", 656 amdgpu_audio_enum_list, sz); 657 658 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 659 adev->mode_info.dither_property = 660 drm_property_create_enum(adev->ddev, 0, 661 "dither", 662 amdgpu_dither_enum_list, sz); 663 664 return 0; 665 } 666 667 void amdgpu_update_display_priority(struct amdgpu_device *adev) 668 { 669 /* adjustment options for the display watermarks */ 670 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 671 adev->mode_info.disp_priority = 0; 672 else 673 adev->mode_info.disp_priority = amdgpu_disp_priority; 674 675 } 676 677 static bool is_hdtv_mode(const struct drm_display_mode *mode) 678 { 679 /* try and guess if this is a tv or a monitor */ 680 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 681 (mode->vdisplay == 576) || /* 576p */ 682 (mode->vdisplay == 720) || /* 720p */ 683 (mode->vdisplay == 1080)) /* 1080p */ 684 return true; 685 else 686 return false; 687 } 688 689 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 690 const struct drm_display_mode *mode, 691 struct drm_display_mode *adjusted_mode) 692 { 693 struct drm_device *dev = crtc->dev; 694 struct drm_encoder *encoder; 695 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 696 struct amdgpu_encoder *amdgpu_encoder; 697 struct drm_connector *connector; 698 struct amdgpu_connector *amdgpu_connector; 699 u32 src_v = 1, dst_v = 1; 700 u32 src_h = 1, dst_h = 1; 701 702 amdgpu_crtc->h_border = 0; 703 amdgpu_crtc->v_border = 0; 704 705 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 706 if (encoder->crtc != crtc) 707 continue; 708 amdgpu_encoder = to_amdgpu_encoder(encoder); 709 connector = amdgpu_get_connector_for_encoder(encoder); 710 amdgpu_connector = to_amdgpu_connector(connector); 711 712 /* set scaling */ 713 if (amdgpu_encoder->rmx_type == RMX_OFF) 714 amdgpu_crtc->rmx_type = RMX_OFF; 715 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 716 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 717 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 718 else 719 amdgpu_crtc->rmx_type = RMX_OFF; 720 /* copy native mode */ 721 memcpy(&amdgpu_crtc->native_mode, 722 &amdgpu_encoder->native_mode, 723 sizeof(struct drm_display_mode)); 724 src_v = crtc->mode.vdisplay; 725 dst_v = amdgpu_crtc->native_mode.vdisplay; 726 src_h = crtc->mode.hdisplay; 727 dst_h = amdgpu_crtc->native_mode.hdisplay; 728 729 /* fix up for overscan on hdmi */ 730 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 731 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 732 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 733 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 734 is_hdtv_mode(mode)))) { 735 if (amdgpu_encoder->underscan_hborder != 0) 736 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 737 else 738 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 739 if (amdgpu_encoder->underscan_vborder != 0) 740 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 741 else 742 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 743 amdgpu_crtc->rmx_type = RMX_FULL; 744 src_v = crtc->mode.vdisplay; 745 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 746 src_h = crtc->mode.hdisplay; 747 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 748 } 749 } 750 if (amdgpu_crtc->rmx_type != RMX_OFF) { 751 fixed20_12 a, b; 752 a.full = dfixed_const(src_v); 753 b.full = dfixed_const(dst_v); 754 amdgpu_crtc->vsc.full = dfixed_div(a, b); 755 a.full = dfixed_const(src_h); 756 b.full = dfixed_const(dst_h); 757 amdgpu_crtc->hsc.full = dfixed_div(a, b); 758 } else { 759 amdgpu_crtc->vsc.full = dfixed_const(1); 760 amdgpu_crtc->hsc.full = dfixed_const(1); 761 } 762 return true; 763 } 764 765 /* 766 * Retrieve current video scanout position of crtc on a given gpu, and 767 * an optional accurate timestamp of when query happened. 768 * 769 * \param dev Device to query. 770 * \param pipe Crtc to query. 771 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 772 * For driver internal use only also supports these flags: 773 * 774 * USE_REAL_VBLANKSTART to use the real start of vblank instead 775 * of a fudged earlier start of vblank. 776 * 777 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 778 * fudged earlier start of vblank in *vpos and the distance 779 * to true start of vblank in *hpos. 780 * 781 * \param *vpos Location where vertical scanout position should be stored. 782 * \param *hpos Location where horizontal scanout position should go. 783 * \param *stime Target location for timestamp taken immediately before 784 * scanout position query. Can be NULL to skip timestamp. 785 * \param *etime Target location for timestamp taken immediately after 786 * scanout position query. Can be NULL to skip timestamp. 787 * 788 * Returns vpos as a positive number while in active scanout area. 789 * Returns vpos as a negative number inside vblank, counting the number 790 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 791 * until start of active scanout / end of vblank." 792 * 793 * \return Flags, or'ed together as follows: 794 * 795 * DRM_SCANOUTPOS_VALID = Query successful. 796 * DRM_SCANOUTPOS_INVBL = Inside vblank. 797 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 798 * this flag means that returned position may be offset by a constant but 799 * unknown small number of scanlines wrt. real scanout position. 800 * 801 */ 802 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 803 unsigned int flags, int *vpos, int *hpos, 804 ktime_t *stime, ktime_t *etime, 805 const struct drm_display_mode *mode) 806 { 807 u32 vbl = 0, position = 0; 808 int vbl_start, vbl_end, vtotal, ret = 0; 809 bool in_vbl = true; 810 811 struct amdgpu_device *adev = dev->dev_private; 812 813 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 814 815 /* Get optional system timestamp before query. */ 816 if (stime) 817 *stime = ktime_get(); 818 819 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 820 ret |= DRM_SCANOUTPOS_VALID; 821 822 /* Get optional system timestamp after query. */ 823 if (etime) 824 *etime = ktime_get(); 825 826 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 827 828 /* Decode into vertical and horizontal scanout position. */ 829 *vpos = position & 0x1fff; 830 *hpos = (position >> 16) & 0x1fff; 831 832 /* Valid vblank area boundaries from gpu retrieved? */ 833 if (vbl > 0) { 834 /* Yes: Decode. */ 835 ret |= DRM_SCANOUTPOS_ACCURATE; 836 vbl_start = vbl & 0x1fff; 837 vbl_end = (vbl >> 16) & 0x1fff; 838 } 839 else { 840 /* No: Fake something reasonable which gives at least ok results. */ 841 vbl_start = mode->crtc_vdisplay; 842 vbl_end = 0; 843 } 844 845 /* Called from driver internal vblank counter query code? */ 846 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 847 /* Caller wants distance from real vbl_start in *hpos */ 848 *hpos = *vpos - vbl_start; 849 } 850 851 /* Fudge vblank to start a few scanlines earlier to handle the 852 * problem that vblank irqs fire a few scanlines before start 853 * of vblank. Some driver internal callers need the true vblank 854 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 855 * 856 * The cause of the "early" vblank irq is that the irq is triggered 857 * by the line buffer logic when the line buffer read position enters 858 * the vblank, whereas our crtc scanout position naturally lags the 859 * line buffer read position. 860 */ 861 if (!(flags & USE_REAL_VBLANKSTART)) 862 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 863 864 /* Test scanout position against vblank region. */ 865 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 866 in_vbl = false; 867 868 /* In vblank? */ 869 if (in_vbl) 870 ret |= DRM_SCANOUTPOS_IN_VBLANK; 871 872 /* Called from driver internal vblank counter query code? */ 873 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 874 /* Caller wants distance from fudged earlier vbl_start */ 875 *vpos -= vbl_start; 876 return ret; 877 } 878 879 /* Check if inside vblank area and apply corrective offsets: 880 * vpos will then be >=0 in video scanout area, but negative 881 * within vblank area, counting down the number of lines until 882 * start of scanout. 883 */ 884 885 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 886 if (in_vbl && (*vpos >= vbl_start)) { 887 vtotal = mode->crtc_vtotal; 888 *vpos = *vpos - vtotal; 889 } 890 891 /* Correct for shifted end of vbl at vbl_end. */ 892 *vpos = *vpos - vbl_end; 893 894 return ret; 895 } 896 897 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 898 { 899 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 900 return AMDGPU_CRTC_IRQ_NONE; 901 902 switch (crtc) { 903 case 0: 904 return AMDGPU_CRTC_IRQ_VBLANK1; 905 case 1: 906 return AMDGPU_CRTC_IRQ_VBLANK2; 907 case 2: 908 return AMDGPU_CRTC_IRQ_VBLANK3; 909 case 3: 910 return AMDGPU_CRTC_IRQ_VBLANK4; 911 case 4: 912 return AMDGPU_CRTC_IRQ_VBLANK5; 913 case 5: 914 return AMDGPU_CRTC_IRQ_VBLANK6; 915 default: 916 return AMDGPU_CRTC_IRQ_NONE; 917 } 918 } 919