1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_runtime.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_vblank.h> 43 44 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 45 struct amdgpu_framebuffer *rfb, 46 const struct drm_mode_fb_cmd2 *mode_cmd, 47 struct drm_gem_object *obj); 48 49 static void amdgpu_display_flip_callback(struct dma_fence *f, 50 struct dma_fence_cb *cb) 51 { 52 struct amdgpu_flip_work *work = 53 container_of(cb, struct amdgpu_flip_work, cb); 54 55 dma_fence_put(f); 56 schedule_work(&work->flip_work.work); 57 } 58 59 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 60 struct dma_fence **f) 61 { 62 struct dma_fence *fence= *f; 63 64 if (fence == NULL) 65 return false; 66 67 *f = NULL; 68 69 if (!dma_fence_add_callback(fence, &work->cb, 70 amdgpu_display_flip_callback)) 71 return true; 72 73 dma_fence_put(fence); 74 return false; 75 } 76 77 static void amdgpu_display_flip_work_func(struct work_struct *__work) 78 { 79 struct delayed_work *delayed_work = 80 container_of(__work, struct delayed_work, work); 81 struct amdgpu_flip_work *work = 82 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 83 struct amdgpu_device *adev = work->adev; 84 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 85 86 struct drm_crtc *crtc = &amdgpu_crtc->base; 87 unsigned long flags; 88 unsigned i; 89 int vpos, hpos; 90 91 for (i = 0; i < work->shared_count; ++i) 92 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 93 return; 94 95 /* Wait until we're out of the vertical blank period before the one 96 * targeted by the flip 97 */ 98 if (amdgpu_crtc->enabled && 99 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 100 &vpos, &hpos, NULL, NULL, 101 &crtc->hwmode) 102 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 103 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 104 (int)(work->target_vblank - 105 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 106 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 107 return; 108 } 109 110 /* We borrow the event spin lock for protecting flip_status */ 111 spin_lock_irqsave(&crtc->dev->event_lock, flags); 112 113 /* Do the flip (mmio) */ 114 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 115 116 /* Set the flip status */ 117 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 118 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 119 120 121 drm_dbg_vbl(adev_to_drm(adev), 122 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 123 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 124 125 } 126 127 /* 128 * Handle unpin events outside the interrupt handler proper. 129 */ 130 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 131 { 132 struct amdgpu_flip_work *work = 133 container_of(__work, struct amdgpu_flip_work, unpin_work); 134 int r; 135 136 /* unpin of the old buffer */ 137 r = amdgpu_bo_reserve(work->old_abo, true); 138 if (likely(r == 0)) { 139 amdgpu_bo_unpin(work->old_abo); 140 amdgpu_bo_unreserve(work->old_abo); 141 } else 142 DRM_ERROR("failed to reserve buffer after flip\n"); 143 144 amdgpu_bo_unref(&work->old_abo); 145 kfree(work->shared); 146 kfree(work); 147 } 148 149 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 150 struct drm_framebuffer *fb, 151 struct drm_pending_vblank_event *event, 152 uint32_t page_flip_flags, uint32_t target, 153 struct drm_modeset_acquire_ctx *ctx) 154 { 155 struct drm_device *dev = crtc->dev; 156 struct amdgpu_device *adev = drm_to_adev(dev); 157 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 158 struct drm_gem_object *obj; 159 struct amdgpu_flip_work *work; 160 struct amdgpu_bo *new_abo; 161 unsigned long flags; 162 u64 tiling_flags; 163 int i, r; 164 165 work = kzalloc(sizeof *work, GFP_KERNEL); 166 if (work == NULL) 167 return -ENOMEM; 168 169 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 170 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 171 172 work->event = event; 173 work->adev = adev; 174 work->crtc_id = amdgpu_crtc->crtc_id; 175 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 176 177 /* schedule unpin of the old buffer */ 178 obj = crtc->primary->fb->obj[0]; 179 180 /* take a reference to the old object */ 181 work->old_abo = gem_to_amdgpu_bo(obj); 182 amdgpu_bo_ref(work->old_abo); 183 184 obj = fb->obj[0]; 185 new_abo = gem_to_amdgpu_bo(obj); 186 187 /* pin the new buffer */ 188 r = amdgpu_bo_reserve(new_abo, false); 189 if (unlikely(r != 0)) { 190 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 191 goto cleanup; 192 } 193 194 if (!adev->enable_virtual_display) { 195 r = amdgpu_bo_pin(new_abo, 196 amdgpu_display_supported_domains(adev, new_abo->flags)); 197 if (unlikely(r != 0)) { 198 DRM_ERROR("failed to pin new abo buffer before flip\n"); 199 goto unreserve; 200 } 201 } 202 203 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 204 if (unlikely(r != 0)) { 205 DRM_ERROR("%p bind failed\n", new_abo); 206 goto unpin; 207 } 208 209 /* TODO: Unify this with other drivers */ 210 r = dma_resv_get_fences(new_abo->tbo.base.resv, true, 211 &work->shared_count, 212 &work->shared); 213 if (unlikely(r != 0)) { 214 DRM_ERROR("failed to get fences for buffer\n"); 215 goto unpin; 216 } 217 218 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 219 amdgpu_bo_unreserve(new_abo); 220 221 if (!adev->enable_virtual_display) 222 work->base = amdgpu_bo_gpu_offset(new_abo); 223 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 224 amdgpu_get_vblank_counter_kms(crtc); 225 226 /* we borrow the event spin lock for protecting flip_wrok */ 227 spin_lock_irqsave(&crtc->dev->event_lock, flags); 228 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 229 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 230 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 231 r = -EBUSY; 232 goto pflip_cleanup; 233 } 234 235 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 236 amdgpu_crtc->pflip_works = work; 237 238 239 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 240 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 241 /* update crtc fb */ 242 crtc->primary->fb = fb; 243 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 244 amdgpu_display_flip_work_func(&work->flip_work.work); 245 return 0; 246 247 pflip_cleanup: 248 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 249 DRM_ERROR("failed to reserve new abo in error path\n"); 250 goto cleanup; 251 } 252 unpin: 253 if (!adev->enable_virtual_display) 254 amdgpu_bo_unpin(new_abo); 255 256 unreserve: 257 amdgpu_bo_unreserve(new_abo); 258 259 cleanup: 260 amdgpu_bo_unref(&work->old_abo); 261 for (i = 0; i < work->shared_count; ++i) 262 dma_fence_put(work->shared[i]); 263 kfree(work->shared); 264 kfree(work); 265 266 return r; 267 } 268 269 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 270 struct drm_modeset_acquire_ctx *ctx) 271 { 272 struct drm_device *dev; 273 struct amdgpu_device *adev; 274 struct drm_crtc *crtc; 275 bool active = false; 276 int ret; 277 278 if (!set || !set->crtc) 279 return -EINVAL; 280 281 dev = set->crtc->dev; 282 283 ret = pm_runtime_get_sync(dev->dev); 284 if (ret < 0) 285 goto out; 286 287 ret = drm_crtc_helper_set_config(set, ctx); 288 289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 290 if (crtc->enabled) 291 active = true; 292 293 pm_runtime_mark_last_busy(dev->dev); 294 295 adev = drm_to_adev(dev); 296 /* if we have active crtcs and we don't have a power ref, 297 take the current one */ 298 if (active && !adev->have_disp_power_ref) { 299 adev->have_disp_power_ref = true; 300 return ret; 301 } 302 /* if we have no active crtcs, then drop the power ref 303 we got before */ 304 if (!active && adev->have_disp_power_ref) { 305 pm_runtime_put_autosuspend(dev->dev); 306 adev->have_disp_power_ref = false; 307 } 308 309 out: 310 /* drop the power reference we got coming in here */ 311 pm_runtime_put_autosuspend(dev->dev); 312 return ret; 313 } 314 315 static const char *encoder_names[41] = { 316 "NONE", 317 "INTERNAL_LVDS", 318 "INTERNAL_TMDS1", 319 "INTERNAL_TMDS2", 320 "INTERNAL_DAC1", 321 "INTERNAL_DAC2", 322 "INTERNAL_SDVOA", 323 "INTERNAL_SDVOB", 324 "SI170B", 325 "CH7303", 326 "CH7301", 327 "INTERNAL_DVO1", 328 "EXTERNAL_SDVOA", 329 "EXTERNAL_SDVOB", 330 "TITFP513", 331 "INTERNAL_LVTM1", 332 "VT1623", 333 "HDMI_SI1930", 334 "HDMI_INTERNAL", 335 "INTERNAL_KLDSCP_TMDS1", 336 "INTERNAL_KLDSCP_DVO1", 337 "INTERNAL_KLDSCP_DAC1", 338 "INTERNAL_KLDSCP_DAC2", 339 "SI178", 340 "MVPU_FPGA", 341 "INTERNAL_DDI", 342 "VT1625", 343 "HDMI_SI1932", 344 "DP_AN9801", 345 "DP_DP501", 346 "INTERNAL_UNIPHY", 347 "INTERNAL_KLDSCP_LVTMA", 348 "INTERNAL_UNIPHY1", 349 "INTERNAL_UNIPHY2", 350 "NUTMEG", 351 "TRAVIS", 352 "INTERNAL_VCE", 353 "INTERNAL_UNIPHY3", 354 "HDMI_ANX9805", 355 "INTERNAL_AMCLK", 356 "VIRTUAL", 357 }; 358 359 static const char *hpd_names[6] = { 360 "HPD1", 361 "HPD2", 362 "HPD3", 363 "HPD4", 364 "HPD5", 365 "HPD6", 366 }; 367 368 void amdgpu_display_print_display_setup(struct drm_device *dev) 369 { 370 struct drm_connector *connector; 371 struct amdgpu_connector *amdgpu_connector; 372 struct drm_encoder *encoder; 373 struct amdgpu_encoder *amdgpu_encoder; 374 struct drm_connector_list_iter iter; 375 uint32_t devices; 376 int i = 0; 377 378 drm_connector_list_iter_begin(dev, &iter); 379 DRM_INFO("AMDGPU Display Connectors\n"); 380 drm_for_each_connector_iter(connector, &iter) { 381 amdgpu_connector = to_amdgpu_connector(connector); 382 DRM_INFO("Connector %d:\n", i); 383 DRM_INFO(" %s\n", connector->name); 384 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 385 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 386 if (amdgpu_connector->ddc_bus) { 387 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 388 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 389 amdgpu_connector->ddc_bus->rec.mask_data_reg, 390 amdgpu_connector->ddc_bus->rec.a_clk_reg, 391 amdgpu_connector->ddc_bus->rec.a_data_reg, 392 amdgpu_connector->ddc_bus->rec.en_clk_reg, 393 amdgpu_connector->ddc_bus->rec.en_data_reg, 394 amdgpu_connector->ddc_bus->rec.y_clk_reg, 395 amdgpu_connector->ddc_bus->rec.y_data_reg); 396 if (amdgpu_connector->router.ddc_valid) 397 DRM_INFO(" DDC Router 0x%x/0x%x\n", 398 amdgpu_connector->router.ddc_mux_control_pin, 399 amdgpu_connector->router.ddc_mux_state); 400 if (amdgpu_connector->router.cd_valid) 401 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 402 amdgpu_connector->router.cd_mux_control_pin, 403 amdgpu_connector->router.cd_mux_state); 404 } else { 405 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 406 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 407 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 408 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 409 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 410 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 411 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 412 } 413 DRM_INFO(" Encoders:\n"); 414 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 415 amdgpu_encoder = to_amdgpu_encoder(encoder); 416 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 417 if (devices) { 418 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 419 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 420 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 421 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 422 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 423 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 424 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 425 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 426 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 427 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 428 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 429 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 430 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 431 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 432 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 433 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 434 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 435 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 436 if (devices & ATOM_DEVICE_TV1_SUPPORT) 437 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 438 if (devices & ATOM_DEVICE_CV_SUPPORT) 439 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 440 } 441 } 442 i++; 443 } 444 drm_connector_list_iter_end(&iter); 445 } 446 447 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 448 bool use_aux) 449 { 450 u8 out = 0x0; 451 u8 buf[8]; 452 int ret; 453 struct i2c_msg msgs[] = { 454 { 455 .addr = DDC_ADDR, 456 .flags = 0, 457 .len = 1, 458 .buf = &out, 459 }, 460 { 461 .addr = DDC_ADDR, 462 .flags = I2C_M_RD, 463 .len = 8, 464 .buf = buf, 465 } 466 }; 467 468 /* on hw with routers, select right port */ 469 if (amdgpu_connector->router.ddc_valid) 470 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 471 472 if (use_aux) { 473 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 474 } else { 475 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 476 } 477 478 if (ret != 2) 479 /* Couldn't find an accessible DDC on this connector */ 480 return false; 481 /* Probe also for valid EDID header 482 * EDID header starts with: 483 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 484 * Only the first 6 bytes must be valid as 485 * drm_edid_block_valid() can fix the last 2 bytes */ 486 if (drm_edid_header_is_valid(buf) < 6) { 487 /* Couldn't find an accessible EDID on this 488 * connector */ 489 return false; 490 } 491 return true; 492 } 493 494 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 495 .destroy = drm_gem_fb_destroy, 496 .create_handle = drm_gem_fb_create_handle, 497 }; 498 499 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 500 uint64_t bo_flags) 501 { 502 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 503 504 #if defined(CONFIG_DRM_AMD_DC) 505 /* 506 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 507 * is not supported for this board. But this mapping is required 508 * to avoid hang caused by placement of scanout BO in GTT on certain 509 * APUs. So force the BO placement to VRAM in case this architecture 510 * will not allow USWC mappings. 511 * Also, don't allow GTT domain if the BO doesn't have USWC flag set. 512 */ 513 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 514 amdgpu_bo_support_uswc(bo_flags) && 515 amdgpu_device_asic_has_dc_support(adev->asic_type) && 516 adev->mode_info.gpu_vm_support) 517 domain |= AMDGPU_GEM_DOMAIN_GTT; 518 #endif 519 520 return domain; 521 } 522 523 static const struct drm_format_info dcc_formats[] = { 524 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 525 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 526 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 527 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 528 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 529 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 530 .has_alpha = true, }, 531 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 532 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 533 .has_alpha = true, }, 534 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2, 535 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 536 .has_alpha = true, }, 537 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 538 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 539 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 540 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 541 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 542 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 543 .has_alpha = true, }, 544 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 545 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 546 .has_alpha = true, }, 547 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2, 548 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 549 }; 550 551 static const struct drm_format_info dcc_retile_formats[] = { 552 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 553 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 554 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 555 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 556 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 557 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 558 .has_alpha = true, }, 559 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 560 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 561 .has_alpha = true, }, 562 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3, 563 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 564 .has_alpha = true, }, 565 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 566 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 567 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 568 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 569 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 570 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 571 .has_alpha = true, }, 572 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 573 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 574 .has_alpha = true, }, 575 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3, 576 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 577 }; 578 579 static const struct drm_format_info * 580 lookup_format_info(const struct drm_format_info formats[], 581 int num_formats, u32 format) 582 { 583 int i; 584 585 for (i = 0; i < num_formats; i++) { 586 if (formats[i].format == format) 587 return &formats[i]; 588 } 589 590 return NULL; 591 } 592 593 const struct drm_format_info * 594 amdgpu_lookup_format_info(u32 format, uint64_t modifier) 595 { 596 if (!IS_AMD_FMT_MOD(modifier)) 597 return NULL; 598 599 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) 600 return lookup_format_info(dcc_retile_formats, 601 ARRAY_SIZE(dcc_retile_formats), 602 format); 603 604 if (AMD_FMT_MOD_GET(DCC, modifier)) 605 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats), 606 format); 607 608 /* returning NULL will cause the default format structs to be used. */ 609 return NULL; 610 } 611 612 613 /* 614 * Tries to extract the renderable DCC offset from the opaque metadata attached 615 * to the buffer. 616 */ 617 static int 618 extract_render_dcc_offset(struct amdgpu_device *adev, 619 struct drm_gem_object *obj, 620 uint64_t *offset) 621 { 622 struct amdgpu_bo *rbo; 623 int r = 0; 624 uint32_t metadata[10]; /* Something that fits a descriptor + header. */ 625 uint32_t size; 626 627 rbo = gem_to_amdgpu_bo(obj); 628 r = amdgpu_bo_reserve(rbo, false); 629 630 if (unlikely(r)) { 631 /* Don't show error message when returning -ERESTARTSYS */ 632 if (r != -ERESTARTSYS) 633 DRM_ERROR("Unable to reserve buffer: %d\n", r); 634 return r; 635 } 636 637 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL); 638 amdgpu_bo_unreserve(rbo); 639 640 if (r) 641 return r; 642 643 /* 644 * The first word is the metadata version, and we need space for at least 645 * the version + pci vendor+device id + 8 words for a descriptor. 646 */ 647 if (size < 40 || metadata[0] != 1) 648 return -EINVAL; 649 650 if (adev->family >= AMDGPU_FAMILY_NV) { 651 /* resource word 6/7 META_DATA_ADDRESS{_LO} */ 652 *offset = ((u64)metadata[9] << 16u) | 653 ((metadata[8] & 0xFF000000u) >> 16); 654 } else { 655 /* resource word 5/7 META_DATA_ADDRESS */ 656 *offset = ((u64)metadata[9] << 8u) | 657 ((u64)(metadata[7] & 0x1FE0000u) << 23); 658 } 659 660 return 0; 661 } 662 663 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 664 { 665 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); 666 uint64_t modifier = 0; 667 668 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 669 modifier = DRM_FORMAT_MOD_LINEAR; 670 } else { 671 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 672 bool has_xor = swizzle >= 16; 673 int block_size_bits; 674 int version; 675 int pipe_xor_bits = 0; 676 int bank_xor_bits = 0; 677 int packers = 0; 678 int rb = 0; 679 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 680 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 681 682 switch (swizzle >> 2) { 683 case 0: /* 256B */ 684 block_size_bits = 8; 685 break; 686 case 1: /* 4KiB */ 687 case 5: /* 4KiB _X */ 688 block_size_bits = 12; 689 break; 690 case 2: /* 64KiB */ 691 case 4: /* 64 KiB _T */ 692 case 6: /* 64 KiB _X */ 693 block_size_bits = 16; 694 break; 695 default: 696 /* RESERVED or VAR */ 697 return -EINVAL; 698 } 699 700 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 701 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 702 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) 703 version = AMD_FMT_MOD_TILE_VER_GFX10; 704 else 705 version = AMD_FMT_MOD_TILE_VER_GFX9; 706 707 switch (swizzle & 3) { 708 case 0: /* Z microtiling */ 709 return -EINVAL; 710 case 1: /* S microtiling */ 711 if (!has_xor) 712 version = AMD_FMT_MOD_TILE_VER_GFX9; 713 break; 714 case 2: 715 if (!has_xor && afb->base.format->cpp[0] != 4) 716 version = AMD_FMT_MOD_TILE_VER_GFX9; 717 break; 718 case 3: 719 break; 720 } 721 722 if (has_xor) { 723 switch (version) { 724 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 725 pipe_xor_bits = min(block_size_bits - 8, pipes); 726 packers = min(block_size_bits - 8 - pipe_xor_bits, 727 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); 728 break; 729 case AMD_FMT_MOD_TILE_VER_GFX10: 730 pipe_xor_bits = min(block_size_bits - 8, pipes); 731 break; 732 case AMD_FMT_MOD_TILE_VER_GFX9: 733 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 734 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 735 pipe_xor_bits = min(block_size_bits - 8, pipes + 736 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 737 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, 738 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 739 break; 740 } 741 } 742 743 modifier = AMD_FMT_MOD | 744 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 745 AMD_FMT_MOD_SET(TILE_VERSION, version) | 746 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 747 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 748 AMD_FMT_MOD_SET(PACKERS, packers); 749 750 if (dcc_offset != 0) { 751 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 752 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 753 const struct drm_format_info *format_info; 754 u64 render_dcc_offset; 755 756 /* Enable constant encode on RAVEN2 and later. */ 757 bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN || 758 (adev->asic_type == CHIP_RAVEN && 759 adev->external_rev_id >= 0x81); 760 761 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : 762 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : 763 AMD_FMT_MOD_DCC_BLOCK_256B; 764 765 modifier |= AMD_FMT_MOD_SET(DCC, 1) | 766 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) | 767 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) | 768 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) | 769 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size); 770 771 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; 772 afb->base.pitches[1] = 773 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 774 775 /* 776 * If the userspace driver uses retiling the tiling flags do not contain 777 * info on the renderable DCC buffer. Luckily the opaque metadata contains 778 * the info so we can try to extract it. The kernel does not use this info 779 * but we should convert it to a modifier plane for getfb2, so the 780 * userspace driver that gets it doesn't have to juggle around another DCC 781 * plane internally. 782 */ 783 if (extract_render_dcc_offset(adev, afb->base.obj[0], 784 &render_dcc_offset) == 0 && 785 render_dcc_offset != 0 && 786 render_dcc_offset != afb->base.offsets[1] && 787 render_dcc_offset < UINT_MAX) { 788 uint32_t dcc_block_bits; /* of base surface data */ 789 790 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); 791 afb->base.offsets[2] = render_dcc_offset; 792 793 if (adev->family >= AMDGPU_FAMILY_NV) { 794 int extra_pipe = 0; 795 796 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && 797 pipes == packers && pipes > 1) 798 extra_pipe = 1; 799 800 dcc_block_bits = max(20, 16 + pipes + extra_pipe); 801 } else { 802 modifier |= AMD_FMT_MOD_SET(RB, rb) | 803 AMD_FMT_MOD_SET(PIPE, pipes); 804 dcc_block_bits = max(20, 18 + rb); 805 } 806 807 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); 808 afb->base.pitches[2] = ALIGN(afb->base.width, 809 1u << ((dcc_block_bits + 1) / 2)); 810 } 811 format_info = amdgpu_lookup_format_info(afb->base.format->format, 812 modifier); 813 if (!format_info) 814 return -EINVAL; 815 816 afb->base.format = format_info; 817 } 818 } 819 820 afb->base.modifier = modifier; 821 afb->base.flags |= DRM_MODE_FB_MODIFIERS; 822 return 0; 823 } 824 825 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ 826 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) 827 { 828 u64 micro_tile_mode; 829 830 /* Zero swizzle mode means linear */ 831 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) 832 return 0; 833 834 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); 835 switch (micro_tile_mode) { 836 case 0: /* DISPLAY */ 837 case 3: /* RENDER */ 838 return 0; 839 default: 840 drm_dbg_kms(afb->base.dev, 841 "Micro tile mode %llu not supported for scanout\n", 842 micro_tile_mode); 843 return -EINVAL; 844 } 845 } 846 847 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, 848 unsigned int *width, unsigned int *height) 849 { 850 unsigned int cpp_log2 = ilog2(cpp); 851 unsigned int pixel_log2 = block_log2 - cpp_log2; 852 unsigned int width_log2 = (pixel_log2 + 1) / 2; 853 unsigned int height_log2 = pixel_log2 - width_log2; 854 855 *width = 1 << width_log2; 856 *height = 1 << height_log2; 857 } 858 859 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, 860 bool pipe_aligned) 861 { 862 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); 863 864 switch (ver) { 865 case AMD_FMT_MOD_TILE_VER_GFX9: { 866 /* 867 * TODO: for pipe aligned we may need to check the alignment of the 868 * total size of the surface, which may need to be bigger than the 869 * natural alignment due to some HW workarounds 870 */ 871 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); 872 } 873 case AMD_FMT_MOD_TILE_VER_GFX10: 874 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: { 875 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 876 877 if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && 878 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) 879 ++pipes_log2; 880 881 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12); 882 } 883 default: 884 return 0; 885 } 886 } 887 888 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane, 889 const struct drm_format_info *format, 890 unsigned int block_width, unsigned int block_height, 891 unsigned int block_size_log2) 892 { 893 unsigned int width = rfb->base.width / 894 ((plane && plane < format->num_planes) ? format->hsub : 1); 895 unsigned int height = rfb->base.height / 896 ((plane && plane < format->num_planes) ? format->vsub : 1); 897 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; 898 unsigned int block_pitch = block_width * cpp; 899 unsigned int min_pitch = ALIGN(width * cpp, block_pitch); 900 unsigned int block_size = 1 << block_size_log2; 901 uint64_t size; 902 903 if (rfb->base.pitches[plane] % block_pitch) { 904 drm_dbg_kms(rfb->base.dev, 905 "pitch %d for plane %d is not a multiple of block pitch %d\n", 906 rfb->base.pitches[plane], plane, block_pitch); 907 return -EINVAL; 908 } 909 if (rfb->base.pitches[plane] < min_pitch) { 910 drm_dbg_kms(rfb->base.dev, 911 "pitch %d for plane %d is less than minimum pitch %d\n", 912 rfb->base.pitches[plane], plane, min_pitch); 913 return -EINVAL; 914 } 915 916 /* Force at least natural alignment. */ 917 if (rfb->base.offsets[plane] % block_size) { 918 drm_dbg_kms(rfb->base.dev, 919 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n", 920 rfb->base.offsets[plane], plane, block_size); 921 return -EINVAL; 922 } 923 924 size = rfb->base.offsets[plane] + 925 (uint64_t)rfb->base.pitches[plane] / block_pitch * 926 block_size * DIV_ROUND_UP(height, block_height); 927 928 if (rfb->base.obj[0]->size < size) { 929 drm_dbg_kms(rfb->base.dev, 930 "BO size 0x%zx is less than 0x%llx required for plane %d\n", 931 rfb->base.obj[0]->size, size, plane); 932 return -EINVAL; 933 } 934 935 return 0; 936 } 937 938 939 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 940 { 941 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); 942 uint64_t modifier = rfb->base.modifier; 943 int ret; 944 unsigned int i, block_width, block_height, block_size_log2; 945 946 if (rfb->base.dev->mode_config.fb_modifiers_not_supported) 947 return 0; 948 949 for (i = 0; i < format_info->num_planes; ++i) { 950 if (modifier == DRM_FORMAT_MOD_LINEAR) { 951 block_width = 256 / format_info->cpp[i]; 952 block_height = 1; 953 block_size_log2 = 8; 954 } else { 955 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); 956 957 switch ((swizzle & ~3) + 1) { 958 case DC_SW_256B_S: 959 block_size_log2 = 8; 960 break; 961 case DC_SW_4KB_S: 962 case DC_SW_4KB_S_X: 963 block_size_log2 = 12; 964 break; 965 case DC_SW_64KB_S: 966 case DC_SW_64KB_S_T: 967 case DC_SW_64KB_S_X: 968 block_size_log2 = 16; 969 break; 970 default: 971 drm_dbg_kms(rfb->base.dev, 972 "Swizzle mode with unknown block size: %d\n", swizzle); 973 return -EINVAL; 974 } 975 976 get_block_dimensions(block_size_log2, format_info->cpp[i], 977 &block_width, &block_height); 978 } 979 980 ret = amdgpu_display_verify_plane(rfb, i, format_info, 981 block_width, block_height, block_size_log2); 982 if (ret) 983 return ret; 984 } 985 986 if (AMD_FMT_MOD_GET(DCC, modifier)) { 987 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { 988 block_size_log2 = get_dcc_block_size(modifier, false, false); 989 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 990 &block_width, &block_height); 991 ret = amdgpu_display_verify_plane(rfb, i, format_info, 992 block_width, block_height, 993 block_size_log2); 994 if (ret) 995 return ret; 996 997 ++i; 998 block_size_log2 = get_dcc_block_size(modifier, true, true); 999 } else { 1000 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); 1001 1002 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); 1003 } 1004 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1005 &block_width, &block_height); 1006 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1007 block_width, block_height, block_size_log2); 1008 if (ret) 1009 return ret; 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1016 uint64_t *tiling_flags, bool *tmz_surface) 1017 { 1018 struct amdgpu_bo *rbo; 1019 int r; 1020 1021 if (!amdgpu_fb) { 1022 *tiling_flags = 0; 1023 *tmz_surface = false; 1024 return 0; 1025 } 1026 1027 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1028 r = amdgpu_bo_reserve(rbo, false); 1029 1030 if (unlikely(r)) { 1031 /* Don't show error message when returning -ERESTARTSYS */ 1032 if (r != -ERESTARTSYS) 1033 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1034 return r; 1035 } 1036 1037 if (tiling_flags) 1038 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1039 1040 if (tmz_surface) 1041 *tmz_surface = amdgpu_bo_encrypted(rbo); 1042 1043 amdgpu_bo_unreserve(rbo); 1044 1045 return r; 1046 } 1047 1048 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, 1049 struct amdgpu_framebuffer *rfb, 1050 struct drm_file *file_priv, 1051 const struct drm_mode_fb_cmd2 *mode_cmd, 1052 struct drm_gem_object *obj) 1053 { 1054 int ret; 1055 1056 rfb->base.obj[0] = obj; 1057 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1058 /* Verify that the modifier is supported. */ 1059 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, 1060 mode_cmd->modifier[0])) { 1061 drm_dbg_kms(dev, 1062 "unsupported pixel format %p4cc / modifier 0x%llx\n", 1063 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 1064 1065 ret = -EINVAL; 1066 goto err; 1067 } 1068 1069 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); 1070 if (ret) 1071 goto err; 1072 1073 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 1074 if (ret) 1075 goto err; 1076 1077 return 0; 1078 err: 1079 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); 1080 rfb->base.obj[0] = NULL; 1081 return ret; 1082 } 1083 1084 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 1085 struct amdgpu_framebuffer *rfb, 1086 const struct drm_mode_fb_cmd2 *mode_cmd, 1087 struct drm_gem_object *obj) 1088 { 1089 struct amdgpu_device *adev = drm_to_adev(dev); 1090 int ret, i; 1091 1092 /* 1093 * This needs to happen before modifier conversion as that might change 1094 * the number of planes. 1095 */ 1096 for (i = 1; i < rfb->base.format->num_planes; ++i) { 1097 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 1098 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", 1099 i, mode_cmd->handles[0], mode_cmd->handles[i]); 1100 ret = -EINVAL; 1101 return ret; 1102 } 1103 } 1104 1105 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 1106 if (ret) 1107 return ret; 1108 1109 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { 1110 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, 1111 "GFX9+ requires FB check based on format modifier\n"); 1112 ret = check_tiling_flags_gfx6(rfb); 1113 if (ret) 1114 return ret; 1115 } 1116 1117 if (!dev->mode_config.fb_modifiers_not_supported && 1118 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { 1119 ret = convert_tiling_flags_to_modifier(rfb); 1120 if (ret) { 1121 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier", 1122 rfb->tiling_flags); 1123 return ret; 1124 } 1125 } 1126 1127 ret = amdgpu_display_verify_sizes(rfb); 1128 if (ret) 1129 return ret; 1130 1131 for (i = 0; i < rfb->base.format->num_planes; ++i) { 1132 drm_gem_object_get(rfb->base.obj[0]); 1133 rfb->base.obj[i] = rfb->base.obj[0]; 1134 } 1135 1136 return 0; 1137 } 1138 1139 struct drm_framebuffer * 1140 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 1141 struct drm_file *file_priv, 1142 const struct drm_mode_fb_cmd2 *mode_cmd) 1143 { 1144 struct amdgpu_framebuffer *amdgpu_fb; 1145 struct drm_gem_object *obj; 1146 struct amdgpu_bo *bo; 1147 uint32_t domains; 1148 int ret; 1149 1150 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1151 if (obj == NULL) { 1152 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " 1153 "can't create framebuffer\n", mode_cmd->handles[0]); 1154 return ERR_PTR(-ENOENT); 1155 } 1156 1157 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1158 bo = gem_to_amdgpu_bo(obj); 1159 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); 1160 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { 1161 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); 1162 drm_gem_object_put(obj); 1163 return ERR_PTR(-EINVAL); 1164 } 1165 1166 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 1167 if (amdgpu_fb == NULL) { 1168 drm_gem_object_put(obj); 1169 return ERR_PTR(-ENOMEM); 1170 } 1171 1172 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, 1173 mode_cmd, obj); 1174 if (ret) { 1175 kfree(amdgpu_fb); 1176 drm_gem_object_put(obj); 1177 return ERR_PTR(ret); 1178 } 1179 1180 drm_gem_object_put(obj); 1181 return &amdgpu_fb->base; 1182 } 1183 1184 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 1185 .fb_create = amdgpu_display_user_framebuffer_create, 1186 .output_poll_changed = drm_fb_helper_output_poll_changed, 1187 }; 1188 1189 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 1190 { { UNDERSCAN_OFF, "off" }, 1191 { UNDERSCAN_ON, "on" }, 1192 { UNDERSCAN_AUTO, "auto" }, 1193 }; 1194 1195 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 1196 { { AMDGPU_AUDIO_DISABLE, "off" }, 1197 { AMDGPU_AUDIO_ENABLE, "on" }, 1198 { AMDGPU_AUDIO_AUTO, "auto" }, 1199 }; 1200 1201 /* XXX support different dither options? spatial, temporal, both, etc. */ 1202 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 1203 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 1204 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 1205 }; 1206 1207 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 1208 { 1209 int sz; 1210 1211 adev->mode_info.coherent_mode_property = 1212 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 1213 if (!adev->mode_info.coherent_mode_property) 1214 return -ENOMEM; 1215 1216 adev->mode_info.load_detect_property = 1217 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 1218 if (!adev->mode_info.load_detect_property) 1219 return -ENOMEM; 1220 1221 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 1222 1223 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 1224 adev->mode_info.underscan_property = 1225 drm_property_create_enum(adev_to_drm(adev), 0, 1226 "underscan", 1227 amdgpu_underscan_enum_list, sz); 1228 1229 adev->mode_info.underscan_hborder_property = 1230 drm_property_create_range(adev_to_drm(adev), 0, 1231 "underscan hborder", 0, 128); 1232 if (!adev->mode_info.underscan_hborder_property) 1233 return -ENOMEM; 1234 1235 adev->mode_info.underscan_vborder_property = 1236 drm_property_create_range(adev_to_drm(adev), 0, 1237 "underscan vborder", 0, 128); 1238 if (!adev->mode_info.underscan_vborder_property) 1239 return -ENOMEM; 1240 1241 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 1242 adev->mode_info.audio_property = 1243 drm_property_create_enum(adev_to_drm(adev), 0, 1244 "audio", 1245 amdgpu_audio_enum_list, sz); 1246 1247 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 1248 adev->mode_info.dither_property = 1249 drm_property_create_enum(adev_to_drm(adev), 0, 1250 "dither", 1251 amdgpu_dither_enum_list, sz); 1252 1253 if (amdgpu_device_has_dc_support(adev)) { 1254 adev->mode_info.abm_level_property = 1255 drm_property_create_range(adev_to_drm(adev), 0, 1256 "abm level", 0, 4); 1257 if (!adev->mode_info.abm_level_property) 1258 return -ENOMEM; 1259 } 1260 1261 return 0; 1262 } 1263 1264 void amdgpu_display_update_priority(struct amdgpu_device *adev) 1265 { 1266 /* adjustment options for the display watermarks */ 1267 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 1268 adev->mode_info.disp_priority = 0; 1269 else 1270 adev->mode_info.disp_priority = amdgpu_disp_priority; 1271 1272 } 1273 1274 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 1275 { 1276 /* try and guess if this is a tv or a monitor */ 1277 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1278 (mode->vdisplay == 576) || /* 576p */ 1279 (mode->vdisplay == 720) || /* 720p */ 1280 (mode->vdisplay == 1080)) /* 1080p */ 1281 return true; 1282 else 1283 return false; 1284 } 1285 1286 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1287 const struct drm_display_mode *mode, 1288 struct drm_display_mode *adjusted_mode) 1289 { 1290 struct drm_device *dev = crtc->dev; 1291 struct drm_encoder *encoder; 1292 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1293 struct amdgpu_encoder *amdgpu_encoder; 1294 struct drm_connector *connector; 1295 u32 src_v = 1, dst_v = 1; 1296 u32 src_h = 1, dst_h = 1; 1297 1298 amdgpu_crtc->h_border = 0; 1299 amdgpu_crtc->v_border = 0; 1300 1301 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1302 if (encoder->crtc != crtc) 1303 continue; 1304 amdgpu_encoder = to_amdgpu_encoder(encoder); 1305 connector = amdgpu_get_connector_for_encoder(encoder); 1306 1307 /* set scaling */ 1308 if (amdgpu_encoder->rmx_type == RMX_OFF) 1309 amdgpu_crtc->rmx_type = RMX_OFF; 1310 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 1311 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 1312 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 1313 else 1314 amdgpu_crtc->rmx_type = RMX_OFF; 1315 /* copy native mode */ 1316 memcpy(&amdgpu_crtc->native_mode, 1317 &amdgpu_encoder->native_mode, 1318 sizeof(struct drm_display_mode)); 1319 src_v = crtc->mode.vdisplay; 1320 dst_v = amdgpu_crtc->native_mode.vdisplay; 1321 src_h = crtc->mode.hdisplay; 1322 dst_h = amdgpu_crtc->native_mode.hdisplay; 1323 1324 /* fix up for overscan on hdmi */ 1325 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1326 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 1327 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 1328 connector->display_info.is_hdmi && 1329 amdgpu_display_is_hdtv_mode(mode)))) { 1330 if (amdgpu_encoder->underscan_hborder != 0) 1331 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 1332 else 1333 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 1334 if (amdgpu_encoder->underscan_vborder != 0) 1335 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 1336 else 1337 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 1338 amdgpu_crtc->rmx_type = RMX_FULL; 1339 src_v = crtc->mode.vdisplay; 1340 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 1341 src_h = crtc->mode.hdisplay; 1342 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 1343 } 1344 } 1345 if (amdgpu_crtc->rmx_type != RMX_OFF) { 1346 fixed20_12 a, b; 1347 a.full = dfixed_const(src_v); 1348 b.full = dfixed_const(dst_v); 1349 amdgpu_crtc->vsc.full = dfixed_div(a, b); 1350 a.full = dfixed_const(src_h); 1351 b.full = dfixed_const(dst_h); 1352 amdgpu_crtc->hsc.full = dfixed_div(a, b); 1353 } else { 1354 amdgpu_crtc->vsc.full = dfixed_const(1); 1355 amdgpu_crtc->hsc.full = dfixed_const(1); 1356 } 1357 return true; 1358 } 1359 1360 /* 1361 * Retrieve current video scanout position of crtc on a given gpu, and 1362 * an optional accurate timestamp of when query happened. 1363 * 1364 * \param dev Device to query. 1365 * \param pipe Crtc to query. 1366 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1367 * For driver internal use only also supports these flags: 1368 * 1369 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1370 * of a fudged earlier start of vblank. 1371 * 1372 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1373 * fudged earlier start of vblank in *vpos and the distance 1374 * to true start of vblank in *hpos. 1375 * 1376 * \param *vpos Location where vertical scanout position should be stored. 1377 * \param *hpos Location where horizontal scanout position should go. 1378 * \param *stime Target location for timestamp taken immediately before 1379 * scanout position query. Can be NULL to skip timestamp. 1380 * \param *etime Target location for timestamp taken immediately after 1381 * scanout position query. Can be NULL to skip timestamp. 1382 * 1383 * Returns vpos as a positive number while in active scanout area. 1384 * Returns vpos as a negative number inside vblank, counting the number 1385 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1386 * until start of active scanout / end of vblank." 1387 * 1388 * \return Flags, or'ed together as follows: 1389 * 1390 * DRM_SCANOUTPOS_VALID = Query successful. 1391 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1392 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1393 * this flag means that returned position may be offset by a constant but 1394 * unknown small number of scanlines wrt. real scanout position. 1395 * 1396 */ 1397 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 1398 unsigned int pipe, unsigned int flags, int *vpos, 1399 int *hpos, ktime_t *stime, ktime_t *etime, 1400 const struct drm_display_mode *mode) 1401 { 1402 u32 vbl = 0, position = 0; 1403 int vbl_start, vbl_end, vtotal, ret = 0; 1404 bool in_vbl = true; 1405 1406 struct amdgpu_device *adev = drm_to_adev(dev); 1407 1408 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1409 1410 /* Get optional system timestamp before query. */ 1411 if (stime) 1412 *stime = ktime_get(); 1413 1414 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 1415 ret |= DRM_SCANOUTPOS_VALID; 1416 1417 /* Get optional system timestamp after query. */ 1418 if (etime) 1419 *etime = ktime_get(); 1420 1421 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1422 1423 /* Decode into vertical and horizontal scanout position. */ 1424 *vpos = position & 0x1fff; 1425 *hpos = (position >> 16) & 0x1fff; 1426 1427 /* Valid vblank area boundaries from gpu retrieved? */ 1428 if (vbl > 0) { 1429 /* Yes: Decode. */ 1430 ret |= DRM_SCANOUTPOS_ACCURATE; 1431 vbl_start = vbl & 0x1fff; 1432 vbl_end = (vbl >> 16) & 0x1fff; 1433 } 1434 else { 1435 /* No: Fake something reasonable which gives at least ok results. */ 1436 vbl_start = mode->crtc_vdisplay; 1437 vbl_end = 0; 1438 } 1439 1440 /* Called from driver internal vblank counter query code? */ 1441 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1442 /* Caller wants distance from real vbl_start in *hpos */ 1443 *hpos = *vpos - vbl_start; 1444 } 1445 1446 /* Fudge vblank to start a few scanlines earlier to handle the 1447 * problem that vblank irqs fire a few scanlines before start 1448 * of vblank. Some driver internal callers need the true vblank 1449 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1450 * 1451 * The cause of the "early" vblank irq is that the irq is triggered 1452 * by the line buffer logic when the line buffer read position enters 1453 * the vblank, whereas our crtc scanout position naturally lags the 1454 * line buffer read position. 1455 */ 1456 if (!(flags & USE_REAL_VBLANKSTART)) 1457 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1458 1459 /* Test scanout position against vblank region. */ 1460 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1461 in_vbl = false; 1462 1463 /* In vblank? */ 1464 if (in_vbl) 1465 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1466 1467 /* Called from driver internal vblank counter query code? */ 1468 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1469 /* Caller wants distance from fudged earlier vbl_start */ 1470 *vpos -= vbl_start; 1471 return ret; 1472 } 1473 1474 /* Check if inside vblank area and apply corrective offsets: 1475 * vpos will then be >=0 in video scanout area, but negative 1476 * within vblank area, counting down the number of lines until 1477 * start of scanout. 1478 */ 1479 1480 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1481 if (in_vbl && (*vpos >= vbl_start)) { 1482 vtotal = mode->crtc_vtotal; 1483 1484 /* With variable refresh rate displays the vpos can exceed 1485 * the vtotal value. Clamp to 0 to return -vbl_end instead 1486 * of guessing the remaining number of lines until scanout. 1487 */ 1488 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 1489 } 1490 1491 /* Correct for shifted end of vbl at vbl_end. */ 1492 *vpos = *vpos - vbl_end; 1493 1494 return ret; 1495 } 1496 1497 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 1498 { 1499 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 1500 return AMDGPU_CRTC_IRQ_NONE; 1501 1502 switch (crtc) { 1503 case 0: 1504 return AMDGPU_CRTC_IRQ_VBLANK1; 1505 case 1: 1506 return AMDGPU_CRTC_IRQ_VBLANK2; 1507 case 2: 1508 return AMDGPU_CRTC_IRQ_VBLANK3; 1509 case 3: 1510 return AMDGPU_CRTC_IRQ_VBLANK4; 1511 case 4: 1512 return AMDGPU_CRTC_IRQ_VBLANK5; 1513 case 5: 1514 return AMDGPU_CRTC_IRQ_VBLANK6; 1515 default: 1516 return AMDGPU_CRTC_IRQ_NONE; 1517 } 1518 } 1519 1520 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 1521 bool in_vblank_irq, int *vpos, 1522 int *hpos, ktime_t *stime, ktime_t *etime, 1523 const struct drm_display_mode *mode) 1524 { 1525 struct drm_device *dev = crtc->dev; 1526 unsigned int pipe = crtc->index; 1527 1528 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1529 stime, etime, mode); 1530 } 1531 1532 int amdgpu_display_suspend_helper(struct amdgpu_device *adev) 1533 { 1534 struct drm_device *dev = adev_to_drm(adev); 1535 struct drm_crtc *crtc; 1536 struct drm_connector *connector; 1537 struct drm_connector_list_iter iter; 1538 int r; 1539 1540 /* turn off display hw */ 1541 drm_modeset_lock_all(dev); 1542 drm_connector_list_iter_begin(dev, &iter); 1543 drm_for_each_connector_iter(connector, &iter) 1544 drm_helper_connector_dpms(connector, 1545 DRM_MODE_DPMS_OFF); 1546 drm_connector_list_iter_end(&iter); 1547 drm_modeset_unlock_all(dev); 1548 /* unpin the front buffers and cursors */ 1549 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1550 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1551 struct drm_framebuffer *fb = crtc->primary->fb; 1552 struct amdgpu_bo *robj; 1553 1554 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1555 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1556 r = amdgpu_bo_reserve(aobj, true); 1557 if (r == 0) { 1558 amdgpu_bo_unpin(aobj); 1559 amdgpu_bo_unreserve(aobj); 1560 } 1561 } 1562 1563 if (fb == NULL || fb->obj[0] == NULL) { 1564 continue; 1565 } 1566 robj = gem_to_amdgpu_bo(fb->obj[0]); 1567 r = amdgpu_bo_reserve(robj, true); 1568 if (r == 0) { 1569 amdgpu_bo_unpin(robj); 1570 amdgpu_bo_unreserve(robj); 1571 } 1572 } 1573 return 0; 1574 } 1575 1576 int amdgpu_display_resume_helper(struct amdgpu_device *adev) 1577 { 1578 struct drm_device *dev = adev_to_drm(adev); 1579 struct drm_connector *connector; 1580 struct drm_connector_list_iter iter; 1581 struct drm_crtc *crtc; 1582 int r; 1583 1584 /* pin cursors */ 1585 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1587 1588 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1589 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1590 r = amdgpu_bo_reserve(aobj, true); 1591 if (r == 0) { 1592 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 1593 if (r != 0) 1594 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 1595 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 1596 amdgpu_bo_unreserve(aobj); 1597 } 1598 } 1599 } 1600 1601 drm_helper_resume_force_mode(dev); 1602 1603 /* turn on display hw */ 1604 drm_modeset_lock_all(dev); 1605 1606 drm_connector_list_iter_begin(dev, &iter); 1607 drm_for_each_connector_iter(connector, &iter) 1608 drm_helper_connector_dpms(connector, 1609 DRM_MODE_DPMS_ON); 1610 drm_connector_list_iter_end(&iter); 1611 1612 drm_modeset_unlock_all(dev); 1613 1614 return 0; 1615 } 1616 1617