1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_runtime.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_vblank.h> 42 43 static void amdgpu_display_flip_callback(struct dma_fence *f, 44 struct dma_fence_cb *cb) 45 { 46 struct amdgpu_flip_work *work = 47 container_of(cb, struct amdgpu_flip_work, cb); 48 49 dma_fence_put(f); 50 schedule_work(&work->flip_work.work); 51 } 52 53 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 54 struct dma_fence **f) 55 { 56 struct dma_fence *fence= *f; 57 58 if (fence == NULL) 59 return false; 60 61 *f = NULL; 62 63 if (!dma_fence_add_callback(fence, &work->cb, 64 amdgpu_display_flip_callback)) 65 return true; 66 67 dma_fence_put(fence); 68 return false; 69 } 70 71 static void amdgpu_display_flip_work_func(struct work_struct *__work) 72 { 73 struct delayed_work *delayed_work = 74 container_of(__work, struct delayed_work, work); 75 struct amdgpu_flip_work *work = 76 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 77 struct amdgpu_device *adev = work->adev; 78 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 79 80 struct drm_crtc *crtc = &amdgpu_crtc->base; 81 unsigned long flags; 82 unsigned i; 83 int vpos, hpos; 84 85 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 86 return; 87 88 for (i = 0; i < work->shared_count; ++i) 89 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 90 return; 91 92 /* Wait until we're out of the vertical blank period before the one 93 * targeted by the flip 94 */ 95 if (amdgpu_crtc->enabled && 96 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, 97 &vpos, &hpos, NULL, NULL, 98 &crtc->hwmode) 99 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 100 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 101 (int)(work->target_vblank - 102 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 103 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 104 return; 105 } 106 107 /* We borrow the event spin lock for protecting flip_status */ 108 spin_lock_irqsave(&crtc->dev->event_lock, flags); 109 110 /* Do the flip (mmio) */ 111 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 112 113 /* Set the flip status */ 114 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 115 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 116 117 118 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 119 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 120 121 } 122 123 /* 124 * Handle unpin events outside the interrupt handler proper. 125 */ 126 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 127 { 128 struct amdgpu_flip_work *work = 129 container_of(__work, struct amdgpu_flip_work, unpin_work); 130 int r; 131 132 /* unpin of the old buffer */ 133 r = amdgpu_bo_reserve(work->old_abo, true); 134 if (likely(r == 0)) { 135 r = amdgpu_bo_unpin(work->old_abo); 136 if (unlikely(r != 0)) { 137 DRM_ERROR("failed to unpin buffer after flip\n"); 138 } 139 amdgpu_bo_unreserve(work->old_abo); 140 } else 141 DRM_ERROR("failed to reserve buffer after flip\n"); 142 143 amdgpu_bo_unref(&work->old_abo); 144 kfree(work->shared); 145 kfree(work); 146 } 147 148 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 149 struct drm_framebuffer *fb, 150 struct drm_pending_vblank_event *event, 151 uint32_t page_flip_flags, uint32_t target, 152 struct drm_modeset_acquire_ctx *ctx) 153 { 154 struct drm_device *dev = crtc->dev; 155 struct amdgpu_device *adev = dev->dev_private; 156 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 157 struct drm_gem_object *obj; 158 struct amdgpu_flip_work *work; 159 struct amdgpu_bo *new_abo; 160 unsigned long flags; 161 u64 tiling_flags; 162 int i, r; 163 164 work = kzalloc(sizeof *work, GFP_KERNEL); 165 if (work == NULL) 166 return -ENOMEM; 167 168 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 169 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 170 171 work->event = event; 172 work->adev = adev; 173 work->crtc_id = amdgpu_crtc->crtc_id; 174 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 175 176 /* schedule unpin of the old buffer */ 177 obj = crtc->primary->fb->obj[0]; 178 179 /* take a reference to the old object */ 180 work->old_abo = gem_to_amdgpu_bo(obj); 181 amdgpu_bo_ref(work->old_abo); 182 183 obj = fb->obj[0]; 184 new_abo = gem_to_amdgpu_bo(obj); 185 186 /* pin the new buffer */ 187 r = amdgpu_bo_reserve(new_abo, false); 188 if (unlikely(r != 0)) { 189 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 190 goto cleanup; 191 } 192 193 if (!adev->enable_virtual_display) { 194 r = amdgpu_bo_pin(new_abo, 195 amdgpu_display_supported_domains(adev, new_abo->flags)); 196 if (unlikely(r != 0)) { 197 DRM_ERROR("failed to pin new abo buffer before flip\n"); 198 goto unreserve; 199 } 200 } 201 202 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 203 if (unlikely(r != 0)) { 204 DRM_ERROR("%p bind failed\n", new_abo); 205 goto unpin; 206 } 207 208 r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, 209 &work->shared_count, 210 &work->shared); 211 if (unlikely(r != 0)) { 212 DRM_ERROR("failed to get fences for buffer\n"); 213 goto unpin; 214 } 215 216 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 217 amdgpu_bo_unreserve(new_abo); 218 219 if (!adev->enable_virtual_display) 220 work->base = amdgpu_bo_gpu_offset(new_abo); 221 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 222 amdgpu_get_vblank_counter_kms(crtc); 223 224 /* we borrow the event spin lock for protecting flip_wrok */ 225 spin_lock_irqsave(&crtc->dev->event_lock, flags); 226 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 227 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 228 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 229 r = -EBUSY; 230 goto pflip_cleanup; 231 } 232 233 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 234 amdgpu_crtc->pflip_works = work; 235 236 237 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 238 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 239 /* update crtc fb */ 240 crtc->primary->fb = fb; 241 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 242 amdgpu_display_flip_work_func(&work->flip_work.work); 243 return 0; 244 245 pflip_cleanup: 246 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 247 DRM_ERROR("failed to reserve new abo in error path\n"); 248 goto cleanup; 249 } 250 unpin: 251 if (!adev->enable_virtual_display) 252 if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) 253 DRM_ERROR("failed to unpin new abo in error path\n"); 254 255 unreserve: 256 amdgpu_bo_unreserve(new_abo); 257 258 cleanup: 259 amdgpu_bo_unref(&work->old_abo); 260 dma_fence_put(work->excl); 261 for (i = 0; i < work->shared_count; ++i) 262 dma_fence_put(work->shared[i]); 263 kfree(work->shared); 264 kfree(work); 265 266 return r; 267 } 268 269 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 270 struct drm_modeset_acquire_ctx *ctx) 271 { 272 struct drm_device *dev; 273 struct amdgpu_device *adev; 274 struct drm_crtc *crtc; 275 bool active = false; 276 int ret; 277 278 if (!set || !set->crtc) 279 return -EINVAL; 280 281 dev = set->crtc->dev; 282 283 ret = pm_runtime_get_sync(dev->dev); 284 if (ret < 0) 285 return ret; 286 287 ret = drm_crtc_helper_set_config(set, ctx); 288 289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 290 if (crtc->enabled) 291 active = true; 292 293 pm_runtime_mark_last_busy(dev->dev); 294 295 adev = dev->dev_private; 296 /* if we have active crtcs and we don't have a power ref, 297 take the current one */ 298 if (active && !adev->have_disp_power_ref) { 299 adev->have_disp_power_ref = true; 300 return ret; 301 } 302 /* if we have no active crtcs, then drop the power ref 303 we got before */ 304 if (!active && adev->have_disp_power_ref) { 305 pm_runtime_put_autosuspend(dev->dev); 306 adev->have_disp_power_ref = false; 307 } 308 309 /* drop the power reference we got coming in here */ 310 pm_runtime_put_autosuspend(dev->dev); 311 return ret; 312 } 313 314 static const char *encoder_names[41] = { 315 "NONE", 316 "INTERNAL_LVDS", 317 "INTERNAL_TMDS1", 318 "INTERNAL_TMDS2", 319 "INTERNAL_DAC1", 320 "INTERNAL_DAC2", 321 "INTERNAL_SDVOA", 322 "INTERNAL_SDVOB", 323 "SI170B", 324 "CH7303", 325 "CH7301", 326 "INTERNAL_DVO1", 327 "EXTERNAL_SDVOA", 328 "EXTERNAL_SDVOB", 329 "TITFP513", 330 "INTERNAL_LVTM1", 331 "VT1623", 332 "HDMI_SI1930", 333 "HDMI_INTERNAL", 334 "INTERNAL_KLDSCP_TMDS1", 335 "INTERNAL_KLDSCP_DVO1", 336 "INTERNAL_KLDSCP_DAC1", 337 "INTERNAL_KLDSCP_DAC2", 338 "SI178", 339 "MVPU_FPGA", 340 "INTERNAL_DDI", 341 "VT1625", 342 "HDMI_SI1932", 343 "DP_AN9801", 344 "DP_DP501", 345 "INTERNAL_UNIPHY", 346 "INTERNAL_KLDSCP_LVTMA", 347 "INTERNAL_UNIPHY1", 348 "INTERNAL_UNIPHY2", 349 "NUTMEG", 350 "TRAVIS", 351 "INTERNAL_VCE", 352 "INTERNAL_UNIPHY3", 353 "HDMI_ANX9805", 354 "INTERNAL_AMCLK", 355 "VIRTUAL", 356 }; 357 358 static const char *hpd_names[6] = { 359 "HPD1", 360 "HPD2", 361 "HPD3", 362 "HPD4", 363 "HPD5", 364 "HPD6", 365 }; 366 367 void amdgpu_display_print_display_setup(struct drm_device *dev) 368 { 369 struct drm_connector *connector; 370 struct amdgpu_connector *amdgpu_connector; 371 struct drm_encoder *encoder; 372 struct amdgpu_encoder *amdgpu_encoder; 373 struct drm_connector_list_iter iter; 374 uint32_t devices; 375 int i = 0; 376 377 drm_connector_list_iter_begin(dev, &iter); 378 DRM_INFO("AMDGPU Display Connectors\n"); 379 drm_for_each_connector_iter(connector, &iter) { 380 amdgpu_connector = to_amdgpu_connector(connector); 381 DRM_INFO("Connector %d:\n", i); 382 DRM_INFO(" %s\n", connector->name); 383 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 384 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 385 if (amdgpu_connector->ddc_bus) { 386 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 387 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 388 amdgpu_connector->ddc_bus->rec.mask_data_reg, 389 amdgpu_connector->ddc_bus->rec.a_clk_reg, 390 amdgpu_connector->ddc_bus->rec.a_data_reg, 391 amdgpu_connector->ddc_bus->rec.en_clk_reg, 392 amdgpu_connector->ddc_bus->rec.en_data_reg, 393 amdgpu_connector->ddc_bus->rec.y_clk_reg, 394 amdgpu_connector->ddc_bus->rec.y_data_reg); 395 if (amdgpu_connector->router.ddc_valid) 396 DRM_INFO(" DDC Router 0x%x/0x%x\n", 397 amdgpu_connector->router.ddc_mux_control_pin, 398 amdgpu_connector->router.ddc_mux_state); 399 if (amdgpu_connector->router.cd_valid) 400 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 401 amdgpu_connector->router.cd_mux_control_pin, 402 amdgpu_connector->router.cd_mux_state); 403 } else { 404 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 405 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 406 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 407 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 408 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 409 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 410 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 411 } 412 DRM_INFO(" Encoders:\n"); 413 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 414 amdgpu_encoder = to_amdgpu_encoder(encoder); 415 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 416 if (devices) { 417 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 418 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 419 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 420 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 421 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 422 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 423 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 424 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 425 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 426 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 427 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 428 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 429 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 430 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 431 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 432 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 433 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 434 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 435 if (devices & ATOM_DEVICE_TV1_SUPPORT) 436 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 437 if (devices & ATOM_DEVICE_CV_SUPPORT) 438 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 439 } 440 } 441 i++; 442 } 443 drm_connector_list_iter_end(&iter); 444 } 445 446 /** 447 * amdgpu_display_ddc_probe 448 * 449 */ 450 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 451 bool use_aux) 452 { 453 u8 out = 0x0; 454 u8 buf[8]; 455 int ret; 456 struct i2c_msg msgs[] = { 457 { 458 .addr = DDC_ADDR, 459 .flags = 0, 460 .len = 1, 461 .buf = &out, 462 }, 463 { 464 .addr = DDC_ADDR, 465 .flags = I2C_M_RD, 466 .len = 8, 467 .buf = buf, 468 } 469 }; 470 471 /* on hw with routers, select right port */ 472 if (amdgpu_connector->router.ddc_valid) 473 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 474 475 if (use_aux) { 476 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 477 } else { 478 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 479 } 480 481 if (ret != 2) 482 /* Couldn't find an accessible DDC on this connector */ 483 return false; 484 /* Probe also for valid EDID header 485 * EDID header starts with: 486 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 487 * Only the first 6 bytes must be valid as 488 * drm_edid_block_valid() can fix the last 2 bytes */ 489 if (drm_edid_header_is_valid(buf) < 6) { 490 /* Couldn't find an accessible EDID on this 491 * connector */ 492 return false; 493 } 494 return true; 495 } 496 497 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 498 .destroy = drm_gem_fb_destroy, 499 .create_handle = drm_gem_fb_create_handle, 500 }; 501 502 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 503 uint64_t bo_flags) 504 { 505 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 506 507 #if defined(CONFIG_DRM_AMD_DC) 508 /* 509 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 510 * is not supported for this board. But this mapping is required 511 * to avoid hang caused by placement of scanout BO in GTT on certain 512 * APUs. So force the BO placement to VRAM in case this architecture 513 * will not allow USWC mappings. 514 * Also, don't allow GTT domain if the BO doens't have USWC falg set. 515 */ 516 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 517 amdgpu_bo_support_uswc(bo_flags) && 518 amdgpu_device_asic_has_dc_support(adev->asic_type)) { 519 switch (adev->asic_type) { 520 case CHIP_CARRIZO: 521 case CHIP_STONEY: 522 domain |= AMDGPU_GEM_DOMAIN_GTT; 523 break; 524 case CHIP_RAVEN: 525 /* enable S/G on PCO and RV2 */ 526 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 527 (adev->apu_flags & AMD_APU_IS_PICASSO)) 528 domain |= AMDGPU_GEM_DOMAIN_GTT; 529 break; 530 default: 531 break; 532 } 533 } 534 #endif 535 536 return domain; 537 } 538 539 int amdgpu_display_framebuffer_init(struct drm_device *dev, 540 struct amdgpu_framebuffer *rfb, 541 const struct drm_mode_fb_cmd2 *mode_cmd, 542 struct drm_gem_object *obj) 543 { 544 int ret; 545 rfb->base.obj[0] = obj; 546 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 547 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 548 if (ret) { 549 rfb->base.obj[0] = NULL; 550 return ret; 551 } 552 return 0; 553 } 554 555 struct drm_framebuffer * 556 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 557 struct drm_file *file_priv, 558 const struct drm_mode_fb_cmd2 *mode_cmd) 559 { 560 struct drm_gem_object *obj; 561 struct amdgpu_framebuffer *amdgpu_fb; 562 int ret; 563 564 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 565 if (obj == NULL) { 566 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 567 "can't create framebuffer\n", mode_cmd->handles[0]); 568 return ERR_PTR(-ENOENT); 569 } 570 571 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 572 if (obj->import_attach) { 573 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 574 return ERR_PTR(-EINVAL); 575 } 576 577 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 578 if (amdgpu_fb == NULL) { 579 drm_gem_object_put_unlocked(obj); 580 return ERR_PTR(-ENOMEM); 581 } 582 583 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 584 if (ret) { 585 kfree(amdgpu_fb); 586 drm_gem_object_put_unlocked(obj); 587 return ERR_PTR(ret); 588 } 589 590 return &amdgpu_fb->base; 591 } 592 593 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 594 .fb_create = amdgpu_display_user_framebuffer_create, 595 .output_poll_changed = drm_fb_helper_output_poll_changed, 596 }; 597 598 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 599 { { UNDERSCAN_OFF, "off" }, 600 { UNDERSCAN_ON, "on" }, 601 { UNDERSCAN_AUTO, "auto" }, 602 }; 603 604 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 605 { { AMDGPU_AUDIO_DISABLE, "off" }, 606 { AMDGPU_AUDIO_ENABLE, "on" }, 607 { AMDGPU_AUDIO_AUTO, "auto" }, 608 }; 609 610 /* XXX support different dither options? spatial, temporal, both, etc. */ 611 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 612 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 613 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 614 }; 615 616 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 617 { 618 int sz; 619 620 adev->mode_info.coherent_mode_property = 621 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 622 if (!adev->mode_info.coherent_mode_property) 623 return -ENOMEM; 624 625 adev->mode_info.load_detect_property = 626 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 627 if (!adev->mode_info.load_detect_property) 628 return -ENOMEM; 629 630 drm_mode_create_scaling_mode_property(adev->ddev); 631 632 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 633 adev->mode_info.underscan_property = 634 drm_property_create_enum(adev->ddev, 0, 635 "underscan", 636 amdgpu_underscan_enum_list, sz); 637 638 adev->mode_info.underscan_hborder_property = 639 drm_property_create_range(adev->ddev, 0, 640 "underscan hborder", 0, 128); 641 if (!adev->mode_info.underscan_hborder_property) 642 return -ENOMEM; 643 644 adev->mode_info.underscan_vborder_property = 645 drm_property_create_range(adev->ddev, 0, 646 "underscan vborder", 0, 128); 647 if (!adev->mode_info.underscan_vborder_property) 648 return -ENOMEM; 649 650 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 651 adev->mode_info.audio_property = 652 drm_property_create_enum(adev->ddev, 0, 653 "audio", 654 amdgpu_audio_enum_list, sz); 655 656 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 657 adev->mode_info.dither_property = 658 drm_property_create_enum(adev->ddev, 0, 659 "dither", 660 amdgpu_dither_enum_list, sz); 661 662 if (amdgpu_device_has_dc_support(adev)) { 663 adev->mode_info.abm_level_property = 664 drm_property_create_range(adev->ddev, 0, 665 "abm level", 0, 4); 666 if (!adev->mode_info.abm_level_property) 667 return -ENOMEM; 668 } 669 670 return 0; 671 } 672 673 void amdgpu_display_update_priority(struct amdgpu_device *adev) 674 { 675 /* adjustment options for the display watermarks */ 676 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 677 adev->mode_info.disp_priority = 0; 678 else 679 adev->mode_info.disp_priority = amdgpu_disp_priority; 680 681 } 682 683 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 684 { 685 /* try and guess if this is a tv or a monitor */ 686 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 687 (mode->vdisplay == 576) || /* 576p */ 688 (mode->vdisplay == 720) || /* 720p */ 689 (mode->vdisplay == 1080)) /* 1080p */ 690 return true; 691 else 692 return false; 693 } 694 695 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 696 const struct drm_display_mode *mode, 697 struct drm_display_mode *adjusted_mode) 698 { 699 struct drm_device *dev = crtc->dev; 700 struct drm_encoder *encoder; 701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 702 struct amdgpu_encoder *amdgpu_encoder; 703 struct drm_connector *connector; 704 u32 src_v = 1, dst_v = 1; 705 u32 src_h = 1, dst_h = 1; 706 707 amdgpu_crtc->h_border = 0; 708 amdgpu_crtc->v_border = 0; 709 710 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 711 if (encoder->crtc != crtc) 712 continue; 713 amdgpu_encoder = to_amdgpu_encoder(encoder); 714 connector = amdgpu_get_connector_for_encoder(encoder); 715 716 /* set scaling */ 717 if (amdgpu_encoder->rmx_type == RMX_OFF) 718 amdgpu_crtc->rmx_type = RMX_OFF; 719 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 720 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 721 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 722 else 723 amdgpu_crtc->rmx_type = RMX_OFF; 724 /* copy native mode */ 725 memcpy(&amdgpu_crtc->native_mode, 726 &amdgpu_encoder->native_mode, 727 sizeof(struct drm_display_mode)); 728 src_v = crtc->mode.vdisplay; 729 dst_v = amdgpu_crtc->native_mode.vdisplay; 730 src_h = crtc->mode.hdisplay; 731 dst_h = amdgpu_crtc->native_mode.hdisplay; 732 733 /* fix up for overscan on hdmi */ 734 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 735 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 736 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 737 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 738 amdgpu_display_is_hdtv_mode(mode)))) { 739 if (amdgpu_encoder->underscan_hborder != 0) 740 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 741 else 742 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 743 if (amdgpu_encoder->underscan_vborder != 0) 744 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 745 else 746 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 747 amdgpu_crtc->rmx_type = RMX_FULL; 748 src_v = crtc->mode.vdisplay; 749 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 750 src_h = crtc->mode.hdisplay; 751 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 752 } 753 } 754 if (amdgpu_crtc->rmx_type != RMX_OFF) { 755 fixed20_12 a, b; 756 a.full = dfixed_const(src_v); 757 b.full = dfixed_const(dst_v); 758 amdgpu_crtc->vsc.full = dfixed_div(a, b); 759 a.full = dfixed_const(src_h); 760 b.full = dfixed_const(dst_h); 761 amdgpu_crtc->hsc.full = dfixed_div(a, b); 762 } else { 763 amdgpu_crtc->vsc.full = dfixed_const(1); 764 amdgpu_crtc->hsc.full = dfixed_const(1); 765 } 766 return true; 767 } 768 769 /* 770 * Retrieve current video scanout position of crtc on a given gpu, and 771 * an optional accurate timestamp of when query happened. 772 * 773 * \param dev Device to query. 774 * \param pipe Crtc to query. 775 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 776 * For driver internal use only also supports these flags: 777 * 778 * USE_REAL_VBLANKSTART to use the real start of vblank instead 779 * of a fudged earlier start of vblank. 780 * 781 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 782 * fudged earlier start of vblank in *vpos and the distance 783 * to true start of vblank in *hpos. 784 * 785 * \param *vpos Location where vertical scanout position should be stored. 786 * \param *hpos Location where horizontal scanout position should go. 787 * \param *stime Target location for timestamp taken immediately before 788 * scanout position query. Can be NULL to skip timestamp. 789 * \param *etime Target location for timestamp taken immediately after 790 * scanout position query. Can be NULL to skip timestamp. 791 * 792 * Returns vpos as a positive number while in active scanout area. 793 * Returns vpos as a negative number inside vblank, counting the number 794 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 795 * until start of active scanout / end of vblank." 796 * 797 * \return Flags, or'ed together as follows: 798 * 799 * DRM_SCANOUTPOS_VALID = Query successful. 800 * DRM_SCANOUTPOS_INVBL = Inside vblank. 801 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 802 * this flag means that returned position may be offset by a constant but 803 * unknown small number of scanlines wrt. real scanout position. 804 * 805 */ 806 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 807 unsigned int pipe, unsigned int flags, int *vpos, 808 int *hpos, ktime_t *stime, ktime_t *etime, 809 const struct drm_display_mode *mode) 810 { 811 u32 vbl = 0, position = 0; 812 int vbl_start, vbl_end, vtotal, ret = 0; 813 bool in_vbl = true; 814 815 struct amdgpu_device *adev = dev->dev_private; 816 817 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 818 819 /* Get optional system timestamp before query. */ 820 if (stime) 821 *stime = ktime_get(); 822 823 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 824 ret |= DRM_SCANOUTPOS_VALID; 825 826 /* Get optional system timestamp after query. */ 827 if (etime) 828 *etime = ktime_get(); 829 830 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 831 832 /* Decode into vertical and horizontal scanout position. */ 833 *vpos = position & 0x1fff; 834 *hpos = (position >> 16) & 0x1fff; 835 836 /* Valid vblank area boundaries from gpu retrieved? */ 837 if (vbl > 0) { 838 /* Yes: Decode. */ 839 ret |= DRM_SCANOUTPOS_ACCURATE; 840 vbl_start = vbl & 0x1fff; 841 vbl_end = (vbl >> 16) & 0x1fff; 842 } 843 else { 844 /* No: Fake something reasonable which gives at least ok results. */ 845 vbl_start = mode->crtc_vdisplay; 846 vbl_end = 0; 847 } 848 849 /* Called from driver internal vblank counter query code? */ 850 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 851 /* Caller wants distance from real vbl_start in *hpos */ 852 *hpos = *vpos - vbl_start; 853 } 854 855 /* Fudge vblank to start a few scanlines earlier to handle the 856 * problem that vblank irqs fire a few scanlines before start 857 * of vblank. Some driver internal callers need the true vblank 858 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 859 * 860 * The cause of the "early" vblank irq is that the irq is triggered 861 * by the line buffer logic when the line buffer read position enters 862 * the vblank, whereas our crtc scanout position naturally lags the 863 * line buffer read position. 864 */ 865 if (!(flags & USE_REAL_VBLANKSTART)) 866 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 867 868 /* Test scanout position against vblank region. */ 869 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 870 in_vbl = false; 871 872 /* In vblank? */ 873 if (in_vbl) 874 ret |= DRM_SCANOUTPOS_IN_VBLANK; 875 876 /* Called from driver internal vblank counter query code? */ 877 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 878 /* Caller wants distance from fudged earlier vbl_start */ 879 *vpos -= vbl_start; 880 return ret; 881 } 882 883 /* Check if inside vblank area and apply corrective offsets: 884 * vpos will then be >=0 in video scanout area, but negative 885 * within vblank area, counting down the number of lines until 886 * start of scanout. 887 */ 888 889 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 890 if (in_vbl && (*vpos >= vbl_start)) { 891 vtotal = mode->crtc_vtotal; 892 893 /* With variable refresh rate displays the vpos can exceed 894 * the vtotal value. Clamp to 0 to return -vbl_end instead 895 * of guessing the remaining number of lines until scanout. 896 */ 897 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 898 } 899 900 /* Correct for shifted end of vbl at vbl_end. */ 901 *vpos = *vpos - vbl_end; 902 903 return ret; 904 } 905 906 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 907 { 908 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 909 return AMDGPU_CRTC_IRQ_NONE; 910 911 switch (crtc) { 912 case 0: 913 return AMDGPU_CRTC_IRQ_VBLANK1; 914 case 1: 915 return AMDGPU_CRTC_IRQ_VBLANK2; 916 case 2: 917 return AMDGPU_CRTC_IRQ_VBLANK3; 918 case 3: 919 return AMDGPU_CRTC_IRQ_VBLANK4; 920 case 4: 921 return AMDGPU_CRTC_IRQ_VBLANK5; 922 case 5: 923 return AMDGPU_CRTC_IRQ_VBLANK6; 924 default: 925 return AMDGPU_CRTC_IRQ_NONE; 926 } 927 } 928 929 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 930 bool in_vblank_irq, int *vpos, 931 int *hpos, ktime_t *stime, ktime_t *etime, 932 const struct drm_display_mode *mode) 933 { 934 struct drm_device *dev = crtc->dev; 935 unsigned int pipe = crtc->index; 936 937 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 938 stime, etime, mode); 939 } 940