1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gmc_v11_0.h" 51 #include "gfxhub_v2_0.h" 52 #include "mmhub_v2_0.h" 53 #include "nbio_v2_3.h" 54 #include "nbio_v4_3.h" 55 #include "nbio_v7_2.h" 56 #include "hdp_v5_0.h" 57 #include "hdp_v6_0.h" 58 #include "nv.h" 59 #include "soc21.h" 60 #include "navi10_ih.h" 61 #include "ih_v6_0.h" 62 #include "gfx_v10_0.h" 63 #include "gfx_v11_0.h" 64 #include "sdma_v5_0.h" 65 #include "sdma_v5_2.h" 66 #include "sdma_v6_0.h" 67 #include "vcn_v2_0.h" 68 #include "jpeg_v2_0.h" 69 #include "vcn_v3_0.h" 70 #include "jpeg_v3_0.h" 71 #include "vcn_v4_0.h" 72 #include "jpeg_v4_0.h" 73 #include "amdgpu_vkms.h" 74 #include "mes_v10_1.h" 75 #include "mes_v11_0.h" 76 #include "smuio_v11_0.h" 77 #include "smuio_v11_0_6.h" 78 #include "smuio_v13_0.h" 79 #include "smuio_v13_0_6.h" 80 81 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 82 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 83 84 #define mmRCC_CONFIG_MEMSIZE 0xde3 85 #define mmMM_INDEX 0x0 86 #define mmMM_INDEX_HI 0x6 87 #define mmMM_DATA 0x1 88 89 static const char *hw_id_names[HW_ID_MAX] = { 90 [MP1_HWID] = "MP1", 91 [MP2_HWID] = "MP2", 92 [THM_HWID] = "THM", 93 [SMUIO_HWID] = "SMUIO", 94 [FUSE_HWID] = "FUSE", 95 [CLKA_HWID] = "CLKA", 96 [PWR_HWID] = "PWR", 97 [GC_HWID] = "GC", 98 [UVD_HWID] = "UVD", 99 [AUDIO_AZ_HWID] = "AUDIO_AZ", 100 [ACP_HWID] = "ACP", 101 [DCI_HWID] = "DCI", 102 [DMU_HWID] = "DMU", 103 [DCO_HWID] = "DCO", 104 [DIO_HWID] = "DIO", 105 [XDMA_HWID] = "XDMA", 106 [DCEAZ_HWID] = "DCEAZ", 107 [DAZ_HWID] = "DAZ", 108 [SDPMUX_HWID] = "SDPMUX", 109 [NTB_HWID] = "NTB", 110 [IOHC_HWID] = "IOHC", 111 [L2IMU_HWID] = "L2IMU", 112 [VCE_HWID] = "VCE", 113 [MMHUB_HWID] = "MMHUB", 114 [ATHUB_HWID] = "ATHUB", 115 [DBGU_NBIO_HWID] = "DBGU_NBIO", 116 [DFX_HWID] = "DFX", 117 [DBGU0_HWID] = "DBGU0", 118 [DBGU1_HWID] = "DBGU1", 119 [OSSSYS_HWID] = "OSSSYS", 120 [HDP_HWID] = "HDP", 121 [SDMA0_HWID] = "SDMA0", 122 [SDMA1_HWID] = "SDMA1", 123 [SDMA2_HWID] = "SDMA2", 124 [SDMA3_HWID] = "SDMA3", 125 [ISP_HWID] = "ISP", 126 [DBGU_IO_HWID] = "DBGU_IO", 127 [DF_HWID] = "DF", 128 [CLKB_HWID] = "CLKB", 129 [FCH_HWID] = "FCH", 130 [DFX_DAP_HWID] = "DFX_DAP", 131 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 132 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 133 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 134 [L1IMU3_HWID] = "L1IMU3", 135 [L1IMU4_HWID] = "L1IMU4", 136 [L1IMU5_HWID] = "L1IMU5", 137 [L1IMU6_HWID] = "L1IMU6", 138 [L1IMU7_HWID] = "L1IMU7", 139 [L1IMU8_HWID] = "L1IMU8", 140 [L1IMU9_HWID] = "L1IMU9", 141 [L1IMU10_HWID] = "L1IMU10", 142 [L1IMU11_HWID] = "L1IMU11", 143 [L1IMU12_HWID] = "L1IMU12", 144 [L1IMU13_HWID] = "L1IMU13", 145 [L1IMU14_HWID] = "L1IMU14", 146 [L1IMU15_HWID] = "L1IMU15", 147 [WAFLC_HWID] = "WAFLC", 148 [FCH_USB_PD_HWID] = "FCH_USB_PD", 149 [PCIE_HWID] = "PCIE", 150 [PCS_HWID] = "PCS", 151 [DDCL_HWID] = "DDCL", 152 [SST_HWID] = "SST", 153 [IOAGR_HWID] = "IOAGR", 154 [NBIF_HWID] = "NBIF", 155 [IOAPIC_HWID] = "IOAPIC", 156 [SYSTEMHUB_HWID] = "SYSTEMHUB", 157 [NTBCCP_HWID] = "NTBCCP", 158 [UMC_HWID] = "UMC", 159 [SATA_HWID] = "SATA", 160 [USB_HWID] = "USB", 161 [CCXSEC_HWID] = "CCXSEC", 162 [XGMI_HWID] = "XGMI", 163 [XGBE_HWID] = "XGBE", 164 [MP0_HWID] = "MP0", 165 }; 166 167 static int hw_id_map[MAX_HWIP] = { 168 [GC_HWIP] = GC_HWID, 169 [HDP_HWIP] = HDP_HWID, 170 [SDMA0_HWIP] = SDMA0_HWID, 171 [SDMA1_HWIP] = SDMA1_HWID, 172 [SDMA2_HWIP] = SDMA2_HWID, 173 [SDMA3_HWIP] = SDMA3_HWID, 174 [MMHUB_HWIP] = MMHUB_HWID, 175 [ATHUB_HWIP] = ATHUB_HWID, 176 [NBIO_HWIP] = NBIF_HWID, 177 [MP0_HWIP] = MP0_HWID, 178 [MP1_HWIP] = MP1_HWID, 179 [UVD_HWIP] = UVD_HWID, 180 [VCE_HWIP] = VCE_HWID, 181 [DF_HWIP] = DF_HWID, 182 [DCE_HWIP] = DMU_HWID, 183 [OSSSYS_HWIP] = OSSSYS_HWID, 184 [SMUIO_HWIP] = SMUIO_HWID, 185 [PWR_HWIP] = PWR_HWID, 186 [NBIF_HWIP] = NBIF_HWID, 187 [THM_HWIP] = THM_HWID, 188 [CLK_HWIP] = CLKA_HWID, 189 [UMC_HWIP] = UMC_HWID, 190 [XGMI_HWIP] = XGMI_HWID, 191 [DCI_HWIP] = DCI_HWID, 192 }; 193 194 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 195 { 196 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 197 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 198 199 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 200 adev->mman.discovery_tmr_size, false); 201 return 0; 202 } 203 204 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 205 { 206 const struct firmware *fw; 207 const char *fw_name; 208 int r; 209 210 switch (amdgpu_discovery) { 211 case 2: 212 fw_name = FIRMWARE_IP_DISCOVERY; 213 break; 214 default: 215 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 216 return -EINVAL; 217 } 218 219 r = request_firmware(&fw, fw_name, adev->dev); 220 if (r) { 221 dev_err(adev->dev, "can't load firmware \"%s\"\n", 222 fw_name); 223 return r; 224 } 225 226 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 227 release_firmware(fw); 228 229 return 0; 230 } 231 232 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 233 { 234 uint16_t checksum = 0; 235 int i; 236 237 for (i = 0; i < size; i++) 238 checksum += data[i]; 239 240 return checksum; 241 } 242 243 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 244 uint16_t expected) 245 { 246 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 247 } 248 249 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 250 { 251 struct binary_header *bhdr; 252 bhdr = (struct binary_header *)binary; 253 254 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 255 } 256 257 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 258 { 259 /* 260 * So far, apply this quirk only on those Navy Flounder boards which 261 * have a bad harvest table of VCN config. 262 */ 263 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 264 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 265 switch (adev->pdev->revision) { 266 case 0xC1: 267 case 0xC2: 268 case 0xC3: 269 case 0xC5: 270 case 0xC7: 271 case 0xCF: 272 case 0xDF: 273 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 274 break; 275 default: 276 break; 277 } 278 } 279 } 280 281 static int amdgpu_discovery_init(struct amdgpu_device *adev) 282 { 283 struct table_info *info; 284 struct binary_header *bhdr; 285 uint16_t offset; 286 uint16_t size; 287 uint16_t checksum; 288 int r; 289 290 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 291 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 292 if (!adev->mman.discovery_bin) 293 return -ENOMEM; 294 295 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 296 if (r) { 297 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 298 r = -EINVAL; 299 goto out; 300 } 301 302 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 303 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 304 /* retry read ip discovery binary from file */ 305 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 306 if (r) { 307 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 308 r = -EINVAL; 309 goto out; 310 } 311 /* check the ip discovery binary signature */ 312 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 313 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 314 r = -EINVAL; 315 goto out; 316 } 317 } 318 319 bhdr = (struct binary_header *)adev->mman.discovery_bin; 320 321 offset = offsetof(struct binary_header, binary_checksum) + 322 sizeof(bhdr->binary_checksum); 323 size = le16_to_cpu(bhdr->binary_size) - offset; 324 checksum = le16_to_cpu(bhdr->binary_checksum); 325 326 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 327 size, checksum)) { 328 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 329 r = -EINVAL; 330 goto out; 331 } 332 333 info = &bhdr->table_list[IP_DISCOVERY]; 334 offset = le16_to_cpu(info->offset); 335 checksum = le16_to_cpu(info->checksum); 336 337 if (offset) { 338 struct ip_discovery_header *ihdr = 339 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 340 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 341 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 342 r = -EINVAL; 343 goto out; 344 } 345 346 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 347 le16_to_cpu(ihdr->size), checksum)) { 348 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 349 r = -EINVAL; 350 goto out; 351 } 352 } 353 354 info = &bhdr->table_list[GC]; 355 offset = le16_to_cpu(info->offset); 356 checksum = le16_to_cpu(info->checksum); 357 358 if (offset) { 359 struct gpu_info_header *ghdr = 360 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 361 362 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 363 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 364 r = -EINVAL; 365 goto out; 366 } 367 368 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 369 le32_to_cpu(ghdr->size), checksum)) { 370 dev_err(adev->dev, "invalid gc data table checksum\n"); 371 r = -EINVAL; 372 goto out; 373 } 374 } 375 376 info = &bhdr->table_list[HARVEST_INFO]; 377 offset = le16_to_cpu(info->offset); 378 checksum = le16_to_cpu(info->checksum); 379 380 if (offset) { 381 struct harvest_info_header *hhdr = 382 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 383 384 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 385 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 386 r = -EINVAL; 387 goto out; 388 } 389 390 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 391 sizeof(struct harvest_table), checksum)) { 392 dev_err(adev->dev, "invalid harvest data table checksum\n"); 393 r = -EINVAL; 394 goto out; 395 } 396 } 397 398 info = &bhdr->table_list[VCN_INFO]; 399 offset = le16_to_cpu(info->offset); 400 checksum = le16_to_cpu(info->checksum); 401 402 if (offset) { 403 struct vcn_info_header *vhdr = 404 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 405 406 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 407 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 408 r = -EINVAL; 409 goto out; 410 } 411 412 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 413 le32_to_cpu(vhdr->size_bytes), checksum)) { 414 dev_err(adev->dev, "invalid vcn data table checksum\n"); 415 r = -EINVAL; 416 goto out; 417 } 418 } 419 420 info = &bhdr->table_list[MALL_INFO]; 421 offset = le16_to_cpu(info->offset); 422 checksum = le16_to_cpu(info->checksum); 423 424 if (0 && offset) { 425 struct mall_info_header *mhdr = 426 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 427 428 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 429 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 430 r = -EINVAL; 431 goto out; 432 } 433 434 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 435 le32_to_cpu(mhdr->size_bytes), checksum)) { 436 dev_err(adev->dev, "invalid mall data table checksum\n"); 437 r = -EINVAL; 438 goto out; 439 } 440 } 441 442 return 0; 443 444 out: 445 kfree(adev->mman.discovery_bin); 446 adev->mman.discovery_bin = NULL; 447 448 return r; 449 } 450 451 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 452 453 void amdgpu_discovery_fini(struct amdgpu_device *adev) 454 { 455 amdgpu_discovery_sysfs_fini(adev); 456 kfree(adev->mman.discovery_bin); 457 adev->mman.discovery_bin = NULL; 458 } 459 460 static int amdgpu_discovery_validate_ip(const struct ip *ip) 461 { 462 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 463 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 464 ip->number_instance); 465 return -EINVAL; 466 } 467 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 468 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 469 le16_to_cpu(ip->hw_id)); 470 return -EINVAL; 471 } 472 473 return 0; 474 } 475 476 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 477 uint32_t *vcn_harvest_count) 478 { 479 struct binary_header *bhdr; 480 struct ip_discovery_header *ihdr; 481 struct die_header *dhdr; 482 struct ip *ip; 483 uint16_t die_offset, ip_offset, num_dies, num_ips; 484 int i, j; 485 486 bhdr = (struct binary_header *)adev->mman.discovery_bin; 487 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 488 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 489 num_dies = le16_to_cpu(ihdr->num_dies); 490 491 /* scan harvest bit of all IP data structures */ 492 for (i = 0; i < num_dies; i++) { 493 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 494 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 495 num_ips = le16_to_cpu(dhdr->num_ips); 496 ip_offset = die_offset + sizeof(*dhdr); 497 498 for (j = 0; j < num_ips; j++) { 499 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 500 501 if (amdgpu_discovery_validate_ip(ip)) 502 goto next_ip; 503 504 if (le16_to_cpu(ip->harvest) == 1) { 505 switch (le16_to_cpu(ip->hw_id)) { 506 case VCN_HWID: 507 (*vcn_harvest_count)++; 508 if (ip->number_instance == 0) 509 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 510 else 511 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 512 break; 513 case DMU_HWID: 514 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 515 break; 516 default: 517 break; 518 } 519 } 520 next_ip: 521 ip_offset += struct_size(ip, base_address, ip->num_base_address); 522 } 523 } 524 } 525 526 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 527 uint32_t *vcn_harvest_count, 528 uint32_t *umc_harvest_count) 529 { 530 struct binary_header *bhdr; 531 struct harvest_table *harvest_info; 532 u16 offset; 533 int i; 534 535 bhdr = (struct binary_header *)adev->mman.discovery_bin; 536 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 537 538 if (!offset) { 539 dev_err(adev->dev, "invalid harvest table offset\n"); 540 return; 541 } 542 543 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 544 545 for (i = 0; i < 32; i++) { 546 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 547 break; 548 549 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 550 case VCN_HWID: 551 (*vcn_harvest_count)++; 552 if (harvest_info->list[i].number_instance == 0) 553 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 554 else 555 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 556 break; 557 case DMU_HWID: 558 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 559 break; 560 case UMC_HWID: 561 (*umc_harvest_count)++; 562 break; 563 default: 564 break; 565 } 566 } 567 } 568 569 /* ================================================== */ 570 571 struct ip_hw_instance { 572 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 573 574 int hw_id; 575 u8 num_instance; 576 u8 major, minor, revision; 577 u8 harvest; 578 579 int num_base_addresses; 580 u32 base_addr[]; 581 }; 582 583 struct ip_hw_id { 584 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 585 int hw_id; 586 }; 587 588 struct ip_die_entry { 589 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 590 u16 num_ips; 591 }; 592 593 /* -------------------------------------------------- */ 594 595 struct ip_hw_instance_attr { 596 struct attribute attr; 597 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 598 }; 599 600 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 601 { 602 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 603 } 604 605 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 606 { 607 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 608 } 609 610 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 611 { 612 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 613 } 614 615 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 616 { 617 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 618 } 619 620 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 621 { 622 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 623 } 624 625 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 626 { 627 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 628 } 629 630 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 631 { 632 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 633 } 634 635 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 636 { 637 ssize_t res, at; 638 int ii; 639 640 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 641 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 642 */ 643 if (at + 12 > PAGE_SIZE) 644 break; 645 res = sysfs_emit_at(buf, at, "0x%08X\n", 646 ip_hw_instance->base_addr[ii]); 647 if (res <= 0) 648 break; 649 at += res; 650 } 651 652 return res < 0 ? res : at; 653 } 654 655 static struct ip_hw_instance_attr ip_hw_attr[] = { 656 __ATTR_RO(hw_id), 657 __ATTR_RO(num_instance), 658 __ATTR_RO(major), 659 __ATTR_RO(minor), 660 __ATTR_RO(revision), 661 __ATTR_RO(harvest), 662 __ATTR_RO(num_base_addresses), 663 __ATTR_RO(base_addr), 664 }; 665 666 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 667 ATTRIBUTE_GROUPS(ip_hw_instance); 668 669 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 670 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 671 672 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 673 struct attribute *attr, 674 char *buf) 675 { 676 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 677 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 678 679 if (!ip_hw_attr->show) 680 return -EIO; 681 682 return ip_hw_attr->show(ip_hw_instance, buf); 683 } 684 685 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 686 .show = ip_hw_instance_attr_show, 687 }; 688 689 static void ip_hw_instance_release(struct kobject *kobj) 690 { 691 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 692 693 kfree(ip_hw_instance); 694 } 695 696 static struct kobj_type ip_hw_instance_ktype = { 697 .release = ip_hw_instance_release, 698 .sysfs_ops = &ip_hw_instance_sysfs_ops, 699 .default_groups = ip_hw_instance_groups, 700 }; 701 702 /* -------------------------------------------------- */ 703 704 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 705 706 static void ip_hw_id_release(struct kobject *kobj) 707 { 708 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 709 710 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 711 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 712 kfree(ip_hw_id); 713 } 714 715 static struct kobj_type ip_hw_id_ktype = { 716 .release = ip_hw_id_release, 717 .sysfs_ops = &kobj_sysfs_ops, 718 }; 719 720 /* -------------------------------------------------- */ 721 722 static void die_kobj_release(struct kobject *kobj); 723 static void ip_disc_release(struct kobject *kobj); 724 725 struct ip_die_entry_attribute { 726 struct attribute attr; 727 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 728 }; 729 730 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 731 732 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 733 { 734 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 735 } 736 737 /* If there are more ip_die_entry attrs, other than the number of IPs, 738 * we can make this intro an array of attrs, and then initialize 739 * ip_die_entry_attrs in a loop. 740 */ 741 static struct ip_die_entry_attribute num_ips_attr = 742 __ATTR_RO(num_ips); 743 744 static struct attribute *ip_die_entry_attrs[] = { 745 &num_ips_attr.attr, 746 NULL, 747 }; 748 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 749 750 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 751 752 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 753 struct attribute *attr, 754 char *buf) 755 { 756 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 757 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 758 759 if (!ip_die_entry_attr->show) 760 return -EIO; 761 762 return ip_die_entry_attr->show(ip_die_entry, buf); 763 } 764 765 static void ip_die_entry_release(struct kobject *kobj) 766 { 767 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 768 769 if (!list_empty(&ip_die_entry->ip_kset.list)) 770 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 771 kfree(ip_die_entry); 772 } 773 774 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 775 .show = ip_die_entry_attr_show, 776 }; 777 778 static struct kobj_type ip_die_entry_ktype = { 779 .release = ip_die_entry_release, 780 .sysfs_ops = &ip_die_entry_sysfs_ops, 781 .default_groups = ip_die_entry_groups, 782 }; 783 784 static struct kobj_type die_kobj_ktype = { 785 .release = die_kobj_release, 786 .sysfs_ops = &kobj_sysfs_ops, 787 }; 788 789 static struct kobj_type ip_discovery_ktype = { 790 .release = ip_disc_release, 791 .sysfs_ops = &kobj_sysfs_ops, 792 }; 793 794 struct ip_discovery_top { 795 struct kobject kobj; /* ip_discovery/ */ 796 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 797 struct amdgpu_device *adev; 798 }; 799 800 static void die_kobj_release(struct kobject *kobj) 801 { 802 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 803 struct ip_discovery_top, 804 die_kset); 805 if (!list_empty(&ip_top->die_kset.list)) 806 DRM_ERROR("ip_top->die_kset is not empty"); 807 } 808 809 static void ip_disc_release(struct kobject *kobj) 810 { 811 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 812 kobj); 813 struct amdgpu_device *adev = ip_top->adev; 814 815 adev->ip_top = NULL; 816 kfree(ip_top); 817 } 818 819 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 820 struct ip_die_entry *ip_die_entry, 821 const size_t _ip_offset, const int num_ips) 822 { 823 int ii, jj, kk, res; 824 825 DRM_DEBUG("num_ips:%d", num_ips); 826 827 /* Find all IPs of a given HW ID, and add their instance to 828 * #die/#hw_id/#instance/<attributes> 829 */ 830 for (ii = 0; ii < HW_ID_MAX; ii++) { 831 struct ip_hw_id *ip_hw_id = NULL; 832 size_t ip_offset = _ip_offset; 833 834 for (jj = 0; jj < num_ips; jj++) { 835 struct ip *ip; 836 struct ip_hw_instance *ip_hw_instance; 837 838 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 839 if (amdgpu_discovery_validate_ip(ip) || 840 le16_to_cpu(ip->hw_id) != ii) 841 goto next_ip; 842 843 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 844 845 /* We have a hw_id match; register the hw 846 * block if not yet registered. 847 */ 848 if (!ip_hw_id) { 849 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 850 if (!ip_hw_id) 851 return -ENOMEM; 852 ip_hw_id->hw_id = ii; 853 854 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 855 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 856 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 857 res = kset_register(&ip_hw_id->hw_id_kset); 858 if (res) { 859 DRM_ERROR("Couldn't register ip_hw_id kset"); 860 kfree(ip_hw_id); 861 return res; 862 } 863 if (hw_id_names[ii]) { 864 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 865 &ip_hw_id->hw_id_kset.kobj, 866 hw_id_names[ii]); 867 if (res) { 868 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 869 hw_id_names[ii], 870 kobject_name(&ip_die_entry->ip_kset.kobj)); 871 } 872 } 873 } 874 875 /* Now register its instance. 876 */ 877 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 878 base_addr, 879 ip->num_base_address), 880 GFP_KERNEL); 881 if (!ip_hw_instance) { 882 DRM_ERROR("no memory for ip_hw_instance"); 883 return -ENOMEM; 884 } 885 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 886 ip_hw_instance->num_instance = ip->number_instance; 887 ip_hw_instance->major = ip->major; 888 ip_hw_instance->minor = ip->minor; 889 ip_hw_instance->revision = ip->revision; 890 ip_hw_instance->harvest = ip->harvest; 891 ip_hw_instance->num_base_addresses = ip->num_base_address; 892 893 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 894 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 895 896 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 897 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 898 res = kobject_add(&ip_hw_instance->kobj, NULL, 899 "%d", ip_hw_instance->num_instance); 900 next_ip: 901 ip_offset += struct_size(ip, base_address, ip->num_base_address); 902 } 903 } 904 905 return 0; 906 } 907 908 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 909 { 910 struct binary_header *bhdr; 911 struct ip_discovery_header *ihdr; 912 struct die_header *dhdr; 913 struct kset *die_kset = &adev->ip_top->die_kset; 914 u16 num_dies, die_offset, num_ips; 915 size_t ip_offset; 916 int ii, res; 917 918 bhdr = (struct binary_header *)adev->mman.discovery_bin; 919 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 920 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 921 num_dies = le16_to_cpu(ihdr->num_dies); 922 923 DRM_DEBUG("number of dies: %d\n", num_dies); 924 925 for (ii = 0; ii < num_dies; ii++) { 926 struct ip_die_entry *ip_die_entry; 927 928 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 929 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 930 num_ips = le16_to_cpu(dhdr->num_ips); 931 ip_offset = die_offset + sizeof(*dhdr); 932 933 /* Add the die to the kset. 934 * 935 * dhdr->die_id == ii, which was checked in 936 * amdgpu_discovery_reg_base_init(). 937 */ 938 939 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 940 if (!ip_die_entry) 941 return -ENOMEM; 942 943 ip_die_entry->num_ips = num_ips; 944 945 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 946 ip_die_entry->ip_kset.kobj.kset = die_kset; 947 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 948 res = kset_register(&ip_die_entry->ip_kset); 949 if (res) { 950 DRM_ERROR("Couldn't register ip_die_entry kset"); 951 kfree(ip_die_entry); 952 return res; 953 } 954 955 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 956 } 957 958 return 0; 959 } 960 961 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 962 { 963 struct kset *die_kset; 964 int res, ii; 965 966 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 967 if (!adev->ip_top) 968 return -ENOMEM; 969 970 adev->ip_top->adev = adev; 971 972 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 973 &adev->dev->kobj, "ip_discovery"); 974 if (res) { 975 DRM_ERROR("Couldn't init and add ip_discovery/"); 976 goto Err; 977 } 978 979 die_kset = &adev->ip_top->die_kset; 980 kobject_set_name(&die_kset->kobj, "%s", "die"); 981 die_kset->kobj.parent = &adev->ip_top->kobj; 982 die_kset->kobj.ktype = &die_kobj_ktype; 983 res = kset_register(&adev->ip_top->die_kset); 984 if (res) { 985 DRM_ERROR("Couldn't register die_kset"); 986 goto Err; 987 } 988 989 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 990 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 991 ip_hw_instance_attrs[ii] = NULL; 992 993 res = amdgpu_discovery_sysfs_recurse(adev); 994 995 return res; 996 Err: 997 kobject_put(&adev->ip_top->kobj); 998 return res; 999 } 1000 1001 /* -------------------------------------------------- */ 1002 1003 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1004 1005 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1006 { 1007 struct list_head *el, *tmp; 1008 struct kset *hw_id_kset; 1009 1010 hw_id_kset = &ip_hw_id->hw_id_kset; 1011 spin_lock(&hw_id_kset->list_lock); 1012 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1013 list_del_init(el); 1014 spin_unlock(&hw_id_kset->list_lock); 1015 /* kobject is embedded in ip_hw_instance */ 1016 kobject_put(list_to_kobj(el)); 1017 spin_lock(&hw_id_kset->list_lock); 1018 } 1019 spin_unlock(&hw_id_kset->list_lock); 1020 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1021 } 1022 1023 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1024 { 1025 struct list_head *el, *tmp; 1026 struct kset *ip_kset; 1027 1028 ip_kset = &ip_die_entry->ip_kset; 1029 spin_lock(&ip_kset->list_lock); 1030 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1031 list_del_init(el); 1032 spin_unlock(&ip_kset->list_lock); 1033 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1034 spin_lock(&ip_kset->list_lock); 1035 } 1036 spin_unlock(&ip_kset->list_lock); 1037 kobject_put(&ip_die_entry->ip_kset.kobj); 1038 } 1039 1040 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1041 { 1042 struct list_head *el, *tmp; 1043 struct kset *die_kset; 1044 1045 die_kset = &adev->ip_top->die_kset; 1046 spin_lock(&die_kset->list_lock); 1047 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1048 list_del_init(el); 1049 spin_unlock(&die_kset->list_lock); 1050 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1051 spin_lock(&die_kset->list_lock); 1052 } 1053 spin_unlock(&die_kset->list_lock); 1054 kobject_put(&adev->ip_top->die_kset.kobj); 1055 kobject_put(&adev->ip_top->kobj); 1056 } 1057 1058 /* ================================================== */ 1059 1060 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1061 { 1062 struct binary_header *bhdr; 1063 struct ip_discovery_header *ihdr; 1064 struct die_header *dhdr; 1065 struct ip *ip; 1066 uint16_t die_offset; 1067 uint16_t ip_offset; 1068 uint16_t num_dies; 1069 uint16_t num_ips; 1070 uint8_t num_base_address; 1071 int hw_ip; 1072 int i, j, k; 1073 int r; 1074 1075 r = amdgpu_discovery_init(adev); 1076 if (r) { 1077 DRM_ERROR("amdgpu_discovery_init failed\n"); 1078 return r; 1079 } 1080 1081 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1082 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1083 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1084 num_dies = le16_to_cpu(ihdr->num_dies); 1085 1086 DRM_DEBUG("number of dies: %d\n", num_dies); 1087 1088 for (i = 0; i < num_dies; i++) { 1089 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1090 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1091 num_ips = le16_to_cpu(dhdr->num_ips); 1092 ip_offset = die_offset + sizeof(*dhdr); 1093 1094 if (le16_to_cpu(dhdr->die_id) != i) { 1095 DRM_ERROR("invalid die id %d, expected %d\n", 1096 le16_to_cpu(dhdr->die_id), i); 1097 return -EINVAL; 1098 } 1099 1100 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1101 le16_to_cpu(dhdr->die_id), num_ips); 1102 1103 for (j = 0; j < num_ips; j++) { 1104 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1105 1106 if (amdgpu_discovery_validate_ip(ip)) 1107 goto next_ip; 1108 1109 num_base_address = ip->num_base_address; 1110 1111 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1112 hw_id_names[le16_to_cpu(ip->hw_id)], 1113 le16_to_cpu(ip->hw_id), 1114 ip->number_instance, 1115 ip->major, ip->minor, 1116 ip->revision); 1117 1118 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1119 /* Bit [5:0]: original revision value 1120 * Bit [7:6]: en/decode capability: 1121 * 0b00 : VCN function normally 1122 * 0b10 : encode is disabled 1123 * 0b01 : decode is disabled 1124 */ 1125 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1126 ip->revision & 0xc0; 1127 ip->revision &= ~0xc0; 1128 adev->vcn.num_vcn_inst++; 1129 } 1130 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1131 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1132 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1133 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 1134 adev->sdma.num_instances++; 1135 1136 if (le16_to_cpu(ip->hw_id) == UMC_HWID) 1137 adev->gmc.num_umc++; 1138 1139 for (k = 0; k < num_base_address; k++) { 1140 /* 1141 * convert the endianness of base addresses in place, 1142 * so that we don't need to convert them when accessing adev->reg_offset. 1143 */ 1144 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1145 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1146 } 1147 1148 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1149 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1150 DRM_DEBUG("set register base offset for %s\n", 1151 hw_id_names[le16_to_cpu(ip->hw_id)]); 1152 adev->reg_offset[hw_ip][ip->number_instance] = 1153 ip->base_address; 1154 /* Instance support is somewhat inconsistent. 1155 * SDMA is a good example. Sienna cichlid has 4 total 1156 * SDMA instances, each enumerated separately (HWIDs 1157 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1158 * but they are enumerated as multiple instances of the 1159 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1160 * example. On most chips there are multiple instances 1161 * with the same HWID. 1162 */ 1163 adev->ip_versions[hw_ip][ip->number_instance] = 1164 IP_VERSION(ip->major, ip->minor, ip->revision); 1165 } 1166 } 1167 1168 next_ip: 1169 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1170 } 1171 } 1172 1173 amdgpu_discovery_sysfs_init(adev); 1174 1175 return 0; 1176 } 1177 1178 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1179 int *major, int *minor, int *revision) 1180 { 1181 struct binary_header *bhdr; 1182 struct ip_discovery_header *ihdr; 1183 struct die_header *dhdr; 1184 struct ip *ip; 1185 uint16_t die_offset; 1186 uint16_t ip_offset; 1187 uint16_t num_dies; 1188 uint16_t num_ips; 1189 int i, j; 1190 1191 if (!adev->mman.discovery_bin) { 1192 DRM_ERROR("ip discovery uninitialized\n"); 1193 return -EINVAL; 1194 } 1195 1196 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1197 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1198 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1199 num_dies = le16_to_cpu(ihdr->num_dies); 1200 1201 for (i = 0; i < num_dies; i++) { 1202 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1203 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1204 num_ips = le16_to_cpu(dhdr->num_ips); 1205 ip_offset = die_offset + sizeof(*dhdr); 1206 1207 for (j = 0; j < num_ips; j++) { 1208 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1209 1210 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1211 if (major) 1212 *major = ip->major; 1213 if (minor) 1214 *minor = ip->minor; 1215 if (revision) 1216 *revision = ip->revision; 1217 return 0; 1218 } 1219 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1220 } 1221 } 1222 1223 return -EINVAL; 1224 } 1225 1226 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1227 { 1228 int vcn_harvest_count = 0; 1229 int umc_harvest_count = 0; 1230 1231 /* 1232 * Harvest table does not fit Navi1x and legacy GPUs, 1233 * so read harvest bit per IP data structure to set 1234 * harvest configuration. 1235 */ 1236 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1237 if ((adev->pdev->device == 0x731E && 1238 (adev->pdev->revision == 0xC6 || 1239 adev->pdev->revision == 0xC7)) || 1240 (adev->pdev->device == 0x7340 && 1241 adev->pdev->revision == 0xC9) || 1242 (adev->pdev->device == 0x7360 && 1243 adev->pdev->revision == 0xC7)) 1244 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1245 &vcn_harvest_count); 1246 } else { 1247 amdgpu_discovery_read_from_harvest_table(adev, 1248 &vcn_harvest_count, 1249 &umc_harvest_count); 1250 } 1251 1252 amdgpu_discovery_harvest_config_quirk(adev); 1253 1254 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1255 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1256 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1257 } 1258 1259 if (umc_harvest_count < adev->gmc.num_umc) { 1260 adev->gmc.num_umc -= umc_harvest_count; 1261 } 1262 } 1263 1264 union gc_info { 1265 struct gc_info_v1_0 v1; 1266 struct gc_info_v1_1 v1_1; 1267 struct gc_info_v1_2 v1_2; 1268 struct gc_info_v2_0 v2; 1269 }; 1270 1271 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1272 { 1273 struct binary_header *bhdr; 1274 union gc_info *gc_info; 1275 u16 offset; 1276 1277 if (!adev->mman.discovery_bin) { 1278 DRM_ERROR("ip discovery uninitialized\n"); 1279 return -EINVAL; 1280 } 1281 1282 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1283 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1284 1285 if (!offset) 1286 return 0; 1287 1288 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1289 1290 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1291 case 1: 1292 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1293 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1294 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1295 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1296 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1297 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1298 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1299 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1300 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1301 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1302 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1303 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1304 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1305 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1306 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1307 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1308 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1309 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1310 if (gc_info->v1.header.version_minor >= 1) { 1311 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1312 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1313 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1314 } 1315 if (gc_info->v1.header.version_minor >= 2) { 1316 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1317 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1318 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1319 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1320 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1321 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1322 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1323 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1324 } 1325 break; 1326 case 2: 1327 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1328 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1329 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1330 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1331 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1332 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1333 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1334 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1335 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1336 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1337 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1338 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1339 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1340 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1341 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1342 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1343 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1344 break; 1345 default: 1346 dev_err(adev->dev, 1347 "Unhandled GC info table %d.%d\n", 1348 le16_to_cpu(gc_info->v1.header.version_major), 1349 le16_to_cpu(gc_info->v1.header.version_minor)); 1350 return -EINVAL; 1351 } 1352 return 0; 1353 } 1354 1355 union mall_info { 1356 struct mall_info_v1_0 v1; 1357 }; 1358 1359 int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1360 { 1361 struct binary_header *bhdr; 1362 union mall_info *mall_info; 1363 u32 u, mall_size_per_umc, m_s_present, half_use; 1364 u64 mall_size; 1365 u16 offset; 1366 1367 if (!adev->mman.discovery_bin) { 1368 DRM_ERROR("ip discovery uninitialized\n"); 1369 return -EINVAL; 1370 } 1371 1372 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1373 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1374 1375 if (!offset) 1376 return 0; 1377 1378 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1379 1380 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1381 case 1: 1382 mall_size = 0; 1383 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1384 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1385 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1386 for (u = 0; u < adev->gmc.num_umc; u++) { 1387 if (m_s_present & (1 << u)) 1388 mall_size += mall_size_per_umc * 2; 1389 else if (half_use & (1 << u)) 1390 mall_size += mall_size_per_umc / 2; 1391 else 1392 mall_size += mall_size_per_umc; 1393 } 1394 adev->gmc.mall_size = mall_size; 1395 break; 1396 default: 1397 dev_err(adev->dev, 1398 "Unhandled MALL info table %d.%d\n", 1399 le16_to_cpu(mall_info->v1.header.version_major), 1400 le16_to_cpu(mall_info->v1.header.version_minor)); 1401 return -EINVAL; 1402 } 1403 return 0; 1404 } 1405 1406 union vcn_info { 1407 struct vcn_info_v1_0 v1; 1408 }; 1409 1410 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1411 { 1412 struct binary_header *bhdr; 1413 union vcn_info *vcn_info; 1414 u16 offset; 1415 int v; 1416 1417 if (!adev->mman.discovery_bin) { 1418 DRM_ERROR("ip discovery uninitialized\n"); 1419 return -EINVAL; 1420 } 1421 1422 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1423 dev_err(adev->dev, "invalid vcn instances\n"); 1424 return -EINVAL; 1425 } 1426 1427 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1428 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1429 1430 if (!offset) 1431 return 0; 1432 1433 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1434 1435 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1436 case 1: 1437 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1438 adev->vcn.vcn_codec_disable_mask[v] = 1439 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1440 } 1441 break; 1442 default: 1443 dev_err(adev->dev, 1444 "Unhandled VCN info table %d.%d\n", 1445 le16_to_cpu(vcn_info->v1.header.version_major), 1446 le16_to_cpu(vcn_info->v1.header.version_minor)); 1447 return -EINVAL; 1448 } 1449 return 0; 1450 } 1451 1452 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1453 { 1454 /* what IP to use for this? */ 1455 switch (adev->ip_versions[GC_HWIP][0]) { 1456 case IP_VERSION(9, 0, 1): 1457 case IP_VERSION(9, 1, 0): 1458 case IP_VERSION(9, 2, 1): 1459 case IP_VERSION(9, 2, 2): 1460 case IP_VERSION(9, 3, 0): 1461 case IP_VERSION(9, 4, 0): 1462 case IP_VERSION(9, 4, 1): 1463 case IP_VERSION(9, 4, 2): 1464 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1465 break; 1466 case IP_VERSION(10, 1, 10): 1467 case IP_VERSION(10, 1, 1): 1468 case IP_VERSION(10, 1, 2): 1469 case IP_VERSION(10, 1, 3): 1470 case IP_VERSION(10, 1, 4): 1471 case IP_VERSION(10, 3, 0): 1472 case IP_VERSION(10, 3, 1): 1473 case IP_VERSION(10, 3, 2): 1474 case IP_VERSION(10, 3, 3): 1475 case IP_VERSION(10, 3, 4): 1476 case IP_VERSION(10, 3, 5): 1477 case IP_VERSION(10, 3, 6): 1478 case IP_VERSION(10, 3, 7): 1479 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1480 break; 1481 case IP_VERSION(11, 0, 0): 1482 case IP_VERSION(11, 0, 2): 1483 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1484 break; 1485 default: 1486 dev_err(adev->dev, 1487 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1488 adev->ip_versions[GC_HWIP][0]); 1489 return -EINVAL; 1490 } 1491 return 0; 1492 } 1493 1494 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1495 { 1496 /* use GC or MMHUB IP version */ 1497 switch (adev->ip_versions[GC_HWIP][0]) { 1498 case IP_VERSION(9, 0, 1): 1499 case IP_VERSION(9, 1, 0): 1500 case IP_VERSION(9, 2, 1): 1501 case IP_VERSION(9, 2, 2): 1502 case IP_VERSION(9, 3, 0): 1503 case IP_VERSION(9, 4, 0): 1504 case IP_VERSION(9, 4, 1): 1505 case IP_VERSION(9, 4, 2): 1506 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1507 break; 1508 case IP_VERSION(10, 1, 10): 1509 case IP_VERSION(10, 1, 1): 1510 case IP_VERSION(10, 1, 2): 1511 case IP_VERSION(10, 1, 3): 1512 case IP_VERSION(10, 1, 4): 1513 case IP_VERSION(10, 3, 0): 1514 case IP_VERSION(10, 3, 1): 1515 case IP_VERSION(10, 3, 2): 1516 case IP_VERSION(10, 3, 3): 1517 case IP_VERSION(10, 3, 4): 1518 case IP_VERSION(10, 3, 5): 1519 case IP_VERSION(10, 3, 6): 1520 case IP_VERSION(10, 3, 7): 1521 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1522 break; 1523 case IP_VERSION(11, 0, 0): 1524 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1525 break; 1526 default: 1527 dev_err(adev->dev, 1528 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1529 adev->ip_versions[GC_HWIP][0]); 1530 return -EINVAL; 1531 } 1532 return 0; 1533 } 1534 1535 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1536 { 1537 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1538 case IP_VERSION(4, 0, 0): 1539 case IP_VERSION(4, 0, 1): 1540 case IP_VERSION(4, 1, 0): 1541 case IP_VERSION(4, 1, 1): 1542 case IP_VERSION(4, 3, 0): 1543 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1544 break; 1545 case IP_VERSION(4, 2, 0): 1546 case IP_VERSION(4, 2, 1): 1547 case IP_VERSION(4, 4, 0): 1548 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1549 break; 1550 case IP_VERSION(5, 0, 0): 1551 case IP_VERSION(5, 0, 1): 1552 case IP_VERSION(5, 0, 2): 1553 case IP_VERSION(5, 0, 3): 1554 case IP_VERSION(5, 2, 0): 1555 case IP_VERSION(5, 2, 1): 1556 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1557 break; 1558 case IP_VERSION(6, 0, 0): 1559 case IP_VERSION(6, 0, 2): 1560 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1561 break; 1562 default: 1563 dev_err(adev->dev, 1564 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1565 adev->ip_versions[OSSSYS_HWIP][0]); 1566 return -EINVAL; 1567 } 1568 return 0; 1569 } 1570 1571 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1572 { 1573 switch (adev->ip_versions[MP0_HWIP][0]) { 1574 case IP_VERSION(9, 0, 0): 1575 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1576 break; 1577 case IP_VERSION(10, 0, 0): 1578 case IP_VERSION(10, 0, 1): 1579 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1580 break; 1581 case IP_VERSION(11, 0, 0): 1582 case IP_VERSION(11, 0, 2): 1583 case IP_VERSION(11, 0, 4): 1584 case IP_VERSION(11, 0, 5): 1585 case IP_VERSION(11, 0, 9): 1586 case IP_VERSION(11, 0, 7): 1587 case IP_VERSION(11, 0, 11): 1588 case IP_VERSION(11, 0, 12): 1589 case IP_VERSION(11, 0, 13): 1590 case IP_VERSION(11, 5, 0): 1591 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1592 break; 1593 case IP_VERSION(11, 0, 8): 1594 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1595 break; 1596 case IP_VERSION(11, 0, 3): 1597 case IP_VERSION(12, 0, 1): 1598 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1599 break; 1600 case IP_VERSION(13, 0, 0): 1601 case IP_VERSION(13, 0, 1): 1602 case IP_VERSION(13, 0, 2): 1603 case IP_VERSION(13, 0, 3): 1604 case IP_VERSION(13, 0, 5): 1605 case IP_VERSION(13, 0, 8): 1606 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1607 break; 1608 default: 1609 dev_err(adev->dev, 1610 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1611 adev->ip_versions[MP0_HWIP][0]); 1612 return -EINVAL; 1613 } 1614 return 0; 1615 } 1616 1617 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1618 { 1619 switch (adev->ip_versions[MP1_HWIP][0]) { 1620 case IP_VERSION(9, 0, 0): 1621 case IP_VERSION(10, 0, 0): 1622 case IP_VERSION(10, 0, 1): 1623 case IP_VERSION(11, 0, 2): 1624 if (adev->asic_type == CHIP_ARCTURUS) 1625 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1626 else 1627 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1628 break; 1629 case IP_VERSION(11, 0, 0): 1630 case IP_VERSION(11, 0, 5): 1631 case IP_VERSION(11, 0, 9): 1632 case IP_VERSION(11, 0, 7): 1633 case IP_VERSION(11, 0, 8): 1634 case IP_VERSION(11, 0, 11): 1635 case IP_VERSION(11, 0, 12): 1636 case IP_VERSION(11, 0, 13): 1637 case IP_VERSION(11, 5, 0): 1638 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1639 break; 1640 case IP_VERSION(12, 0, 0): 1641 case IP_VERSION(12, 0, 1): 1642 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1643 break; 1644 case IP_VERSION(13, 0, 0): 1645 case IP_VERSION(13, 0, 1): 1646 case IP_VERSION(13, 0, 2): 1647 case IP_VERSION(13, 0, 3): 1648 case IP_VERSION(13, 0, 5): 1649 case IP_VERSION(13, 0, 7): 1650 case IP_VERSION(13, 0, 8): 1651 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1652 break; 1653 default: 1654 dev_err(adev->dev, 1655 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1656 adev->ip_versions[MP1_HWIP][0]); 1657 return -EINVAL; 1658 } 1659 return 0; 1660 } 1661 1662 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1663 { 1664 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 1665 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1666 return 0; 1667 } 1668 1669 if (!amdgpu_device_has_dc_support(adev)) 1670 return 0; 1671 1672 #if defined(CONFIG_DRM_AMD_DC) 1673 if (adev->ip_versions[DCE_HWIP][0]) { 1674 switch (adev->ip_versions[DCE_HWIP][0]) { 1675 case IP_VERSION(1, 0, 0): 1676 case IP_VERSION(1, 0, 1): 1677 case IP_VERSION(2, 0, 2): 1678 case IP_VERSION(2, 0, 0): 1679 case IP_VERSION(2, 0, 3): 1680 case IP_VERSION(2, 1, 0): 1681 case IP_VERSION(3, 0, 0): 1682 case IP_VERSION(3, 0, 2): 1683 case IP_VERSION(3, 0, 3): 1684 case IP_VERSION(3, 0, 1): 1685 case IP_VERSION(3, 1, 2): 1686 case IP_VERSION(3, 1, 3): 1687 case IP_VERSION(3, 1, 5): 1688 case IP_VERSION(3, 1, 6): 1689 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1690 break; 1691 default: 1692 dev_err(adev->dev, 1693 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1694 adev->ip_versions[DCE_HWIP][0]); 1695 return -EINVAL; 1696 } 1697 } else if (adev->ip_versions[DCI_HWIP][0]) { 1698 switch (adev->ip_versions[DCI_HWIP][0]) { 1699 case IP_VERSION(12, 0, 0): 1700 case IP_VERSION(12, 0, 1): 1701 case IP_VERSION(12, 1, 0): 1702 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1703 break; 1704 default: 1705 dev_err(adev->dev, 1706 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1707 adev->ip_versions[DCI_HWIP][0]); 1708 return -EINVAL; 1709 } 1710 } 1711 #endif 1712 return 0; 1713 } 1714 1715 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1716 { 1717 switch (adev->ip_versions[GC_HWIP][0]) { 1718 case IP_VERSION(9, 0, 1): 1719 case IP_VERSION(9, 1, 0): 1720 case IP_VERSION(9, 2, 1): 1721 case IP_VERSION(9, 2, 2): 1722 case IP_VERSION(9, 3, 0): 1723 case IP_VERSION(9, 4, 0): 1724 case IP_VERSION(9, 4, 1): 1725 case IP_VERSION(9, 4, 2): 1726 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1727 break; 1728 case IP_VERSION(10, 1, 10): 1729 case IP_VERSION(10, 1, 2): 1730 case IP_VERSION(10, 1, 1): 1731 case IP_VERSION(10, 1, 3): 1732 case IP_VERSION(10, 1, 4): 1733 case IP_VERSION(10, 3, 0): 1734 case IP_VERSION(10, 3, 2): 1735 case IP_VERSION(10, 3, 1): 1736 case IP_VERSION(10, 3, 4): 1737 case IP_VERSION(10, 3, 5): 1738 case IP_VERSION(10, 3, 6): 1739 case IP_VERSION(10, 3, 3): 1740 case IP_VERSION(10, 3, 7): 1741 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1742 break; 1743 case IP_VERSION(11, 0, 0): 1744 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1745 break; 1746 default: 1747 dev_err(adev->dev, 1748 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1749 adev->ip_versions[GC_HWIP][0]); 1750 return -EINVAL; 1751 } 1752 return 0; 1753 } 1754 1755 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1756 { 1757 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1758 case IP_VERSION(4, 0, 0): 1759 case IP_VERSION(4, 0, 1): 1760 case IP_VERSION(4, 1, 0): 1761 case IP_VERSION(4, 1, 1): 1762 case IP_VERSION(4, 1, 2): 1763 case IP_VERSION(4, 2, 0): 1764 case IP_VERSION(4, 2, 2): 1765 case IP_VERSION(4, 4, 0): 1766 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1767 break; 1768 case IP_VERSION(5, 0, 0): 1769 case IP_VERSION(5, 0, 1): 1770 case IP_VERSION(5, 0, 2): 1771 case IP_VERSION(5, 0, 5): 1772 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1773 break; 1774 case IP_VERSION(5, 2, 0): 1775 case IP_VERSION(5, 2, 2): 1776 case IP_VERSION(5, 2, 4): 1777 case IP_VERSION(5, 2, 5): 1778 case IP_VERSION(5, 2, 6): 1779 case IP_VERSION(5, 2, 3): 1780 case IP_VERSION(5, 2, 1): 1781 case IP_VERSION(5, 2, 7): 1782 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1783 break; 1784 case IP_VERSION(6, 0, 0): 1785 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1786 break; 1787 default: 1788 dev_err(adev->dev, 1789 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1790 adev->ip_versions[SDMA0_HWIP][0]); 1791 return -EINVAL; 1792 } 1793 return 0; 1794 } 1795 1796 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1797 { 1798 if (adev->ip_versions[VCE_HWIP][0]) { 1799 switch (adev->ip_versions[UVD_HWIP][0]) { 1800 case IP_VERSION(7, 0, 0): 1801 case IP_VERSION(7, 2, 0): 1802 /* UVD is not supported on vega20 SR-IOV */ 1803 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1804 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1805 break; 1806 default: 1807 dev_err(adev->dev, 1808 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1809 adev->ip_versions[UVD_HWIP][0]); 1810 return -EINVAL; 1811 } 1812 switch (adev->ip_versions[VCE_HWIP][0]) { 1813 case IP_VERSION(4, 0, 0): 1814 case IP_VERSION(4, 1, 0): 1815 /* VCE is not supported on vega20 SR-IOV */ 1816 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1817 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1818 break; 1819 default: 1820 dev_err(adev->dev, 1821 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1822 adev->ip_versions[VCE_HWIP][0]); 1823 return -EINVAL; 1824 } 1825 } else { 1826 switch (adev->ip_versions[UVD_HWIP][0]) { 1827 case IP_VERSION(1, 0, 0): 1828 case IP_VERSION(1, 0, 1): 1829 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1830 break; 1831 case IP_VERSION(2, 0, 0): 1832 case IP_VERSION(2, 0, 2): 1833 case IP_VERSION(2, 2, 0): 1834 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1835 if (!amdgpu_sriov_vf(adev)) 1836 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1837 break; 1838 case IP_VERSION(2, 0, 3): 1839 break; 1840 case IP_VERSION(2, 5, 0): 1841 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1842 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1843 break; 1844 case IP_VERSION(2, 6, 0): 1845 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1846 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1847 break; 1848 case IP_VERSION(3, 0, 0): 1849 case IP_VERSION(3, 0, 16): 1850 case IP_VERSION(3, 1, 1): 1851 case IP_VERSION(3, 1, 2): 1852 case IP_VERSION(3, 0, 2): 1853 case IP_VERSION(3, 0, 192): 1854 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1855 if (!amdgpu_sriov_vf(adev)) 1856 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1857 break; 1858 case IP_VERSION(3, 0, 33): 1859 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1860 break; 1861 case IP_VERSION(4, 0, 0): 1862 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 1863 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 1864 break; 1865 default: 1866 dev_err(adev->dev, 1867 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1868 adev->ip_versions[UVD_HWIP][0]); 1869 return -EINVAL; 1870 } 1871 } 1872 return 0; 1873 } 1874 1875 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1876 { 1877 switch (adev->ip_versions[GC_HWIP][0]) { 1878 case IP_VERSION(10, 1, 10): 1879 case IP_VERSION(10, 1, 1): 1880 case IP_VERSION(10, 1, 2): 1881 case IP_VERSION(10, 1, 3): 1882 case IP_VERSION(10, 1, 4): 1883 case IP_VERSION(10, 3, 0): 1884 case IP_VERSION(10, 3, 1): 1885 case IP_VERSION(10, 3, 2): 1886 case IP_VERSION(10, 3, 3): 1887 case IP_VERSION(10, 3, 4): 1888 case IP_VERSION(10, 3, 5): 1889 case IP_VERSION(10, 3, 6): 1890 if (amdgpu_mes) { 1891 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1892 adev->enable_mes = true; 1893 if (amdgpu_mes_kiq) 1894 adev->enable_mes_kiq = true; 1895 } 1896 break; 1897 case IP_VERSION(11, 0, 0): 1898 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 1899 adev->enable_mes = true; 1900 adev->enable_mes_kiq = true; 1901 break; 1902 default: 1903 break; 1904 } 1905 return 0; 1906 } 1907 1908 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1909 { 1910 int r; 1911 1912 switch (adev->asic_type) { 1913 case CHIP_VEGA10: 1914 vega10_reg_base_init(adev); 1915 adev->sdma.num_instances = 2; 1916 adev->gmc.num_umc = 4; 1917 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1918 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1919 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1920 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1921 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1922 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1923 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1924 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1925 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1926 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1927 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1928 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1929 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1930 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1931 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1932 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1933 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1934 break; 1935 case CHIP_VEGA12: 1936 vega10_reg_base_init(adev); 1937 adev->sdma.num_instances = 2; 1938 adev->gmc.num_umc = 4; 1939 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1940 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1941 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1942 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1943 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1944 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1945 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1946 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1947 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1948 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1949 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1950 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1951 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1952 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1953 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1954 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1955 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1956 break; 1957 case CHIP_RAVEN: 1958 vega10_reg_base_init(adev); 1959 adev->sdma.num_instances = 1; 1960 adev->vcn.num_vcn_inst = 1; 1961 adev->gmc.num_umc = 2; 1962 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1963 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1964 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1965 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1966 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1967 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1968 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1969 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1970 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1971 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1972 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1973 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1974 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1975 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1976 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1977 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1978 } else { 1979 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1980 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1981 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1982 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1983 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1984 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1985 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1986 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1987 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1988 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1989 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1990 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1991 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1992 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1993 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1994 } 1995 break; 1996 case CHIP_VEGA20: 1997 vega20_reg_base_init(adev); 1998 adev->sdma.num_instances = 2; 1999 adev->gmc.num_umc = 8; 2000 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2001 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2002 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2003 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2004 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2005 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2006 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2007 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2008 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2009 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2010 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2011 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2012 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2013 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2014 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2015 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2016 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2017 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2018 break; 2019 case CHIP_ARCTURUS: 2020 arct_reg_base_init(adev); 2021 adev->sdma.num_instances = 8; 2022 adev->vcn.num_vcn_inst = 2; 2023 adev->gmc.num_umc = 8; 2024 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2025 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2026 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2027 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2028 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2029 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2030 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2031 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2032 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2033 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2034 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2035 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2036 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2037 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2038 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2039 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2040 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2041 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2042 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2043 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2044 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2045 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2046 break; 2047 case CHIP_ALDEBARAN: 2048 aldebaran_reg_base_init(adev); 2049 adev->sdma.num_instances = 5; 2050 adev->vcn.num_vcn_inst = 2; 2051 adev->gmc.num_umc = 4; 2052 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2053 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2054 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2055 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2056 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2057 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2058 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2059 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2060 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2061 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2062 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2063 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2064 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2065 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2066 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2067 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2068 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2069 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2070 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2071 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2072 break; 2073 default: 2074 r = amdgpu_discovery_reg_base_init(adev); 2075 if (r) 2076 return -EINVAL; 2077 2078 amdgpu_discovery_harvest_ip(adev); 2079 amdgpu_discovery_get_gfx_info(adev); 2080 amdgpu_discovery_get_mall_info(adev); 2081 amdgpu_discovery_get_vcn_info(adev); 2082 break; 2083 } 2084 2085 switch (adev->ip_versions[GC_HWIP][0]) { 2086 case IP_VERSION(9, 0, 1): 2087 case IP_VERSION(9, 2, 1): 2088 case IP_VERSION(9, 4, 0): 2089 case IP_VERSION(9, 4, 1): 2090 case IP_VERSION(9, 4, 2): 2091 adev->family = AMDGPU_FAMILY_AI; 2092 break; 2093 case IP_VERSION(9, 1, 0): 2094 case IP_VERSION(9, 2, 2): 2095 case IP_VERSION(9, 3, 0): 2096 adev->family = AMDGPU_FAMILY_RV; 2097 break; 2098 case IP_VERSION(10, 1, 10): 2099 case IP_VERSION(10, 1, 1): 2100 case IP_VERSION(10, 1, 2): 2101 case IP_VERSION(10, 1, 3): 2102 case IP_VERSION(10, 1, 4): 2103 case IP_VERSION(10, 3, 0): 2104 case IP_VERSION(10, 3, 2): 2105 case IP_VERSION(10, 3, 4): 2106 case IP_VERSION(10, 3, 5): 2107 adev->family = AMDGPU_FAMILY_NV; 2108 break; 2109 case IP_VERSION(10, 3, 1): 2110 adev->family = AMDGPU_FAMILY_VGH; 2111 break; 2112 case IP_VERSION(10, 3, 3): 2113 adev->family = AMDGPU_FAMILY_YC; 2114 break; 2115 case IP_VERSION(10, 3, 6): 2116 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2117 break; 2118 case IP_VERSION(10, 3, 7): 2119 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2120 break; 2121 case IP_VERSION(11, 0, 0): 2122 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2123 break; 2124 default: 2125 return -EINVAL; 2126 } 2127 2128 switch (adev->ip_versions[GC_HWIP][0]) { 2129 case IP_VERSION(9, 1, 0): 2130 case IP_VERSION(9, 2, 2): 2131 case IP_VERSION(9, 3, 0): 2132 case IP_VERSION(10, 1, 3): 2133 case IP_VERSION(10, 1, 4): 2134 case IP_VERSION(10, 3, 1): 2135 case IP_VERSION(10, 3, 3): 2136 case IP_VERSION(10, 3, 6): 2137 case IP_VERSION(10, 3, 7): 2138 adev->flags |= AMD_IS_APU; 2139 break; 2140 default: 2141 break; 2142 } 2143 2144 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2145 adev->gmc.xgmi.supported = true; 2146 2147 /* set NBIO version */ 2148 switch (adev->ip_versions[NBIO_HWIP][0]) { 2149 case IP_VERSION(6, 1, 0): 2150 case IP_VERSION(6, 2, 0): 2151 adev->nbio.funcs = &nbio_v6_1_funcs; 2152 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2153 break; 2154 case IP_VERSION(7, 0, 0): 2155 case IP_VERSION(7, 0, 1): 2156 case IP_VERSION(2, 5, 0): 2157 adev->nbio.funcs = &nbio_v7_0_funcs; 2158 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2159 break; 2160 case IP_VERSION(7, 4, 0): 2161 case IP_VERSION(7, 4, 1): 2162 adev->nbio.funcs = &nbio_v7_4_funcs; 2163 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2164 break; 2165 case IP_VERSION(7, 4, 4): 2166 adev->nbio.funcs = &nbio_v7_4_funcs; 2167 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 2168 break; 2169 case IP_VERSION(7, 2, 0): 2170 case IP_VERSION(7, 2, 1): 2171 case IP_VERSION(7, 3, 0): 2172 case IP_VERSION(7, 5, 0): 2173 case IP_VERSION(7, 5, 1): 2174 adev->nbio.funcs = &nbio_v7_2_funcs; 2175 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2176 break; 2177 case IP_VERSION(2, 1, 1): 2178 case IP_VERSION(2, 3, 0): 2179 case IP_VERSION(2, 3, 1): 2180 case IP_VERSION(2, 3, 2): 2181 adev->nbio.funcs = &nbio_v2_3_funcs; 2182 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2183 break; 2184 case IP_VERSION(3, 3, 0): 2185 case IP_VERSION(3, 3, 1): 2186 case IP_VERSION(3, 3, 2): 2187 case IP_VERSION(3, 3, 3): 2188 adev->nbio.funcs = &nbio_v2_3_funcs; 2189 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 2190 break; 2191 case IP_VERSION(4, 3, 0): 2192 case IP_VERSION(4, 3, 1): 2193 adev->nbio.funcs = &nbio_v4_3_funcs; 2194 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2195 break; 2196 default: 2197 break; 2198 } 2199 2200 switch (adev->ip_versions[HDP_HWIP][0]) { 2201 case IP_VERSION(4, 0, 0): 2202 case IP_VERSION(4, 0, 1): 2203 case IP_VERSION(4, 1, 0): 2204 case IP_VERSION(4, 1, 1): 2205 case IP_VERSION(4, 1, 2): 2206 case IP_VERSION(4, 2, 0): 2207 case IP_VERSION(4, 2, 1): 2208 case IP_VERSION(4, 4, 0): 2209 adev->hdp.funcs = &hdp_v4_0_funcs; 2210 break; 2211 case IP_VERSION(5, 0, 0): 2212 case IP_VERSION(5, 0, 1): 2213 case IP_VERSION(5, 0, 2): 2214 case IP_VERSION(5, 0, 3): 2215 case IP_VERSION(5, 0, 4): 2216 case IP_VERSION(5, 2, 0): 2217 adev->hdp.funcs = &hdp_v5_0_funcs; 2218 break; 2219 case IP_VERSION(6, 0, 0): 2220 case IP_VERSION(6, 0, 1): 2221 adev->hdp.funcs = &hdp_v6_0_funcs; 2222 break; 2223 default: 2224 break; 2225 } 2226 2227 switch (adev->ip_versions[DF_HWIP][0]) { 2228 case IP_VERSION(3, 6, 0): 2229 case IP_VERSION(3, 6, 1): 2230 case IP_VERSION(3, 6, 2): 2231 adev->df.funcs = &df_v3_6_funcs; 2232 break; 2233 case IP_VERSION(2, 1, 0): 2234 case IP_VERSION(2, 1, 1): 2235 case IP_VERSION(2, 5, 0): 2236 case IP_VERSION(3, 5, 1): 2237 case IP_VERSION(3, 5, 2): 2238 adev->df.funcs = &df_v1_7_funcs; 2239 break; 2240 default: 2241 break; 2242 } 2243 2244 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2245 case IP_VERSION(9, 0, 0): 2246 case IP_VERSION(9, 0, 1): 2247 case IP_VERSION(10, 0, 0): 2248 case IP_VERSION(10, 0, 1): 2249 case IP_VERSION(10, 0, 2): 2250 adev->smuio.funcs = &smuio_v9_0_funcs; 2251 break; 2252 case IP_VERSION(11, 0, 0): 2253 case IP_VERSION(11, 0, 2): 2254 case IP_VERSION(11, 0, 3): 2255 case IP_VERSION(11, 0, 4): 2256 case IP_VERSION(11, 0, 7): 2257 case IP_VERSION(11, 0, 8): 2258 adev->smuio.funcs = &smuio_v11_0_funcs; 2259 break; 2260 case IP_VERSION(11, 0, 6): 2261 case IP_VERSION(11, 0, 10): 2262 case IP_VERSION(11, 0, 11): 2263 case IP_VERSION(11, 5, 0): 2264 case IP_VERSION(13, 0, 1): 2265 case IP_VERSION(13, 0, 9): 2266 case IP_VERSION(13, 0, 10): 2267 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2268 break; 2269 case IP_VERSION(13, 0, 2): 2270 adev->smuio.funcs = &smuio_v13_0_funcs; 2271 break; 2272 case IP_VERSION(13, 0, 6): 2273 case IP_VERSION(13, 0, 8): 2274 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2275 break; 2276 default: 2277 break; 2278 } 2279 2280 r = amdgpu_discovery_set_common_ip_blocks(adev); 2281 if (r) 2282 return r; 2283 2284 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2285 if (r) 2286 return r; 2287 2288 /* For SR-IOV, PSP needs to be initialized before IH */ 2289 if (amdgpu_sriov_vf(adev)) { 2290 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2291 if (r) 2292 return r; 2293 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2294 if (r) 2295 return r; 2296 } else { 2297 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2298 if (r) 2299 return r; 2300 2301 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2302 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2303 if (r) 2304 return r; 2305 } 2306 } 2307 2308 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2309 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2310 if (r) 2311 return r; 2312 } 2313 2314 r = amdgpu_discovery_set_display_ip_blocks(adev); 2315 if (r) 2316 return r; 2317 2318 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2319 if (r) 2320 return r; 2321 2322 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2323 if (r) 2324 return r; 2325 2326 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2327 !amdgpu_sriov_vf(adev)) || 2328 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2329 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2330 if (r) 2331 return r; 2332 } 2333 2334 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2335 if (r) 2336 return r; 2337 2338 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2339 if (r) 2340 return r; 2341 2342 return 0; 2343 } 2344 2345