1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gfxhub_v2_0.h" 51 #include "mmhub_v2_0.h" 52 #include "nbio_v2_3.h" 53 #include "nbio_v7_2.h" 54 #include "hdp_v5_0.h" 55 #include "nv.h" 56 #include "navi10_ih.h" 57 #include "gfx_v10_0.h" 58 #include "sdma_v5_0.h" 59 #include "sdma_v5_2.h" 60 #include "vcn_v2_0.h" 61 #include "jpeg_v2_0.h" 62 #include "vcn_v3_0.h" 63 #include "jpeg_v3_0.h" 64 #include "amdgpu_vkms.h" 65 #include "mes_v10_1.h" 66 #include "smuio_v11_0.h" 67 #include "smuio_v11_0_6.h" 68 #include "smuio_v13_0.h" 69 70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 72 73 #define mmRCC_CONFIG_MEMSIZE 0xde3 74 #define mmMM_INDEX 0x0 75 #define mmMM_INDEX_HI 0x6 76 #define mmMM_DATA 0x1 77 78 static const char *hw_id_names[HW_ID_MAX] = { 79 [MP1_HWID] = "MP1", 80 [MP2_HWID] = "MP2", 81 [THM_HWID] = "THM", 82 [SMUIO_HWID] = "SMUIO", 83 [FUSE_HWID] = "FUSE", 84 [CLKA_HWID] = "CLKA", 85 [PWR_HWID] = "PWR", 86 [GC_HWID] = "GC", 87 [UVD_HWID] = "UVD", 88 [AUDIO_AZ_HWID] = "AUDIO_AZ", 89 [ACP_HWID] = "ACP", 90 [DCI_HWID] = "DCI", 91 [DMU_HWID] = "DMU", 92 [DCO_HWID] = "DCO", 93 [DIO_HWID] = "DIO", 94 [XDMA_HWID] = "XDMA", 95 [DCEAZ_HWID] = "DCEAZ", 96 [DAZ_HWID] = "DAZ", 97 [SDPMUX_HWID] = "SDPMUX", 98 [NTB_HWID] = "NTB", 99 [IOHC_HWID] = "IOHC", 100 [L2IMU_HWID] = "L2IMU", 101 [VCE_HWID] = "VCE", 102 [MMHUB_HWID] = "MMHUB", 103 [ATHUB_HWID] = "ATHUB", 104 [DBGU_NBIO_HWID] = "DBGU_NBIO", 105 [DFX_HWID] = "DFX", 106 [DBGU0_HWID] = "DBGU0", 107 [DBGU1_HWID] = "DBGU1", 108 [OSSSYS_HWID] = "OSSSYS", 109 [HDP_HWID] = "HDP", 110 [SDMA0_HWID] = "SDMA0", 111 [SDMA1_HWID] = "SDMA1", 112 [SDMA2_HWID] = "SDMA2", 113 [SDMA3_HWID] = "SDMA3", 114 [ISP_HWID] = "ISP", 115 [DBGU_IO_HWID] = "DBGU_IO", 116 [DF_HWID] = "DF", 117 [CLKB_HWID] = "CLKB", 118 [FCH_HWID] = "FCH", 119 [DFX_DAP_HWID] = "DFX_DAP", 120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 123 [L1IMU3_HWID] = "L1IMU3", 124 [L1IMU4_HWID] = "L1IMU4", 125 [L1IMU5_HWID] = "L1IMU5", 126 [L1IMU6_HWID] = "L1IMU6", 127 [L1IMU7_HWID] = "L1IMU7", 128 [L1IMU8_HWID] = "L1IMU8", 129 [L1IMU9_HWID] = "L1IMU9", 130 [L1IMU10_HWID] = "L1IMU10", 131 [L1IMU11_HWID] = "L1IMU11", 132 [L1IMU12_HWID] = "L1IMU12", 133 [L1IMU13_HWID] = "L1IMU13", 134 [L1IMU14_HWID] = "L1IMU14", 135 [L1IMU15_HWID] = "L1IMU15", 136 [WAFLC_HWID] = "WAFLC", 137 [FCH_USB_PD_HWID] = "FCH_USB_PD", 138 [PCIE_HWID] = "PCIE", 139 [PCS_HWID] = "PCS", 140 [DDCL_HWID] = "DDCL", 141 [SST_HWID] = "SST", 142 [IOAGR_HWID] = "IOAGR", 143 [NBIF_HWID] = "NBIF", 144 [IOAPIC_HWID] = "IOAPIC", 145 [SYSTEMHUB_HWID] = "SYSTEMHUB", 146 [NTBCCP_HWID] = "NTBCCP", 147 [UMC_HWID] = "UMC", 148 [SATA_HWID] = "SATA", 149 [USB_HWID] = "USB", 150 [CCXSEC_HWID] = "CCXSEC", 151 [XGMI_HWID] = "XGMI", 152 [XGBE_HWID] = "XGBE", 153 [MP0_HWID] = "MP0", 154 }; 155 156 static int hw_id_map[MAX_HWIP] = { 157 [GC_HWIP] = GC_HWID, 158 [HDP_HWIP] = HDP_HWID, 159 [SDMA0_HWIP] = SDMA0_HWID, 160 [SDMA1_HWIP] = SDMA1_HWID, 161 [SDMA2_HWIP] = SDMA2_HWID, 162 [SDMA3_HWIP] = SDMA3_HWID, 163 [MMHUB_HWIP] = MMHUB_HWID, 164 [ATHUB_HWIP] = ATHUB_HWID, 165 [NBIO_HWIP] = NBIF_HWID, 166 [MP0_HWIP] = MP0_HWID, 167 [MP1_HWIP] = MP1_HWID, 168 [UVD_HWIP] = UVD_HWID, 169 [VCE_HWIP] = VCE_HWID, 170 [DF_HWIP] = DF_HWID, 171 [DCE_HWIP] = DMU_HWID, 172 [OSSSYS_HWIP] = OSSSYS_HWID, 173 [SMUIO_HWIP] = SMUIO_HWID, 174 [PWR_HWIP] = PWR_HWID, 175 [NBIF_HWIP] = NBIF_HWID, 176 [THM_HWIP] = THM_HWID, 177 [CLK_HWIP] = CLKA_HWID, 178 [UMC_HWIP] = UMC_HWID, 179 [XGMI_HWIP] = XGMI_HWID, 180 [DCI_HWIP] = DCI_HWID, 181 }; 182 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 184 { 185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 187 188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 189 adev->mman.discovery_tmr_size, false); 190 return 0; 191 } 192 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 194 { 195 const struct firmware *fw; 196 const char *fw_name; 197 int r; 198 199 switch (amdgpu_discovery) { 200 case 2: 201 fw_name = FIRMWARE_IP_DISCOVERY; 202 break; 203 default: 204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 205 return -EINVAL; 206 } 207 208 r = request_firmware(&fw, fw_name, adev->dev); 209 if (r) { 210 dev_err(adev->dev, "can't load firmware \"%s\"\n", 211 fw_name); 212 return r; 213 } 214 215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 216 release_firmware(fw); 217 218 return 0; 219 } 220 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 222 { 223 uint16_t checksum = 0; 224 int i; 225 226 for (i = 0; i < size; i++) 227 checksum += data[i]; 228 229 return checksum; 230 } 231 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 233 uint16_t expected) 234 { 235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 236 } 237 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 239 { 240 struct binary_header *bhdr; 241 bhdr = (struct binary_header *)binary; 242 243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 244 } 245 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 247 { 248 /* 249 * So far, apply this quirk only on those Navy Flounder boards which 250 * have a bad harvest table of VCN config. 251 */ 252 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 253 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 254 switch (adev->pdev->revision) { 255 case 0xC1: 256 case 0xC2: 257 case 0xC3: 258 case 0xC5: 259 case 0xC7: 260 case 0xCF: 261 case 0xDF: 262 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 263 break; 264 default: 265 break; 266 } 267 } 268 } 269 270 static int amdgpu_discovery_init(struct amdgpu_device *adev) 271 { 272 struct table_info *info; 273 struct binary_header *bhdr; 274 struct ip_discovery_header *ihdr; 275 struct gpu_info_header *ghdr; 276 uint16_t offset; 277 uint16_t size; 278 uint16_t checksum; 279 int r; 280 281 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 282 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 283 if (!adev->mman.discovery_bin) 284 return -ENOMEM; 285 286 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 287 if (r) { 288 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 289 r = -EINVAL; 290 goto out; 291 } 292 293 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 294 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 295 /* retry read ip discovery binary from file */ 296 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 297 if (r) { 298 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 299 r = -EINVAL; 300 goto out; 301 } 302 /* check the ip discovery binary signature */ 303 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 304 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 305 r = -EINVAL; 306 goto out; 307 } 308 } 309 310 bhdr = (struct binary_header *)adev->mman.discovery_bin; 311 312 offset = offsetof(struct binary_header, binary_checksum) + 313 sizeof(bhdr->binary_checksum); 314 size = le16_to_cpu(bhdr->binary_size) - offset; 315 checksum = le16_to_cpu(bhdr->binary_checksum); 316 317 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 318 size, checksum)) { 319 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 320 r = -EINVAL; 321 goto out; 322 } 323 324 info = &bhdr->table_list[IP_DISCOVERY]; 325 offset = le16_to_cpu(info->offset); 326 checksum = le16_to_cpu(info->checksum); 327 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 328 329 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 330 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 331 r = -EINVAL; 332 goto out; 333 } 334 335 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 336 le16_to_cpu(ihdr->size), checksum)) { 337 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 338 r = -EINVAL; 339 goto out; 340 } 341 342 info = &bhdr->table_list[GC]; 343 offset = le16_to_cpu(info->offset); 344 checksum = le16_to_cpu(info->checksum); 345 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 346 347 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 348 le32_to_cpu(ghdr->size), checksum)) { 349 dev_err(adev->dev, "invalid gc data table checksum\n"); 350 r = -EINVAL; 351 goto out; 352 } 353 354 return 0; 355 356 out: 357 kfree(adev->mman.discovery_bin); 358 adev->mman.discovery_bin = NULL; 359 360 return r; 361 } 362 363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 364 365 void amdgpu_discovery_fini(struct amdgpu_device *adev) 366 { 367 amdgpu_discovery_sysfs_fini(adev); 368 kfree(adev->mman.discovery_bin); 369 adev->mman.discovery_bin = NULL; 370 } 371 372 static int amdgpu_discovery_validate_ip(const struct ip *ip) 373 { 374 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 375 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 376 ip->number_instance); 377 return -EINVAL; 378 } 379 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 380 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 381 le16_to_cpu(ip->hw_id)); 382 return -EINVAL; 383 } 384 385 return 0; 386 } 387 388 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 389 uint32_t *vcn_harvest_count) 390 { 391 struct binary_header *bhdr; 392 struct ip_discovery_header *ihdr; 393 struct die_header *dhdr; 394 struct ip *ip; 395 uint16_t die_offset, ip_offset, num_dies, num_ips; 396 int i, j; 397 398 bhdr = (struct binary_header *)adev->mman.discovery_bin; 399 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 400 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 401 num_dies = le16_to_cpu(ihdr->num_dies); 402 403 /* scan harvest bit of all IP data structures */ 404 for (i = 0; i < num_dies; i++) { 405 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 406 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 407 num_ips = le16_to_cpu(dhdr->num_ips); 408 ip_offset = die_offset + sizeof(*dhdr); 409 410 for (j = 0; j < num_ips; j++) { 411 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 412 413 if (amdgpu_discovery_validate_ip(ip)) 414 goto next_ip; 415 416 if (le16_to_cpu(ip->harvest) == 1) { 417 switch (le16_to_cpu(ip->hw_id)) { 418 case VCN_HWID: 419 (*vcn_harvest_count)++; 420 if (ip->number_instance == 0) 421 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 422 else 423 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 424 break; 425 case DMU_HWID: 426 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 427 break; 428 default: 429 break; 430 } 431 } 432 next_ip: 433 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 434 } 435 } 436 } 437 438 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 439 uint32_t *vcn_harvest_count) 440 { 441 struct binary_header *bhdr; 442 struct harvest_table *harvest_info; 443 int i; 444 445 bhdr = (struct binary_header *)adev->mman.discovery_bin; 446 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + 447 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset)); 448 for (i = 0; i < 32; i++) { 449 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 450 break; 451 452 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 453 case VCN_HWID: 454 (*vcn_harvest_count)++; 455 if (harvest_info->list[i].number_instance == 0) 456 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 457 else 458 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 459 break; 460 case DMU_HWID: 461 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 462 break; 463 default: 464 break; 465 } 466 } 467 } 468 469 /* ================================================== */ 470 471 struct ip_hw_instance { 472 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 473 474 int hw_id; 475 u8 num_instance; 476 u8 major, minor, revision; 477 u8 harvest; 478 479 int num_base_addresses; 480 u32 base_addr[]; 481 }; 482 483 struct ip_hw_id { 484 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 485 int hw_id; 486 }; 487 488 struct ip_die_entry { 489 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 490 u16 num_ips; 491 }; 492 493 /* -------------------------------------------------- */ 494 495 struct ip_hw_instance_attr { 496 struct attribute attr; 497 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 498 }; 499 500 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 501 { 502 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 503 } 504 505 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 506 { 507 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 508 } 509 510 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 511 { 512 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 513 } 514 515 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 516 { 517 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 518 } 519 520 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 521 { 522 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 523 } 524 525 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 526 { 527 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 528 } 529 530 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 531 { 532 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 533 } 534 535 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 536 { 537 ssize_t res, at; 538 int ii; 539 540 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 541 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 542 */ 543 if (at + 12 > PAGE_SIZE) 544 break; 545 res = sysfs_emit_at(buf, at, "0x%08X\n", 546 ip_hw_instance->base_addr[ii]); 547 if (res <= 0) 548 break; 549 at += res; 550 } 551 552 return res < 0 ? res : at; 553 } 554 555 static struct ip_hw_instance_attr ip_hw_attr[] = { 556 __ATTR_RO(hw_id), 557 __ATTR_RO(num_instance), 558 __ATTR_RO(major), 559 __ATTR_RO(minor), 560 __ATTR_RO(revision), 561 __ATTR_RO(harvest), 562 __ATTR_RO(num_base_addresses), 563 __ATTR_RO(base_addr), 564 }; 565 566 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 567 ATTRIBUTE_GROUPS(ip_hw_instance); 568 569 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 570 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 571 572 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 573 struct attribute *attr, 574 char *buf) 575 { 576 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 577 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 578 579 if (!ip_hw_attr->show) 580 return -EIO; 581 582 return ip_hw_attr->show(ip_hw_instance, buf); 583 } 584 585 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 586 .show = ip_hw_instance_attr_show, 587 }; 588 589 static void ip_hw_instance_release(struct kobject *kobj) 590 { 591 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 592 593 kfree(ip_hw_instance); 594 } 595 596 static struct kobj_type ip_hw_instance_ktype = { 597 .release = ip_hw_instance_release, 598 .sysfs_ops = &ip_hw_instance_sysfs_ops, 599 .default_groups = ip_hw_instance_groups, 600 }; 601 602 /* -------------------------------------------------- */ 603 604 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 605 606 static void ip_hw_id_release(struct kobject *kobj) 607 { 608 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 609 610 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 611 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 612 kfree(ip_hw_id); 613 } 614 615 static struct kobj_type ip_hw_id_ktype = { 616 .release = ip_hw_id_release, 617 .sysfs_ops = &kobj_sysfs_ops, 618 }; 619 620 /* -------------------------------------------------- */ 621 622 static void die_kobj_release(struct kobject *kobj); 623 static void ip_disc_release(struct kobject *kobj); 624 625 struct ip_die_entry_attribute { 626 struct attribute attr; 627 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 628 }; 629 630 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 631 632 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 633 { 634 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 635 } 636 637 /* If there are more ip_die_entry attrs, other than the number of IPs, 638 * we can make this intro an array of attrs, and then initialize 639 * ip_die_entry_attrs in a loop. 640 */ 641 static struct ip_die_entry_attribute num_ips_attr = 642 __ATTR_RO(num_ips); 643 644 static struct attribute *ip_die_entry_attrs[] = { 645 &num_ips_attr.attr, 646 NULL, 647 }; 648 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 649 650 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 651 652 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 653 struct attribute *attr, 654 char *buf) 655 { 656 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 657 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 658 659 if (!ip_die_entry_attr->show) 660 return -EIO; 661 662 return ip_die_entry_attr->show(ip_die_entry, buf); 663 } 664 665 static void ip_die_entry_release(struct kobject *kobj) 666 { 667 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 668 669 if (!list_empty(&ip_die_entry->ip_kset.list)) 670 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 671 kfree(ip_die_entry); 672 } 673 674 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 675 .show = ip_die_entry_attr_show, 676 }; 677 678 static struct kobj_type ip_die_entry_ktype = { 679 .release = ip_die_entry_release, 680 .sysfs_ops = &ip_die_entry_sysfs_ops, 681 .default_groups = ip_die_entry_groups, 682 }; 683 684 static struct kobj_type die_kobj_ktype = { 685 .release = die_kobj_release, 686 .sysfs_ops = &kobj_sysfs_ops, 687 }; 688 689 static struct kobj_type ip_discovery_ktype = { 690 .release = ip_disc_release, 691 .sysfs_ops = &kobj_sysfs_ops, 692 }; 693 694 struct ip_discovery_top { 695 struct kobject kobj; /* ip_discovery/ */ 696 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 697 struct amdgpu_device *adev; 698 }; 699 700 static void die_kobj_release(struct kobject *kobj) 701 { 702 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 703 struct ip_discovery_top, 704 die_kset); 705 if (!list_empty(&ip_top->die_kset.list)) 706 DRM_ERROR("ip_top->die_kset is not empty"); 707 } 708 709 static void ip_disc_release(struct kobject *kobj) 710 { 711 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 712 kobj); 713 struct amdgpu_device *adev = ip_top->adev; 714 715 adev->ip_top = NULL; 716 kfree(ip_top); 717 } 718 719 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 720 struct ip_die_entry *ip_die_entry, 721 const size_t _ip_offset, const int num_ips) 722 { 723 int ii, jj, kk, res; 724 725 DRM_DEBUG("num_ips:%d", num_ips); 726 727 /* Find all IPs of a given HW ID, and add their instance to 728 * #die/#hw_id/#instance/<attributes> 729 */ 730 for (ii = 0; ii < HW_ID_MAX; ii++) { 731 struct ip_hw_id *ip_hw_id = NULL; 732 size_t ip_offset = _ip_offset; 733 734 for (jj = 0; jj < num_ips; jj++) { 735 struct ip *ip; 736 struct ip_hw_instance *ip_hw_instance; 737 738 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 739 if (amdgpu_discovery_validate_ip(ip) || 740 le16_to_cpu(ip->hw_id) != ii) 741 goto next_ip; 742 743 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 744 745 /* We have a hw_id match; register the hw 746 * block if not yet registered. 747 */ 748 if (!ip_hw_id) { 749 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 750 if (!ip_hw_id) 751 return -ENOMEM; 752 ip_hw_id->hw_id = ii; 753 754 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 755 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 756 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 757 res = kset_register(&ip_hw_id->hw_id_kset); 758 if (res) { 759 DRM_ERROR("Couldn't register ip_hw_id kset"); 760 kfree(ip_hw_id); 761 return res; 762 } 763 if (hw_id_names[ii]) { 764 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 765 &ip_hw_id->hw_id_kset.kobj, 766 hw_id_names[ii]); 767 if (res) { 768 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 769 hw_id_names[ii], 770 kobject_name(&ip_die_entry->ip_kset.kobj)); 771 } 772 } 773 } 774 775 /* Now register its instance. 776 */ 777 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 778 base_addr, 779 ip->num_base_address), 780 GFP_KERNEL); 781 if (!ip_hw_instance) { 782 DRM_ERROR("no memory for ip_hw_instance"); 783 return -ENOMEM; 784 } 785 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 786 ip_hw_instance->num_instance = ip->number_instance; 787 ip_hw_instance->major = ip->major; 788 ip_hw_instance->minor = ip->minor; 789 ip_hw_instance->revision = ip->revision; 790 ip_hw_instance->harvest = ip->harvest; 791 ip_hw_instance->num_base_addresses = ip->num_base_address; 792 793 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 794 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 795 796 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 797 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 798 res = kobject_add(&ip_hw_instance->kobj, NULL, 799 "%d", ip_hw_instance->num_instance); 800 next_ip: 801 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 802 } 803 } 804 805 return 0; 806 } 807 808 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 809 { 810 struct binary_header *bhdr; 811 struct ip_discovery_header *ihdr; 812 struct die_header *dhdr; 813 struct kset *die_kset = &adev->ip_top->die_kset; 814 u16 num_dies, die_offset, num_ips; 815 size_t ip_offset; 816 int ii, res; 817 818 bhdr = (struct binary_header *)adev->mman.discovery_bin; 819 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 820 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 821 num_dies = le16_to_cpu(ihdr->num_dies); 822 823 DRM_DEBUG("number of dies: %d\n", num_dies); 824 825 for (ii = 0; ii < num_dies; ii++) { 826 struct ip_die_entry *ip_die_entry; 827 828 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 829 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 830 num_ips = le16_to_cpu(dhdr->num_ips); 831 ip_offset = die_offset + sizeof(*dhdr); 832 833 /* Add the die to the kset. 834 * 835 * dhdr->die_id == ii, which was checked in 836 * amdgpu_discovery_reg_base_init(). 837 */ 838 839 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 840 if (!ip_die_entry) 841 return -ENOMEM; 842 843 ip_die_entry->num_ips = num_ips; 844 845 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 846 ip_die_entry->ip_kset.kobj.kset = die_kset; 847 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 848 res = kset_register(&ip_die_entry->ip_kset); 849 if (res) { 850 DRM_ERROR("Couldn't register ip_die_entry kset"); 851 kfree(ip_die_entry); 852 return res; 853 } 854 855 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 856 } 857 858 return 0; 859 } 860 861 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 862 { 863 struct kset *die_kset; 864 int res, ii; 865 866 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 867 if (!adev->ip_top) 868 return -ENOMEM; 869 870 adev->ip_top->adev = adev; 871 872 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 873 &adev->dev->kobj, "ip_discovery"); 874 if (res) { 875 DRM_ERROR("Couldn't init and add ip_discovery/"); 876 goto Err; 877 } 878 879 die_kset = &adev->ip_top->die_kset; 880 kobject_set_name(&die_kset->kobj, "%s", "die"); 881 die_kset->kobj.parent = &adev->ip_top->kobj; 882 die_kset->kobj.ktype = &die_kobj_ktype; 883 res = kset_register(&adev->ip_top->die_kset); 884 if (res) { 885 DRM_ERROR("Couldn't register die_kset"); 886 goto Err; 887 } 888 889 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 890 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 891 ip_hw_instance_attrs[ii] = NULL; 892 893 res = amdgpu_discovery_sysfs_recurse(adev); 894 895 return res; 896 Err: 897 kobject_put(&adev->ip_top->kobj); 898 return res; 899 } 900 901 /* -------------------------------------------------- */ 902 903 #define list_to_kobj(el) container_of(el, struct kobject, entry) 904 905 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 906 { 907 struct list_head *el, *tmp; 908 struct kset *hw_id_kset; 909 910 hw_id_kset = &ip_hw_id->hw_id_kset; 911 spin_lock(&hw_id_kset->list_lock); 912 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 913 list_del_init(el); 914 spin_unlock(&hw_id_kset->list_lock); 915 /* kobject is embedded in ip_hw_instance */ 916 kobject_put(list_to_kobj(el)); 917 spin_lock(&hw_id_kset->list_lock); 918 } 919 spin_unlock(&hw_id_kset->list_lock); 920 kobject_put(&ip_hw_id->hw_id_kset.kobj); 921 } 922 923 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 924 { 925 struct list_head *el, *tmp; 926 struct kset *ip_kset; 927 928 ip_kset = &ip_die_entry->ip_kset; 929 spin_lock(&ip_kset->list_lock); 930 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 931 list_del_init(el); 932 spin_unlock(&ip_kset->list_lock); 933 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 934 spin_lock(&ip_kset->list_lock); 935 } 936 spin_unlock(&ip_kset->list_lock); 937 kobject_put(&ip_die_entry->ip_kset.kobj); 938 } 939 940 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 941 { 942 struct list_head *el, *tmp; 943 struct kset *die_kset; 944 945 die_kset = &adev->ip_top->die_kset; 946 spin_lock(&die_kset->list_lock); 947 list_for_each_prev_safe(el, tmp, &die_kset->list) { 948 list_del_init(el); 949 spin_unlock(&die_kset->list_lock); 950 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 951 spin_lock(&die_kset->list_lock); 952 } 953 spin_unlock(&die_kset->list_lock); 954 kobject_put(&adev->ip_top->die_kset.kobj); 955 kobject_put(&adev->ip_top->kobj); 956 } 957 958 /* ================================================== */ 959 960 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 961 { 962 struct binary_header *bhdr; 963 struct ip_discovery_header *ihdr; 964 struct die_header *dhdr; 965 struct ip *ip; 966 uint16_t die_offset; 967 uint16_t ip_offset; 968 uint16_t num_dies; 969 uint16_t num_ips; 970 uint8_t num_base_address; 971 int hw_ip; 972 int i, j, k; 973 int r; 974 975 r = amdgpu_discovery_init(adev); 976 if (r) { 977 DRM_ERROR("amdgpu_discovery_init failed\n"); 978 return r; 979 } 980 981 bhdr = (struct binary_header *)adev->mman.discovery_bin; 982 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 983 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 984 num_dies = le16_to_cpu(ihdr->num_dies); 985 986 DRM_DEBUG("number of dies: %d\n", num_dies); 987 988 for (i = 0; i < num_dies; i++) { 989 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 990 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 991 num_ips = le16_to_cpu(dhdr->num_ips); 992 ip_offset = die_offset + sizeof(*dhdr); 993 994 if (le16_to_cpu(dhdr->die_id) != i) { 995 DRM_ERROR("invalid die id %d, expected %d\n", 996 le16_to_cpu(dhdr->die_id), i); 997 return -EINVAL; 998 } 999 1000 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1001 le16_to_cpu(dhdr->die_id), num_ips); 1002 1003 for (j = 0; j < num_ips; j++) { 1004 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1005 1006 if (amdgpu_discovery_validate_ip(ip)) 1007 goto next_ip; 1008 1009 num_base_address = ip->num_base_address; 1010 1011 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1012 hw_id_names[le16_to_cpu(ip->hw_id)], 1013 le16_to_cpu(ip->hw_id), 1014 ip->number_instance, 1015 ip->major, ip->minor, 1016 ip->revision); 1017 1018 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1019 /* Bit [5:0]: original revision value 1020 * Bit [7:6]: en/decode capability: 1021 * 0b00 : VCN function normally 1022 * 0b10 : encode is disabled 1023 * 0b01 : decode is disabled 1024 */ 1025 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1026 ip->revision & 0xc0; 1027 ip->revision &= ~0xc0; 1028 adev->vcn.num_vcn_inst++; 1029 } 1030 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1031 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1032 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1033 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 1034 adev->sdma.num_instances++; 1035 1036 for (k = 0; k < num_base_address; k++) { 1037 /* 1038 * convert the endianness of base addresses in place, 1039 * so that we don't need to convert them when accessing adev->reg_offset. 1040 */ 1041 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1042 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1043 } 1044 1045 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1046 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1047 DRM_DEBUG("set register base offset for %s\n", 1048 hw_id_names[le16_to_cpu(ip->hw_id)]); 1049 adev->reg_offset[hw_ip][ip->number_instance] = 1050 ip->base_address; 1051 /* Instance support is somewhat inconsistent. 1052 * SDMA is a good example. Sienna cichlid has 4 total 1053 * SDMA instances, each enumerated separately (HWIDs 1054 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1055 * but they are enumerated as multiple instances of the 1056 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1057 * example. On most chips there are multiple instances 1058 * with the same HWID. 1059 */ 1060 adev->ip_versions[hw_ip][ip->number_instance] = 1061 IP_VERSION(ip->major, ip->minor, ip->revision); 1062 } 1063 } 1064 1065 next_ip: 1066 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 1067 } 1068 } 1069 1070 amdgpu_discovery_sysfs_init(adev); 1071 1072 return 0; 1073 } 1074 1075 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1076 int *major, int *minor, int *revision) 1077 { 1078 struct binary_header *bhdr; 1079 struct ip_discovery_header *ihdr; 1080 struct die_header *dhdr; 1081 struct ip *ip; 1082 uint16_t die_offset; 1083 uint16_t ip_offset; 1084 uint16_t num_dies; 1085 uint16_t num_ips; 1086 int i, j; 1087 1088 if (!adev->mman.discovery_bin) { 1089 DRM_ERROR("ip discovery uninitialized\n"); 1090 return -EINVAL; 1091 } 1092 1093 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1094 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1095 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1096 num_dies = le16_to_cpu(ihdr->num_dies); 1097 1098 for (i = 0; i < num_dies; i++) { 1099 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1100 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1101 num_ips = le16_to_cpu(dhdr->num_ips); 1102 ip_offset = die_offset + sizeof(*dhdr); 1103 1104 for (j = 0; j < num_ips; j++) { 1105 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1106 1107 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1108 if (major) 1109 *major = ip->major; 1110 if (minor) 1111 *minor = ip->minor; 1112 if (revision) 1113 *revision = ip->revision; 1114 return 0; 1115 } 1116 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 1117 } 1118 } 1119 1120 return -EINVAL; 1121 } 1122 1123 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1124 { 1125 int vcn_harvest_count = 0; 1126 1127 /* 1128 * Harvest table does not fit Navi1x and legacy GPUs, 1129 * so read harvest bit per IP data structure to set 1130 * harvest configuration. 1131 */ 1132 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1133 if ((adev->pdev->device == 0x731E && 1134 (adev->pdev->revision == 0xC6 || 1135 adev->pdev->revision == 0xC7)) || 1136 (adev->pdev->device == 0x7340 && 1137 adev->pdev->revision == 0xC9) || 1138 (adev->pdev->device == 0x7360 && 1139 adev->pdev->revision == 0xC7)) 1140 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1141 &vcn_harvest_count); 1142 } else { 1143 amdgpu_discovery_read_from_harvest_table(adev, 1144 &vcn_harvest_count); 1145 } 1146 1147 amdgpu_discovery_harvest_config_quirk(adev); 1148 1149 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1150 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1151 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1152 } 1153 if ((adev->pdev->device == 0x731E && 1154 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) || 1155 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) || 1156 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) { 1157 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1158 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1159 } 1160 } 1161 1162 union gc_info { 1163 struct gc_info_v1_0 v1; 1164 struct gc_info_v2_0 v2; 1165 }; 1166 1167 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1168 { 1169 struct binary_header *bhdr; 1170 union gc_info *gc_info; 1171 1172 if (!adev->mman.discovery_bin) { 1173 DRM_ERROR("ip discovery uninitialized\n"); 1174 return -EINVAL; 1175 } 1176 1177 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1178 gc_info = (union gc_info *)(adev->mman.discovery_bin + 1179 le16_to_cpu(bhdr->table_list[GC].offset)); 1180 switch (gc_info->v1.header.version_major) { 1181 case 1: 1182 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1183 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1184 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1185 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1186 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1187 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1188 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1189 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1190 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1191 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1192 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1193 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1194 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1195 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1196 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1197 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1198 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1199 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1200 break; 1201 case 2: 1202 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1203 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1204 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1205 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1206 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1207 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1208 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1209 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1210 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1211 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1212 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1213 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1214 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1215 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1216 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1217 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1218 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1219 break; 1220 default: 1221 dev_err(adev->dev, 1222 "Unhandled GC info table %d.%d\n", 1223 gc_info->v1.header.version_major, 1224 gc_info->v1.header.version_minor); 1225 return -EINVAL; 1226 } 1227 return 0; 1228 } 1229 1230 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1231 { 1232 /* what IP to use for this? */ 1233 switch (adev->ip_versions[GC_HWIP][0]) { 1234 case IP_VERSION(9, 0, 1): 1235 case IP_VERSION(9, 1, 0): 1236 case IP_VERSION(9, 2, 1): 1237 case IP_VERSION(9, 2, 2): 1238 case IP_VERSION(9, 3, 0): 1239 case IP_VERSION(9, 4, 0): 1240 case IP_VERSION(9, 4, 1): 1241 case IP_VERSION(9, 4, 2): 1242 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1243 break; 1244 case IP_VERSION(10, 1, 10): 1245 case IP_VERSION(10, 1, 1): 1246 case IP_VERSION(10, 1, 2): 1247 case IP_VERSION(10, 1, 3): 1248 case IP_VERSION(10, 1, 4): 1249 case IP_VERSION(10, 3, 0): 1250 case IP_VERSION(10, 3, 1): 1251 case IP_VERSION(10, 3, 2): 1252 case IP_VERSION(10, 3, 3): 1253 case IP_VERSION(10, 3, 4): 1254 case IP_VERSION(10, 3, 5): 1255 case IP_VERSION(10, 3, 6): 1256 case IP_VERSION(10, 3, 7): 1257 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1258 break; 1259 default: 1260 dev_err(adev->dev, 1261 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1262 adev->ip_versions[GC_HWIP][0]); 1263 return -EINVAL; 1264 } 1265 return 0; 1266 } 1267 1268 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1269 { 1270 /* use GC or MMHUB IP version */ 1271 switch (adev->ip_versions[GC_HWIP][0]) { 1272 case IP_VERSION(9, 0, 1): 1273 case IP_VERSION(9, 1, 0): 1274 case IP_VERSION(9, 2, 1): 1275 case IP_VERSION(9, 2, 2): 1276 case IP_VERSION(9, 3, 0): 1277 case IP_VERSION(9, 4, 0): 1278 case IP_VERSION(9, 4, 1): 1279 case IP_VERSION(9, 4, 2): 1280 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1281 break; 1282 case IP_VERSION(10, 1, 10): 1283 case IP_VERSION(10, 1, 1): 1284 case IP_VERSION(10, 1, 2): 1285 case IP_VERSION(10, 1, 3): 1286 case IP_VERSION(10, 1, 4): 1287 case IP_VERSION(10, 3, 0): 1288 case IP_VERSION(10, 3, 1): 1289 case IP_VERSION(10, 3, 2): 1290 case IP_VERSION(10, 3, 3): 1291 case IP_VERSION(10, 3, 4): 1292 case IP_VERSION(10, 3, 5): 1293 case IP_VERSION(10, 3, 6): 1294 case IP_VERSION(10, 3, 7): 1295 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1296 break; 1297 default: 1298 dev_err(adev->dev, 1299 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1300 adev->ip_versions[GC_HWIP][0]); 1301 return -EINVAL; 1302 } 1303 return 0; 1304 } 1305 1306 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1307 { 1308 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1309 case IP_VERSION(4, 0, 0): 1310 case IP_VERSION(4, 0, 1): 1311 case IP_VERSION(4, 1, 0): 1312 case IP_VERSION(4, 1, 1): 1313 case IP_VERSION(4, 3, 0): 1314 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1315 break; 1316 case IP_VERSION(4, 2, 0): 1317 case IP_VERSION(4, 2, 1): 1318 case IP_VERSION(4, 4, 0): 1319 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1320 break; 1321 case IP_VERSION(5, 0, 0): 1322 case IP_VERSION(5, 0, 1): 1323 case IP_VERSION(5, 0, 2): 1324 case IP_VERSION(5, 0, 3): 1325 case IP_VERSION(5, 2, 0): 1326 case IP_VERSION(5, 2, 1): 1327 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1328 break; 1329 default: 1330 dev_err(adev->dev, 1331 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1332 adev->ip_versions[OSSSYS_HWIP][0]); 1333 return -EINVAL; 1334 } 1335 return 0; 1336 } 1337 1338 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1339 { 1340 switch (adev->ip_versions[MP0_HWIP][0]) { 1341 case IP_VERSION(9, 0, 0): 1342 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1343 break; 1344 case IP_VERSION(10, 0, 0): 1345 case IP_VERSION(10, 0, 1): 1346 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1347 break; 1348 case IP_VERSION(11, 0, 0): 1349 case IP_VERSION(11, 0, 2): 1350 case IP_VERSION(11, 0, 4): 1351 case IP_VERSION(11, 0, 5): 1352 case IP_VERSION(11, 0, 9): 1353 case IP_VERSION(11, 0, 7): 1354 case IP_VERSION(11, 0, 11): 1355 case IP_VERSION(11, 0, 12): 1356 case IP_VERSION(11, 0, 13): 1357 case IP_VERSION(11, 5, 0): 1358 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1359 break; 1360 case IP_VERSION(11, 0, 8): 1361 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1362 break; 1363 case IP_VERSION(11, 0, 3): 1364 case IP_VERSION(12, 0, 1): 1365 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1366 break; 1367 case IP_VERSION(13, 0, 1): 1368 case IP_VERSION(13, 0, 2): 1369 case IP_VERSION(13, 0, 3): 1370 case IP_VERSION(13, 0, 5): 1371 case IP_VERSION(13, 0, 8): 1372 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1373 break; 1374 default: 1375 dev_err(adev->dev, 1376 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1377 adev->ip_versions[MP0_HWIP][0]); 1378 return -EINVAL; 1379 } 1380 return 0; 1381 } 1382 1383 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1384 { 1385 switch (adev->ip_versions[MP1_HWIP][0]) { 1386 case IP_VERSION(9, 0, 0): 1387 case IP_VERSION(10, 0, 0): 1388 case IP_VERSION(10, 0, 1): 1389 case IP_VERSION(11, 0, 2): 1390 if (adev->asic_type == CHIP_ARCTURUS) 1391 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1392 else 1393 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1394 break; 1395 case IP_VERSION(11, 0, 0): 1396 case IP_VERSION(11, 0, 5): 1397 case IP_VERSION(11, 0, 9): 1398 case IP_VERSION(11, 0, 7): 1399 case IP_VERSION(11, 0, 8): 1400 case IP_VERSION(11, 0, 11): 1401 case IP_VERSION(11, 0, 12): 1402 case IP_VERSION(11, 0, 13): 1403 case IP_VERSION(11, 5, 0): 1404 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1405 break; 1406 case IP_VERSION(12, 0, 0): 1407 case IP_VERSION(12, 0, 1): 1408 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1409 break; 1410 case IP_VERSION(13, 0, 1): 1411 case IP_VERSION(13, 0, 2): 1412 case IP_VERSION(13, 0, 3): 1413 case IP_VERSION(13, 0, 5): 1414 case IP_VERSION(13, 0, 8): 1415 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1416 break; 1417 default: 1418 dev_err(adev->dev, 1419 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1420 adev->ip_versions[MP1_HWIP][0]); 1421 return -EINVAL; 1422 } 1423 return 0; 1424 } 1425 1426 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1427 { 1428 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 1429 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1430 return 0; 1431 } 1432 1433 if (!amdgpu_device_has_dc_support(adev)) 1434 return 0; 1435 1436 #if defined(CONFIG_DRM_AMD_DC) 1437 if (adev->ip_versions[DCE_HWIP][0]) { 1438 switch (adev->ip_versions[DCE_HWIP][0]) { 1439 case IP_VERSION(1, 0, 0): 1440 case IP_VERSION(1, 0, 1): 1441 case IP_VERSION(2, 0, 2): 1442 case IP_VERSION(2, 0, 0): 1443 case IP_VERSION(2, 0, 3): 1444 case IP_VERSION(2, 1, 0): 1445 case IP_VERSION(3, 0, 0): 1446 case IP_VERSION(3, 0, 2): 1447 case IP_VERSION(3, 0, 3): 1448 case IP_VERSION(3, 0, 1): 1449 case IP_VERSION(3, 1, 2): 1450 case IP_VERSION(3, 1, 3): 1451 case IP_VERSION(3, 1, 5): 1452 case IP_VERSION(3, 1, 6): 1453 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1454 break; 1455 default: 1456 dev_err(adev->dev, 1457 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1458 adev->ip_versions[DCE_HWIP][0]); 1459 return -EINVAL; 1460 } 1461 } else if (adev->ip_versions[DCI_HWIP][0]) { 1462 switch (adev->ip_versions[DCI_HWIP][0]) { 1463 case IP_VERSION(12, 0, 0): 1464 case IP_VERSION(12, 0, 1): 1465 case IP_VERSION(12, 1, 0): 1466 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1467 break; 1468 default: 1469 dev_err(adev->dev, 1470 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1471 adev->ip_versions[DCI_HWIP][0]); 1472 return -EINVAL; 1473 } 1474 } 1475 #endif 1476 return 0; 1477 } 1478 1479 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1480 { 1481 switch (adev->ip_versions[GC_HWIP][0]) { 1482 case IP_VERSION(9, 0, 1): 1483 case IP_VERSION(9, 1, 0): 1484 case IP_VERSION(9, 2, 1): 1485 case IP_VERSION(9, 2, 2): 1486 case IP_VERSION(9, 3, 0): 1487 case IP_VERSION(9, 4, 0): 1488 case IP_VERSION(9, 4, 1): 1489 case IP_VERSION(9, 4, 2): 1490 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1491 break; 1492 case IP_VERSION(10, 1, 10): 1493 case IP_VERSION(10, 1, 2): 1494 case IP_VERSION(10, 1, 1): 1495 case IP_VERSION(10, 1, 3): 1496 case IP_VERSION(10, 1, 4): 1497 case IP_VERSION(10, 3, 0): 1498 case IP_VERSION(10, 3, 2): 1499 case IP_VERSION(10, 3, 1): 1500 case IP_VERSION(10, 3, 4): 1501 case IP_VERSION(10, 3, 5): 1502 case IP_VERSION(10, 3, 6): 1503 case IP_VERSION(10, 3, 3): 1504 case IP_VERSION(10, 3, 7): 1505 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1506 break; 1507 default: 1508 dev_err(adev->dev, 1509 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1510 adev->ip_versions[GC_HWIP][0]); 1511 return -EINVAL; 1512 } 1513 return 0; 1514 } 1515 1516 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1517 { 1518 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1519 case IP_VERSION(4, 0, 0): 1520 case IP_VERSION(4, 0, 1): 1521 case IP_VERSION(4, 1, 0): 1522 case IP_VERSION(4, 1, 1): 1523 case IP_VERSION(4, 1, 2): 1524 case IP_VERSION(4, 2, 0): 1525 case IP_VERSION(4, 2, 2): 1526 case IP_VERSION(4, 4, 0): 1527 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1528 break; 1529 case IP_VERSION(5, 0, 0): 1530 case IP_VERSION(5, 0, 1): 1531 case IP_VERSION(5, 0, 2): 1532 case IP_VERSION(5, 0, 5): 1533 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1534 break; 1535 case IP_VERSION(5, 2, 0): 1536 case IP_VERSION(5, 2, 2): 1537 case IP_VERSION(5, 2, 4): 1538 case IP_VERSION(5, 2, 5): 1539 case IP_VERSION(5, 2, 6): 1540 case IP_VERSION(5, 2, 3): 1541 case IP_VERSION(5, 2, 1): 1542 case IP_VERSION(5, 2, 7): 1543 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1544 break; 1545 default: 1546 dev_err(adev->dev, 1547 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1548 adev->ip_versions[SDMA0_HWIP][0]); 1549 return -EINVAL; 1550 } 1551 return 0; 1552 } 1553 1554 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1555 { 1556 if (adev->ip_versions[VCE_HWIP][0]) { 1557 switch (adev->ip_versions[UVD_HWIP][0]) { 1558 case IP_VERSION(7, 0, 0): 1559 case IP_VERSION(7, 2, 0): 1560 /* UVD is not supported on vega20 SR-IOV */ 1561 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1562 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1563 break; 1564 default: 1565 dev_err(adev->dev, 1566 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1567 adev->ip_versions[UVD_HWIP][0]); 1568 return -EINVAL; 1569 } 1570 switch (adev->ip_versions[VCE_HWIP][0]) { 1571 case IP_VERSION(4, 0, 0): 1572 case IP_VERSION(4, 1, 0): 1573 /* VCE is not supported on vega20 SR-IOV */ 1574 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1575 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1576 break; 1577 default: 1578 dev_err(adev->dev, 1579 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1580 adev->ip_versions[VCE_HWIP][0]); 1581 return -EINVAL; 1582 } 1583 } else { 1584 switch (adev->ip_versions[UVD_HWIP][0]) { 1585 case IP_VERSION(1, 0, 0): 1586 case IP_VERSION(1, 0, 1): 1587 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1588 break; 1589 case IP_VERSION(2, 0, 0): 1590 case IP_VERSION(2, 0, 2): 1591 case IP_VERSION(2, 2, 0): 1592 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1593 if (!amdgpu_sriov_vf(adev)) 1594 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1595 break; 1596 case IP_VERSION(2, 0, 3): 1597 break; 1598 case IP_VERSION(2, 5, 0): 1599 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1600 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1601 break; 1602 case IP_VERSION(2, 6, 0): 1603 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1604 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1605 break; 1606 case IP_VERSION(3, 0, 0): 1607 case IP_VERSION(3, 0, 16): 1608 case IP_VERSION(3, 1, 1): 1609 case IP_VERSION(3, 1, 2): 1610 case IP_VERSION(3, 0, 2): 1611 case IP_VERSION(3, 0, 192): 1612 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1613 if (!amdgpu_sriov_vf(adev)) 1614 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1615 break; 1616 case IP_VERSION(3, 0, 33): 1617 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1618 break; 1619 default: 1620 dev_err(adev->dev, 1621 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1622 adev->ip_versions[UVD_HWIP][0]); 1623 return -EINVAL; 1624 } 1625 } 1626 return 0; 1627 } 1628 1629 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1630 { 1631 switch (adev->ip_versions[GC_HWIP][0]) { 1632 case IP_VERSION(10, 1, 10): 1633 case IP_VERSION(10, 1, 1): 1634 case IP_VERSION(10, 1, 2): 1635 case IP_VERSION(10, 1, 3): 1636 case IP_VERSION(10, 1, 4): 1637 case IP_VERSION(10, 3, 0): 1638 case IP_VERSION(10, 3, 1): 1639 case IP_VERSION(10, 3, 2): 1640 case IP_VERSION(10, 3, 3): 1641 case IP_VERSION(10, 3, 4): 1642 case IP_VERSION(10, 3, 5): 1643 case IP_VERSION(10, 3, 6): 1644 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1645 break; 1646 default: 1647 break; 1648 } 1649 return 0; 1650 } 1651 1652 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1653 { 1654 int r; 1655 1656 switch (adev->asic_type) { 1657 case CHIP_VEGA10: 1658 vega10_reg_base_init(adev); 1659 adev->sdma.num_instances = 2; 1660 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1661 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1662 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1663 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1664 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1665 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1666 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1667 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1668 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1669 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1670 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1671 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1672 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1673 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1674 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1675 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1676 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1677 break; 1678 case CHIP_VEGA12: 1679 vega10_reg_base_init(adev); 1680 adev->sdma.num_instances = 2; 1681 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1682 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1683 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1684 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1685 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1686 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1687 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1688 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1689 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1690 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1691 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1692 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1693 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1694 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1695 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1696 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1697 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1698 break; 1699 case CHIP_RAVEN: 1700 vega10_reg_base_init(adev); 1701 adev->sdma.num_instances = 1; 1702 adev->vcn.num_vcn_inst = 1; 1703 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1704 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1705 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1706 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1707 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1708 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1709 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1710 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1711 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1712 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1713 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1714 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1715 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1716 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1717 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1718 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1719 } else { 1720 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1721 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1722 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1723 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1724 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1725 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1726 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1727 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1728 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1729 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1730 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1731 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1732 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1733 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1734 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1735 } 1736 break; 1737 case CHIP_VEGA20: 1738 vega20_reg_base_init(adev); 1739 adev->sdma.num_instances = 2; 1740 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1741 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1742 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1743 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1744 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1745 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1746 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1747 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1748 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 1749 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 1750 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1751 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 1752 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 1753 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 1754 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 1755 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 1756 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 1757 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 1758 break; 1759 case CHIP_ARCTURUS: 1760 arct_reg_base_init(adev); 1761 adev->sdma.num_instances = 8; 1762 adev->vcn.num_vcn_inst = 2; 1763 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1764 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1765 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 1766 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 1767 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 1768 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 1769 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 1770 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 1771 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 1772 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 1773 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 1774 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 1775 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 1776 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 1777 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 1778 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 1779 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1780 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 1781 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 1782 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 1783 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 1784 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 1785 break; 1786 case CHIP_ALDEBARAN: 1787 aldebaran_reg_base_init(adev); 1788 adev->sdma.num_instances = 5; 1789 adev->vcn.num_vcn_inst = 2; 1790 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1791 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1792 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 1793 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 1794 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 1795 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 1796 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 1797 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 1798 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 1799 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 1800 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 1801 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 1802 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 1803 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 1804 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 1805 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 1806 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 1807 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 1808 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 1809 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 1810 break; 1811 default: 1812 r = amdgpu_discovery_reg_base_init(adev); 1813 if (r) 1814 return -EINVAL; 1815 1816 amdgpu_discovery_harvest_ip(adev); 1817 break; 1818 } 1819 1820 switch (adev->ip_versions[GC_HWIP][0]) { 1821 case IP_VERSION(9, 0, 1): 1822 case IP_VERSION(9, 2, 1): 1823 case IP_VERSION(9, 4, 0): 1824 case IP_VERSION(9, 4, 1): 1825 case IP_VERSION(9, 4, 2): 1826 adev->family = AMDGPU_FAMILY_AI; 1827 break; 1828 case IP_VERSION(9, 1, 0): 1829 case IP_VERSION(9, 2, 2): 1830 case IP_VERSION(9, 3, 0): 1831 adev->family = AMDGPU_FAMILY_RV; 1832 break; 1833 case IP_VERSION(10, 1, 10): 1834 case IP_VERSION(10, 1, 1): 1835 case IP_VERSION(10, 1, 2): 1836 case IP_VERSION(10, 1, 3): 1837 case IP_VERSION(10, 1, 4): 1838 case IP_VERSION(10, 3, 0): 1839 case IP_VERSION(10, 3, 2): 1840 case IP_VERSION(10, 3, 4): 1841 case IP_VERSION(10, 3, 5): 1842 adev->family = AMDGPU_FAMILY_NV; 1843 break; 1844 case IP_VERSION(10, 3, 1): 1845 adev->family = AMDGPU_FAMILY_VGH; 1846 break; 1847 case IP_VERSION(10, 3, 3): 1848 adev->family = AMDGPU_FAMILY_YC; 1849 break; 1850 case IP_VERSION(10, 3, 6): 1851 adev->family = AMDGPU_FAMILY_GC_10_3_6; 1852 break; 1853 case IP_VERSION(10, 3, 7): 1854 adev->family = AMDGPU_FAMILY_GC_10_3_7; 1855 break; 1856 default: 1857 return -EINVAL; 1858 } 1859 1860 switch (adev->ip_versions[GC_HWIP][0]) { 1861 case IP_VERSION(9, 1, 0): 1862 case IP_VERSION(9, 2, 2): 1863 case IP_VERSION(9, 3, 0): 1864 case IP_VERSION(10, 1, 3): 1865 case IP_VERSION(10, 1, 4): 1866 case IP_VERSION(10, 3, 1): 1867 case IP_VERSION(10, 3, 3): 1868 case IP_VERSION(10, 3, 6): 1869 case IP_VERSION(10, 3, 7): 1870 adev->flags |= AMD_IS_APU; 1871 break; 1872 default: 1873 break; 1874 } 1875 1876 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 1877 adev->gmc.xgmi.supported = true; 1878 1879 /* set NBIO version */ 1880 switch (adev->ip_versions[NBIO_HWIP][0]) { 1881 case IP_VERSION(6, 1, 0): 1882 case IP_VERSION(6, 2, 0): 1883 adev->nbio.funcs = &nbio_v6_1_funcs; 1884 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 1885 break; 1886 case IP_VERSION(7, 0, 0): 1887 case IP_VERSION(7, 0, 1): 1888 case IP_VERSION(2, 5, 0): 1889 adev->nbio.funcs = &nbio_v7_0_funcs; 1890 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 1891 break; 1892 case IP_VERSION(7, 4, 0): 1893 case IP_VERSION(7, 4, 1): 1894 adev->nbio.funcs = &nbio_v7_4_funcs; 1895 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 1896 break; 1897 case IP_VERSION(7, 4, 4): 1898 adev->nbio.funcs = &nbio_v7_4_funcs; 1899 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 1900 break; 1901 case IP_VERSION(7, 2, 0): 1902 case IP_VERSION(7, 2, 1): 1903 case IP_VERSION(7, 3, 0): 1904 case IP_VERSION(7, 5, 0): 1905 case IP_VERSION(7, 5, 1): 1906 adev->nbio.funcs = &nbio_v7_2_funcs; 1907 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 1908 break; 1909 case IP_VERSION(2, 1, 1): 1910 case IP_VERSION(2, 3, 0): 1911 case IP_VERSION(2, 3, 1): 1912 case IP_VERSION(2, 3, 2): 1913 adev->nbio.funcs = &nbio_v2_3_funcs; 1914 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 1915 break; 1916 case IP_VERSION(3, 3, 0): 1917 case IP_VERSION(3, 3, 1): 1918 case IP_VERSION(3, 3, 2): 1919 case IP_VERSION(3, 3, 3): 1920 adev->nbio.funcs = &nbio_v2_3_funcs; 1921 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 1922 break; 1923 default: 1924 break; 1925 } 1926 1927 switch (adev->ip_versions[HDP_HWIP][0]) { 1928 case IP_VERSION(4, 0, 0): 1929 case IP_VERSION(4, 0, 1): 1930 case IP_VERSION(4, 1, 0): 1931 case IP_VERSION(4, 1, 1): 1932 case IP_VERSION(4, 1, 2): 1933 case IP_VERSION(4, 2, 0): 1934 case IP_VERSION(4, 2, 1): 1935 case IP_VERSION(4, 4, 0): 1936 adev->hdp.funcs = &hdp_v4_0_funcs; 1937 break; 1938 case IP_VERSION(5, 0, 0): 1939 case IP_VERSION(5, 0, 1): 1940 case IP_VERSION(5, 0, 2): 1941 case IP_VERSION(5, 0, 3): 1942 case IP_VERSION(5, 0, 4): 1943 case IP_VERSION(5, 2, 0): 1944 adev->hdp.funcs = &hdp_v5_0_funcs; 1945 break; 1946 default: 1947 break; 1948 } 1949 1950 switch (adev->ip_versions[DF_HWIP][0]) { 1951 case IP_VERSION(3, 6, 0): 1952 case IP_VERSION(3, 6, 1): 1953 case IP_VERSION(3, 6, 2): 1954 adev->df.funcs = &df_v3_6_funcs; 1955 break; 1956 case IP_VERSION(2, 1, 0): 1957 case IP_VERSION(2, 1, 1): 1958 case IP_VERSION(2, 5, 0): 1959 case IP_VERSION(3, 5, 1): 1960 case IP_VERSION(3, 5, 2): 1961 adev->df.funcs = &df_v1_7_funcs; 1962 break; 1963 default: 1964 break; 1965 } 1966 1967 switch (adev->ip_versions[SMUIO_HWIP][0]) { 1968 case IP_VERSION(9, 0, 0): 1969 case IP_VERSION(9, 0, 1): 1970 case IP_VERSION(10, 0, 0): 1971 case IP_VERSION(10, 0, 1): 1972 case IP_VERSION(10, 0, 2): 1973 adev->smuio.funcs = &smuio_v9_0_funcs; 1974 break; 1975 case IP_VERSION(11, 0, 0): 1976 case IP_VERSION(11, 0, 2): 1977 case IP_VERSION(11, 0, 3): 1978 case IP_VERSION(11, 0, 4): 1979 case IP_VERSION(11, 0, 7): 1980 case IP_VERSION(11, 0, 8): 1981 adev->smuio.funcs = &smuio_v11_0_funcs; 1982 break; 1983 case IP_VERSION(11, 0, 6): 1984 case IP_VERSION(11, 0, 10): 1985 case IP_VERSION(11, 0, 11): 1986 case IP_VERSION(11, 5, 0): 1987 case IP_VERSION(13, 0, 1): 1988 case IP_VERSION(13, 0, 9): 1989 case IP_VERSION(13, 0, 10): 1990 adev->smuio.funcs = &smuio_v11_0_6_funcs; 1991 break; 1992 case IP_VERSION(13, 0, 2): 1993 adev->smuio.funcs = &smuio_v13_0_funcs; 1994 break; 1995 default: 1996 break; 1997 } 1998 1999 r = amdgpu_discovery_set_common_ip_blocks(adev); 2000 if (r) 2001 return r; 2002 2003 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2004 if (r) 2005 return r; 2006 2007 /* For SR-IOV, PSP needs to be initialized before IH */ 2008 if (amdgpu_sriov_vf(adev)) { 2009 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2010 if (r) 2011 return r; 2012 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2013 if (r) 2014 return r; 2015 } else { 2016 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2017 if (r) 2018 return r; 2019 2020 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2021 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2022 if (r) 2023 return r; 2024 } 2025 } 2026 2027 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2028 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2029 if (r) 2030 return r; 2031 } 2032 2033 r = amdgpu_discovery_set_display_ip_blocks(adev); 2034 if (r) 2035 return r; 2036 2037 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2038 if (r) 2039 return r; 2040 2041 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2042 if (r) 2043 return r; 2044 2045 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2046 !amdgpu_sriov_vf(adev)) { 2047 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2048 if (r) 2049 return r; 2050 } 2051 2052 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2053 if (r) 2054 return r; 2055 2056 if (adev->enable_mes) { 2057 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2058 if (r) 2059 return r; 2060 } 2061 2062 return 0; 2063 } 2064 2065