1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gmc_v11_0.h" 51 #include "gfxhub_v2_0.h" 52 #include "mmhub_v2_0.h" 53 #include "nbio_v2_3.h" 54 #include "nbio_v4_3.h" 55 #include "nbio_v7_2.h" 56 #include "nbio_v7_7.h" 57 #include "hdp_v5_0.h" 58 #include "hdp_v5_2.h" 59 #include "hdp_v6_0.h" 60 #include "nv.h" 61 #include "soc21.h" 62 #include "navi10_ih.h" 63 #include "ih_v6_0.h" 64 #include "gfx_v10_0.h" 65 #include "gfx_v11_0.h" 66 #include "sdma_v5_0.h" 67 #include "sdma_v5_2.h" 68 #include "sdma_v6_0.h" 69 #include "lsdma_v6_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v3_0.h" 73 #include "jpeg_v3_0.h" 74 #include "vcn_v4_0.h" 75 #include "jpeg_v4_0.h" 76 #include "amdgpu_vkms.h" 77 #include "mes_v10_1.h" 78 #include "mes_v11_0.h" 79 #include "smuio_v11_0.h" 80 #include "smuio_v11_0_6.h" 81 #include "smuio_v13_0.h" 82 #include "smuio_v13_0_6.h" 83 84 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 85 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 86 87 #define mmRCC_CONFIG_MEMSIZE 0xde3 88 #define mmMM_INDEX 0x0 89 #define mmMM_INDEX_HI 0x6 90 #define mmMM_DATA 0x1 91 92 static const char *hw_id_names[HW_ID_MAX] = { 93 [MP1_HWID] = "MP1", 94 [MP2_HWID] = "MP2", 95 [THM_HWID] = "THM", 96 [SMUIO_HWID] = "SMUIO", 97 [FUSE_HWID] = "FUSE", 98 [CLKA_HWID] = "CLKA", 99 [PWR_HWID] = "PWR", 100 [GC_HWID] = "GC", 101 [UVD_HWID] = "UVD", 102 [AUDIO_AZ_HWID] = "AUDIO_AZ", 103 [ACP_HWID] = "ACP", 104 [DCI_HWID] = "DCI", 105 [DMU_HWID] = "DMU", 106 [DCO_HWID] = "DCO", 107 [DIO_HWID] = "DIO", 108 [XDMA_HWID] = "XDMA", 109 [DCEAZ_HWID] = "DCEAZ", 110 [DAZ_HWID] = "DAZ", 111 [SDPMUX_HWID] = "SDPMUX", 112 [NTB_HWID] = "NTB", 113 [IOHC_HWID] = "IOHC", 114 [L2IMU_HWID] = "L2IMU", 115 [VCE_HWID] = "VCE", 116 [MMHUB_HWID] = "MMHUB", 117 [ATHUB_HWID] = "ATHUB", 118 [DBGU_NBIO_HWID] = "DBGU_NBIO", 119 [DFX_HWID] = "DFX", 120 [DBGU0_HWID] = "DBGU0", 121 [DBGU1_HWID] = "DBGU1", 122 [OSSSYS_HWID] = "OSSSYS", 123 [HDP_HWID] = "HDP", 124 [SDMA0_HWID] = "SDMA0", 125 [SDMA1_HWID] = "SDMA1", 126 [SDMA2_HWID] = "SDMA2", 127 [SDMA3_HWID] = "SDMA3", 128 [LSDMA_HWID] = "LSDMA", 129 [ISP_HWID] = "ISP", 130 [DBGU_IO_HWID] = "DBGU_IO", 131 [DF_HWID] = "DF", 132 [CLKB_HWID] = "CLKB", 133 [FCH_HWID] = "FCH", 134 [DFX_DAP_HWID] = "DFX_DAP", 135 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 136 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 137 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 138 [L1IMU3_HWID] = "L1IMU3", 139 [L1IMU4_HWID] = "L1IMU4", 140 [L1IMU5_HWID] = "L1IMU5", 141 [L1IMU6_HWID] = "L1IMU6", 142 [L1IMU7_HWID] = "L1IMU7", 143 [L1IMU8_HWID] = "L1IMU8", 144 [L1IMU9_HWID] = "L1IMU9", 145 [L1IMU10_HWID] = "L1IMU10", 146 [L1IMU11_HWID] = "L1IMU11", 147 [L1IMU12_HWID] = "L1IMU12", 148 [L1IMU13_HWID] = "L1IMU13", 149 [L1IMU14_HWID] = "L1IMU14", 150 [L1IMU15_HWID] = "L1IMU15", 151 [WAFLC_HWID] = "WAFLC", 152 [FCH_USB_PD_HWID] = "FCH_USB_PD", 153 [PCIE_HWID] = "PCIE", 154 [PCS_HWID] = "PCS", 155 [DDCL_HWID] = "DDCL", 156 [SST_HWID] = "SST", 157 [IOAGR_HWID] = "IOAGR", 158 [NBIF_HWID] = "NBIF", 159 [IOAPIC_HWID] = "IOAPIC", 160 [SYSTEMHUB_HWID] = "SYSTEMHUB", 161 [NTBCCP_HWID] = "NTBCCP", 162 [UMC_HWID] = "UMC", 163 [SATA_HWID] = "SATA", 164 [USB_HWID] = "USB", 165 [CCXSEC_HWID] = "CCXSEC", 166 [XGMI_HWID] = "XGMI", 167 [XGBE_HWID] = "XGBE", 168 [MP0_HWID] = "MP0", 169 }; 170 171 static int hw_id_map[MAX_HWIP] = { 172 [GC_HWIP] = GC_HWID, 173 [HDP_HWIP] = HDP_HWID, 174 [SDMA0_HWIP] = SDMA0_HWID, 175 [SDMA1_HWIP] = SDMA1_HWID, 176 [SDMA2_HWIP] = SDMA2_HWID, 177 [SDMA3_HWIP] = SDMA3_HWID, 178 [LSDMA_HWIP] = LSDMA_HWID, 179 [MMHUB_HWIP] = MMHUB_HWID, 180 [ATHUB_HWIP] = ATHUB_HWID, 181 [NBIO_HWIP] = NBIF_HWID, 182 [MP0_HWIP] = MP0_HWID, 183 [MP1_HWIP] = MP1_HWID, 184 [UVD_HWIP] = UVD_HWID, 185 [VCE_HWIP] = VCE_HWID, 186 [DF_HWIP] = DF_HWID, 187 [DCE_HWIP] = DMU_HWID, 188 [OSSSYS_HWIP] = OSSSYS_HWID, 189 [SMUIO_HWIP] = SMUIO_HWID, 190 [PWR_HWIP] = PWR_HWID, 191 [NBIF_HWIP] = NBIF_HWID, 192 [THM_HWIP] = THM_HWID, 193 [CLK_HWIP] = CLKA_HWID, 194 [UMC_HWIP] = UMC_HWID, 195 [XGMI_HWIP] = XGMI_HWID, 196 [DCI_HWIP] = DCI_HWID, 197 }; 198 199 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 200 { 201 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 202 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 203 204 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 205 adev->mman.discovery_tmr_size, false); 206 return 0; 207 } 208 209 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 210 { 211 const struct firmware *fw; 212 const char *fw_name; 213 int r; 214 215 switch (amdgpu_discovery) { 216 case 2: 217 fw_name = FIRMWARE_IP_DISCOVERY; 218 break; 219 default: 220 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 221 return -EINVAL; 222 } 223 224 r = request_firmware(&fw, fw_name, adev->dev); 225 if (r) { 226 dev_err(adev->dev, "can't load firmware \"%s\"\n", 227 fw_name); 228 return r; 229 } 230 231 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 232 release_firmware(fw); 233 234 return 0; 235 } 236 237 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 238 { 239 uint16_t checksum = 0; 240 int i; 241 242 for (i = 0; i < size; i++) 243 checksum += data[i]; 244 245 return checksum; 246 } 247 248 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 249 uint16_t expected) 250 { 251 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 252 } 253 254 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 255 { 256 struct binary_header *bhdr; 257 bhdr = (struct binary_header *)binary; 258 259 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 260 } 261 262 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 263 { 264 /* 265 * So far, apply this quirk only on those Navy Flounder boards which 266 * have a bad harvest table of VCN config. 267 */ 268 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 269 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 270 switch (adev->pdev->revision) { 271 case 0xC1: 272 case 0xC2: 273 case 0xC3: 274 case 0xC5: 275 case 0xC7: 276 case 0xCF: 277 case 0xDF: 278 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 279 break; 280 default: 281 break; 282 } 283 } 284 } 285 286 static int amdgpu_discovery_init(struct amdgpu_device *adev) 287 { 288 struct table_info *info; 289 struct binary_header *bhdr; 290 uint16_t offset; 291 uint16_t size; 292 uint16_t checksum; 293 int r; 294 295 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 296 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 297 if (!adev->mman.discovery_bin) 298 return -ENOMEM; 299 300 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 301 if (r) { 302 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 303 r = -EINVAL; 304 goto out; 305 } 306 307 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 308 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 309 /* retry read ip discovery binary from file */ 310 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 311 if (r) { 312 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 313 r = -EINVAL; 314 goto out; 315 } 316 /* check the ip discovery binary signature */ 317 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 318 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 319 r = -EINVAL; 320 goto out; 321 } 322 } 323 324 bhdr = (struct binary_header *)adev->mman.discovery_bin; 325 326 offset = offsetof(struct binary_header, binary_checksum) + 327 sizeof(bhdr->binary_checksum); 328 size = le16_to_cpu(bhdr->binary_size) - offset; 329 checksum = le16_to_cpu(bhdr->binary_checksum); 330 331 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 332 size, checksum)) { 333 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 334 r = -EINVAL; 335 goto out; 336 } 337 338 info = &bhdr->table_list[IP_DISCOVERY]; 339 offset = le16_to_cpu(info->offset); 340 checksum = le16_to_cpu(info->checksum); 341 342 if (offset) { 343 struct ip_discovery_header *ihdr = 344 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 345 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 346 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 347 r = -EINVAL; 348 goto out; 349 } 350 351 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 352 le16_to_cpu(ihdr->size), checksum)) { 353 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 354 r = -EINVAL; 355 goto out; 356 } 357 } 358 359 info = &bhdr->table_list[GC]; 360 offset = le16_to_cpu(info->offset); 361 checksum = le16_to_cpu(info->checksum); 362 363 if (offset) { 364 struct gpu_info_header *ghdr = 365 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 366 367 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 368 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 369 r = -EINVAL; 370 goto out; 371 } 372 373 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 374 le32_to_cpu(ghdr->size), checksum)) { 375 dev_err(adev->dev, "invalid gc data table checksum\n"); 376 r = -EINVAL; 377 goto out; 378 } 379 } 380 381 info = &bhdr->table_list[HARVEST_INFO]; 382 offset = le16_to_cpu(info->offset); 383 checksum = le16_to_cpu(info->checksum); 384 385 if (offset) { 386 struct harvest_info_header *hhdr = 387 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 388 389 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 390 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 391 r = -EINVAL; 392 goto out; 393 } 394 395 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 396 sizeof(struct harvest_table), checksum)) { 397 dev_err(adev->dev, "invalid harvest data table checksum\n"); 398 r = -EINVAL; 399 goto out; 400 } 401 } 402 403 info = &bhdr->table_list[VCN_INFO]; 404 offset = le16_to_cpu(info->offset); 405 checksum = le16_to_cpu(info->checksum); 406 407 if (offset) { 408 struct vcn_info_header *vhdr = 409 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 410 411 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 412 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 413 r = -EINVAL; 414 goto out; 415 } 416 417 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 418 le32_to_cpu(vhdr->size_bytes), checksum)) { 419 dev_err(adev->dev, "invalid vcn data table checksum\n"); 420 r = -EINVAL; 421 goto out; 422 } 423 } 424 425 info = &bhdr->table_list[MALL_INFO]; 426 offset = le16_to_cpu(info->offset); 427 checksum = le16_to_cpu(info->checksum); 428 429 if (0 && offset) { 430 struct mall_info_header *mhdr = 431 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 432 433 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 434 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 435 r = -EINVAL; 436 goto out; 437 } 438 439 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 440 le32_to_cpu(mhdr->size_bytes), checksum)) { 441 dev_err(adev->dev, "invalid mall data table checksum\n"); 442 r = -EINVAL; 443 goto out; 444 } 445 } 446 447 return 0; 448 449 out: 450 kfree(adev->mman.discovery_bin); 451 adev->mman.discovery_bin = NULL; 452 453 return r; 454 } 455 456 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 457 458 void amdgpu_discovery_fini(struct amdgpu_device *adev) 459 { 460 amdgpu_discovery_sysfs_fini(adev); 461 kfree(adev->mman.discovery_bin); 462 adev->mman.discovery_bin = NULL; 463 } 464 465 static int amdgpu_discovery_validate_ip(const struct ip *ip) 466 { 467 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 468 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 469 ip->number_instance); 470 return -EINVAL; 471 } 472 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 473 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 474 le16_to_cpu(ip->hw_id)); 475 return -EINVAL; 476 } 477 478 return 0; 479 } 480 481 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 482 uint32_t *vcn_harvest_count) 483 { 484 struct binary_header *bhdr; 485 struct ip_discovery_header *ihdr; 486 struct die_header *dhdr; 487 struct ip *ip; 488 uint16_t die_offset, ip_offset, num_dies, num_ips; 489 int i, j; 490 491 bhdr = (struct binary_header *)adev->mman.discovery_bin; 492 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 493 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 494 num_dies = le16_to_cpu(ihdr->num_dies); 495 496 /* scan harvest bit of all IP data structures */ 497 for (i = 0; i < num_dies; i++) { 498 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 499 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 500 num_ips = le16_to_cpu(dhdr->num_ips); 501 ip_offset = die_offset + sizeof(*dhdr); 502 503 for (j = 0; j < num_ips; j++) { 504 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 505 506 if (amdgpu_discovery_validate_ip(ip)) 507 goto next_ip; 508 509 if (le16_to_cpu(ip->harvest) == 1) { 510 switch (le16_to_cpu(ip->hw_id)) { 511 case VCN_HWID: 512 (*vcn_harvest_count)++; 513 if (ip->number_instance == 0) 514 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 515 else 516 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 517 break; 518 case DMU_HWID: 519 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 520 break; 521 default: 522 break; 523 } 524 } 525 next_ip: 526 ip_offset += struct_size(ip, base_address, ip->num_base_address); 527 } 528 } 529 } 530 531 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 532 uint32_t *vcn_harvest_count, 533 uint32_t *umc_harvest_count) 534 { 535 struct binary_header *bhdr; 536 struct harvest_table *harvest_info; 537 u16 offset; 538 int i; 539 540 bhdr = (struct binary_header *)adev->mman.discovery_bin; 541 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 542 543 if (!offset) { 544 dev_err(adev->dev, "invalid harvest table offset\n"); 545 return; 546 } 547 548 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 549 550 for (i = 0; i < 32; i++) { 551 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 552 break; 553 554 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 555 case VCN_HWID: 556 (*vcn_harvest_count)++; 557 if (harvest_info->list[i].number_instance == 0) 558 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 559 else 560 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 561 break; 562 case DMU_HWID: 563 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 564 break; 565 case UMC_HWID: 566 (*umc_harvest_count)++; 567 break; 568 default: 569 break; 570 } 571 } 572 } 573 574 /* ================================================== */ 575 576 struct ip_hw_instance { 577 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 578 579 int hw_id; 580 u8 num_instance; 581 u8 major, minor, revision; 582 u8 harvest; 583 584 int num_base_addresses; 585 u32 base_addr[]; 586 }; 587 588 struct ip_hw_id { 589 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 590 int hw_id; 591 }; 592 593 struct ip_die_entry { 594 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 595 u16 num_ips; 596 }; 597 598 /* -------------------------------------------------- */ 599 600 struct ip_hw_instance_attr { 601 struct attribute attr; 602 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 603 }; 604 605 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 606 { 607 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 608 } 609 610 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 611 { 612 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 613 } 614 615 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 616 { 617 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 618 } 619 620 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 621 { 622 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 623 } 624 625 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 626 { 627 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 628 } 629 630 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 631 { 632 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 633 } 634 635 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 636 { 637 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 638 } 639 640 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 641 { 642 ssize_t res, at; 643 int ii; 644 645 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 646 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 647 */ 648 if (at + 12 > PAGE_SIZE) 649 break; 650 res = sysfs_emit_at(buf, at, "0x%08X\n", 651 ip_hw_instance->base_addr[ii]); 652 if (res <= 0) 653 break; 654 at += res; 655 } 656 657 return res < 0 ? res : at; 658 } 659 660 static struct ip_hw_instance_attr ip_hw_attr[] = { 661 __ATTR_RO(hw_id), 662 __ATTR_RO(num_instance), 663 __ATTR_RO(major), 664 __ATTR_RO(minor), 665 __ATTR_RO(revision), 666 __ATTR_RO(harvest), 667 __ATTR_RO(num_base_addresses), 668 __ATTR_RO(base_addr), 669 }; 670 671 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 672 ATTRIBUTE_GROUPS(ip_hw_instance); 673 674 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 675 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 676 677 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 678 struct attribute *attr, 679 char *buf) 680 { 681 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 682 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 683 684 if (!ip_hw_attr->show) 685 return -EIO; 686 687 return ip_hw_attr->show(ip_hw_instance, buf); 688 } 689 690 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 691 .show = ip_hw_instance_attr_show, 692 }; 693 694 static void ip_hw_instance_release(struct kobject *kobj) 695 { 696 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 697 698 kfree(ip_hw_instance); 699 } 700 701 static struct kobj_type ip_hw_instance_ktype = { 702 .release = ip_hw_instance_release, 703 .sysfs_ops = &ip_hw_instance_sysfs_ops, 704 .default_groups = ip_hw_instance_groups, 705 }; 706 707 /* -------------------------------------------------- */ 708 709 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 710 711 static void ip_hw_id_release(struct kobject *kobj) 712 { 713 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 714 715 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 716 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 717 kfree(ip_hw_id); 718 } 719 720 static struct kobj_type ip_hw_id_ktype = { 721 .release = ip_hw_id_release, 722 .sysfs_ops = &kobj_sysfs_ops, 723 }; 724 725 /* -------------------------------------------------- */ 726 727 static void die_kobj_release(struct kobject *kobj); 728 static void ip_disc_release(struct kobject *kobj); 729 730 struct ip_die_entry_attribute { 731 struct attribute attr; 732 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 733 }; 734 735 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 736 737 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 738 { 739 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 740 } 741 742 /* If there are more ip_die_entry attrs, other than the number of IPs, 743 * we can make this intro an array of attrs, and then initialize 744 * ip_die_entry_attrs in a loop. 745 */ 746 static struct ip_die_entry_attribute num_ips_attr = 747 __ATTR_RO(num_ips); 748 749 static struct attribute *ip_die_entry_attrs[] = { 750 &num_ips_attr.attr, 751 NULL, 752 }; 753 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 754 755 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 756 757 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 758 struct attribute *attr, 759 char *buf) 760 { 761 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 762 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 763 764 if (!ip_die_entry_attr->show) 765 return -EIO; 766 767 return ip_die_entry_attr->show(ip_die_entry, buf); 768 } 769 770 static void ip_die_entry_release(struct kobject *kobj) 771 { 772 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 773 774 if (!list_empty(&ip_die_entry->ip_kset.list)) 775 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 776 kfree(ip_die_entry); 777 } 778 779 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 780 .show = ip_die_entry_attr_show, 781 }; 782 783 static struct kobj_type ip_die_entry_ktype = { 784 .release = ip_die_entry_release, 785 .sysfs_ops = &ip_die_entry_sysfs_ops, 786 .default_groups = ip_die_entry_groups, 787 }; 788 789 static struct kobj_type die_kobj_ktype = { 790 .release = die_kobj_release, 791 .sysfs_ops = &kobj_sysfs_ops, 792 }; 793 794 static struct kobj_type ip_discovery_ktype = { 795 .release = ip_disc_release, 796 .sysfs_ops = &kobj_sysfs_ops, 797 }; 798 799 struct ip_discovery_top { 800 struct kobject kobj; /* ip_discovery/ */ 801 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 802 struct amdgpu_device *adev; 803 }; 804 805 static void die_kobj_release(struct kobject *kobj) 806 { 807 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 808 struct ip_discovery_top, 809 die_kset); 810 if (!list_empty(&ip_top->die_kset.list)) 811 DRM_ERROR("ip_top->die_kset is not empty"); 812 } 813 814 static void ip_disc_release(struct kobject *kobj) 815 { 816 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 817 kobj); 818 struct amdgpu_device *adev = ip_top->adev; 819 820 adev->ip_top = NULL; 821 kfree(ip_top); 822 } 823 824 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 825 struct ip_die_entry *ip_die_entry, 826 const size_t _ip_offset, const int num_ips) 827 { 828 int ii, jj, kk, res; 829 830 DRM_DEBUG("num_ips:%d", num_ips); 831 832 /* Find all IPs of a given HW ID, and add their instance to 833 * #die/#hw_id/#instance/<attributes> 834 */ 835 for (ii = 0; ii < HW_ID_MAX; ii++) { 836 struct ip_hw_id *ip_hw_id = NULL; 837 size_t ip_offset = _ip_offset; 838 839 for (jj = 0; jj < num_ips; jj++) { 840 struct ip *ip; 841 struct ip_hw_instance *ip_hw_instance; 842 843 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 844 if (amdgpu_discovery_validate_ip(ip) || 845 le16_to_cpu(ip->hw_id) != ii) 846 goto next_ip; 847 848 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 849 850 /* We have a hw_id match; register the hw 851 * block if not yet registered. 852 */ 853 if (!ip_hw_id) { 854 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 855 if (!ip_hw_id) 856 return -ENOMEM; 857 ip_hw_id->hw_id = ii; 858 859 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 860 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 861 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 862 res = kset_register(&ip_hw_id->hw_id_kset); 863 if (res) { 864 DRM_ERROR("Couldn't register ip_hw_id kset"); 865 kfree(ip_hw_id); 866 return res; 867 } 868 if (hw_id_names[ii]) { 869 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 870 &ip_hw_id->hw_id_kset.kobj, 871 hw_id_names[ii]); 872 if (res) { 873 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 874 hw_id_names[ii], 875 kobject_name(&ip_die_entry->ip_kset.kobj)); 876 } 877 } 878 } 879 880 /* Now register its instance. 881 */ 882 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 883 base_addr, 884 ip->num_base_address), 885 GFP_KERNEL); 886 if (!ip_hw_instance) { 887 DRM_ERROR("no memory for ip_hw_instance"); 888 return -ENOMEM; 889 } 890 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 891 ip_hw_instance->num_instance = ip->number_instance; 892 ip_hw_instance->major = ip->major; 893 ip_hw_instance->minor = ip->minor; 894 ip_hw_instance->revision = ip->revision; 895 ip_hw_instance->harvest = ip->harvest; 896 ip_hw_instance->num_base_addresses = ip->num_base_address; 897 898 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 899 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 900 901 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 902 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 903 res = kobject_add(&ip_hw_instance->kobj, NULL, 904 "%d", ip_hw_instance->num_instance); 905 next_ip: 906 ip_offset += struct_size(ip, base_address, ip->num_base_address); 907 } 908 } 909 910 return 0; 911 } 912 913 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 914 { 915 struct binary_header *bhdr; 916 struct ip_discovery_header *ihdr; 917 struct die_header *dhdr; 918 struct kset *die_kset = &adev->ip_top->die_kset; 919 u16 num_dies, die_offset, num_ips; 920 size_t ip_offset; 921 int ii, res; 922 923 bhdr = (struct binary_header *)adev->mman.discovery_bin; 924 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 925 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 926 num_dies = le16_to_cpu(ihdr->num_dies); 927 928 DRM_DEBUG("number of dies: %d\n", num_dies); 929 930 for (ii = 0; ii < num_dies; ii++) { 931 struct ip_die_entry *ip_die_entry; 932 933 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 934 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 935 num_ips = le16_to_cpu(dhdr->num_ips); 936 ip_offset = die_offset + sizeof(*dhdr); 937 938 /* Add the die to the kset. 939 * 940 * dhdr->die_id == ii, which was checked in 941 * amdgpu_discovery_reg_base_init(). 942 */ 943 944 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 945 if (!ip_die_entry) 946 return -ENOMEM; 947 948 ip_die_entry->num_ips = num_ips; 949 950 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 951 ip_die_entry->ip_kset.kobj.kset = die_kset; 952 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 953 res = kset_register(&ip_die_entry->ip_kset); 954 if (res) { 955 DRM_ERROR("Couldn't register ip_die_entry kset"); 956 kfree(ip_die_entry); 957 return res; 958 } 959 960 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 961 } 962 963 return 0; 964 } 965 966 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 967 { 968 struct kset *die_kset; 969 int res, ii; 970 971 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 972 if (!adev->ip_top) 973 return -ENOMEM; 974 975 adev->ip_top->adev = adev; 976 977 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 978 &adev->dev->kobj, "ip_discovery"); 979 if (res) { 980 DRM_ERROR("Couldn't init and add ip_discovery/"); 981 goto Err; 982 } 983 984 die_kset = &adev->ip_top->die_kset; 985 kobject_set_name(&die_kset->kobj, "%s", "die"); 986 die_kset->kobj.parent = &adev->ip_top->kobj; 987 die_kset->kobj.ktype = &die_kobj_ktype; 988 res = kset_register(&adev->ip_top->die_kset); 989 if (res) { 990 DRM_ERROR("Couldn't register die_kset"); 991 goto Err; 992 } 993 994 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 995 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 996 ip_hw_instance_attrs[ii] = NULL; 997 998 res = amdgpu_discovery_sysfs_recurse(adev); 999 1000 return res; 1001 Err: 1002 kobject_put(&adev->ip_top->kobj); 1003 return res; 1004 } 1005 1006 /* -------------------------------------------------- */ 1007 1008 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1009 1010 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1011 { 1012 struct list_head *el, *tmp; 1013 struct kset *hw_id_kset; 1014 1015 hw_id_kset = &ip_hw_id->hw_id_kset; 1016 spin_lock(&hw_id_kset->list_lock); 1017 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1018 list_del_init(el); 1019 spin_unlock(&hw_id_kset->list_lock); 1020 /* kobject is embedded in ip_hw_instance */ 1021 kobject_put(list_to_kobj(el)); 1022 spin_lock(&hw_id_kset->list_lock); 1023 } 1024 spin_unlock(&hw_id_kset->list_lock); 1025 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1026 } 1027 1028 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1029 { 1030 struct list_head *el, *tmp; 1031 struct kset *ip_kset; 1032 1033 ip_kset = &ip_die_entry->ip_kset; 1034 spin_lock(&ip_kset->list_lock); 1035 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1036 list_del_init(el); 1037 spin_unlock(&ip_kset->list_lock); 1038 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1039 spin_lock(&ip_kset->list_lock); 1040 } 1041 spin_unlock(&ip_kset->list_lock); 1042 kobject_put(&ip_die_entry->ip_kset.kobj); 1043 } 1044 1045 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1046 { 1047 struct list_head *el, *tmp; 1048 struct kset *die_kset; 1049 1050 die_kset = &adev->ip_top->die_kset; 1051 spin_lock(&die_kset->list_lock); 1052 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1053 list_del_init(el); 1054 spin_unlock(&die_kset->list_lock); 1055 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1056 spin_lock(&die_kset->list_lock); 1057 } 1058 spin_unlock(&die_kset->list_lock); 1059 kobject_put(&adev->ip_top->die_kset.kobj); 1060 kobject_put(&adev->ip_top->kobj); 1061 } 1062 1063 /* ================================================== */ 1064 1065 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1066 { 1067 struct binary_header *bhdr; 1068 struct ip_discovery_header *ihdr; 1069 struct die_header *dhdr; 1070 struct ip *ip; 1071 uint16_t die_offset; 1072 uint16_t ip_offset; 1073 uint16_t num_dies; 1074 uint16_t num_ips; 1075 uint8_t num_base_address; 1076 int hw_ip; 1077 int i, j, k; 1078 int r; 1079 1080 r = amdgpu_discovery_init(adev); 1081 if (r) { 1082 DRM_ERROR("amdgpu_discovery_init failed\n"); 1083 return r; 1084 } 1085 1086 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1087 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1088 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1089 num_dies = le16_to_cpu(ihdr->num_dies); 1090 1091 DRM_DEBUG("number of dies: %d\n", num_dies); 1092 1093 for (i = 0; i < num_dies; i++) { 1094 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1095 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1096 num_ips = le16_to_cpu(dhdr->num_ips); 1097 ip_offset = die_offset + sizeof(*dhdr); 1098 1099 if (le16_to_cpu(dhdr->die_id) != i) { 1100 DRM_ERROR("invalid die id %d, expected %d\n", 1101 le16_to_cpu(dhdr->die_id), i); 1102 return -EINVAL; 1103 } 1104 1105 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1106 le16_to_cpu(dhdr->die_id), num_ips); 1107 1108 for (j = 0; j < num_ips; j++) { 1109 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1110 1111 if (amdgpu_discovery_validate_ip(ip)) 1112 goto next_ip; 1113 1114 num_base_address = ip->num_base_address; 1115 1116 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1117 hw_id_names[le16_to_cpu(ip->hw_id)], 1118 le16_to_cpu(ip->hw_id), 1119 ip->number_instance, 1120 ip->major, ip->minor, 1121 ip->revision); 1122 1123 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1124 /* Bit [5:0]: original revision value 1125 * Bit [7:6]: en/decode capability: 1126 * 0b00 : VCN function normally 1127 * 0b10 : encode is disabled 1128 * 0b01 : decode is disabled 1129 */ 1130 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1131 ip->revision & 0xc0; 1132 ip->revision &= ~0xc0; 1133 adev->vcn.num_vcn_inst++; 1134 } 1135 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1136 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1137 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1138 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 1139 adev->sdma.num_instances++; 1140 1141 if (le16_to_cpu(ip->hw_id) == UMC_HWID) 1142 adev->gmc.num_umc++; 1143 1144 for (k = 0; k < num_base_address; k++) { 1145 /* 1146 * convert the endianness of base addresses in place, 1147 * so that we don't need to convert them when accessing adev->reg_offset. 1148 */ 1149 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1150 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1151 } 1152 1153 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1154 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1155 DRM_DEBUG("set register base offset for %s\n", 1156 hw_id_names[le16_to_cpu(ip->hw_id)]); 1157 adev->reg_offset[hw_ip][ip->number_instance] = 1158 ip->base_address; 1159 /* Instance support is somewhat inconsistent. 1160 * SDMA is a good example. Sienna cichlid has 4 total 1161 * SDMA instances, each enumerated separately (HWIDs 1162 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1163 * but they are enumerated as multiple instances of the 1164 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1165 * example. On most chips there are multiple instances 1166 * with the same HWID. 1167 */ 1168 adev->ip_versions[hw_ip][ip->number_instance] = 1169 IP_VERSION(ip->major, ip->minor, ip->revision); 1170 } 1171 } 1172 1173 next_ip: 1174 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1175 } 1176 } 1177 1178 amdgpu_discovery_sysfs_init(adev); 1179 1180 return 0; 1181 } 1182 1183 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1184 int *major, int *minor, int *revision) 1185 { 1186 struct binary_header *bhdr; 1187 struct ip_discovery_header *ihdr; 1188 struct die_header *dhdr; 1189 struct ip *ip; 1190 uint16_t die_offset; 1191 uint16_t ip_offset; 1192 uint16_t num_dies; 1193 uint16_t num_ips; 1194 int i, j; 1195 1196 if (!adev->mman.discovery_bin) { 1197 DRM_ERROR("ip discovery uninitialized\n"); 1198 return -EINVAL; 1199 } 1200 1201 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1202 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1203 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1204 num_dies = le16_to_cpu(ihdr->num_dies); 1205 1206 for (i = 0; i < num_dies; i++) { 1207 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1208 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1209 num_ips = le16_to_cpu(dhdr->num_ips); 1210 ip_offset = die_offset + sizeof(*dhdr); 1211 1212 for (j = 0; j < num_ips; j++) { 1213 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1214 1215 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1216 if (major) 1217 *major = ip->major; 1218 if (minor) 1219 *minor = ip->minor; 1220 if (revision) 1221 *revision = ip->revision; 1222 return 0; 1223 } 1224 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1225 } 1226 } 1227 1228 return -EINVAL; 1229 } 1230 1231 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1232 { 1233 int vcn_harvest_count = 0; 1234 int umc_harvest_count = 0; 1235 1236 /* 1237 * Harvest table does not fit Navi1x and legacy GPUs, 1238 * so read harvest bit per IP data structure to set 1239 * harvest configuration. 1240 */ 1241 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1242 if ((adev->pdev->device == 0x731E && 1243 (adev->pdev->revision == 0xC6 || 1244 adev->pdev->revision == 0xC7)) || 1245 (adev->pdev->device == 0x7340 && 1246 adev->pdev->revision == 0xC9) || 1247 (adev->pdev->device == 0x7360 && 1248 adev->pdev->revision == 0xC7)) 1249 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1250 &vcn_harvest_count); 1251 } else { 1252 amdgpu_discovery_read_from_harvest_table(adev, 1253 &vcn_harvest_count, 1254 &umc_harvest_count); 1255 } 1256 1257 amdgpu_discovery_harvest_config_quirk(adev); 1258 1259 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1260 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1261 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1262 } 1263 1264 if (umc_harvest_count < adev->gmc.num_umc) { 1265 adev->gmc.num_umc -= umc_harvest_count; 1266 } 1267 } 1268 1269 union gc_info { 1270 struct gc_info_v1_0 v1; 1271 struct gc_info_v1_1 v1_1; 1272 struct gc_info_v1_2 v1_2; 1273 struct gc_info_v2_0 v2; 1274 }; 1275 1276 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1277 { 1278 struct binary_header *bhdr; 1279 union gc_info *gc_info; 1280 u16 offset; 1281 1282 if (!adev->mman.discovery_bin) { 1283 DRM_ERROR("ip discovery uninitialized\n"); 1284 return -EINVAL; 1285 } 1286 1287 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1288 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1289 1290 if (!offset) 1291 return 0; 1292 1293 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1294 1295 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1296 case 1: 1297 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1298 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1299 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1300 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1301 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1302 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1303 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1304 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1305 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1306 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1307 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1308 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1309 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1310 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1311 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1312 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1313 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1314 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1315 if (gc_info->v1.header.version_minor >= 1) { 1316 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1317 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1318 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1319 } 1320 if (gc_info->v1.header.version_minor >= 2) { 1321 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1322 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1323 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1324 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1325 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1326 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1327 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1328 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1329 } 1330 break; 1331 case 2: 1332 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1333 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1334 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1335 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1336 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1337 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1338 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1339 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1340 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1341 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1342 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1343 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1344 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1345 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1346 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1347 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1348 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1349 break; 1350 default: 1351 dev_err(adev->dev, 1352 "Unhandled GC info table %d.%d\n", 1353 le16_to_cpu(gc_info->v1.header.version_major), 1354 le16_to_cpu(gc_info->v1.header.version_minor)); 1355 return -EINVAL; 1356 } 1357 return 0; 1358 } 1359 1360 union mall_info { 1361 struct mall_info_v1_0 v1; 1362 }; 1363 1364 int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1365 { 1366 struct binary_header *bhdr; 1367 union mall_info *mall_info; 1368 u32 u, mall_size_per_umc, m_s_present, half_use; 1369 u64 mall_size; 1370 u16 offset; 1371 1372 if (!adev->mman.discovery_bin) { 1373 DRM_ERROR("ip discovery uninitialized\n"); 1374 return -EINVAL; 1375 } 1376 1377 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1378 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1379 1380 if (!offset) 1381 return 0; 1382 1383 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1384 1385 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1386 case 1: 1387 mall_size = 0; 1388 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1389 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1390 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1391 for (u = 0; u < adev->gmc.num_umc; u++) { 1392 if (m_s_present & (1 << u)) 1393 mall_size += mall_size_per_umc * 2; 1394 else if (half_use & (1 << u)) 1395 mall_size += mall_size_per_umc / 2; 1396 else 1397 mall_size += mall_size_per_umc; 1398 } 1399 adev->gmc.mall_size = mall_size; 1400 break; 1401 default: 1402 dev_err(adev->dev, 1403 "Unhandled MALL info table %d.%d\n", 1404 le16_to_cpu(mall_info->v1.header.version_major), 1405 le16_to_cpu(mall_info->v1.header.version_minor)); 1406 return -EINVAL; 1407 } 1408 return 0; 1409 } 1410 1411 union vcn_info { 1412 struct vcn_info_v1_0 v1; 1413 }; 1414 1415 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1416 { 1417 struct binary_header *bhdr; 1418 union vcn_info *vcn_info; 1419 u16 offset; 1420 int v; 1421 1422 if (!adev->mman.discovery_bin) { 1423 DRM_ERROR("ip discovery uninitialized\n"); 1424 return -EINVAL; 1425 } 1426 1427 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1428 dev_err(adev->dev, "invalid vcn instances\n"); 1429 return -EINVAL; 1430 } 1431 1432 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1433 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1434 1435 if (!offset) 1436 return 0; 1437 1438 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1439 1440 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1441 case 1: 1442 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1443 adev->vcn.vcn_codec_disable_mask[v] = 1444 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1445 } 1446 break; 1447 default: 1448 dev_err(adev->dev, 1449 "Unhandled VCN info table %d.%d\n", 1450 le16_to_cpu(vcn_info->v1.header.version_major), 1451 le16_to_cpu(vcn_info->v1.header.version_minor)); 1452 return -EINVAL; 1453 } 1454 return 0; 1455 } 1456 1457 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1458 { 1459 /* what IP to use for this? */ 1460 switch (adev->ip_versions[GC_HWIP][0]) { 1461 case IP_VERSION(9, 0, 1): 1462 case IP_VERSION(9, 1, 0): 1463 case IP_VERSION(9, 2, 1): 1464 case IP_VERSION(9, 2, 2): 1465 case IP_VERSION(9, 3, 0): 1466 case IP_VERSION(9, 4, 0): 1467 case IP_VERSION(9, 4, 1): 1468 case IP_VERSION(9, 4, 2): 1469 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1470 break; 1471 case IP_VERSION(10, 1, 10): 1472 case IP_VERSION(10, 1, 1): 1473 case IP_VERSION(10, 1, 2): 1474 case IP_VERSION(10, 1, 3): 1475 case IP_VERSION(10, 1, 4): 1476 case IP_VERSION(10, 3, 0): 1477 case IP_VERSION(10, 3, 1): 1478 case IP_VERSION(10, 3, 2): 1479 case IP_VERSION(10, 3, 3): 1480 case IP_VERSION(10, 3, 4): 1481 case IP_VERSION(10, 3, 5): 1482 case IP_VERSION(10, 3, 6): 1483 case IP_VERSION(10, 3, 7): 1484 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1485 break; 1486 case IP_VERSION(11, 0, 0): 1487 case IP_VERSION(11, 0, 1): 1488 case IP_VERSION(11, 0, 2): 1489 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1490 break; 1491 default: 1492 dev_err(adev->dev, 1493 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1494 adev->ip_versions[GC_HWIP][0]); 1495 return -EINVAL; 1496 } 1497 return 0; 1498 } 1499 1500 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1501 { 1502 /* use GC or MMHUB IP version */ 1503 switch (adev->ip_versions[GC_HWIP][0]) { 1504 case IP_VERSION(9, 0, 1): 1505 case IP_VERSION(9, 1, 0): 1506 case IP_VERSION(9, 2, 1): 1507 case IP_VERSION(9, 2, 2): 1508 case IP_VERSION(9, 3, 0): 1509 case IP_VERSION(9, 4, 0): 1510 case IP_VERSION(9, 4, 1): 1511 case IP_VERSION(9, 4, 2): 1512 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1513 break; 1514 case IP_VERSION(10, 1, 10): 1515 case IP_VERSION(10, 1, 1): 1516 case IP_VERSION(10, 1, 2): 1517 case IP_VERSION(10, 1, 3): 1518 case IP_VERSION(10, 1, 4): 1519 case IP_VERSION(10, 3, 0): 1520 case IP_VERSION(10, 3, 1): 1521 case IP_VERSION(10, 3, 2): 1522 case IP_VERSION(10, 3, 3): 1523 case IP_VERSION(10, 3, 4): 1524 case IP_VERSION(10, 3, 5): 1525 case IP_VERSION(10, 3, 6): 1526 case IP_VERSION(10, 3, 7): 1527 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1528 break; 1529 case IP_VERSION(11, 0, 0): 1530 case IP_VERSION(11, 0, 1): 1531 case IP_VERSION(11, 0, 2): 1532 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1533 break; 1534 default: 1535 dev_err(adev->dev, 1536 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1537 adev->ip_versions[GC_HWIP][0]); 1538 return -EINVAL; 1539 } 1540 return 0; 1541 } 1542 1543 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1544 { 1545 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1546 case IP_VERSION(4, 0, 0): 1547 case IP_VERSION(4, 0, 1): 1548 case IP_VERSION(4, 1, 0): 1549 case IP_VERSION(4, 1, 1): 1550 case IP_VERSION(4, 3, 0): 1551 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1552 break; 1553 case IP_VERSION(4, 2, 0): 1554 case IP_VERSION(4, 2, 1): 1555 case IP_VERSION(4, 4, 0): 1556 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1557 break; 1558 case IP_VERSION(5, 0, 0): 1559 case IP_VERSION(5, 0, 1): 1560 case IP_VERSION(5, 0, 2): 1561 case IP_VERSION(5, 0, 3): 1562 case IP_VERSION(5, 2, 0): 1563 case IP_VERSION(5, 2, 1): 1564 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1565 break; 1566 case IP_VERSION(6, 0, 0): 1567 case IP_VERSION(6, 0, 1): 1568 case IP_VERSION(6, 0, 2): 1569 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1570 break; 1571 default: 1572 dev_err(adev->dev, 1573 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1574 adev->ip_versions[OSSSYS_HWIP][0]); 1575 return -EINVAL; 1576 } 1577 return 0; 1578 } 1579 1580 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1581 { 1582 switch (adev->ip_versions[MP0_HWIP][0]) { 1583 case IP_VERSION(9, 0, 0): 1584 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1585 break; 1586 case IP_VERSION(10, 0, 0): 1587 case IP_VERSION(10, 0, 1): 1588 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1589 break; 1590 case IP_VERSION(11, 0, 0): 1591 case IP_VERSION(11, 0, 2): 1592 case IP_VERSION(11, 0, 4): 1593 case IP_VERSION(11, 0, 5): 1594 case IP_VERSION(11, 0, 9): 1595 case IP_VERSION(11, 0, 7): 1596 case IP_VERSION(11, 0, 11): 1597 case IP_VERSION(11, 0, 12): 1598 case IP_VERSION(11, 0, 13): 1599 case IP_VERSION(11, 5, 0): 1600 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1601 break; 1602 case IP_VERSION(11, 0, 8): 1603 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1604 break; 1605 case IP_VERSION(11, 0, 3): 1606 case IP_VERSION(12, 0, 1): 1607 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1608 break; 1609 case IP_VERSION(13, 0, 0): 1610 case IP_VERSION(13, 0, 1): 1611 case IP_VERSION(13, 0, 2): 1612 case IP_VERSION(13, 0, 3): 1613 case IP_VERSION(13, 0, 4): 1614 case IP_VERSION(13, 0, 5): 1615 case IP_VERSION(13, 0, 7): 1616 case IP_VERSION(13, 0, 8): 1617 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1618 break; 1619 default: 1620 dev_err(adev->dev, 1621 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1622 adev->ip_versions[MP0_HWIP][0]); 1623 return -EINVAL; 1624 } 1625 return 0; 1626 } 1627 1628 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1629 { 1630 switch (adev->ip_versions[MP1_HWIP][0]) { 1631 case IP_VERSION(9, 0, 0): 1632 case IP_VERSION(10, 0, 0): 1633 case IP_VERSION(10, 0, 1): 1634 case IP_VERSION(11, 0, 2): 1635 if (adev->asic_type == CHIP_ARCTURUS) 1636 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1637 else 1638 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1639 break; 1640 case IP_VERSION(11, 0, 0): 1641 case IP_VERSION(11, 0, 5): 1642 case IP_VERSION(11, 0, 9): 1643 case IP_VERSION(11, 0, 7): 1644 case IP_VERSION(11, 0, 8): 1645 case IP_VERSION(11, 0, 11): 1646 case IP_VERSION(11, 0, 12): 1647 case IP_VERSION(11, 0, 13): 1648 case IP_VERSION(11, 5, 0): 1649 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1650 break; 1651 case IP_VERSION(12, 0, 0): 1652 case IP_VERSION(12, 0, 1): 1653 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1654 break; 1655 case IP_VERSION(13, 0, 0): 1656 case IP_VERSION(13, 0, 1): 1657 case IP_VERSION(13, 0, 2): 1658 case IP_VERSION(13, 0, 3): 1659 case IP_VERSION(13, 0, 4): 1660 case IP_VERSION(13, 0, 5): 1661 case IP_VERSION(13, 0, 7): 1662 case IP_VERSION(13, 0, 8): 1663 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1664 break; 1665 default: 1666 dev_err(adev->dev, 1667 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1668 adev->ip_versions[MP1_HWIP][0]); 1669 return -EINVAL; 1670 } 1671 return 0; 1672 } 1673 1674 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1675 { 1676 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 1677 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1678 return 0; 1679 } 1680 1681 if (!amdgpu_device_has_dc_support(adev)) 1682 return 0; 1683 1684 #if defined(CONFIG_DRM_AMD_DC) 1685 if (adev->ip_versions[DCE_HWIP][0]) { 1686 switch (adev->ip_versions[DCE_HWIP][0]) { 1687 case IP_VERSION(1, 0, 0): 1688 case IP_VERSION(1, 0, 1): 1689 case IP_VERSION(2, 0, 2): 1690 case IP_VERSION(2, 0, 0): 1691 case IP_VERSION(2, 0, 3): 1692 case IP_VERSION(2, 1, 0): 1693 case IP_VERSION(3, 0, 0): 1694 case IP_VERSION(3, 0, 2): 1695 case IP_VERSION(3, 0, 3): 1696 case IP_VERSION(3, 0, 1): 1697 case IP_VERSION(3, 1, 2): 1698 case IP_VERSION(3, 1, 3): 1699 case IP_VERSION(3, 1, 5): 1700 case IP_VERSION(3, 1, 6): 1701 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1702 break; 1703 default: 1704 dev_err(adev->dev, 1705 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1706 adev->ip_versions[DCE_HWIP][0]); 1707 return -EINVAL; 1708 } 1709 } else if (adev->ip_versions[DCI_HWIP][0]) { 1710 switch (adev->ip_versions[DCI_HWIP][0]) { 1711 case IP_VERSION(12, 0, 0): 1712 case IP_VERSION(12, 0, 1): 1713 case IP_VERSION(12, 1, 0): 1714 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1715 break; 1716 default: 1717 dev_err(adev->dev, 1718 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1719 adev->ip_versions[DCI_HWIP][0]); 1720 return -EINVAL; 1721 } 1722 } 1723 #endif 1724 return 0; 1725 } 1726 1727 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1728 { 1729 switch (adev->ip_versions[GC_HWIP][0]) { 1730 case IP_VERSION(9, 0, 1): 1731 case IP_VERSION(9, 1, 0): 1732 case IP_VERSION(9, 2, 1): 1733 case IP_VERSION(9, 2, 2): 1734 case IP_VERSION(9, 3, 0): 1735 case IP_VERSION(9, 4, 0): 1736 case IP_VERSION(9, 4, 1): 1737 case IP_VERSION(9, 4, 2): 1738 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1739 break; 1740 case IP_VERSION(10, 1, 10): 1741 case IP_VERSION(10, 1, 2): 1742 case IP_VERSION(10, 1, 1): 1743 case IP_VERSION(10, 1, 3): 1744 case IP_VERSION(10, 1, 4): 1745 case IP_VERSION(10, 3, 0): 1746 case IP_VERSION(10, 3, 2): 1747 case IP_VERSION(10, 3, 1): 1748 case IP_VERSION(10, 3, 4): 1749 case IP_VERSION(10, 3, 5): 1750 case IP_VERSION(10, 3, 6): 1751 case IP_VERSION(10, 3, 3): 1752 case IP_VERSION(10, 3, 7): 1753 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1754 break; 1755 case IP_VERSION(11, 0, 0): 1756 case IP_VERSION(11, 0, 1): 1757 case IP_VERSION(11, 0, 2): 1758 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1759 break; 1760 default: 1761 dev_err(adev->dev, 1762 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1763 adev->ip_versions[GC_HWIP][0]); 1764 return -EINVAL; 1765 } 1766 return 0; 1767 } 1768 1769 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1770 { 1771 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1772 case IP_VERSION(4, 0, 0): 1773 case IP_VERSION(4, 0, 1): 1774 case IP_VERSION(4, 1, 0): 1775 case IP_VERSION(4, 1, 1): 1776 case IP_VERSION(4, 1, 2): 1777 case IP_VERSION(4, 2, 0): 1778 case IP_VERSION(4, 2, 2): 1779 case IP_VERSION(4, 4, 0): 1780 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1781 break; 1782 case IP_VERSION(5, 0, 0): 1783 case IP_VERSION(5, 0, 1): 1784 case IP_VERSION(5, 0, 2): 1785 case IP_VERSION(5, 0, 5): 1786 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1787 break; 1788 case IP_VERSION(5, 2, 0): 1789 case IP_VERSION(5, 2, 2): 1790 case IP_VERSION(5, 2, 4): 1791 case IP_VERSION(5, 2, 5): 1792 case IP_VERSION(5, 2, 6): 1793 case IP_VERSION(5, 2, 3): 1794 case IP_VERSION(5, 2, 1): 1795 case IP_VERSION(5, 2, 7): 1796 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1797 break; 1798 case IP_VERSION(6, 0, 0): 1799 case IP_VERSION(6, 0, 1): 1800 case IP_VERSION(6, 0, 2): 1801 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1802 break; 1803 default: 1804 dev_err(adev->dev, 1805 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1806 adev->ip_versions[SDMA0_HWIP][0]); 1807 return -EINVAL; 1808 } 1809 return 0; 1810 } 1811 1812 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1813 { 1814 if (adev->ip_versions[VCE_HWIP][0]) { 1815 switch (adev->ip_versions[UVD_HWIP][0]) { 1816 case IP_VERSION(7, 0, 0): 1817 case IP_VERSION(7, 2, 0): 1818 /* UVD is not supported on vega20 SR-IOV */ 1819 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1820 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1821 break; 1822 default: 1823 dev_err(adev->dev, 1824 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1825 adev->ip_versions[UVD_HWIP][0]); 1826 return -EINVAL; 1827 } 1828 switch (adev->ip_versions[VCE_HWIP][0]) { 1829 case IP_VERSION(4, 0, 0): 1830 case IP_VERSION(4, 1, 0): 1831 /* VCE is not supported on vega20 SR-IOV */ 1832 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1833 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1834 break; 1835 default: 1836 dev_err(adev->dev, 1837 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1838 adev->ip_versions[VCE_HWIP][0]); 1839 return -EINVAL; 1840 } 1841 } else { 1842 switch (adev->ip_versions[UVD_HWIP][0]) { 1843 case IP_VERSION(1, 0, 0): 1844 case IP_VERSION(1, 0, 1): 1845 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1846 break; 1847 case IP_VERSION(2, 0, 0): 1848 case IP_VERSION(2, 0, 2): 1849 case IP_VERSION(2, 2, 0): 1850 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1851 if (!amdgpu_sriov_vf(adev)) 1852 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1853 break; 1854 case IP_VERSION(2, 0, 3): 1855 break; 1856 case IP_VERSION(2, 5, 0): 1857 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1858 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1859 break; 1860 case IP_VERSION(2, 6, 0): 1861 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1862 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1863 break; 1864 case IP_VERSION(3, 0, 0): 1865 case IP_VERSION(3, 0, 16): 1866 case IP_VERSION(3, 1, 1): 1867 case IP_VERSION(3, 1, 2): 1868 case IP_VERSION(3, 0, 2): 1869 case IP_VERSION(3, 0, 192): 1870 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1871 if (!amdgpu_sriov_vf(adev)) 1872 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1873 break; 1874 case IP_VERSION(3, 0, 33): 1875 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1876 break; 1877 case IP_VERSION(4, 0, 0): 1878 case IP_VERSION(4, 0, 4): 1879 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 1880 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 1881 break; 1882 default: 1883 dev_err(adev->dev, 1884 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1885 adev->ip_versions[UVD_HWIP][0]); 1886 return -EINVAL; 1887 } 1888 } 1889 return 0; 1890 } 1891 1892 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1893 { 1894 switch (adev->ip_versions[GC_HWIP][0]) { 1895 case IP_VERSION(10, 1, 10): 1896 case IP_VERSION(10, 1, 1): 1897 case IP_VERSION(10, 1, 2): 1898 case IP_VERSION(10, 1, 3): 1899 case IP_VERSION(10, 1, 4): 1900 case IP_VERSION(10, 3, 0): 1901 case IP_VERSION(10, 3, 1): 1902 case IP_VERSION(10, 3, 2): 1903 case IP_VERSION(10, 3, 3): 1904 case IP_VERSION(10, 3, 4): 1905 case IP_VERSION(10, 3, 5): 1906 case IP_VERSION(10, 3, 6): 1907 if (amdgpu_mes) { 1908 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1909 adev->enable_mes = true; 1910 if (amdgpu_mes_kiq) 1911 adev->enable_mes_kiq = true; 1912 } 1913 break; 1914 case IP_VERSION(11, 0, 0): 1915 case IP_VERSION(11, 0, 1): 1916 case IP_VERSION(11, 0, 2): 1917 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 1918 adev->enable_mes = true; 1919 adev->enable_mes_kiq = true; 1920 break; 1921 default: 1922 break; 1923 } 1924 return 0; 1925 } 1926 1927 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1928 { 1929 int r; 1930 1931 switch (adev->asic_type) { 1932 case CHIP_VEGA10: 1933 vega10_reg_base_init(adev); 1934 adev->sdma.num_instances = 2; 1935 adev->gmc.num_umc = 4; 1936 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1937 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1938 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1939 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1940 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1941 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1942 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1943 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1944 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1945 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1946 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1947 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1948 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1949 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1950 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1951 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1952 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1953 break; 1954 case CHIP_VEGA12: 1955 vega10_reg_base_init(adev); 1956 adev->sdma.num_instances = 2; 1957 adev->gmc.num_umc = 4; 1958 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1959 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1960 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1961 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1962 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1963 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1964 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1965 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1966 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1967 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1968 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1969 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1970 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1971 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1972 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1973 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1974 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1975 break; 1976 case CHIP_RAVEN: 1977 vega10_reg_base_init(adev); 1978 adev->sdma.num_instances = 1; 1979 adev->vcn.num_vcn_inst = 1; 1980 adev->gmc.num_umc = 2; 1981 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1982 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1983 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1984 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1985 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1986 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1987 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1988 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1989 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1990 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1991 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1992 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1993 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1994 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1995 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1996 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1997 } else { 1998 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1999 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2000 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2001 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2002 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2003 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2004 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2005 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2006 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2007 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2008 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2009 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2010 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2011 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2012 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2013 } 2014 break; 2015 case CHIP_VEGA20: 2016 vega20_reg_base_init(adev); 2017 adev->sdma.num_instances = 2; 2018 adev->gmc.num_umc = 8; 2019 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2020 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2021 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2022 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2023 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2024 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2025 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2026 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2027 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2028 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2029 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2030 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2031 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2032 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2033 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2034 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2035 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2036 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2037 break; 2038 case CHIP_ARCTURUS: 2039 arct_reg_base_init(adev); 2040 adev->sdma.num_instances = 8; 2041 adev->vcn.num_vcn_inst = 2; 2042 adev->gmc.num_umc = 8; 2043 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2044 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2045 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2046 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2047 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2048 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2049 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2050 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2051 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2052 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2053 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2054 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2055 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2056 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2057 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2058 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2059 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2060 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2061 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2062 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2063 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2064 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2065 break; 2066 case CHIP_ALDEBARAN: 2067 aldebaran_reg_base_init(adev); 2068 adev->sdma.num_instances = 5; 2069 adev->vcn.num_vcn_inst = 2; 2070 adev->gmc.num_umc = 4; 2071 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2072 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2073 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2074 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2075 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2076 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2077 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2078 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2079 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2080 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2081 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2082 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2083 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2084 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2085 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2086 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2087 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2088 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2089 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2090 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2091 break; 2092 default: 2093 r = amdgpu_discovery_reg_base_init(adev); 2094 if (r) 2095 return -EINVAL; 2096 2097 amdgpu_discovery_harvest_ip(adev); 2098 amdgpu_discovery_get_gfx_info(adev); 2099 amdgpu_discovery_get_mall_info(adev); 2100 amdgpu_discovery_get_vcn_info(adev); 2101 break; 2102 } 2103 2104 switch (adev->ip_versions[GC_HWIP][0]) { 2105 case IP_VERSION(9, 0, 1): 2106 case IP_VERSION(9, 2, 1): 2107 case IP_VERSION(9, 4, 0): 2108 case IP_VERSION(9, 4, 1): 2109 case IP_VERSION(9, 4, 2): 2110 adev->family = AMDGPU_FAMILY_AI; 2111 break; 2112 case IP_VERSION(9, 1, 0): 2113 case IP_VERSION(9, 2, 2): 2114 case IP_VERSION(9, 3, 0): 2115 adev->family = AMDGPU_FAMILY_RV; 2116 break; 2117 case IP_VERSION(10, 1, 10): 2118 case IP_VERSION(10, 1, 1): 2119 case IP_VERSION(10, 1, 2): 2120 case IP_VERSION(10, 1, 3): 2121 case IP_VERSION(10, 1, 4): 2122 case IP_VERSION(10, 3, 0): 2123 case IP_VERSION(10, 3, 2): 2124 case IP_VERSION(10, 3, 4): 2125 case IP_VERSION(10, 3, 5): 2126 adev->family = AMDGPU_FAMILY_NV; 2127 break; 2128 case IP_VERSION(10, 3, 1): 2129 adev->family = AMDGPU_FAMILY_VGH; 2130 break; 2131 case IP_VERSION(10, 3, 3): 2132 adev->family = AMDGPU_FAMILY_YC; 2133 break; 2134 case IP_VERSION(10, 3, 6): 2135 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2136 break; 2137 case IP_VERSION(10, 3, 7): 2138 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2139 break; 2140 case IP_VERSION(11, 0, 0): 2141 case IP_VERSION(11, 0, 2): 2142 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2143 break; 2144 case IP_VERSION(11, 0, 1): 2145 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2146 break; 2147 default: 2148 return -EINVAL; 2149 } 2150 2151 switch (adev->ip_versions[GC_HWIP][0]) { 2152 case IP_VERSION(9, 1, 0): 2153 case IP_VERSION(9, 2, 2): 2154 case IP_VERSION(9, 3, 0): 2155 case IP_VERSION(10, 1, 3): 2156 case IP_VERSION(10, 1, 4): 2157 case IP_VERSION(10, 3, 1): 2158 case IP_VERSION(10, 3, 3): 2159 case IP_VERSION(10, 3, 6): 2160 case IP_VERSION(10, 3, 7): 2161 case IP_VERSION(11, 0, 1): 2162 adev->flags |= AMD_IS_APU; 2163 break; 2164 default: 2165 break; 2166 } 2167 2168 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2169 adev->gmc.xgmi.supported = true; 2170 2171 /* set NBIO version */ 2172 switch (adev->ip_versions[NBIO_HWIP][0]) { 2173 case IP_VERSION(6, 1, 0): 2174 case IP_VERSION(6, 2, 0): 2175 adev->nbio.funcs = &nbio_v6_1_funcs; 2176 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2177 break; 2178 case IP_VERSION(7, 0, 0): 2179 case IP_VERSION(7, 0, 1): 2180 case IP_VERSION(2, 5, 0): 2181 adev->nbio.funcs = &nbio_v7_0_funcs; 2182 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2183 break; 2184 case IP_VERSION(7, 4, 0): 2185 case IP_VERSION(7, 4, 1): 2186 adev->nbio.funcs = &nbio_v7_4_funcs; 2187 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2188 break; 2189 case IP_VERSION(7, 4, 4): 2190 adev->nbio.funcs = &nbio_v7_4_funcs; 2191 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 2192 break; 2193 case IP_VERSION(7, 2, 0): 2194 case IP_VERSION(7, 2, 1): 2195 case IP_VERSION(7, 3, 0): 2196 case IP_VERSION(7, 5, 0): 2197 case IP_VERSION(7, 5, 1): 2198 adev->nbio.funcs = &nbio_v7_2_funcs; 2199 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2200 break; 2201 case IP_VERSION(2, 1, 1): 2202 case IP_VERSION(2, 3, 0): 2203 case IP_VERSION(2, 3, 1): 2204 case IP_VERSION(2, 3, 2): 2205 adev->nbio.funcs = &nbio_v2_3_funcs; 2206 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2207 break; 2208 case IP_VERSION(3, 3, 0): 2209 case IP_VERSION(3, 3, 1): 2210 case IP_VERSION(3, 3, 2): 2211 case IP_VERSION(3, 3, 3): 2212 adev->nbio.funcs = &nbio_v2_3_funcs; 2213 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 2214 break; 2215 case IP_VERSION(4, 3, 0): 2216 case IP_VERSION(4, 3, 1): 2217 adev->nbio.funcs = &nbio_v4_3_funcs; 2218 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2219 break; 2220 case IP_VERSION(7, 7, 0): 2221 adev->nbio.funcs = &nbio_v7_7_funcs; 2222 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2223 break; 2224 default: 2225 break; 2226 } 2227 2228 switch (adev->ip_versions[HDP_HWIP][0]) { 2229 case IP_VERSION(4, 0, 0): 2230 case IP_VERSION(4, 0, 1): 2231 case IP_VERSION(4, 1, 0): 2232 case IP_VERSION(4, 1, 1): 2233 case IP_VERSION(4, 1, 2): 2234 case IP_VERSION(4, 2, 0): 2235 case IP_VERSION(4, 2, 1): 2236 case IP_VERSION(4, 4, 0): 2237 adev->hdp.funcs = &hdp_v4_0_funcs; 2238 break; 2239 case IP_VERSION(5, 0, 0): 2240 case IP_VERSION(5, 0, 1): 2241 case IP_VERSION(5, 0, 2): 2242 case IP_VERSION(5, 0, 3): 2243 case IP_VERSION(5, 0, 4): 2244 case IP_VERSION(5, 2, 0): 2245 adev->hdp.funcs = &hdp_v5_0_funcs; 2246 break; 2247 case IP_VERSION(5, 2, 1): 2248 adev->hdp.funcs = &hdp_v5_2_funcs; 2249 break; 2250 case IP_VERSION(6, 0, 0): 2251 case IP_VERSION(6, 0, 1): 2252 adev->hdp.funcs = &hdp_v6_0_funcs; 2253 break; 2254 default: 2255 break; 2256 } 2257 2258 switch (adev->ip_versions[DF_HWIP][0]) { 2259 case IP_VERSION(3, 6, 0): 2260 case IP_VERSION(3, 6, 1): 2261 case IP_VERSION(3, 6, 2): 2262 adev->df.funcs = &df_v3_6_funcs; 2263 break; 2264 case IP_VERSION(2, 1, 0): 2265 case IP_VERSION(2, 1, 1): 2266 case IP_VERSION(2, 5, 0): 2267 case IP_VERSION(3, 5, 1): 2268 case IP_VERSION(3, 5, 2): 2269 adev->df.funcs = &df_v1_7_funcs; 2270 break; 2271 default: 2272 break; 2273 } 2274 2275 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2276 case IP_VERSION(9, 0, 0): 2277 case IP_VERSION(9, 0, 1): 2278 case IP_VERSION(10, 0, 0): 2279 case IP_VERSION(10, 0, 1): 2280 case IP_VERSION(10, 0, 2): 2281 adev->smuio.funcs = &smuio_v9_0_funcs; 2282 break; 2283 case IP_VERSION(11, 0, 0): 2284 case IP_VERSION(11, 0, 2): 2285 case IP_VERSION(11, 0, 3): 2286 case IP_VERSION(11, 0, 4): 2287 case IP_VERSION(11, 0, 7): 2288 case IP_VERSION(11, 0, 8): 2289 adev->smuio.funcs = &smuio_v11_0_funcs; 2290 break; 2291 case IP_VERSION(11, 0, 6): 2292 case IP_VERSION(11, 0, 10): 2293 case IP_VERSION(11, 0, 11): 2294 case IP_VERSION(11, 5, 0): 2295 case IP_VERSION(13, 0, 1): 2296 case IP_VERSION(13, 0, 9): 2297 case IP_VERSION(13, 0, 10): 2298 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2299 break; 2300 case IP_VERSION(13, 0, 2): 2301 adev->smuio.funcs = &smuio_v13_0_funcs; 2302 break; 2303 case IP_VERSION(13, 0, 6): 2304 case IP_VERSION(13, 0, 8): 2305 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2306 break; 2307 default: 2308 break; 2309 } 2310 2311 switch (adev->ip_versions[LSDMA_HWIP][0]) { 2312 case IP_VERSION(6, 0, 0): 2313 case IP_VERSION(6, 0, 2): 2314 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2315 break; 2316 default: 2317 break; 2318 } 2319 2320 r = amdgpu_discovery_set_common_ip_blocks(adev); 2321 if (r) 2322 return r; 2323 2324 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2325 if (r) 2326 return r; 2327 2328 /* For SR-IOV, PSP needs to be initialized before IH */ 2329 if (amdgpu_sriov_vf(adev)) { 2330 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2331 if (r) 2332 return r; 2333 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2334 if (r) 2335 return r; 2336 } else { 2337 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2338 if (r) 2339 return r; 2340 2341 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2342 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2343 if (r) 2344 return r; 2345 } 2346 } 2347 2348 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2349 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2350 if (r) 2351 return r; 2352 } 2353 2354 r = amdgpu_discovery_set_display_ip_blocks(adev); 2355 if (r) 2356 return r; 2357 2358 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2359 if (r) 2360 return r; 2361 2362 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2363 if (r) 2364 return r; 2365 2366 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2367 !amdgpu_sriov_vf(adev)) || 2368 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2369 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2370 if (r) 2371 return r; 2372 } 2373 2374 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2375 if (r) 2376 return r; 2377 2378 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2379 if (r) 2380 return r; 2381 2382 return 0; 2383 } 2384 2385