1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gfxhub_v2_0.h" 51 #include "mmhub_v2_0.h" 52 #include "nbio_v2_3.h" 53 #include "nbio_v7_2.h" 54 #include "hdp_v5_0.h" 55 #include "nv.h" 56 #include "navi10_ih.h" 57 #include "gfx_v10_0.h" 58 #include "sdma_v5_0.h" 59 #include "sdma_v5_2.h" 60 #include "vcn_v2_0.h" 61 #include "jpeg_v2_0.h" 62 #include "vcn_v3_0.h" 63 #include "jpeg_v3_0.h" 64 #include "amdgpu_vkms.h" 65 #include "mes_v10_1.h" 66 #include "smuio_v11_0.h" 67 #include "smuio_v11_0_6.h" 68 #include "smuio_v13_0.h" 69 70 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 71 72 #define mmRCC_CONFIG_MEMSIZE 0xde3 73 #define mmMM_INDEX 0x0 74 #define mmMM_INDEX_HI 0x6 75 #define mmMM_DATA 0x1 76 77 static const char *hw_id_names[HW_ID_MAX] = { 78 [MP1_HWID] = "MP1", 79 [MP2_HWID] = "MP2", 80 [THM_HWID] = "THM", 81 [SMUIO_HWID] = "SMUIO", 82 [FUSE_HWID] = "FUSE", 83 [CLKA_HWID] = "CLKA", 84 [PWR_HWID] = "PWR", 85 [GC_HWID] = "GC", 86 [UVD_HWID] = "UVD", 87 [AUDIO_AZ_HWID] = "AUDIO_AZ", 88 [ACP_HWID] = "ACP", 89 [DCI_HWID] = "DCI", 90 [DMU_HWID] = "DMU", 91 [DCO_HWID] = "DCO", 92 [DIO_HWID] = "DIO", 93 [XDMA_HWID] = "XDMA", 94 [DCEAZ_HWID] = "DCEAZ", 95 [DAZ_HWID] = "DAZ", 96 [SDPMUX_HWID] = "SDPMUX", 97 [NTB_HWID] = "NTB", 98 [IOHC_HWID] = "IOHC", 99 [L2IMU_HWID] = "L2IMU", 100 [VCE_HWID] = "VCE", 101 [MMHUB_HWID] = "MMHUB", 102 [ATHUB_HWID] = "ATHUB", 103 [DBGU_NBIO_HWID] = "DBGU_NBIO", 104 [DFX_HWID] = "DFX", 105 [DBGU0_HWID] = "DBGU0", 106 [DBGU1_HWID] = "DBGU1", 107 [OSSSYS_HWID] = "OSSSYS", 108 [HDP_HWID] = "HDP", 109 [SDMA0_HWID] = "SDMA0", 110 [SDMA1_HWID] = "SDMA1", 111 [SDMA2_HWID] = "SDMA2", 112 [SDMA3_HWID] = "SDMA3", 113 [ISP_HWID] = "ISP", 114 [DBGU_IO_HWID] = "DBGU_IO", 115 [DF_HWID] = "DF", 116 [CLKB_HWID] = "CLKB", 117 [FCH_HWID] = "FCH", 118 [DFX_DAP_HWID] = "DFX_DAP", 119 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 120 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 121 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 122 [L1IMU3_HWID] = "L1IMU3", 123 [L1IMU4_HWID] = "L1IMU4", 124 [L1IMU5_HWID] = "L1IMU5", 125 [L1IMU6_HWID] = "L1IMU6", 126 [L1IMU7_HWID] = "L1IMU7", 127 [L1IMU8_HWID] = "L1IMU8", 128 [L1IMU9_HWID] = "L1IMU9", 129 [L1IMU10_HWID] = "L1IMU10", 130 [L1IMU11_HWID] = "L1IMU11", 131 [L1IMU12_HWID] = "L1IMU12", 132 [L1IMU13_HWID] = "L1IMU13", 133 [L1IMU14_HWID] = "L1IMU14", 134 [L1IMU15_HWID] = "L1IMU15", 135 [WAFLC_HWID] = "WAFLC", 136 [FCH_USB_PD_HWID] = "FCH_USB_PD", 137 [PCIE_HWID] = "PCIE", 138 [PCS_HWID] = "PCS", 139 [DDCL_HWID] = "DDCL", 140 [SST_HWID] = "SST", 141 [IOAGR_HWID] = "IOAGR", 142 [NBIF_HWID] = "NBIF", 143 [IOAPIC_HWID] = "IOAPIC", 144 [SYSTEMHUB_HWID] = "SYSTEMHUB", 145 [NTBCCP_HWID] = "NTBCCP", 146 [UMC_HWID] = "UMC", 147 [SATA_HWID] = "SATA", 148 [USB_HWID] = "USB", 149 [CCXSEC_HWID] = "CCXSEC", 150 [XGMI_HWID] = "XGMI", 151 [XGBE_HWID] = "XGBE", 152 [MP0_HWID] = "MP0", 153 }; 154 155 static int hw_id_map[MAX_HWIP] = { 156 [GC_HWIP] = GC_HWID, 157 [HDP_HWIP] = HDP_HWID, 158 [SDMA0_HWIP] = SDMA0_HWID, 159 [SDMA1_HWIP] = SDMA1_HWID, 160 [SDMA2_HWIP] = SDMA2_HWID, 161 [SDMA3_HWIP] = SDMA3_HWID, 162 [MMHUB_HWIP] = MMHUB_HWID, 163 [ATHUB_HWIP] = ATHUB_HWID, 164 [NBIO_HWIP] = NBIF_HWID, 165 [MP0_HWIP] = MP0_HWID, 166 [MP1_HWIP] = MP1_HWID, 167 [UVD_HWIP] = UVD_HWID, 168 [VCE_HWIP] = VCE_HWID, 169 [DF_HWIP] = DF_HWID, 170 [DCE_HWIP] = DMU_HWID, 171 [OSSSYS_HWIP] = OSSSYS_HWID, 172 [SMUIO_HWIP] = SMUIO_HWID, 173 [PWR_HWIP] = PWR_HWID, 174 [NBIF_HWIP] = NBIF_HWID, 175 [THM_HWIP] = THM_HWID, 176 [CLK_HWIP] = CLKA_HWID, 177 [UMC_HWIP] = UMC_HWID, 178 [XGMI_HWIP] = XGMI_HWID, 179 [DCI_HWIP] = DCI_HWID, 180 }; 181 182 static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary) 183 { 184 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 185 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 186 187 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 188 adev->mman.discovery_tmr_size, false); 189 return 0; 190 } 191 192 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 193 { 194 uint16_t checksum = 0; 195 int i; 196 197 for (i = 0; i < size; i++) 198 checksum += data[i]; 199 200 return checksum; 201 } 202 203 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 204 uint16_t expected) 205 { 206 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 207 } 208 209 static int amdgpu_discovery_init(struct amdgpu_device *adev) 210 { 211 struct table_info *info; 212 struct binary_header *bhdr; 213 struct ip_discovery_header *ihdr; 214 struct gpu_info_header *ghdr; 215 const struct firmware *fw; 216 uint16_t offset; 217 uint16_t size; 218 uint16_t checksum; 219 int r; 220 221 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 222 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 223 if (!adev->mman.discovery_bin) 224 return -ENOMEM; 225 226 if (amdgpu_discovery == 2) { 227 r = request_firmware(&fw, "amdgpu/ip_discovery.bin", adev->dev); 228 if (r) 229 goto get_from_vram; 230 dev_info(adev->dev, "Using IP discovery from file\n"); 231 memcpy((u8 *)adev->mman.discovery_bin, (u8 *)fw->data, 232 adev->mman.discovery_tmr_size); 233 release_firmware(fw); 234 } else { 235 get_from_vram: 236 r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin); 237 if (r) { 238 DRM_ERROR("failed to read ip discovery binary\n"); 239 goto out; 240 } 241 } 242 243 bhdr = (struct binary_header *)adev->mman.discovery_bin; 244 245 if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) { 246 DRM_ERROR("invalid ip discovery binary signature\n"); 247 r = -EINVAL; 248 goto out; 249 } 250 251 offset = offsetof(struct binary_header, binary_checksum) + 252 sizeof(bhdr->binary_checksum); 253 size = le16_to_cpu(bhdr->binary_size) - offset; 254 checksum = le16_to_cpu(bhdr->binary_checksum); 255 256 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 257 size, checksum)) { 258 DRM_ERROR("invalid ip discovery binary checksum\n"); 259 r = -EINVAL; 260 goto out; 261 } 262 263 info = &bhdr->table_list[IP_DISCOVERY]; 264 offset = le16_to_cpu(info->offset); 265 checksum = le16_to_cpu(info->checksum); 266 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 267 268 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 269 DRM_ERROR("invalid ip discovery data table signature\n"); 270 r = -EINVAL; 271 goto out; 272 } 273 274 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 275 le16_to_cpu(ihdr->size), checksum)) { 276 DRM_ERROR("invalid ip discovery data table checksum\n"); 277 r = -EINVAL; 278 goto out; 279 } 280 281 info = &bhdr->table_list[GC]; 282 offset = le16_to_cpu(info->offset); 283 checksum = le16_to_cpu(info->checksum); 284 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 285 286 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 287 le32_to_cpu(ghdr->size), checksum)) { 288 DRM_ERROR("invalid gc data table checksum\n"); 289 r = -EINVAL; 290 goto out; 291 } 292 293 return 0; 294 295 out: 296 kfree(adev->mman.discovery_bin); 297 adev->mman.discovery_bin = NULL; 298 299 return r; 300 } 301 302 void amdgpu_discovery_fini(struct amdgpu_device *adev) 303 { 304 kfree(adev->mman.discovery_bin); 305 adev->mman.discovery_bin = NULL; 306 } 307 308 static int amdgpu_discovery_validate_ip(const struct ip *ip) 309 { 310 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 311 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 312 ip->number_instance); 313 return -EINVAL; 314 } 315 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 316 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 317 le16_to_cpu(ip->hw_id)); 318 return -EINVAL; 319 } 320 321 return 0; 322 } 323 324 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 325 { 326 struct binary_header *bhdr; 327 struct ip_discovery_header *ihdr; 328 struct die_header *dhdr; 329 struct ip *ip; 330 uint16_t die_offset; 331 uint16_t ip_offset; 332 uint16_t num_dies; 333 uint16_t num_ips; 334 uint8_t num_base_address; 335 int hw_ip; 336 int i, j, k; 337 int r; 338 339 r = amdgpu_discovery_init(adev); 340 if (r) { 341 DRM_ERROR("amdgpu_discovery_init failed\n"); 342 return r; 343 } 344 345 bhdr = (struct binary_header *)adev->mman.discovery_bin; 346 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 347 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 348 num_dies = le16_to_cpu(ihdr->num_dies); 349 350 DRM_DEBUG("number of dies: %d\n", num_dies); 351 352 for (i = 0; i < num_dies; i++) { 353 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 354 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 355 num_ips = le16_to_cpu(dhdr->num_ips); 356 ip_offset = die_offset + sizeof(*dhdr); 357 358 if (le16_to_cpu(dhdr->die_id) != i) { 359 DRM_ERROR("invalid die id %d, expected %d\n", 360 le16_to_cpu(dhdr->die_id), i); 361 return -EINVAL; 362 } 363 364 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 365 le16_to_cpu(dhdr->die_id), num_ips); 366 367 for (j = 0; j < num_ips; j++) { 368 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 369 370 if (amdgpu_discovery_validate_ip(ip)) 371 goto next_ip; 372 373 num_base_address = ip->num_base_address; 374 375 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 376 hw_id_names[le16_to_cpu(ip->hw_id)], 377 le16_to_cpu(ip->hw_id), 378 ip->number_instance, 379 ip->major, ip->minor, 380 ip->revision); 381 382 if (le16_to_cpu(ip->hw_id) == VCN_HWID) 383 adev->vcn.num_vcn_inst++; 384 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 385 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 386 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 387 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 388 adev->sdma.num_instances++; 389 390 for (k = 0; k < num_base_address; k++) { 391 /* 392 * convert the endianness of base addresses in place, 393 * so that we don't need to convert them when accessing adev->reg_offset. 394 */ 395 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 396 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 397 } 398 399 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 400 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 401 DRM_DEBUG("set register base offset for %s\n", 402 hw_id_names[le16_to_cpu(ip->hw_id)]); 403 adev->reg_offset[hw_ip][ip->number_instance] = 404 ip->base_address; 405 /* Instance support is somewhat inconsistent. 406 * SDMA is a good example. Sienna cichlid has 4 total 407 * SDMA instances, each enumerated separately (HWIDs 408 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 409 * but they are enumerated as multiple instances of the 410 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 411 * example. On most chips there are multiple instances 412 * with the same HWID. 413 */ 414 adev->ip_versions[hw_ip][ip->number_instance] = 415 IP_VERSION(ip->major, ip->minor, ip->revision); 416 } 417 } 418 419 next_ip: 420 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 421 } 422 } 423 424 return 0; 425 } 426 427 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 428 int *major, int *minor, int *revision) 429 { 430 struct binary_header *bhdr; 431 struct ip_discovery_header *ihdr; 432 struct die_header *dhdr; 433 struct ip *ip; 434 uint16_t die_offset; 435 uint16_t ip_offset; 436 uint16_t num_dies; 437 uint16_t num_ips; 438 int i, j; 439 440 if (!adev->mman.discovery_bin) { 441 DRM_ERROR("ip discovery uninitialized\n"); 442 return -EINVAL; 443 } 444 445 bhdr = (struct binary_header *)adev->mman.discovery_bin; 446 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 447 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 448 num_dies = le16_to_cpu(ihdr->num_dies); 449 450 for (i = 0; i < num_dies; i++) { 451 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 452 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 453 num_ips = le16_to_cpu(dhdr->num_ips); 454 ip_offset = die_offset + sizeof(*dhdr); 455 456 for (j = 0; j < num_ips; j++) { 457 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 458 459 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 460 if (major) 461 *major = ip->major; 462 if (minor) 463 *minor = ip->minor; 464 if (revision) 465 *revision = ip->revision; 466 return 0; 467 } 468 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 469 } 470 } 471 472 return -EINVAL; 473 } 474 475 476 int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance, 477 int *major, int *minor, int *revision) 478 { 479 return amdgpu_discovery_get_ip_version(adev, VCN_HWID, 480 vcn_instance, major, minor, revision); 481 } 482 483 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 484 { 485 struct binary_header *bhdr; 486 struct harvest_table *harvest_info; 487 int i, vcn_harvest_count = 0; 488 489 bhdr = (struct binary_header *)adev->mman.discovery_bin; 490 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + 491 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset)); 492 493 for (i = 0; i < 32; i++) { 494 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 495 break; 496 497 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 498 case VCN_HWID: 499 vcn_harvest_count++; 500 if (harvest_info->list[i].number_instance == 0) 501 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 502 else 503 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 504 break; 505 case DMU_HWID: 506 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 507 break; 508 default: 509 break; 510 } 511 } 512 /* some IP discovery tables on Navy Flounder don't have this set correctly */ 513 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 514 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) 515 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 516 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 517 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 518 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 519 } 520 if ((adev->pdev->device == 0x731E && 521 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) || 522 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) || 523 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) { 524 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 525 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 526 } 527 } 528 529 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 530 { 531 struct binary_header *bhdr; 532 struct gc_info_v1_0 *gc_info; 533 534 if (!adev->mman.discovery_bin) { 535 DRM_ERROR("ip discovery uninitialized\n"); 536 return -EINVAL; 537 } 538 539 bhdr = (struct binary_header *)adev->mman.discovery_bin; 540 gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin + 541 le16_to_cpu(bhdr->table_list[GC].offset)); 542 543 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); 544 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + 545 le32_to_cpu(gc_info->gc_num_wgp1_per_sa)); 546 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); 547 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); 548 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); 549 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); 550 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); 551 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); 552 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); 553 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); 554 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size); 555 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd); 556 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu); 557 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size); 558 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) / 559 le32_to_cpu(gc_info->gc_num_sa_per_se); 560 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc); 561 562 return 0; 563 } 564 565 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 566 { 567 /* what IP to use for this? */ 568 switch (adev->ip_versions[GC_HWIP][0]) { 569 case IP_VERSION(9, 0, 1): 570 case IP_VERSION(9, 1, 0): 571 case IP_VERSION(9, 2, 1): 572 case IP_VERSION(9, 2, 2): 573 case IP_VERSION(9, 3, 0): 574 case IP_VERSION(9, 4, 0): 575 case IP_VERSION(9, 4, 1): 576 case IP_VERSION(9, 4, 2): 577 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 578 break; 579 case IP_VERSION(10, 1, 10): 580 case IP_VERSION(10, 1, 1): 581 case IP_VERSION(10, 1, 2): 582 case IP_VERSION(10, 1, 3): 583 case IP_VERSION(10, 3, 0): 584 case IP_VERSION(10, 3, 1): 585 case IP_VERSION(10, 3, 2): 586 case IP_VERSION(10, 3, 3): 587 case IP_VERSION(10, 3, 4): 588 case IP_VERSION(10, 3, 5): 589 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 590 break; 591 default: 592 dev_err(adev->dev, 593 "Failed to add common ip block(GC_HWIP:0x%x)\n", 594 adev->ip_versions[GC_HWIP][0]); 595 return -EINVAL; 596 } 597 return 0; 598 } 599 600 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 601 { 602 /* use GC or MMHUB IP version */ 603 switch (adev->ip_versions[GC_HWIP][0]) { 604 case IP_VERSION(9, 0, 1): 605 case IP_VERSION(9, 1, 0): 606 case IP_VERSION(9, 2, 1): 607 case IP_VERSION(9, 2, 2): 608 case IP_VERSION(9, 3, 0): 609 case IP_VERSION(9, 4, 0): 610 case IP_VERSION(9, 4, 1): 611 case IP_VERSION(9, 4, 2): 612 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 613 break; 614 case IP_VERSION(10, 1, 10): 615 case IP_VERSION(10, 1, 1): 616 case IP_VERSION(10, 1, 2): 617 case IP_VERSION(10, 1, 3): 618 case IP_VERSION(10, 3, 0): 619 case IP_VERSION(10, 3, 1): 620 case IP_VERSION(10, 3, 2): 621 case IP_VERSION(10, 3, 3): 622 case IP_VERSION(10, 3, 4): 623 case IP_VERSION(10, 3, 5): 624 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 625 break; 626 default: 627 dev_err(adev->dev, 628 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 629 adev->ip_versions[GC_HWIP][0]); 630 return -EINVAL; 631 } 632 return 0; 633 } 634 635 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 636 { 637 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 638 case IP_VERSION(4, 0, 0): 639 case IP_VERSION(4, 0, 1): 640 case IP_VERSION(4, 1, 0): 641 case IP_VERSION(4, 1, 1): 642 case IP_VERSION(4, 3, 0): 643 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 644 break; 645 case IP_VERSION(4, 2, 0): 646 case IP_VERSION(4, 2, 1): 647 case IP_VERSION(4, 4, 0): 648 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 649 break; 650 case IP_VERSION(5, 0, 0): 651 case IP_VERSION(5, 0, 1): 652 case IP_VERSION(5, 0, 2): 653 case IP_VERSION(5, 0, 3): 654 case IP_VERSION(5, 2, 0): 655 case IP_VERSION(5, 2, 1): 656 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 657 break; 658 default: 659 dev_err(adev->dev, 660 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 661 adev->ip_versions[OSSSYS_HWIP][0]); 662 return -EINVAL; 663 } 664 return 0; 665 } 666 667 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 668 { 669 switch (adev->ip_versions[MP0_HWIP][0]) { 670 case IP_VERSION(9, 0, 0): 671 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 672 break; 673 case IP_VERSION(10, 0, 0): 674 case IP_VERSION(10, 0, 1): 675 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 676 break; 677 case IP_VERSION(11, 0, 0): 678 case IP_VERSION(11, 0, 2): 679 case IP_VERSION(11, 0, 4): 680 case IP_VERSION(11, 0, 5): 681 case IP_VERSION(11, 0, 9): 682 case IP_VERSION(11, 0, 7): 683 case IP_VERSION(11, 0, 11): 684 case IP_VERSION(11, 0, 12): 685 case IP_VERSION(11, 0, 13): 686 case IP_VERSION(11, 5, 0): 687 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 688 break; 689 case IP_VERSION(11, 0, 8): 690 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 691 break; 692 case IP_VERSION(11, 0, 3): 693 case IP_VERSION(12, 0, 1): 694 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 695 break; 696 case IP_VERSION(13, 0, 1): 697 case IP_VERSION(13, 0, 2): 698 case IP_VERSION(13, 0, 3): 699 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 700 break; 701 default: 702 dev_err(adev->dev, 703 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 704 adev->ip_versions[MP0_HWIP][0]); 705 return -EINVAL; 706 } 707 return 0; 708 } 709 710 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 711 { 712 switch (adev->ip_versions[MP1_HWIP][0]) { 713 case IP_VERSION(9, 0, 0): 714 case IP_VERSION(10, 0, 0): 715 case IP_VERSION(10, 0, 1): 716 case IP_VERSION(11, 0, 2): 717 if (adev->asic_type == CHIP_ARCTURUS) 718 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 719 else 720 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 721 break; 722 case IP_VERSION(11, 0, 0): 723 case IP_VERSION(11, 0, 5): 724 case IP_VERSION(11, 0, 9): 725 case IP_VERSION(11, 0, 7): 726 case IP_VERSION(11, 0, 8): 727 case IP_VERSION(11, 0, 11): 728 case IP_VERSION(11, 0, 12): 729 case IP_VERSION(11, 0, 13): 730 case IP_VERSION(11, 5, 0): 731 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 732 break; 733 case IP_VERSION(12, 0, 0): 734 case IP_VERSION(12, 0, 1): 735 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 736 break; 737 case IP_VERSION(13, 0, 1): 738 case IP_VERSION(13, 0, 2): 739 case IP_VERSION(13, 0, 3): 740 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 741 break; 742 default: 743 dev_err(adev->dev, 744 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 745 adev->ip_versions[MP1_HWIP][0]); 746 return -EINVAL; 747 } 748 return 0; 749 } 750 751 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 752 { 753 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 754 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 755 #if defined(CONFIG_DRM_AMD_DC) 756 } else if (adev->ip_versions[DCE_HWIP][0]) { 757 switch (adev->ip_versions[DCE_HWIP][0]) { 758 case IP_VERSION(1, 0, 0): 759 case IP_VERSION(1, 0, 1): 760 case IP_VERSION(2, 0, 2): 761 case IP_VERSION(2, 0, 0): 762 case IP_VERSION(2, 0, 3): 763 case IP_VERSION(2, 1, 0): 764 case IP_VERSION(3, 0, 0): 765 case IP_VERSION(3, 0, 2): 766 case IP_VERSION(3, 0, 3): 767 case IP_VERSION(3, 0, 1): 768 case IP_VERSION(3, 1, 2): 769 case IP_VERSION(3, 1, 3): 770 amdgpu_device_ip_block_add(adev, &dm_ip_block); 771 break; 772 default: 773 dev_err(adev->dev, 774 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 775 adev->ip_versions[DCE_HWIP][0]); 776 return -EINVAL; 777 } 778 } else if (adev->ip_versions[DCI_HWIP][0]) { 779 switch (adev->ip_versions[DCI_HWIP][0]) { 780 case IP_VERSION(12, 0, 0): 781 case IP_VERSION(12, 0, 1): 782 case IP_VERSION(12, 1, 0): 783 amdgpu_device_ip_block_add(adev, &dm_ip_block); 784 break; 785 default: 786 dev_err(adev->dev, 787 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 788 adev->ip_versions[DCI_HWIP][0]); 789 return -EINVAL; 790 } 791 #endif 792 } 793 return 0; 794 } 795 796 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 797 { 798 switch (adev->ip_versions[GC_HWIP][0]) { 799 case IP_VERSION(9, 0, 1): 800 case IP_VERSION(9, 1, 0): 801 case IP_VERSION(9, 2, 1): 802 case IP_VERSION(9, 2, 2): 803 case IP_VERSION(9, 3, 0): 804 case IP_VERSION(9, 4, 0): 805 case IP_VERSION(9, 4, 1): 806 case IP_VERSION(9, 4, 2): 807 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 808 break; 809 case IP_VERSION(10, 1, 10): 810 case IP_VERSION(10, 1, 2): 811 case IP_VERSION(10, 1, 1): 812 case IP_VERSION(10, 1, 3): 813 case IP_VERSION(10, 3, 0): 814 case IP_VERSION(10, 3, 2): 815 case IP_VERSION(10, 3, 1): 816 case IP_VERSION(10, 3, 4): 817 case IP_VERSION(10, 3, 5): 818 case IP_VERSION(10, 3, 3): 819 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 820 break; 821 default: 822 dev_err(adev->dev, 823 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 824 adev->ip_versions[GC_HWIP][0]); 825 return -EINVAL; 826 } 827 return 0; 828 } 829 830 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 831 { 832 switch (adev->ip_versions[SDMA0_HWIP][0]) { 833 case IP_VERSION(4, 0, 0): 834 case IP_VERSION(4, 0, 1): 835 case IP_VERSION(4, 1, 0): 836 case IP_VERSION(4, 1, 1): 837 case IP_VERSION(4, 1, 2): 838 case IP_VERSION(4, 2, 0): 839 case IP_VERSION(4, 2, 2): 840 case IP_VERSION(4, 4, 0): 841 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 842 break; 843 case IP_VERSION(5, 0, 0): 844 case IP_VERSION(5, 0, 1): 845 case IP_VERSION(5, 0, 2): 846 case IP_VERSION(5, 0, 5): 847 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 848 break; 849 case IP_VERSION(5, 2, 0): 850 case IP_VERSION(5, 2, 2): 851 case IP_VERSION(5, 2, 4): 852 case IP_VERSION(5, 2, 5): 853 case IP_VERSION(5, 2, 3): 854 case IP_VERSION(5, 2, 1): 855 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 856 break; 857 default: 858 dev_err(adev->dev, 859 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 860 adev->ip_versions[SDMA0_HWIP][0]); 861 return -EINVAL; 862 } 863 return 0; 864 } 865 866 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 867 { 868 if (adev->ip_versions[VCE_HWIP][0]) { 869 switch (adev->ip_versions[UVD_HWIP][0]) { 870 case IP_VERSION(7, 0, 0): 871 case IP_VERSION(7, 2, 0): 872 /* UVD is not supported on vega20 SR-IOV */ 873 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 874 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 875 break; 876 default: 877 dev_err(adev->dev, 878 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 879 adev->ip_versions[UVD_HWIP][0]); 880 return -EINVAL; 881 } 882 switch (adev->ip_versions[VCE_HWIP][0]) { 883 case IP_VERSION(4, 0, 0): 884 case IP_VERSION(4, 1, 0): 885 /* VCE is not supported on vega20 SR-IOV */ 886 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 887 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 888 break; 889 default: 890 dev_err(adev->dev, 891 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 892 adev->ip_versions[VCE_HWIP][0]); 893 return -EINVAL; 894 } 895 } else { 896 switch (adev->ip_versions[UVD_HWIP][0]) { 897 case IP_VERSION(1, 0, 0): 898 case IP_VERSION(1, 0, 1): 899 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 900 break; 901 case IP_VERSION(2, 0, 0): 902 case IP_VERSION(2, 0, 2): 903 case IP_VERSION(2, 2, 0): 904 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 905 if (!amdgpu_sriov_vf(adev)) 906 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 907 break; 908 case IP_VERSION(2, 0, 3): 909 break; 910 case IP_VERSION(2, 5, 0): 911 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 912 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 913 break; 914 case IP_VERSION(2, 6, 0): 915 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 916 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 917 break; 918 case IP_VERSION(3, 0, 0): 919 case IP_VERSION(3, 0, 16): 920 case IP_VERSION(3, 0, 64): 921 case IP_VERSION(3, 1, 1): 922 case IP_VERSION(3, 0, 2): 923 case IP_VERSION(3, 0, 192): 924 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 925 if (!amdgpu_sriov_vf(adev)) 926 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 927 break; 928 case IP_VERSION(3, 0, 33): 929 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 930 break; 931 default: 932 dev_err(adev->dev, 933 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 934 adev->ip_versions[UVD_HWIP][0]); 935 return -EINVAL; 936 } 937 } 938 return 0; 939 } 940 941 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 942 { 943 switch (adev->ip_versions[GC_HWIP][0]) { 944 case IP_VERSION(10, 1, 10): 945 case IP_VERSION(10, 1, 1): 946 case IP_VERSION(10, 1, 2): 947 case IP_VERSION(10, 1, 3): 948 case IP_VERSION(10, 3, 0): 949 case IP_VERSION(10, 3, 1): 950 case IP_VERSION(10, 3, 2): 951 case IP_VERSION(10, 3, 3): 952 case IP_VERSION(10, 3, 4): 953 case IP_VERSION(10, 3, 5): 954 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 955 break; 956 default: 957 break;; 958 } 959 return 0; 960 } 961 962 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 963 { 964 int r; 965 966 switch (adev->asic_type) { 967 case CHIP_VEGA10: 968 vega10_reg_base_init(adev); 969 adev->sdma.num_instances = 2; 970 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 971 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 972 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 973 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 974 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 975 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 976 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 977 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 978 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 979 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 980 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 981 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 982 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 983 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 984 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 985 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 986 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 987 break; 988 case CHIP_VEGA12: 989 vega10_reg_base_init(adev); 990 adev->sdma.num_instances = 2; 991 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 992 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 993 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 994 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 995 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 996 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 997 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 998 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 999 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1000 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1001 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1002 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1003 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1004 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1005 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1006 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1007 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1008 break; 1009 case CHIP_RAVEN: 1010 vega10_reg_base_init(adev); 1011 adev->sdma.num_instances = 1; 1012 adev->vcn.num_vcn_inst = 1; 1013 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1014 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1015 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1016 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1017 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1018 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1019 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1020 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1021 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1022 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1023 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1024 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1025 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1026 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1027 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1028 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1029 } else { 1030 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1031 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1032 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1033 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1034 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1035 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1036 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1037 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1038 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1039 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1040 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1041 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1042 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1043 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1044 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1045 } 1046 break; 1047 case CHIP_VEGA20: 1048 vega20_reg_base_init(adev); 1049 adev->sdma.num_instances = 2; 1050 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1051 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1052 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1053 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1054 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1055 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1056 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1057 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1058 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 1059 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 1060 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1061 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 1062 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 1063 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 1064 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 1065 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 1066 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 1067 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 1068 break; 1069 case CHIP_ARCTURUS: 1070 arct_reg_base_init(adev); 1071 adev->sdma.num_instances = 8; 1072 adev->vcn.num_vcn_inst = 2; 1073 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1074 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1075 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 1076 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 1077 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 1078 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 1079 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 1080 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 1081 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 1082 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 1083 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 1084 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 1085 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 1086 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 1087 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 1088 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 1089 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1090 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 1091 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 1092 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 1093 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 1094 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 1095 break; 1096 case CHIP_ALDEBARAN: 1097 aldebaran_reg_base_init(adev); 1098 adev->sdma.num_instances = 5; 1099 adev->vcn.num_vcn_inst = 2; 1100 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1101 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1102 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 1103 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 1104 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 1105 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 1106 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 1107 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 1108 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 1109 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 1110 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 1111 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 1112 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 1113 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 1114 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 1115 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 1116 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 1117 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 1118 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 1119 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 1120 break; 1121 default: 1122 r = amdgpu_discovery_reg_base_init(adev); 1123 if (r) 1124 return -EINVAL; 1125 1126 amdgpu_discovery_harvest_ip(adev); 1127 1128 if (!adev->mman.discovery_bin) { 1129 DRM_ERROR("ip discovery uninitialized\n"); 1130 return -EINVAL; 1131 } 1132 break; 1133 } 1134 1135 switch (adev->ip_versions[GC_HWIP][0]) { 1136 case IP_VERSION(9, 0, 1): 1137 case IP_VERSION(9, 2, 1): 1138 case IP_VERSION(9, 4, 0): 1139 case IP_VERSION(9, 4, 1): 1140 case IP_VERSION(9, 4, 2): 1141 adev->family = AMDGPU_FAMILY_AI; 1142 break; 1143 case IP_VERSION(9, 1, 0): 1144 case IP_VERSION(9, 2, 2): 1145 case IP_VERSION(9, 3, 0): 1146 adev->family = AMDGPU_FAMILY_RV; 1147 break; 1148 case IP_VERSION(10, 1, 10): 1149 case IP_VERSION(10, 1, 1): 1150 case IP_VERSION(10, 1, 2): 1151 case IP_VERSION(10, 1, 3): 1152 case IP_VERSION(10, 3, 0): 1153 case IP_VERSION(10, 3, 2): 1154 case IP_VERSION(10, 3, 4): 1155 case IP_VERSION(10, 3, 5): 1156 adev->family = AMDGPU_FAMILY_NV; 1157 break; 1158 case IP_VERSION(10, 3, 1): 1159 adev->family = AMDGPU_FAMILY_VGH; 1160 break; 1161 case IP_VERSION(10, 3, 3): 1162 adev->family = AMDGPU_FAMILY_YC; 1163 break; 1164 default: 1165 return -EINVAL; 1166 } 1167 1168 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 1169 adev->gmc.xgmi.supported = true; 1170 1171 /* set NBIO version */ 1172 switch (adev->ip_versions[NBIO_HWIP][0]) { 1173 case IP_VERSION(6, 1, 0): 1174 case IP_VERSION(6, 2, 0): 1175 adev->nbio.funcs = &nbio_v6_1_funcs; 1176 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 1177 break; 1178 case IP_VERSION(7, 0, 0): 1179 case IP_VERSION(7, 0, 1): 1180 case IP_VERSION(2, 5, 0): 1181 adev->nbio.funcs = &nbio_v7_0_funcs; 1182 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 1183 break; 1184 case IP_VERSION(7, 4, 0): 1185 case IP_VERSION(7, 4, 1): 1186 adev->nbio.funcs = &nbio_v7_4_funcs; 1187 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 1188 break; 1189 case IP_VERSION(7, 4, 4): 1190 adev->nbio.funcs = &nbio_v7_4_funcs; 1191 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 1192 break; 1193 case IP_VERSION(7, 2, 0): 1194 case IP_VERSION(7, 2, 1): 1195 case IP_VERSION(7, 5, 0): 1196 adev->nbio.funcs = &nbio_v7_2_funcs; 1197 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 1198 break; 1199 case IP_VERSION(2, 1, 1): 1200 case IP_VERSION(2, 3, 0): 1201 case IP_VERSION(2, 3, 1): 1202 case IP_VERSION(2, 3, 2): 1203 adev->nbio.funcs = &nbio_v2_3_funcs; 1204 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 1205 break; 1206 case IP_VERSION(3, 3, 0): 1207 case IP_VERSION(3, 3, 1): 1208 case IP_VERSION(3, 3, 2): 1209 case IP_VERSION(3, 3, 3): 1210 adev->nbio.funcs = &nbio_v2_3_funcs; 1211 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 1212 break; 1213 default: 1214 break; 1215 } 1216 1217 switch (adev->ip_versions[HDP_HWIP][0]) { 1218 case IP_VERSION(4, 0, 0): 1219 case IP_VERSION(4, 0, 1): 1220 case IP_VERSION(4, 1, 0): 1221 case IP_VERSION(4, 1, 1): 1222 case IP_VERSION(4, 1, 2): 1223 case IP_VERSION(4, 2, 0): 1224 case IP_VERSION(4, 2, 1): 1225 case IP_VERSION(4, 4, 0): 1226 adev->hdp.funcs = &hdp_v4_0_funcs; 1227 break; 1228 case IP_VERSION(5, 0, 0): 1229 case IP_VERSION(5, 0, 1): 1230 case IP_VERSION(5, 0, 2): 1231 case IP_VERSION(5, 0, 3): 1232 case IP_VERSION(5, 0, 4): 1233 case IP_VERSION(5, 2, 0): 1234 adev->hdp.funcs = &hdp_v5_0_funcs; 1235 break; 1236 default: 1237 break; 1238 } 1239 1240 switch (adev->ip_versions[DF_HWIP][0]) { 1241 case IP_VERSION(3, 6, 0): 1242 case IP_VERSION(3, 6, 1): 1243 case IP_VERSION(3, 6, 2): 1244 adev->df.funcs = &df_v3_6_funcs; 1245 break; 1246 case IP_VERSION(2, 1, 0): 1247 case IP_VERSION(2, 1, 1): 1248 case IP_VERSION(2, 5, 0): 1249 case IP_VERSION(3, 5, 1): 1250 case IP_VERSION(3, 5, 2): 1251 adev->df.funcs = &df_v1_7_funcs; 1252 break; 1253 default: 1254 break; 1255 } 1256 1257 switch (adev->ip_versions[SMUIO_HWIP][0]) { 1258 case IP_VERSION(9, 0, 0): 1259 case IP_VERSION(9, 0, 1): 1260 case IP_VERSION(10, 0, 0): 1261 case IP_VERSION(10, 0, 1): 1262 case IP_VERSION(10, 0, 2): 1263 adev->smuio.funcs = &smuio_v9_0_funcs; 1264 break; 1265 case IP_VERSION(11, 0, 0): 1266 case IP_VERSION(11, 0, 2): 1267 case IP_VERSION(11, 0, 3): 1268 case IP_VERSION(11, 0, 4): 1269 case IP_VERSION(11, 0, 7): 1270 case IP_VERSION(11, 0, 8): 1271 adev->smuio.funcs = &smuio_v11_0_funcs; 1272 break; 1273 case IP_VERSION(11, 0, 6): 1274 case IP_VERSION(11, 0, 10): 1275 case IP_VERSION(11, 0, 11): 1276 case IP_VERSION(11, 5, 0): 1277 case IP_VERSION(13, 0, 1): 1278 adev->smuio.funcs = &smuio_v11_0_6_funcs; 1279 break; 1280 case IP_VERSION(13, 0, 2): 1281 adev->smuio.funcs = &smuio_v13_0_funcs; 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 r = amdgpu_discovery_set_common_ip_blocks(adev); 1288 if (r) 1289 return r; 1290 1291 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 1292 if (r) 1293 return r; 1294 1295 /* For SR-IOV, PSP needs to be initialized before IH */ 1296 if (amdgpu_sriov_vf(adev)) { 1297 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1298 if (r) 1299 return r; 1300 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1301 if (r) 1302 return r; 1303 } else { 1304 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1305 if (r) 1306 return r; 1307 1308 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1309 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1310 if (r) 1311 return r; 1312 } 1313 } 1314 1315 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1316 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1317 if (r) 1318 return r; 1319 } 1320 1321 r = amdgpu_discovery_set_display_ip_blocks(adev); 1322 if (r) 1323 return r; 1324 1325 r = amdgpu_discovery_set_gc_ip_blocks(adev); 1326 if (r) 1327 return r; 1328 1329 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 1330 if (r) 1331 return r; 1332 1333 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 1334 !amdgpu_sriov_vf(adev)) { 1335 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1336 if (r) 1337 return r; 1338 } 1339 1340 r = amdgpu_discovery_set_mm_ip_blocks(adev); 1341 if (r) 1342 return r; 1343 1344 if (adev->enable_mes) { 1345 r = amdgpu_discovery_set_mes_ip_blocks(adev); 1346 if (r) 1347 return r; 1348 } 1349 1350 return 0; 1351 } 1352 1353