1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gfxhub_v2_0.h" 51 #include "mmhub_v2_0.h" 52 #include "nbio_v2_3.h" 53 #include "nbio_v4_3.h" 54 #include "nbio_v7_2.h" 55 #include "hdp_v5_0.h" 56 #include "hdp_v6_0.h" 57 #include "nv.h" 58 #include "soc21.h" 59 #include "navi10_ih.h" 60 #include "ih_v6_0.h" 61 #include "gfx_v10_0.h" 62 #include "sdma_v5_0.h" 63 #include "sdma_v5_2.h" 64 #include "vcn_v2_0.h" 65 #include "jpeg_v2_0.h" 66 #include "vcn_v3_0.h" 67 #include "jpeg_v3_0.h" 68 #include "amdgpu_vkms.h" 69 #include "mes_v10_1.h" 70 #include "smuio_v11_0.h" 71 #include "smuio_v11_0_6.h" 72 #include "smuio_v13_0.h" 73 #include "smuio_v13_0_6.h" 74 75 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 76 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 77 78 #define mmRCC_CONFIG_MEMSIZE 0xde3 79 #define mmMM_INDEX 0x0 80 #define mmMM_INDEX_HI 0x6 81 #define mmMM_DATA 0x1 82 83 static const char *hw_id_names[HW_ID_MAX] = { 84 [MP1_HWID] = "MP1", 85 [MP2_HWID] = "MP2", 86 [THM_HWID] = "THM", 87 [SMUIO_HWID] = "SMUIO", 88 [FUSE_HWID] = "FUSE", 89 [CLKA_HWID] = "CLKA", 90 [PWR_HWID] = "PWR", 91 [GC_HWID] = "GC", 92 [UVD_HWID] = "UVD", 93 [AUDIO_AZ_HWID] = "AUDIO_AZ", 94 [ACP_HWID] = "ACP", 95 [DCI_HWID] = "DCI", 96 [DMU_HWID] = "DMU", 97 [DCO_HWID] = "DCO", 98 [DIO_HWID] = "DIO", 99 [XDMA_HWID] = "XDMA", 100 [DCEAZ_HWID] = "DCEAZ", 101 [DAZ_HWID] = "DAZ", 102 [SDPMUX_HWID] = "SDPMUX", 103 [NTB_HWID] = "NTB", 104 [IOHC_HWID] = "IOHC", 105 [L2IMU_HWID] = "L2IMU", 106 [VCE_HWID] = "VCE", 107 [MMHUB_HWID] = "MMHUB", 108 [ATHUB_HWID] = "ATHUB", 109 [DBGU_NBIO_HWID] = "DBGU_NBIO", 110 [DFX_HWID] = "DFX", 111 [DBGU0_HWID] = "DBGU0", 112 [DBGU1_HWID] = "DBGU1", 113 [OSSSYS_HWID] = "OSSSYS", 114 [HDP_HWID] = "HDP", 115 [SDMA0_HWID] = "SDMA0", 116 [SDMA1_HWID] = "SDMA1", 117 [SDMA2_HWID] = "SDMA2", 118 [SDMA3_HWID] = "SDMA3", 119 [ISP_HWID] = "ISP", 120 [DBGU_IO_HWID] = "DBGU_IO", 121 [DF_HWID] = "DF", 122 [CLKB_HWID] = "CLKB", 123 [FCH_HWID] = "FCH", 124 [DFX_DAP_HWID] = "DFX_DAP", 125 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 126 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 127 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 128 [L1IMU3_HWID] = "L1IMU3", 129 [L1IMU4_HWID] = "L1IMU4", 130 [L1IMU5_HWID] = "L1IMU5", 131 [L1IMU6_HWID] = "L1IMU6", 132 [L1IMU7_HWID] = "L1IMU7", 133 [L1IMU8_HWID] = "L1IMU8", 134 [L1IMU9_HWID] = "L1IMU9", 135 [L1IMU10_HWID] = "L1IMU10", 136 [L1IMU11_HWID] = "L1IMU11", 137 [L1IMU12_HWID] = "L1IMU12", 138 [L1IMU13_HWID] = "L1IMU13", 139 [L1IMU14_HWID] = "L1IMU14", 140 [L1IMU15_HWID] = "L1IMU15", 141 [WAFLC_HWID] = "WAFLC", 142 [FCH_USB_PD_HWID] = "FCH_USB_PD", 143 [PCIE_HWID] = "PCIE", 144 [PCS_HWID] = "PCS", 145 [DDCL_HWID] = "DDCL", 146 [SST_HWID] = "SST", 147 [IOAGR_HWID] = "IOAGR", 148 [NBIF_HWID] = "NBIF", 149 [IOAPIC_HWID] = "IOAPIC", 150 [SYSTEMHUB_HWID] = "SYSTEMHUB", 151 [NTBCCP_HWID] = "NTBCCP", 152 [UMC_HWID] = "UMC", 153 [SATA_HWID] = "SATA", 154 [USB_HWID] = "USB", 155 [CCXSEC_HWID] = "CCXSEC", 156 [XGMI_HWID] = "XGMI", 157 [XGBE_HWID] = "XGBE", 158 [MP0_HWID] = "MP0", 159 }; 160 161 static int hw_id_map[MAX_HWIP] = { 162 [GC_HWIP] = GC_HWID, 163 [HDP_HWIP] = HDP_HWID, 164 [SDMA0_HWIP] = SDMA0_HWID, 165 [SDMA1_HWIP] = SDMA1_HWID, 166 [SDMA2_HWIP] = SDMA2_HWID, 167 [SDMA3_HWIP] = SDMA3_HWID, 168 [MMHUB_HWIP] = MMHUB_HWID, 169 [ATHUB_HWIP] = ATHUB_HWID, 170 [NBIO_HWIP] = NBIF_HWID, 171 [MP0_HWIP] = MP0_HWID, 172 [MP1_HWIP] = MP1_HWID, 173 [UVD_HWIP] = UVD_HWID, 174 [VCE_HWIP] = VCE_HWID, 175 [DF_HWIP] = DF_HWID, 176 [DCE_HWIP] = DMU_HWID, 177 [OSSSYS_HWIP] = OSSSYS_HWID, 178 [SMUIO_HWIP] = SMUIO_HWID, 179 [PWR_HWIP] = PWR_HWID, 180 [NBIF_HWIP] = NBIF_HWID, 181 [THM_HWIP] = THM_HWID, 182 [CLK_HWIP] = CLKA_HWID, 183 [UMC_HWIP] = UMC_HWID, 184 [XGMI_HWIP] = XGMI_HWID, 185 [DCI_HWIP] = DCI_HWID, 186 }; 187 188 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 189 { 190 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 191 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 192 193 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 194 adev->mman.discovery_tmr_size, false); 195 return 0; 196 } 197 198 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 199 { 200 const struct firmware *fw; 201 const char *fw_name; 202 int r; 203 204 switch (amdgpu_discovery) { 205 case 2: 206 fw_name = FIRMWARE_IP_DISCOVERY; 207 break; 208 default: 209 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 210 return -EINVAL; 211 } 212 213 r = request_firmware(&fw, fw_name, adev->dev); 214 if (r) { 215 dev_err(adev->dev, "can't load firmware \"%s\"\n", 216 fw_name); 217 return r; 218 } 219 220 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 221 release_firmware(fw); 222 223 return 0; 224 } 225 226 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 227 { 228 uint16_t checksum = 0; 229 int i; 230 231 for (i = 0; i < size; i++) 232 checksum += data[i]; 233 234 return checksum; 235 } 236 237 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 238 uint16_t expected) 239 { 240 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 241 } 242 243 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 244 { 245 struct binary_header *bhdr; 246 bhdr = (struct binary_header *)binary; 247 248 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 249 } 250 251 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 252 { 253 /* 254 * So far, apply this quirk only on those Navy Flounder boards which 255 * have a bad harvest table of VCN config. 256 */ 257 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 258 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 259 switch (adev->pdev->revision) { 260 case 0xC1: 261 case 0xC2: 262 case 0xC3: 263 case 0xC5: 264 case 0xC7: 265 case 0xCF: 266 case 0xDF: 267 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 268 break; 269 default: 270 break; 271 } 272 } 273 } 274 275 static int amdgpu_discovery_init(struct amdgpu_device *adev) 276 { 277 struct table_info *info; 278 struct binary_header *bhdr; 279 uint16_t offset; 280 uint16_t size; 281 uint16_t checksum; 282 int r; 283 284 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 285 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 286 if (!adev->mman.discovery_bin) 287 return -ENOMEM; 288 289 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 290 if (r) { 291 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 292 r = -EINVAL; 293 goto out; 294 } 295 296 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 297 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 298 /* retry read ip discovery binary from file */ 299 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 300 if (r) { 301 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 302 r = -EINVAL; 303 goto out; 304 } 305 /* check the ip discovery binary signature */ 306 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 307 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 308 r = -EINVAL; 309 goto out; 310 } 311 } 312 313 bhdr = (struct binary_header *)adev->mman.discovery_bin; 314 315 offset = offsetof(struct binary_header, binary_checksum) + 316 sizeof(bhdr->binary_checksum); 317 size = le16_to_cpu(bhdr->binary_size) - offset; 318 checksum = le16_to_cpu(bhdr->binary_checksum); 319 320 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 321 size, checksum)) { 322 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 323 r = -EINVAL; 324 goto out; 325 } 326 327 info = &bhdr->table_list[IP_DISCOVERY]; 328 offset = le16_to_cpu(info->offset); 329 checksum = le16_to_cpu(info->checksum); 330 331 if (offset) { 332 struct ip_discovery_header *ihdr = 333 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 334 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 335 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 336 r = -EINVAL; 337 goto out; 338 } 339 340 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 341 le16_to_cpu(ihdr->size), checksum)) { 342 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 343 r = -EINVAL; 344 goto out; 345 } 346 } 347 348 info = &bhdr->table_list[GC]; 349 offset = le16_to_cpu(info->offset); 350 checksum = le16_to_cpu(info->checksum); 351 352 if (offset) { 353 struct gpu_info_header *ghdr = 354 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 355 356 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 357 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 358 r = -EINVAL; 359 goto out; 360 } 361 362 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 363 le32_to_cpu(ghdr->size), checksum)) { 364 dev_err(adev->dev, "invalid gc data table checksum\n"); 365 r = -EINVAL; 366 goto out; 367 } 368 } 369 370 info = &bhdr->table_list[HARVEST_INFO]; 371 offset = le16_to_cpu(info->offset); 372 checksum = le16_to_cpu(info->checksum); 373 374 if (offset) { 375 struct harvest_info_header *hhdr = 376 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 377 378 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 379 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 380 r = -EINVAL; 381 goto out; 382 } 383 384 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 385 sizeof(struct harvest_table), checksum)) { 386 dev_err(adev->dev, "invalid harvest data table checksum\n"); 387 r = -EINVAL; 388 goto out; 389 } 390 } 391 392 info = &bhdr->table_list[VCN_INFO]; 393 offset = le16_to_cpu(info->offset); 394 checksum = le16_to_cpu(info->checksum); 395 396 if (offset) { 397 struct vcn_info_header *vhdr = 398 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 399 400 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 401 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 402 r = -EINVAL; 403 goto out; 404 } 405 406 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 407 le32_to_cpu(vhdr->size_bytes), checksum)) { 408 dev_err(adev->dev, "invalid vcn data table checksum\n"); 409 r = -EINVAL; 410 goto out; 411 } 412 } 413 414 info = &bhdr->table_list[MALL_INFO]; 415 offset = le16_to_cpu(info->offset); 416 checksum = le16_to_cpu(info->checksum); 417 418 if (0 && offset) { 419 struct mall_info_header *mhdr = 420 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 421 422 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 423 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 424 r = -EINVAL; 425 goto out; 426 } 427 428 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 429 le32_to_cpu(mhdr->size_bytes), checksum)) { 430 dev_err(adev->dev, "invalid mall data table checksum\n"); 431 r = -EINVAL; 432 goto out; 433 } 434 } 435 436 return 0; 437 438 out: 439 kfree(adev->mman.discovery_bin); 440 adev->mman.discovery_bin = NULL; 441 442 return r; 443 } 444 445 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 446 447 void amdgpu_discovery_fini(struct amdgpu_device *adev) 448 { 449 amdgpu_discovery_sysfs_fini(adev); 450 kfree(adev->mman.discovery_bin); 451 adev->mman.discovery_bin = NULL; 452 } 453 454 static int amdgpu_discovery_validate_ip(const struct ip *ip) 455 { 456 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 457 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 458 ip->number_instance); 459 return -EINVAL; 460 } 461 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 462 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 463 le16_to_cpu(ip->hw_id)); 464 return -EINVAL; 465 } 466 467 return 0; 468 } 469 470 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 471 uint32_t *vcn_harvest_count) 472 { 473 struct binary_header *bhdr; 474 struct ip_discovery_header *ihdr; 475 struct die_header *dhdr; 476 struct ip *ip; 477 uint16_t die_offset, ip_offset, num_dies, num_ips; 478 int i, j; 479 480 bhdr = (struct binary_header *)adev->mman.discovery_bin; 481 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 482 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 483 num_dies = le16_to_cpu(ihdr->num_dies); 484 485 /* scan harvest bit of all IP data structures */ 486 for (i = 0; i < num_dies; i++) { 487 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 488 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 489 num_ips = le16_to_cpu(dhdr->num_ips); 490 ip_offset = die_offset + sizeof(*dhdr); 491 492 for (j = 0; j < num_ips; j++) { 493 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 494 495 if (amdgpu_discovery_validate_ip(ip)) 496 goto next_ip; 497 498 if (le16_to_cpu(ip->harvest) == 1) { 499 switch (le16_to_cpu(ip->hw_id)) { 500 case VCN_HWID: 501 (*vcn_harvest_count)++; 502 if (ip->number_instance == 0) 503 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 504 else 505 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 506 break; 507 case DMU_HWID: 508 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 509 break; 510 default: 511 break; 512 } 513 } 514 next_ip: 515 ip_offset += struct_size(ip, base_address, ip->num_base_address); 516 } 517 } 518 } 519 520 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 521 uint32_t *vcn_harvest_count, 522 uint32_t *umc_harvest_count) 523 { 524 struct binary_header *bhdr; 525 struct harvest_table *harvest_info; 526 u16 offset; 527 int i; 528 529 bhdr = (struct binary_header *)adev->mman.discovery_bin; 530 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 531 532 if (!offset) { 533 dev_err(adev->dev, "invalid harvest table offset\n"); 534 return; 535 } 536 537 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 538 539 for (i = 0; i < 32; i++) { 540 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 541 break; 542 543 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 544 case VCN_HWID: 545 (*vcn_harvest_count)++; 546 if (harvest_info->list[i].number_instance == 0) 547 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 548 else 549 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 550 break; 551 case DMU_HWID: 552 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 553 break; 554 case UMC_HWID: 555 (*umc_harvest_count)++; 556 break; 557 default: 558 break; 559 } 560 } 561 } 562 563 /* ================================================== */ 564 565 struct ip_hw_instance { 566 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 567 568 int hw_id; 569 u8 num_instance; 570 u8 major, minor, revision; 571 u8 harvest; 572 573 int num_base_addresses; 574 u32 base_addr[]; 575 }; 576 577 struct ip_hw_id { 578 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 579 int hw_id; 580 }; 581 582 struct ip_die_entry { 583 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 584 u16 num_ips; 585 }; 586 587 /* -------------------------------------------------- */ 588 589 struct ip_hw_instance_attr { 590 struct attribute attr; 591 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 592 }; 593 594 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 595 { 596 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 597 } 598 599 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 600 { 601 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 602 } 603 604 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 605 { 606 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 607 } 608 609 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 610 { 611 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 612 } 613 614 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 615 { 616 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 617 } 618 619 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 620 { 621 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 622 } 623 624 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 625 { 626 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 627 } 628 629 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 630 { 631 ssize_t res, at; 632 int ii; 633 634 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 635 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 636 */ 637 if (at + 12 > PAGE_SIZE) 638 break; 639 res = sysfs_emit_at(buf, at, "0x%08X\n", 640 ip_hw_instance->base_addr[ii]); 641 if (res <= 0) 642 break; 643 at += res; 644 } 645 646 return res < 0 ? res : at; 647 } 648 649 static struct ip_hw_instance_attr ip_hw_attr[] = { 650 __ATTR_RO(hw_id), 651 __ATTR_RO(num_instance), 652 __ATTR_RO(major), 653 __ATTR_RO(minor), 654 __ATTR_RO(revision), 655 __ATTR_RO(harvest), 656 __ATTR_RO(num_base_addresses), 657 __ATTR_RO(base_addr), 658 }; 659 660 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 661 ATTRIBUTE_GROUPS(ip_hw_instance); 662 663 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 664 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 665 666 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 667 struct attribute *attr, 668 char *buf) 669 { 670 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 671 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 672 673 if (!ip_hw_attr->show) 674 return -EIO; 675 676 return ip_hw_attr->show(ip_hw_instance, buf); 677 } 678 679 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 680 .show = ip_hw_instance_attr_show, 681 }; 682 683 static void ip_hw_instance_release(struct kobject *kobj) 684 { 685 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 686 687 kfree(ip_hw_instance); 688 } 689 690 static struct kobj_type ip_hw_instance_ktype = { 691 .release = ip_hw_instance_release, 692 .sysfs_ops = &ip_hw_instance_sysfs_ops, 693 .default_groups = ip_hw_instance_groups, 694 }; 695 696 /* -------------------------------------------------- */ 697 698 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 699 700 static void ip_hw_id_release(struct kobject *kobj) 701 { 702 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 703 704 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 705 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 706 kfree(ip_hw_id); 707 } 708 709 static struct kobj_type ip_hw_id_ktype = { 710 .release = ip_hw_id_release, 711 .sysfs_ops = &kobj_sysfs_ops, 712 }; 713 714 /* -------------------------------------------------- */ 715 716 static void die_kobj_release(struct kobject *kobj); 717 static void ip_disc_release(struct kobject *kobj); 718 719 struct ip_die_entry_attribute { 720 struct attribute attr; 721 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 722 }; 723 724 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 725 726 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 727 { 728 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 729 } 730 731 /* If there are more ip_die_entry attrs, other than the number of IPs, 732 * we can make this intro an array of attrs, and then initialize 733 * ip_die_entry_attrs in a loop. 734 */ 735 static struct ip_die_entry_attribute num_ips_attr = 736 __ATTR_RO(num_ips); 737 738 static struct attribute *ip_die_entry_attrs[] = { 739 &num_ips_attr.attr, 740 NULL, 741 }; 742 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 743 744 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 745 746 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 747 struct attribute *attr, 748 char *buf) 749 { 750 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 751 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 752 753 if (!ip_die_entry_attr->show) 754 return -EIO; 755 756 return ip_die_entry_attr->show(ip_die_entry, buf); 757 } 758 759 static void ip_die_entry_release(struct kobject *kobj) 760 { 761 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 762 763 if (!list_empty(&ip_die_entry->ip_kset.list)) 764 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 765 kfree(ip_die_entry); 766 } 767 768 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 769 .show = ip_die_entry_attr_show, 770 }; 771 772 static struct kobj_type ip_die_entry_ktype = { 773 .release = ip_die_entry_release, 774 .sysfs_ops = &ip_die_entry_sysfs_ops, 775 .default_groups = ip_die_entry_groups, 776 }; 777 778 static struct kobj_type die_kobj_ktype = { 779 .release = die_kobj_release, 780 .sysfs_ops = &kobj_sysfs_ops, 781 }; 782 783 static struct kobj_type ip_discovery_ktype = { 784 .release = ip_disc_release, 785 .sysfs_ops = &kobj_sysfs_ops, 786 }; 787 788 struct ip_discovery_top { 789 struct kobject kobj; /* ip_discovery/ */ 790 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 791 struct amdgpu_device *adev; 792 }; 793 794 static void die_kobj_release(struct kobject *kobj) 795 { 796 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 797 struct ip_discovery_top, 798 die_kset); 799 if (!list_empty(&ip_top->die_kset.list)) 800 DRM_ERROR("ip_top->die_kset is not empty"); 801 } 802 803 static void ip_disc_release(struct kobject *kobj) 804 { 805 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 806 kobj); 807 struct amdgpu_device *adev = ip_top->adev; 808 809 adev->ip_top = NULL; 810 kfree(ip_top); 811 } 812 813 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 814 struct ip_die_entry *ip_die_entry, 815 const size_t _ip_offset, const int num_ips) 816 { 817 int ii, jj, kk, res; 818 819 DRM_DEBUG("num_ips:%d", num_ips); 820 821 /* Find all IPs of a given HW ID, and add their instance to 822 * #die/#hw_id/#instance/<attributes> 823 */ 824 for (ii = 0; ii < HW_ID_MAX; ii++) { 825 struct ip_hw_id *ip_hw_id = NULL; 826 size_t ip_offset = _ip_offset; 827 828 for (jj = 0; jj < num_ips; jj++) { 829 struct ip *ip; 830 struct ip_hw_instance *ip_hw_instance; 831 832 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 833 if (amdgpu_discovery_validate_ip(ip) || 834 le16_to_cpu(ip->hw_id) != ii) 835 goto next_ip; 836 837 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 838 839 /* We have a hw_id match; register the hw 840 * block if not yet registered. 841 */ 842 if (!ip_hw_id) { 843 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 844 if (!ip_hw_id) 845 return -ENOMEM; 846 ip_hw_id->hw_id = ii; 847 848 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 849 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 850 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 851 res = kset_register(&ip_hw_id->hw_id_kset); 852 if (res) { 853 DRM_ERROR("Couldn't register ip_hw_id kset"); 854 kfree(ip_hw_id); 855 return res; 856 } 857 if (hw_id_names[ii]) { 858 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 859 &ip_hw_id->hw_id_kset.kobj, 860 hw_id_names[ii]); 861 if (res) { 862 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 863 hw_id_names[ii], 864 kobject_name(&ip_die_entry->ip_kset.kobj)); 865 } 866 } 867 } 868 869 /* Now register its instance. 870 */ 871 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 872 base_addr, 873 ip->num_base_address), 874 GFP_KERNEL); 875 if (!ip_hw_instance) { 876 DRM_ERROR("no memory for ip_hw_instance"); 877 return -ENOMEM; 878 } 879 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 880 ip_hw_instance->num_instance = ip->number_instance; 881 ip_hw_instance->major = ip->major; 882 ip_hw_instance->minor = ip->minor; 883 ip_hw_instance->revision = ip->revision; 884 ip_hw_instance->harvest = ip->harvest; 885 ip_hw_instance->num_base_addresses = ip->num_base_address; 886 887 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 888 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 889 890 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 891 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 892 res = kobject_add(&ip_hw_instance->kobj, NULL, 893 "%d", ip_hw_instance->num_instance); 894 next_ip: 895 ip_offset += struct_size(ip, base_address, ip->num_base_address); 896 } 897 } 898 899 return 0; 900 } 901 902 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 903 { 904 struct binary_header *bhdr; 905 struct ip_discovery_header *ihdr; 906 struct die_header *dhdr; 907 struct kset *die_kset = &adev->ip_top->die_kset; 908 u16 num_dies, die_offset, num_ips; 909 size_t ip_offset; 910 int ii, res; 911 912 bhdr = (struct binary_header *)adev->mman.discovery_bin; 913 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 914 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 915 num_dies = le16_to_cpu(ihdr->num_dies); 916 917 DRM_DEBUG("number of dies: %d\n", num_dies); 918 919 for (ii = 0; ii < num_dies; ii++) { 920 struct ip_die_entry *ip_die_entry; 921 922 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 923 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 924 num_ips = le16_to_cpu(dhdr->num_ips); 925 ip_offset = die_offset + sizeof(*dhdr); 926 927 /* Add the die to the kset. 928 * 929 * dhdr->die_id == ii, which was checked in 930 * amdgpu_discovery_reg_base_init(). 931 */ 932 933 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 934 if (!ip_die_entry) 935 return -ENOMEM; 936 937 ip_die_entry->num_ips = num_ips; 938 939 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 940 ip_die_entry->ip_kset.kobj.kset = die_kset; 941 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 942 res = kset_register(&ip_die_entry->ip_kset); 943 if (res) { 944 DRM_ERROR("Couldn't register ip_die_entry kset"); 945 kfree(ip_die_entry); 946 return res; 947 } 948 949 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 950 } 951 952 return 0; 953 } 954 955 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 956 { 957 struct kset *die_kset; 958 int res, ii; 959 960 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 961 if (!adev->ip_top) 962 return -ENOMEM; 963 964 adev->ip_top->adev = adev; 965 966 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 967 &adev->dev->kobj, "ip_discovery"); 968 if (res) { 969 DRM_ERROR("Couldn't init and add ip_discovery/"); 970 goto Err; 971 } 972 973 die_kset = &adev->ip_top->die_kset; 974 kobject_set_name(&die_kset->kobj, "%s", "die"); 975 die_kset->kobj.parent = &adev->ip_top->kobj; 976 die_kset->kobj.ktype = &die_kobj_ktype; 977 res = kset_register(&adev->ip_top->die_kset); 978 if (res) { 979 DRM_ERROR("Couldn't register die_kset"); 980 goto Err; 981 } 982 983 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 984 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 985 ip_hw_instance_attrs[ii] = NULL; 986 987 res = amdgpu_discovery_sysfs_recurse(adev); 988 989 return res; 990 Err: 991 kobject_put(&adev->ip_top->kobj); 992 return res; 993 } 994 995 /* -------------------------------------------------- */ 996 997 #define list_to_kobj(el) container_of(el, struct kobject, entry) 998 999 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1000 { 1001 struct list_head *el, *tmp; 1002 struct kset *hw_id_kset; 1003 1004 hw_id_kset = &ip_hw_id->hw_id_kset; 1005 spin_lock(&hw_id_kset->list_lock); 1006 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1007 list_del_init(el); 1008 spin_unlock(&hw_id_kset->list_lock); 1009 /* kobject is embedded in ip_hw_instance */ 1010 kobject_put(list_to_kobj(el)); 1011 spin_lock(&hw_id_kset->list_lock); 1012 } 1013 spin_unlock(&hw_id_kset->list_lock); 1014 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1015 } 1016 1017 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1018 { 1019 struct list_head *el, *tmp; 1020 struct kset *ip_kset; 1021 1022 ip_kset = &ip_die_entry->ip_kset; 1023 spin_lock(&ip_kset->list_lock); 1024 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1025 list_del_init(el); 1026 spin_unlock(&ip_kset->list_lock); 1027 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1028 spin_lock(&ip_kset->list_lock); 1029 } 1030 spin_unlock(&ip_kset->list_lock); 1031 kobject_put(&ip_die_entry->ip_kset.kobj); 1032 } 1033 1034 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1035 { 1036 struct list_head *el, *tmp; 1037 struct kset *die_kset; 1038 1039 die_kset = &adev->ip_top->die_kset; 1040 spin_lock(&die_kset->list_lock); 1041 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1042 list_del_init(el); 1043 spin_unlock(&die_kset->list_lock); 1044 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1045 spin_lock(&die_kset->list_lock); 1046 } 1047 spin_unlock(&die_kset->list_lock); 1048 kobject_put(&adev->ip_top->die_kset.kobj); 1049 kobject_put(&adev->ip_top->kobj); 1050 } 1051 1052 /* ================================================== */ 1053 1054 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1055 { 1056 struct binary_header *bhdr; 1057 struct ip_discovery_header *ihdr; 1058 struct die_header *dhdr; 1059 struct ip *ip; 1060 uint16_t die_offset; 1061 uint16_t ip_offset; 1062 uint16_t num_dies; 1063 uint16_t num_ips; 1064 uint8_t num_base_address; 1065 int hw_ip; 1066 int i, j, k; 1067 int r; 1068 1069 r = amdgpu_discovery_init(adev); 1070 if (r) { 1071 DRM_ERROR("amdgpu_discovery_init failed\n"); 1072 return r; 1073 } 1074 1075 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1076 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1077 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1078 num_dies = le16_to_cpu(ihdr->num_dies); 1079 1080 DRM_DEBUG("number of dies: %d\n", num_dies); 1081 1082 for (i = 0; i < num_dies; i++) { 1083 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1084 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1085 num_ips = le16_to_cpu(dhdr->num_ips); 1086 ip_offset = die_offset + sizeof(*dhdr); 1087 1088 if (le16_to_cpu(dhdr->die_id) != i) { 1089 DRM_ERROR("invalid die id %d, expected %d\n", 1090 le16_to_cpu(dhdr->die_id), i); 1091 return -EINVAL; 1092 } 1093 1094 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1095 le16_to_cpu(dhdr->die_id), num_ips); 1096 1097 for (j = 0; j < num_ips; j++) { 1098 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1099 1100 if (amdgpu_discovery_validate_ip(ip)) 1101 goto next_ip; 1102 1103 num_base_address = ip->num_base_address; 1104 1105 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1106 hw_id_names[le16_to_cpu(ip->hw_id)], 1107 le16_to_cpu(ip->hw_id), 1108 ip->number_instance, 1109 ip->major, ip->minor, 1110 ip->revision); 1111 1112 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1113 /* Bit [5:0]: original revision value 1114 * Bit [7:6]: en/decode capability: 1115 * 0b00 : VCN function normally 1116 * 0b10 : encode is disabled 1117 * 0b01 : decode is disabled 1118 */ 1119 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1120 ip->revision & 0xc0; 1121 ip->revision &= ~0xc0; 1122 adev->vcn.num_vcn_inst++; 1123 } 1124 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1125 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1126 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1127 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 1128 adev->sdma.num_instances++; 1129 1130 if (le16_to_cpu(ip->hw_id) == UMC_HWID) 1131 adev->gmc.num_umc++; 1132 1133 for (k = 0; k < num_base_address; k++) { 1134 /* 1135 * convert the endianness of base addresses in place, 1136 * so that we don't need to convert them when accessing adev->reg_offset. 1137 */ 1138 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1139 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1140 } 1141 1142 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1143 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1144 DRM_DEBUG("set register base offset for %s\n", 1145 hw_id_names[le16_to_cpu(ip->hw_id)]); 1146 adev->reg_offset[hw_ip][ip->number_instance] = 1147 ip->base_address; 1148 /* Instance support is somewhat inconsistent. 1149 * SDMA is a good example. Sienna cichlid has 4 total 1150 * SDMA instances, each enumerated separately (HWIDs 1151 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1152 * but they are enumerated as multiple instances of the 1153 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1154 * example. On most chips there are multiple instances 1155 * with the same HWID. 1156 */ 1157 adev->ip_versions[hw_ip][ip->number_instance] = 1158 IP_VERSION(ip->major, ip->minor, ip->revision); 1159 } 1160 } 1161 1162 next_ip: 1163 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1164 } 1165 } 1166 1167 amdgpu_discovery_sysfs_init(adev); 1168 1169 return 0; 1170 } 1171 1172 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1173 int *major, int *minor, int *revision) 1174 { 1175 struct binary_header *bhdr; 1176 struct ip_discovery_header *ihdr; 1177 struct die_header *dhdr; 1178 struct ip *ip; 1179 uint16_t die_offset; 1180 uint16_t ip_offset; 1181 uint16_t num_dies; 1182 uint16_t num_ips; 1183 int i, j; 1184 1185 if (!adev->mman.discovery_bin) { 1186 DRM_ERROR("ip discovery uninitialized\n"); 1187 return -EINVAL; 1188 } 1189 1190 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1191 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1192 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1193 num_dies = le16_to_cpu(ihdr->num_dies); 1194 1195 for (i = 0; i < num_dies; i++) { 1196 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1197 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1198 num_ips = le16_to_cpu(dhdr->num_ips); 1199 ip_offset = die_offset + sizeof(*dhdr); 1200 1201 for (j = 0; j < num_ips; j++) { 1202 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1203 1204 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1205 if (major) 1206 *major = ip->major; 1207 if (minor) 1208 *minor = ip->minor; 1209 if (revision) 1210 *revision = ip->revision; 1211 return 0; 1212 } 1213 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1214 } 1215 } 1216 1217 return -EINVAL; 1218 } 1219 1220 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1221 { 1222 int vcn_harvest_count = 0; 1223 int umc_harvest_count = 0; 1224 1225 /* 1226 * Harvest table does not fit Navi1x and legacy GPUs, 1227 * so read harvest bit per IP data structure to set 1228 * harvest configuration. 1229 */ 1230 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1231 if ((adev->pdev->device == 0x731E && 1232 (adev->pdev->revision == 0xC6 || 1233 adev->pdev->revision == 0xC7)) || 1234 (adev->pdev->device == 0x7340 && 1235 adev->pdev->revision == 0xC9) || 1236 (adev->pdev->device == 0x7360 && 1237 adev->pdev->revision == 0xC7)) 1238 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1239 &vcn_harvest_count); 1240 } else { 1241 amdgpu_discovery_read_from_harvest_table(adev, 1242 &vcn_harvest_count, 1243 &umc_harvest_count); 1244 } 1245 1246 amdgpu_discovery_harvest_config_quirk(adev); 1247 1248 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1249 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1250 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1251 } 1252 1253 if (umc_harvest_count < adev->gmc.num_umc) { 1254 adev->gmc.num_umc -= umc_harvest_count; 1255 } 1256 } 1257 1258 union gc_info { 1259 struct gc_info_v1_0 v1; 1260 struct gc_info_v1_1 v1_1; 1261 struct gc_info_v1_2 v1_2; 1262 struct gc_info_v2_0 v2; 1263 }; 1264 1265 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1266 { 1267 struct binary_header *bhdr; 1268 union gc_info *gc_info; 1269 u16 offset; 1270 1271 if (!adev->mman.discovery_bin) { 1272 DRM_ERROR("ip discovery uninitialized\n"); 1273 return -EINVAL; 1274 } 1275 1276 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1277 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1278 1279 if (!offset) 1280 return 0; 1281 1282 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1283 1284 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1285 case 1: 1286 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1287 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1288 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1289 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1290 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1291 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1292 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1293 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1294 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1295 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1296 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1297 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1298 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1299 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1300 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1301 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1302 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1303 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1304 if (gc_info->v1.header.version_minor >= 1) { 1305 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1306 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1307 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1308 } 1309 if (gc_info->v1.header.version_minor >= 2) { 1310 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1311 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1312 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1313 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1314 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1315 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1316 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1317 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1318 } 1319 break; 1320 case 2: 1321 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1322 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1323 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1324 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1325 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1326 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1327 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1328 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1329 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1330 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1331 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1332 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1333 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1334 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1335 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1336 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1337 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1338 break; 1339 default: 1340 dev_err(adev->dev, 1341 "Unhandled GC info table %d.%d\n", 1342 le16_to_cpu(gc_info->v1.header.version_major), 1343 le16_to_cpu(gc_info->v1.header.version_minor)); 1344 return -EINVAL; 1345 } 1346 return 0; 1347 } 1348 1349 union mall_info { 1350 struct mall_info_v1_0 v1; 1351 }; 1352 1353 int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1354 { 1355 struct binary_header *bhdr; 1356 union mall_info *mall_info; 1357 u32 u, mall_size_per_umc, m_s_present, half_use; 1358 u64 mall_size; 1359 u16 offset; 1360 1361 if (!adev->mman.discovery_bin) { 1362 DRM_ERROR("ip discovery uninitialized\n"); 1363 return -EINVAL; 1364 } 1365 1366 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1367 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1368 1369 if (!offset) 1370 return 0; 1371 1372 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1373 1374 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1375 case 1: 1376 mall_size = 0; 1377 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1378 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1379 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1380 for (u = 0; u < adev->gmc.num_umc; u++) { 1381 if (m_s_present & (1 << u)) 1382 mall_size += mall_size_per_umc * 2; 1383 else if (half_use & (1 << u)) 1384 mall_size += mall_size_per_umc / 2; 1385 else 1386 mall_size += mall_size_per_umc; 1387 } 1388 adev->gmc.mall_size = mall_size; 1389 break; 1390 default: 1391 dev_err(adev->dev, 1392 "Unhandled MALL info table %d.%d\n", 1393 le16_to_cpu(mall_info->v1.header.version_major), 1394 le16_to_cpu(mall_info->v1.header.version_minor)); 1395 return -EINVAL; 1396 } 1397 return 0; 1398 } 1399 1400 union vcn_info { 1401 struct vcn_info_v1_0 v1; 1402 }; 1403 1404 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1405 { 1406 struct binary_header *bhdr; 1407 union vcn_info *vcn_info; 1408 u16 offset; 1409 int v; 1410 1411 if (!adev->mman.discovery_bin) { 1412 DRM_ERROR("ip discovery uninitialized\n"); 1413 return -EINVAL; 1414 } 1415 1416 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1417 dev_err(adev->dev, "invalid vcn instances\n"); 1418 return -EINVAL; 1419 } 1420 1421 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1422 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1423 1424 if (!offset) 1425 return 0; 1426 1427 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1428 1429 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1430 case 1: 1431 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1432 adev->vcn.vcn_codec_disable_mask[v] = 1433 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1434 } 1435 break; 1436 default: 1437 dev_err(adev->dev, 1438 "Unhandled VCN info table %d.%d\n", 1439 le16_to_cpu(vcn_info->v1.header.version_major), 1440 le16_to_cpu(vcn_info->v1.header.version_minor)); 1441 return -EINVAL; 1442 } 1443 return 0; 1444 } 1445 1446 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1447 { 1448 /* what IP to use for this? */ 1449 switch (adev->ip_versions[GC_HWIP][0]) { 1450 case IP_VERSION(9, 0, 1): 1451 case IP_VERSION(9, 1, 0): 1452 case IP_VERSION(9, 2, 1): 1453 case IP_VERSION(9, 2, 2): 1454 case IP_VERSION(9, 3, 0): 1455 case IP_VERSION(9, 4, 0): 1456 case IP_VERSION(9, 4, 1): 1457 case IP_VERSION(9, 4, 2): 1458 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1459 break; 1460 case IP_VERSION(10, 1, 10): 1461 case IP_VERSION(10, 1, 1): 1462 case IP_VERSION(10, 1, 2): 1463 case IP_VERSION(10, 1, 3): 1464 case IP_VERSION(10, 1, 4): 1465 case IP_VERSION(10, 3, 0): 1466 case IP_VERSION(10, 3, 1): 1467 case IP_VERSION(10, 3, 2): 1468 case IP_VERSION(10, 3, 3): 1469 case IP_VERSION(10, 3, 4): 1470 case IP_VERSION(10, 3, 5): 1471 case IP_VERSION(10, 3, 6): 1472 case IP_VERSION(10, 3, 7): 1473 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1474 break; 1475 case IP_VERSION(11, 0, 0): 1476 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1477 break; 1478 default: 1479 dev_err(adev->dev, 1480 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1481 adev->ip_versions[GC_HWIP][0]); 1482 return -EINVAL; 1483 } 1484 return 0; 1485 } 1486 1487 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1488 { 1489 /* use GC or MMHUB IP version */ 1490 switch (adev->ip_versions[GC_HWIP][0]) { 1491 case IP_VERSION(9, 0, 1): 1492 case IP_VERSION(9, 1, 0): 1493 case IP_VERSION(9, 2, 1): 1494 case IP_VERSION(9, 2, 2): 1495 case IP_VERSION(9, 3, 0): 1496 case IP_VERSION(9, 4, 0): 1497 case IP_VERSION(9, 4, 1): 1498 case IP_VERSION(9, 4, 2): 1499 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1500 break; 1501 case IP_VERSION(10, 1, 10): 1502 case IP_VERSION(10, 1, 1): 1503 case IP_VERSION(10, 1, 2): 1504 case IP_VERSION(10, 1, 3): 1505 case IP_VERSION(10, 1, 4): 1506 case IP_VERSION(10, 3, 0): 1507 case IP_VERSION(10, 3, 1): 1508 case IP_VERSION(10, 3, 2): 1509 case IP_VERSION(10, 3, 3): 1510 case IP_VERSION(10, 3, 4): 1511 case IP_VERSION(10, 3, 5): 1512 case IP_VERSION(10, 3, 6): 1513 case IP_VERSION(10, 3, 7): 1514 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1515 break; 1516 default: 1517 dev_err(adev->dev, 1518 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1519 adev->ip_versions[GC_HWIP][0]); 1520 return -EINVAL; 1521 } 1522 return 0; 1523 } 1524 1525 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1526 { 1527 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1528 case IP_VERSION(4, 0, 0): 1529 case IP_VERSION(4, 0, 1): 1530 case IP_VERSION(4, 1, 0): 1531 case IP_VERSION(4, 1, 1): 1532 case IP_VERSION(4, 3, 0): 1533 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1534 break; 1535 case IP_VERSION(4, 2, 0): 1536 case IP_VERSION(4, 2, 1): 1537 case IP_VERSION(4, 4, 0): 1538 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1539 break; 1540 case IP_VERSION(5, 0, 0): 1541 case IP_VERSION(5, 0, 1): 1542 case IP_VERSION(5, 0, 2): 1543 case IP_VERSION(5, 0, 3): 1544 case IP_VERSION(5, 2, 0): 1545 case IP_VERSION(5, 2, 1): 1546 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1547 break; 1548 case IP_VERSION(6, 0, 0): 1549 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1550 break; 1551 default: 1552 dev_err(adev->dev, 1553 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1554 adev->ip_versions[OSSSYS_HWIP][0]); 1555 return -EINVAL; 1556 } 1557 return 0; 1558 } 1559 1560 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1561 { 1562 switch (adev->ip_versions[MP0_HWIP][0]) { 1563 case IP_VERSION(9, 0, 0): 1564 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1565 break; 1566 case IP_VERSION(10, 0, 0): 1567 case IP_VERSION(10, 0, 1): 1568 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1569 break; 1570 case IP_VERSION(11, 0, 0): 1571 case IP_VERSION(11, 0, 2): 1572 case IP_VERSION(11, 0, 4): 1573 case IP_VERSION(11, 0, 5): 1574 case IP_VERSION(11, 0, 9): 1575 case IP_VERSION(11, 0, 7): 1576 case IP_VERSION(11, 0, 11): 1577 case IP_VERSION(11, 0, 12): 1578 case IP_VERSION(11, 0, 13): 1579 case IP_VERSION(11, 5, 0): 1580 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1581 break; 1582 case IP_VERSION(11, 0, 8): 1583 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1584 break; 1585 case IP_VERSION(11, 0, 3): 1586 case IP_VERSION(12, 0, 1): 1587 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1588 break; 1589 case IP_VERSION(13, 0, 0): 1590 case IP_VERSION(13, 0, 1): 1591 case IP_VERSION(13, 0, 2): 1592 case IP_VERSION(13, 0, 3): 1593 case IP_VERSION(13, 0, 5): 1594 case IP_VERSION(13, 0, 8): 1595 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1596 break; 1597 default: 1598 dev_err(adev->dev, 1599 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1600 adev->ip_versions[MP0_HWIP][0]); 1601 return -EINVAL; 1602 } 1603 return 0; 1604 } 1605 1606 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1607 { 1608 switch (adev->ip_versions[MP1_HWIP][0]) { 1609 case IP_VERSION(9, 0, 0): 1610 case IP_VERSION(10, 0, 0): 1611 case IP_VERSION(10, 0, 1): 1612 case IP_VERSION(11, 0, 2): 1613 if (adev->asic_type == CHIP_ARCTURUS) 1614 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1615 else 1616 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1617 break; 1618 case IP_VERSION(11, 0, 0): 1619 case IP_VERSION(11, 0, 5): 1620 case IP_VERSION(11, 0, 9): 1621 case IP_VERSION(11, 0, 7): 1622 case IP_VERSION(11, 0, 8): 1623 case IP_VERSION(11, 0, 11): 1624 case IP_VERSION(11, 0, 12): 1625 case IP_VERSION(11, 0, 13): 1626 case IP_VERSION(11, 5, 0): 1627 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1628 break; 1629 case IP_VERSION(12, 0, 0): 1630 case IP_VERSION(12, 0, 1): 1631 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1632 break; 1633 case IP_VERSION(13, 0, 1): 1634 case IP_VERSION(13, 0, 2): 1635 case IP_VERSION(13, 0, 3): 1636 case IP_VERSION(13, 0, 5): 1637 case IP_VERSION(13, 0, 8): 1638 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1639 break; 1640 default: 1641 dev_err(adev->dev, 1642 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1643 adev->ip_versions[MP1_HWIP][0]); 1644 return -EINVAL; 1645 } 1646 return 0; 1647 } 1648 1649 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1650 { 1651 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 1652 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1653 return 0; 1654 } 1655 1656 if (!amdgpu_device_has_dc_support(adev)) 1657 return 0; 1658 1659 #if defined(CONFIG_DRM_AMD_DC) 1660 if (adev->ip_versions[DCE_HWIP][0]) { 1661 switch (adev->ip_versions[DCE_HWIP][0]) { 1662 case IP_VERSION(1, 0, 0): 1663 case IP_VERSION(1, 0, 1): 1664 case IP_VERSION(2, 0, 2): 1665 case IP_VERSION(2, 0, 0): 1666 case IP_VERSION(2, 0, 3): 1667 case IP_VERSION(2, 1, 0): 1668 case IP_VERSION(3, 0, 0): 1669 case IP_VERSION(3, 0, 2): 1670 case IP_VERSION(3, 0, 3): 1671 case IP_VERSION(3, 0, 1): 1672 case IP_VERSION(3, 1, 2): 1673 case IP_VERSION(3, 1, 3): 1674 case IP_VERSION(3, 1, 5): 1675 case IP_VERSION(3, 1, 6): 1676 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1677 break; 1678 default: 1679 dev_err(adev->dev, 1680 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1681 adev->ip_versions[DCE_HWIP][0]); 1682 return -EINVAL; 1683 } 1684 } else if (adev->ip_versions[DCI_HWIP][0]) { 1685 switch (adev->ip_versions[DCI_HWIP][0]) { 1686 case IP_VERSION(12, 0, 0): 1687 case IP_VERSION(12, 0, 1): 1688 case IP_VERSION(12, 1, 0): 1689 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1690 break; 1691 default: 1692 dev_err(adev->dev, 1693 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1694 adev->ip_versions[DCI_HWIP][0]); 1695 return -EINVAL; 1696 } 1697 } 1698 #endif 1699 return 0; 1700 } 1701 1702 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1703 { 1704 switch (adev->ip_versions[GC_HWIP][0]) { 1705 case IP_VERSION(9, 0, 1): 1706 case IP_VERSION(9, 1, 0): 1707 case IP_VERSION(9, 2, 1): 1708 case IP_VERSION(9, 2, 2): 1709 case IP_VERSION(9, 3, 0): 1710 case IP_VERSION(9, 4, 0): 1711 case IP_VERSION(9, 4, 1): 1712 case IP_VERSION(9, 4, 2): 1713 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1714 break; 1715 case IP_VERSION(10, 1, 10): 1716 case IP_VERSION(10, 1, 2): 1717 case IP_VERSION(10, 1, 1): 1718 case IP_VERSION(10, 1, 3): 1719 case IP_VERSION(10, 1, 4): 1720 case IP_VERSION(10, 3, 0): 1721 case IP_VERSION(10, 3, 2): 1722 case IP_VERSION(10, 3, 1): 1723 case IP_VERSION(10, 3, 4): 1724 case IP_VERSION(10, 3, 5): 1725 case IP_VERSION(10, 3, 6): 1726 case IP_VERSION(10, 3, 3): 1727 case IP_VERSION(10, 3, 7): 1728 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1729 break; 1730 default: 1731 dev_err(adev->dev, 1732 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1733 adev->ip_versions[GC_HWIP][0]); 1734 return -EINVAL; 1735 } 1736 return 0; 1737 } 1738 1739 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1740 { 1741 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1742 case IP_VERSION(4, 0, 0): 1743 case IP_VERSION(4, 0, 1): 1744 case IP_VERSION(4, 1, 0): 1745 case IP_VERSION(4, 1, 1): 1746 case IP_VERSION(4, 1, 2): 1747 case IP_VERSION(4, 2, 0): 1748 case IP_VERSION(4, 2, 2): 1749 case IP_VERSION(4, 4, 0): 1750 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1751 break; 1752 case IP_VERSION(5, 0, 0): 1753 case IP_VERSION(5, 0, 1): 1754 case IP_VERSION(5, 0, 2): 1755 case IP_VERSION(5, 0, 5): 1756 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1757 break; 1758 case IP_VERSION(5, 2, 0): 1759 case IP_VERSION(5, 2, 2): 1760 case IP_VERSION(5, 2, 4): 1761 case IP_VERSION(5, 2, 5): 1762 case IP_VERSION(5, 2, 6): 1763 case IP_VERSION(5, 2, 3): 1764 case IP_VERSION(5, 2, 1): 1765 case IP_VERSION(5, 2, 7): 1766 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1767 break; 1768 default: 1769 dev_err(adev->dev, 1770 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1771 adev->ip_versions[SDMA0_HWIP][0]); 1772 return -EINVAL; 1773 } 1774 return 0; 1775 } 1776 1777 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1778 { 1779 if (adev->ip_versions[VCE_HWIP][0]) { 1780 switch (adev->ip_versions[UVD_HWIP][0]) { 1781 case IP_VERSION(7, 0, 0): 1782 case IP_VERSION(7, 2, 0): 1783 /* UVD is not supported on vega20 SR-IOV */ 1784 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1785 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1786 break; 1787 default: 1788 dev_err(adev->dev, 1789 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1790 adev->ip_versions[UVD_HWIP][0]); 1791 return -EINVAL; 1792 } 1793 switch (adev->ip_versions[VCE_HWIP][0]) { 1794 case IP_VERSION(4, 0, 0): 1795 case IP_VERSION(4, 1, 0): 1796 /* VCE is not supported on vega20 SR-IOV */ 1797 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1798 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1799 break; 1800 default: 1801 dev_err(adev->dev, 1802 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1803 adev->ip_versions[VCE_HWIP][0]); 1804 return -EINVAL; 1805 } 1806 } else { 1807 switch (adev->ip_versions[UVD_HWIP][0]) { 1808 case IP_VERSION(1, 0, 0): 1809 case IP_VERSION(1, 0, 1): 1810 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1811 break; 1812 case IP_VERSION(2, 0, 0): 1813 case IP_VERSION(2, 0, 2): 1814 case IP_VERSION(2, 2, 0): 1815 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1816 if (!amdgpu_sriov_vf(adev)) 1817 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1818 break; 1819 case IP_VERSION(2, 0, 3): 1820 break; 1821 case IP_VERSION(2, 5, 0): 1822 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1823 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1824 break; 1825 case IP_VERSION(2, 6, 0): 1826 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1827 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1828 break; 1829 case IP_VERSION(3, 0, 0): 1830 case IP_VERSION(3, 0, 16): 1831 case IP_VERSION(3, 1, 1): 1832 case IP_VERSION(3, 1, 2): 1833 case IP_VERSION(3, 0, 2): 1834 case IP_VERSION(3, 0, 192): 1835 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1836 if (!amdgpu_sriov_vf(adev)) 1837 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1838 break; 1839 case IP_VERSION(3, 0, 33): 1840 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1841 break; 1842 default: 1843 dev_err(adev->dev, 1844 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1845 adev->ip_versions[UVD_HWIP][0]); 1846 return -EINVAL; 1847 } 1848 } 1849 return 0; 1850 } 1851 1852 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1853 { 1854 switch (adev->ip_versions[GC_HWIP][0]) { 1855 case IP_VERSION(10, 1, 10): 1856 case IP_VERSION(10, 1, 1): 1857 case IP_VERSION(10, 1, 2): 1858 case IP_VERSION(10, 1, 3): 1859 case IP_VERSION(10, 1, 4): 1860 case IP_VERSION(10, 3, 0): 1861 case IP_VERSION(10, 3, 1): 1862 case IP_VERSION(10, 3, 2): 1863 case IP_VERSION(10, 3, 3): 1864 case IP_VERSION(10, 3, 4): 1865 case IP_VERSION(10, 3, 5): 1866 case IP_VERSION(10, 3, 6): 1867 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1868 break; 1869 default: 1870 break; 1871 } 1872 return 0; 1873 } 1874 1875 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1876 { 1877 int r; 1878 1879 switch (adev->asic_type) { 1880 case CHIP_VEGA10: 1881 vega10_reg_base_init(adev); 1882 adev->sdma.num_instances = 2; 1883 adev->gmc.num_umc = 4; 1884 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1885 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1886 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1887 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1888 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1889 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1890 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1891 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1892 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1893 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1894 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1895 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1896 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1897 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1898 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1899 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1900 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1901 break; 1902 case CHIP_VEGA12: 1903 vega10_reg_base_init(adev); 1904 adev->sdma.num_instances = 2; 1905 adev->gmc.num_umc = 4; 1906 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1907 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1908 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1909 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1910 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1911 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1912 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1913 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1914 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1915 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1916 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1917 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1918 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1919 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1920 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1921 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1922 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1923 break; 1924 case CHIP_RAVEN: 1925 vega10_reg_base_init(adev); 1926 adev->sdma.num_instances = 1; 1927 adev->vcn.num_vcn_inst = 1; 1928 adev->gmc.num_umc = 2; 1929 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1930 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1931 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1932 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1933 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1934 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1935 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1936 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1937 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1938 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1939 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1940 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1941 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1942 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1943 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1944 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1945 } else { 1946 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1947 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1948 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1949 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1950 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1951 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1952 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1953 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1954 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1955 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1956 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1957 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1958 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1959 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1960 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1961 } 1962 break; 1963 case CHIP_VEGA20: 1964 vega20_reg_base_init(adev); 1965 adev->sdma.num_instances = 2; 1966 adev->gmc.num_umc = 8; 1967 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1968 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1969 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1970 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1971 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1972 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1973 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1974 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1975 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 1976 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 1977 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1978 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 1979 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 1980 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 1981 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 1982 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 1983 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 1984 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 1985 break; 1986 case CHIP_ARCTURUS: 1987 arct_reg_base_init(adev); 1988 adev->sdma.num_instances = 8; 1989 adev->vcn.num_vcn_inst = 2; 1990 adev->gmc.num_umc = 8; 1991 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1992 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1993 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 1994 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 1995 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 1996 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 1997 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 1998 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 1999 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2000 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2001 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2002 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2003 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2004 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2005 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2006 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2007 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2008 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2009 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2010 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2011 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2012 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2013 break; 2014 case CHIP_ALDEBARAN: 2015 aldebaran_reg_base_init(adev); 2016 adev->sdma.num_instances = 5; 2017 adev->vcn.num_vcn_inst = 2; 2018 adev->gmc.num_umc = 4; 2019 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2020 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2021 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2022 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2023 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2024 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2025 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2026 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2027 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2028 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2029 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2030 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2031 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2032 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2033 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2034 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2035 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2036 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2037 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2038 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2039 break; 2040 default: 2041 r = amdgpu_discovery_reg_base_init(adev); 2042 if (r) 2043 return -EINVAL; 2044 2045 amdgpu_discovery_harvest_ip(adev); 2046 amdgpu_discovery_get_gfx_info(adev); 2047 amdgpu_discovery_get_mall_info(adev); 2048 amdgpu_discovery_get_vcn_info(adev); 2049 break; 2050 } 2051 2052 switch (adev->ip_versions[GC_HWIP][0]) { 2053 case IP_VERSION(9, 0, 1): 2054 case IP_VERSION(9, 2, 1): 2055 case IP_VERSION(9, 4, 0): 2056 case IP_VERSION(9, 4, 1): 2057 case IP_VERSION(9, 4, 2): 2058 adev->family = AMDGPU_FAMILY_AI; 2059 break; 2060 case IP_VERSION(9, 1, 0): 2061 case IP_VERSION(9, 2, 2): 2062 case IP_VERSION(9, 3, 0): 2063 adev->family = AMDGPU_FAMILY_RV; 2064 break; 2065 case IP_VERSION(10, 1, 10): 2066 case IP_VERSION(10, 1, 1): 2067 case IP_VERSION(10, 1, 2): 2068 case IP_VERSION(10, 1, 3): 2069 case IP_VERSION(10, 1, 4): 2070 case IP_VERSION(10, 3, 0): 2071 case IP_VERSION(10, 3, 2): 2072 case IP_VERSION(10, 3, 4): 2073 case IP_VERSION(10, 3, 5): 2074 adev->family = AMDGPU_FAMILY_NV; 2075 break; 2076 case IP_VERSION(10, 3, 1): 2077 adev->family = AMDGPU_FAMILY_VGH; 2078 break; 2079 case IP_VERSION(10, 3, 3): 2080 adev->family = AMDGPU_FAMILY_YC; 2081 break; 2082 case IP_VERSION(10, 3, 6): 2083 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2084 break; 2085 case IP_VERSION(10, 3, 7): 2086 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2087 break; 2088 default: 2089 return -EINVAL; 2090 } 2091 2092 switch (adev->ip_versions[GC_HWIP][0]) { 2093 case IP_VERSION(9, 1, 0): 2094 case IP_VERSION(9, 2, 2): 2095 case IP_VERSION(9, 3, 0): 2096 case IP_VERSION(10, 1, 3): 2097 case IP_VERSION(10, 1, 4): 2098 case IP_VERSION(10, 3, 1): 2099 case IP_VERSION(10, 3, 3): 2100 case IP_VERSION(10, 3, 6): 2101 case IP_VERSION(10, 3, 7): 2102 adev->flags |= AMD_IS_APU; 2103 break; 2104 default: 2105 break; 2106 } 2107 2108 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2109 adev->gmc.xgmi.supported = true; 2110 2111 /* set NBIO version */ 2112 switch (adev->ip_versions[NBIO_HWIP][0]) { 2113 case IP_VERSION(6, 1, 0): 2114 case IP_VERSION(6, 2, 0): 2115 adev->nbio.funcs = &nbio_v6_1_funcs; 2116 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2117 break; 2118 case IP_VERSION(7, 0, 0): 2119 case IP_VERSION(7, 0, 1): 2120 case IP_VERSION(2, 5, 0): 2121 adev->nbio.funcs = &nbio_v7_0_funcs; 2122 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2123 break; 2124 case IP_VERSION(7, 4, 0): 2125 case IP_VERSION(7, 4, 1): 2126 adev->nbio.funcs = &nbio_v7_4_funcs; 2127 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2128 break; 2129 case IP_VERSION(7, 4, 4): 2130 adev->nbio.funcs = &nbio_v7_4_funcs; 2131 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 2132 break; 2133 case IP_VERSION(7, 2, 0): 2134 case IP_VERSION(7, 2, 1): 2135 case IP_VERSION(7, 3, 0): 2136 case IP_VERSION(7, 5, 0): 2137 case IP_VERSION(7, 5, 1): 2138 adev->nbio.funcs = &nbio_v7_2_funcs; 2139 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2140 break; 2141 case IP_VERSION(2, 1, 1): 2142 case IP_VERSION(2, 3, 0): 2143 case IP_VERSION(2, 3, 1): 2144 case IP_VERSION(2, 3, 2): 2145 adev->nbio.funcs = &nbio_v2_3_funcs; 2146 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2147 break; 2148 case IP_VERSION(3, 3, 0): 2149 case IP_VERSION(3, 3, 1): 2150 case IP_VERSION(3, 3, 2): 2151 case IP_VERSION(3, 3, 3): 2152 adev->nbio.funcs = &nbio_v2_3_funcs; 2153 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 2154 break; 2155 case IP_VERSION(4, 3, 0): 2156 adev->nbio.funcs = &nbio_v4_3_funcs; 2157 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2158 break; 2159 default: 2160 break; 2161 } 2162 2163 switch (adev->ip_versions[HDP_HWIP][0]) { 2164 case IP_VERSION(4, 0, 0): 2165 case IP_VERSION(4, 0, 1): 2166 case IP_VERSION(4, 1, 0): 2167 case IP_VERSION(4, 1, 1): 2168 case IP_VERSION(4, 1, 2): 2169 case IP_VERSION(4, 2, 0): 2170 case IP_VERSION(4, 2, 1): 2171 case IP_VERSION(4, 4, 0): 2172 adev->hdp.funcs = &hdp_v4_0_funcs; 2173 break; 2174 case IP_VERSION(5, 0, 0): 2175 case IP_VERSION(5, 0, 1): 2176 case IP_VERSION(5, 0, 2): 2177 case IP_VERSION(5, 0, 3): 2178 case IP_VERSION(5, 0, 4): 2179 case IP_VERSION(5, 2, 0): 2180 adev->hdp.funcs = &hdp_v5_0_funcs; 2181 break; 2182 case IP_VERSION(6, 0, 0): 2183 adev->hdp.funcs = &hdp_v6_0_funcs; 2184 break; 2185 default: 2186 break; 2187 } 2188 2189 switch (adev->ip_versions[DF_HWIP][0]) { 2190 case IP_VERSION(3, 6, 0): 2191 case IP_VERSION(3, 6, 1): 2192 case IP_VERSION(3, 6, 2): 2193 adev->df.funcs = &df_v3_6_funcs; 2194 break; 2195 case IP_VERSION(2, 1, 0): 2196 case IP_VERSION(2, 1, 1): 2197 case IP_VERSION(2, 5, 0): 2198 case IP_VERSION(3, 5, 1): 2199 case IP_VERSION(3, 5, 2): 2200 adev->df.funcs = &df_v1_7_funcs; 2201 break; 2202 default: 2203 break; 2204 } 2205 2206 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2207 case IP_VERSION(9, 0, 0): 2208 case IP_VERSION(9, 0, 1): 2209 case IP_VERSION(10, 0, 0): 2210 case IP_VERSION(10, 0, 1): 2211 case IP_VERSION(10, 0, 2): 2212 adev->smuio.funcs = &smuio_v9_0_funcs; 2213 break; 2214 case IP_VERSION(11, 0, 0): 2215 case IP_VERSION(11, 0, 2): 2216 case IP_VERSION(11, 0, 3): 2217 case IP_VERSION(11, 0, 4): 2218 case IP_VERSION(11, 0, 7): 2219 case IP_VERSION(11, 0, 8): 2220 adev->smuio.funcs = &smuio_v11_0_funcs; 2221 break; 2222 case IP_VERSION(11, 0, 6): 2223 case IP_VERSION(11, 0, 10): 2224 case IP_VERSION(11, 0, 11): 2225 case IP_VERSION(11, 5, 0): 2226 case IP_VERSION(13, 0, 1): 2227 case IP_VERSION(13, 0, 9): 2228 case IP_VERSION(13, 0, 10): 2229 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2230 break; 2231 case IP_VERSION(13, 0, 2): 2232 adev->smuio.funcs = &smuio_v13_0_funcs; 2233 break; 2234 case IP_VERSION(13, 0, 6): 2235 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2236 break; 2237 default: 2238 break; 2239 } 2240 2241 r = amdgpu_discovery_set_common_ip_blocks(adev); 2242 if (r) 2243 return r; 2244 2245 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2246 if (r) 2247 return r; 2248 2249 /* For SR-IOV, PSP needs to be initialized before IH */ 2250 if (amdgpu_sriov_vf(adev)) { 2251 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2252 if (r) 2253 return r; 2254 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2255 if (r) 2256 return r; 2257 } else { 2258 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2259 if (r) 2260 return r; 2261 2262 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2263 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2264 if (r) 2265 return r; 2266 } 2267 } 2268 2269 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2270 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2271 if (r) 2272 return r; 2273 } 2274 2275 r = amdgpu_discovery_set_display_ip_blocks(adev); 2276 if (r) 2277 return r; 2278 2279 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2280 if (r) 2281 return r; 2282 2283 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2284 if (r) 2285 return r; 2286 2287 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2288 !amdgpu_sriov_vf(adev)) { 2289 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2290 if (r) 2291 return r; 2292 } 2293 2294 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2295 if (r) 2296 return r; 2297 2298 if (adev->enable_mes) { 2299 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2300 if (r) 2301 return r; 2302 } 2303 2304 return 0; 2305 } 2306 2307