1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "df_v4_3.h" 37 #include "nbio_v6_1.h" 38 #include "nbio_v7_0.h" 39 #include "nbio_v7_4.h" 40 #include "nbio_v7_9.h" 41 #include "hdp_v4_0.h" 42 #include "vega10_ih.h" 43 #include "vega20_ih.h" 44 #include "sdma_v4_0.h" 45 #include "sdma_v4_4_2.h" 46 #include "uvd_v7_0.h" 47 #include "vce_v4_0.h" 48 #include "vcn_v1_0.h" 49 #include "vcn_v2_5.h" 50 #include "jpeg_v2_5.h" 51 #include "smuio_v9_0.h" 52 #include "gmc_v10_0.h" 53 #include "gmc_v11_0.h" 54 #include "gfxhub_v2_0.h" 55 #include "mmhub_v2_0.h" 56 #include "nbio_v2_3.h" 57 #include "nbio_v4_3.h" 58 #include "nbio_v7_2.h" 59 #include "nbio_v7_7.h" 60 #include "hdp_v5_0.h" 61 #include "hdp_v5_2.h" 62 #include "hdp_v6_0.h" 63 #include "nv.h" 64 #include "soc21.h" 65 #include "navi10_ih.h" 66 #include "ih_v6_0.h" 67 #include "gfx_v10_0.h" 68 #include "gfx_v11_0.h" 69 #include "sdma_v5_0.h" 70 #include "sdma_v5_2.h" 71 #include "sdma_v6_0.h" 72 #include "lsdma_v6_0.h" 73 #include "vcn_v2_0.h" 74 #include "jpeg_v2_0.h" 75 #include "vcn_v3_0.h" 76 #include "jpeg_v3_0.h" 77 #include "vcn_v4_0.h" 78 #include "jpeg_v4_0.h" 79 #include "vcn_v4_0_3.h" 80 #include "jpeg_v4_0_3.h" 81 #include "amdgpu_vkms.h" 82 #include "mes_v10_1.h" 83 #include "mes_v11_0.h" 84 #include "smuio_v11_0.h" 85 #include "smuio_v11_0_6.h" 86 #include "smuio_v13_0.h" 87 #include "smuio_v13_0_3.h" 88 #include "smuio_v13_0_6.h" 89 90 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 91 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 92 93 #define mmRCC_CONFIG_MEMSIZE 0xde3 94 #define mmMM_INDEX 0x0 95 #define mmMM_INDEX_HI 0x6 96 #define mmMM_DATA 0x1 97 98 static const char *hw_id_names[HW_ID_MAX] = { 99 [MP1_HWID] = "MP1", 100 [MP2_HWID] = "MP2", 101 [THM_HWID] = "THM", 102 [SMUIO_HWID] = "SMUIO", 103 [FUSE_HWID] = "FUSE", 104 [CLKA_HWID] = "CLKA", 105 [PWR_HWID] = "PWR", 106 [GC_HWID] = "GC", 107 [UVD_HWID] = "UVD", 108 [AUDIO_AZ_HWID] = "AUDIO_AZ", 109 [ACP_HWID] = "ACP", 110 [DCI_HWID] = "DCI", 111 [DMU_HWID] = "DMU", 112 [DCO_HWID] = "DCO", 113 [DIO_HWID] = "DIO", 114 [XDMA_HWID] = "XDMA", 115 [DCEAZ_HWID] = "DCEAZ", 116 [DAZ_HWID] = "DAZ", 117 [SDPMUX_HWID] = "SDPMUX", 118 [NTB_HWID] = "NTB", 119 [IOHC_HWID] = "IOHC", 120 [L2IMU_HWID] = "L2IMU", 121 [VCE_HWID] = "VCE", 122 [MMHUB_HWID] = "MMHUB", 123 [ATHUB_HWID] = "ATHUB", 124 [DBGU_NBIO_HWID] = "DBGU_NBIO", 125 [DFX_HWID] = "DFX", 126 [DBGU0_HWID] = "DBGU0", 127 [DBGU1_HWID] = "DBGU1", 128 [OSSSYS_HWID] = "OSSSYS", 129 [HDP_HWID] = "HDP", 130 [SDMA0_HWID] = "SDMA0", 131 [SDMA1_HWID] = "SDMA1", 132 [SDMA2_HWID] = "SDMA2", 133 [SDMA3_HWID] = "SDMA3", 134 [LSDMA_HWID] = "LSDMA", 135 [ISP_HWID] = "ISP", 136 [DBGU_IO_HWID] = "DBGU_IO", 137 [DF_HWID] = "DF", 138 [CLKB_HWID] = "CLKB", 139 [FCH_HWID] = "FCH", 140 [DFX_DAP_HWID] = "DFX_DAP", 141 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 142 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 143 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 144 [L1IMU3_HWID] = "L1IMU3", 145 [L1IMU4_HWID] = "L1IMU4", 146 [L1IMU5_HWID] = "L1IMU5", 147 [L1IMU6_HWID] = "L1IMU6", 148 [L1IMU7_HWID] = "L1IMU7", 149 [L1IMU8_HWID] = "L1IMU8", 150 [L1IMU9_HWID] = "L1IMU9", 151 [L1IMU10_HWID] = "L1IMU10", 152 [L1IMU11_HWID] = "L1IMU11", 153 [L1IMU12_HWID] = "L1IMU12", 154 [L1IMU13_HWID] = "L1IMU13", 155 [L1IMU14_HWID] = "L1IMU14", 156 [L1IMU15_HWID] = "L1IMU15", 157 [WAFLC_HWID] = "WAFLC", 158 [FCH_USB_PD_HWID] = "FCH_USB_PD", 159 [PCIE_HWID] = "PCIE", 160 [PCS_HWID] = "PCS", 161 [DDCL_HWID] = "DDCL", 162 [SST_HWID] = "SST", 163 [IOAGR_HWID] = "IOAGR", 164 [NBIF_HWID] = "NBIF", 165 [IOAPIC_HWID] = "IOAPIC", 166 [SYSTEMHUB_HWID] = "SYSTEMHUB", 167 [NTBCCP_HWID] = "NTBCCP", 168 [UMC_HWID] = "UMC", 169 [SATA_HWID] = "SATA", 170 [USB_HWID] = "USB", 171 [CCXSEC_HWID] = "CCXSEC", 172 [XGMI_HWID] = "XGMI", 173 [XGBE_HWID] = "XGBE", 174 [MP0_HWID] = "MP0", 175 }; 176 177 static int hw_id_map[MAX_HWIP] = { 178 [GC_HWIP] = GC_HWID, 179 [HDP_HWIP] = HDP_HWID, 180 [SDMA0_HWIP] = SDMA0_HWID, 181 [SDMA1_HWIP] = SDMA1_HWID, 182 [SDMA2_HWIP] = SDMA2_HWID, 183 [SDMA3_HWIP] = SDMA3_HWID, 184 [LSDMA_HWIP] = LSDMA_HWID, 185 [MMHUB_HWIP] = MMHUB_HWID, 186 [ATHUB_HWIP] = ATHUB_HWID, 187 [NBIO_HWIP] = NBIF_HWID, 188 [MP0_HWIP] = MP0_HWID, 189 [MP1_HWIP] = MP1_HWID, 190 [UVD_HWIP] = UVD_HWID, 191 [VCE_HWIP] = VCE_HWID, 192 [DF_HWIP] = DF_HWID, 193 [DCE_HWIP] = DMU_HWID, 194 [OSSSYS_HWIP] = OSSSYS_HWID, 195 [SMUIO_HWIP] = SMUIO_HWID, 196 [PWR_HWIP] = PWR_HWID, 197 [NBIF_HWIP] = NBIF_HWID, 198 [THM_HWIP] = THM_HWID, 199 [CLK_HWIP] = CLKA_HWID, 200 [UMC_HWIP] = UMC_HWID, 201 [XGMI_HWIP] = XGMI_HWID, 202 [DCI_HWIP] = DCI_HWID, 203 [PCIE_HWIP] = PCIE_HWID, 204 }; 205 206 static void amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 207 { 208 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 209 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 210 211 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 212 adev->mman.discovery_tmr_size, false); 213 } 214 215 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 216 { 217 const struct firmware *fw; 218 const char *fw_name; 219 int r; 220 221 switch (amdgpu_discovery) { 222 case 2: 223 fw_name = FIRMWARE_IP_DISCOVERY; 224 break; 225 default: 226 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 227 return -EINVAL; 228 } 229 230 r = request_firmware(&fw, fw_name, adev->dev); 231 if (r) { 232 dev_err(adev->dev, "can't load firmware \"%s\"\n", 233 fw_name); 234 return r; 235 } 236 237 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 238 release_firmware(fw); 239 240 return 0; 241 } 242 243 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 244 { 245 uint16_t checksum = 0; 246 int i; 247 248 for (i = 0; i < size; i++) 249 checksum += data[i]; 250 251 return checksum; 252 } 253 254 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 255 uint16_t expected) 256 { 257 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 258 } 259 260 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 261 { 262 struct binary_header *bhdr; 263 bhdr = (struct binary_header *)binary; 264 265 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 266 } 267 268 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 269 { 270 /* 271 * So far, apply this quirk only on those Navy Flounder boards which 272 * have a bad harvest table of VCN config. 273 */ 274 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 275 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 276 switch (adev->pdev->revision) { 277 case 0xC1: 278 case 0xC2: 279 case 0xC3: 280 case 0xC5: 281 case 0xC7: 282 case 0xCF: 283 case 0xDF: 284 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 285 break; 286 default: 287 break; 288 } 289 } 290 } 291 292 static int amdgpu_discovery_init(struct amdgpu_device *adev) 293 { 294 struct table_info *info; 295 struct binary_header *bhdr; 296 uint16_t offset; 297 uint16_t size; 298 uint16_t checksum; 299 int r; 300 301 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 302 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 303 if (!adev->mman.discovery_bin) 304 return -ENOMEM; 305 306 /* Read from file if it is the preferred option */ 307 if (amdgpu_discovery == 2) { 308 dev_info(adev->dev, "use ip discovery information from file"); 309 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 310 311 if (r) { 312 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 313 r = -EINVAL; 314 goto out; 315 } 316 317 } else { 318 amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 319 } 320 321 /* check the ip discovery binary signature */ 322 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 323 dev_err(adev->dev, 324 "get invalid ip discovery binary signature\n"); 325 r = -EINVAL; 326 goto out; 327 } 328 329 bhdr = (struct binary_header *)adev->mman.discovery_bin; 330 331 offset = offsetof(struct binary_header, binary_checksum) + 332 sizeof(bhdr->binary_checksum); 333 size = le16_to_cpu(bhdr->binary_size) - offset; 334 checksum = le16_to_cpu(bhdr->binary_checksum); 335 336 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 337 size, checksum)) { 338 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 339 r = -EINVAL; 340 goto out; 341 } 342 343 info = &bhdr->table_list[IP_DISCOVERY]; 344 offset = le16_to_cpu(info->offset); 345 checksum = le16_to_cpu(info->checksum); 346 347 if (offset) { 348 struct ip_discovery_header *ihdr = 349 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 350 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 351 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 352 r = -EINVAL; 353 goto out; 354 } 355 356 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 357 le16_to_cpu(ihdr->size), checksum)) { 358 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 359 r = -EINVAL; 360 goto out; 361 } 362 } 363 364 info = &bhdr->table_list[GC]; 365 offset = le16_to_cpu(info->offset); 366 checksum = le16_to_cpu(info->checksum); 367 368 if (offset) { 369 struct gpu_info_header *ghdr = 370 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 371 372 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 373 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 374 r = -EINVAL; 375 goto out; 376 } 377 378 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 379 le32_to_cpu(ghdr->size), checksum)) { 380 dev_err(adev->dev, "invalid gc data table checksum\n"); 381 r = -EINVAL; 382 goto out; 383 } 384 } 385 386 info = &bhdr->table_list[HARVEST_INFO]; 387 offset = le16_to_cpu(info->offset); 388 checksum = le16_to_cpu(info->checksum); 389 390 if (offset) { 391 struct harvest_info_header *hhdr = 392 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 393 394 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 395 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 396 r = -EINVAL; 397 goto out; 398 } 399 400 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 401 sizeof(struct harvest_table), checksum)) { 402 dev_err(adev->dev, "invalid harvest data table checksum\n"); 403 r = -EINVAL; 404 goto out; 405 } 406 } 407 408 info = &bhdr->table_list[VCN_INFO]; 409 offset = le16_to_cpu(info->offset); 410 checksum = le16_to_cpu(info->checksum); 411 412 if (offset) { 413 struct vcn_info_header *vhdr = 414 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 415 416 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 417 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 418 r = -EINVAL; 419 goto out; 420 } 421 422 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 423 le32_to_cpu(vhdr->size_bytes), checksum)) { 424 dev_err(adev->dev, "invalid vcn data table checksum\n"); 425 r = -EINVAL; 426 goto out; 427 } 428 } 429 430 info = &bhdr->table_list[MALL_INFO]; 431 offset = le16_to_cpu(info->offset); 432 checksum = le16_to_cpu(info->checksum); 433 434 if (0 && offset) { 435 struct mall_info_header *mhdr = 436 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 437 438 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 439 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 440 r = -EINVAL; 441 goto out; 442 } 443 444 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 445 le32_to_cpu(mhdr->size_bytes), checksum)) { 446 dev_err(adev->dev, "invalid mall data table checksum\n"); 447 r = -EINVAL; 448 goto out; 449 } 450 } 451 452 return 0; 453 454 out: 455 kfree(adev->mman.discovery_bin); 456 adev->mman.discovery_bin = NULL; 457 458 return r; 459 } 460 461 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 462 463 void amdgpu_discovery_fini(struct amdgpu_device *adev) 464 { 465 amdgpu_discovery_sysfs_fini(adev); 466 kfree(adev->mman.discovery_bin); 467 adev->mman.discovery_bin = NULL; 468 } 469 470 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 471 { 472 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 473 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 474 ip->instance_number); 475 return -EINVAL; 476 } 477 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 478 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 479 le16_to_cpu(ip->hw_id)); 480 return -EINVAL; 481 } 482 483 return 0; 484 } 485 486 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 487 uint32_t *vcn_harvest_count) 488 { 489 struct binary_header *bhdr; 490 struct ip_discovery_header *ihdr; 491 struct die_header *dhdr; 492 struct ip_v4 *ip; 493 uint16_t die_offset, ip_offset, num_dies, num_ips; 494 int i, j; 495 496 bhdr = (struct binary_header *)adev->mman.discovery_bin; 497 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 498 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 499 num_dies = le16_to_cpu(ihdr->num_dies); 500 501 /* scan harvest bit of all IP data structures */ 502 for (i = 0; i < num_dies; i++) { 503 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 504 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 505 num_ips = le16_to_cpu(dhdr->num_ips); 506 ip_offset = die_offset + sizeof(*dhdr); 507 508 for (j = 0; j < num_ips; j++) { 509 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 510 511 if (amdgpu_discovery_validate_ip(ip)) 512 goto next_ip; 513 514 if (le16_to_cpu(ip->variant) == 1) { 515 switch (le16_to_cpu(ip->hw_id)) { 516 case VCN_HWID: 517 (*vcn_harvest_count)++; 518 if (ip->instance_number == 0) 519 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 520 else 521 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 522 break; 523 case DMU_HWID: 524 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 525 break; 526 default: 527 break; 528 } 529 } 530 next_ip: 531 if (ihdr->base_addr_64_bit) 532 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 533 else 534 ip_offset += struct_size(ip, base_address, ip->num_base_address); 535 } 536 } 537 } 538 539 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 540 uint32_t *vcn_harvest_count, 541 uint32_t *umc_harvest_count) 542 { 543 struct binary_header *bhdr; 544 struct harvest_table *harvest_info; 545 u16 offset; 546 int i; 547 uint32_t umc_harvest_config = 0; 548 549 bhdr = (struct binary_header *)adev->mman.discovery_bin; 550 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 551 552 if (!offset) { 553 dev_err(adev->dev, "invalid harvest table offset\n"); 554 return; 555 } 556 557 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 558 559 for (i = 0; i < 32; i++) { 560 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 561 break; 562 563 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 564 case VCN_HWID: 565 (*vcn_harvest_count)++; 566 adev->vcn.harvest_config |= 567 (1 << harvest_info->list[i].number_instance); 568 adev->jpeg.harvest_config |= 569 (1 << harvest_info->list[i].number_instance); 570 break; 571 case DMU_HWID: 572 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 573 break; 574 case UMC_HWID: 575 umc_harvest_config |= 576 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 577 (*umc_harvest_count)++; 578 break; 579 case GC_HWID: 580 adev->gfx.xcc_mask &= 581 ~(1U << harvest_info->list[i].number_instance); 582 break; 583 case SDMA0_HWID: 584 adev->sdma.sdma_mask &= 585 ~(1U << harvest_info->list[i].number_instance); 586 break; 587 default: 588 break; 589 } 590 } 591 592 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 593 ~umc_harvest_config; 594 } 595 596 /* ================================================== */ 597 598 struct ip_hw_instance { 599 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 600 601 int hw_id; 602 u8 num_instance; 603 u8 major, minor, revision; 604 u8 harvest; 605 606 int num_base_addresses; 607 u32 base_addr[]; 608 }; 609 610 struct ip_hw_id { 611 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 612 int hw_id; 613 }; 614 615 struct ip_die_entry { 616 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 617 u16 num_ips; 618 }; 619 620 /* -------------------------------------------------- */ 621 622 struct ip_hw_instance_attr { 623 struct attribute attr; 624 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 625 }; 626 627 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 628 { 629 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 630 } 631 632 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 633 { 634 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 635 } 636 637 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 638 { 639 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 640 } 641 642 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 643 { 644 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 645 } 646 647 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 648 { 649 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 650 } 651 652 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 653 { 654 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 655 } 656 657 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 658 { 659 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 660 } 661 662 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 663 { 664 ssize_t res, at; 665 int ii; 666 667 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 668 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 669 */ 670 if (at + 12 > PAGE_SIZE) 671 break; 672 res = sysfs_emit_at(buf, at, "0x%08X\n", 673 ip_hw_instance->base_addr[ii]); 674 if (res <= 0) 675 break; 676 at += res; 677 } 678 679 return res < 0 ? res : at; 680 } 681 682 static struct ip_hw_instance_attr ip_hw_attr[] = { 683 __ATTR_RO(hw_id), 684 __ATTR_RO(num_instance), 685 __ATTR_RO(major), 686 __ATTR_RO(minor), 687 __ATTR_RO(revision), 688 __ATTR_RO(harvest), 689 __ATTR_RO(num_base_addresses), 690 __ATTR_RO(base_addr), 691 }; 692 693 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 694 ATTRIBUTE_GROUPS(ip_hw_instance); 695 696 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 697 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 698 699 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 700 struct attribute *attr, 701 char *buf) 702 { 703 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 704 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 705 706 if (!ip_hw_attr->show) 707 return -EIO; 708 709 return ip_hw_attr->show(ip_hw_instance, buf); 710 } 711 712 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 713 .show = ip_hw_instance_attr_show, 714 }; 715 716 static void ip_hw_instance_release(struct kobject *kobj) 717 { 718 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 719 720 kfree(ip_hw_instance); 721 } 722 723 static const struct kobj_type ip_hw_instance_ktype = { 724 .release = ip_hw_instance_release, 725 .sysfs_ops = &ip_hw_instance_sysfs_ops, 726 .default_groups = ip_hw_instance_groups, 727 }; 728 729 /* -------------------------------------------------- */ 730 731 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 732 733 static void ip_hw_id_release(struct kobject *kobj) 734 { 735 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 736 737 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 738 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 739 kfree(ip_hw_id); 740 } 741 742 static const struct kobj_type ip_hw_id_ktype = { 743 .release = ip_hw_id_release, 744 .sysfs_ops = &kobj_sysfs_ops, 745 }; 746 747 /* -------------------------------------------------- */ 748 749 static void die_kobj_release(struct kobject *kobj); 750 static void ip_disc_release(struct kobject *kobj); 751 752 struct ip_die_entry_attribute { 753 struct attribute attr; 754 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 755 }; 756 757 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 758 759 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 760 { 761 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 762 } 763 764 /* If there are more ip_die_entry attrs, other than the number of IPs, 765 * we can make this intro an array of attrs, and then initialize 766 * ip_die_entry_attrs in a loop. 767 */ 768 static struct ip_die_entry_attribute num_ips_attr = 769 __ATTR_RO(num_ips); 770 771 static struct attribute *ip_die_entry_attrs[] = { 772 &num_ips_attr.attr, 773 NULL, 774 }; 775 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 776 777 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 778 779 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 780 struct attribute *attr, 781 char *buf) 782 { 783 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 784 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 785 786 if (!ip_die_entry_attr->show) 787 return -EIO; 788 789 return ip_die_entry_attr->show(ip_die_entry, buf); 790 } 791 792 static void ip_die_entry_release(struct kobject *kobj) 793 { 794 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 795 796 if (!list_empty(&ip_die_entry->ip_kset.list)) 797 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 798 kfree(ip_die_entry); 799 } 800 801 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 802 .show = ip_die_entry_attr_show, 803 }; 804 805 static const struct kobj_type ip_die_entry_ktype = { 806 .release = ip_die_entry_release, 807 .sysfs_ops = &ip_die_entry_sysfs_ops, 808 .default_groups = ip_die_entry_groups, 809 }; 810 811 static const struct kobj_type die_kobj_ktype = { 812 .release = die_kobj_release, 813 .sysfs_ops = &kobj_sysfs_ops, 814 }; 815 816 static const struct kobj_type ip_discovery_ktype = { 817 .release = ip_disc_release, 818 .sysfs_ops = &kobj_sysfs_ops, 819 }; 820 821 struct ip_discovery_top { 822 struct kobject kobj; /* ip_discovery/ */ 823 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 824 struct amdgpu_device *adev; 825 }; 826 827 static void die_kobj_release(struct kobject *kobj) 828 { 829 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 830 struct ip_discovery_top, 831 die_kset); 832 if (!list_empty(&ip_top->die_kset.list)) 833 DRM_ERROR("ip_top->die_kset is not empty"); 834 } 835 836 static void ip_disc_release(struct kobject *kobj) 837 { 838 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 839 kobj); 840 struct amdgpu_device *adev = ip_top->adev; 841 842 adev->ip_top = NULL; 843 kfree(ip_top); 844 } 845 846 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 847 struct ip_die_entry *ip_die_entry, 848 const size_t _ip_offset, const int num_ips, 849 bool reg_base_64) 850 { 851 int ii, jj, kk, res; 852 853 DRM_DEBUG("num_ips:%d", num_ips); 854 855 /* Find all IPs of a given HW ID, and add their instance to 856 * #die/#hw_id/#instance/<attributes> 857 */ 858 for (ii = 0; ii < HW_ID_MAX; ii++) { 859 struct ip_hw_id *ip_hw_id = NULL; 860 size_t ip_offset = _ip_offset; 861 862 for (jj = 0; jj < num_ips; jj++) { 863 struct ip_v4 *ip; 864 struct ip_hw_instance *ip_hw_instance; 865 866 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 867 if (amdgpu_discovery_validate_ip(ip) || 868 le16_to_cpu(ip->hw_id) != ii) 869 goto next_ip; 870 871 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 872 873 /* We have a hw_id match; register the hw 874 * block if not yet registered. 875 */ 876 if (!ip_hw_id) { 877 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 878 if (!ip_hw_id) 879 return -ENOMEM; 880 ip_hw_id->hw_id = ii; 881 882 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 883 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 884 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 885 res = kset_register(&ip_hw_id->hw_id_kset); 886 if (res) { 887 DRM_ERROR("Couldn't register ip_hw_id kset"); 888 kfree(ip_hw_id); 889 return res; 890 } 891 if (hw_id_names[ii]) { 892 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 893 &ip_hw_id->hw_id_kset.kobj, 894 hw_id_names[ii]); 895 if (res) { 896 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 897 hw_id_names[ii], 898 kobject_name(&ip_die_entry->ip_kset.kobj)); 899 } 900 } 901 } 902 903 /* Now register its instance. 904 */ 905 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 906 base_addr, 907 ip->num_base_address), 908 GFP_KERNEL); 909 if (!ip_hw_instance) { 910 DRM_ERROR("no memory for ip_hw_instance"); 911 return -ENOMEM; 912 } 913 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 914 ip_hw_instance->num_instance = ip->instance_number; 915 ip_hw_instance->major = ip->major; 916 ip_hw_instance->minor = ip->minor; 917 ip_hw_instance->revision = ip->revision; 918 ip_hw_instance->harvest = ip->variant; 919 ip_hw_instance->num_base_addresses = ip->num_base_address; 920 921 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 922 if (reg_base_64) 923 ip_hw_instance->base_addr[kk] = 924 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 925 else 926 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 927 } 928 929 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 930 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 931 res = kobject_add(&ip_hw_instance->kobj, NULL, 932 "%d", ip_hw_instance->num_instance); 933 next_ip: 934 if (reg_base_64) 935 ip_offset += struct_size(ip, base_address_64, 936 ip->num_base_address); 937 else 938 ip_offset += struct_size(ip, base_address, 939 ip->num_base_address); 940 } 941 } 942 943 return 0; 944 } 945 946 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 947 { 948 struct binary_header *bhdr; 949 struct ip_discovery_header *ihdr; 950 struct die_header *dhdr; 951 struct kset *die_kset = &adev->ip_top->die_kset; 952 u16 num_dies, die_offset, num_ips; 953 size_t ip_offset; 954 int ii, res; 955 956 bhdr = (struct binary_header *)adev->mman.discovery_bin; 957 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 958 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 959 num_dies = le16_to_cpu(ihdr->num_dies); 960 961 DRM_DEBUG("number of dies: %d\n", num_dies); 962 963 for (ii = 0; ii < num_dies; ii++) { 964 struct ip_die_entry *ip_die_entry; 965 966 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 967 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 968 num_ips = le16_to_cpu(dhdr->num_ips); 969 ip_offset = die_offset + sizeof(*dhdr); 970 971 /* Add the die to the kset. 972 * 973 * dhdr->die_id == ii, which was checked in 974 * amdgpu_discovery_reg_base_init(). 975 */ 976 977 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 978 if (!ip_die_entry) 979 return -ENOMEM; 980 981 ip_die_entry->num_ips = num_ips; 982 983 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 984 ip_die_entry->ip_kset.kobj.kset = die_kset; 985 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 986 res = kset_register(&ip_die_entry->ip_kset); 987 if (res) { 988 DRM_ERROR("Couldn't register ip_die_entry kset"); 989 kfree(ip_die_entry); 990 return res; 991 } 992 993 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 994 } 995 996 return 0; 997 } 998 999 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1000 { 1001 struct kset *die_kset; 1002 int res, ii; 1003 1004 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1005 if (!adev->ip_top) 1006 return -ENOMEM; 1007 1008 adev->ip_top->adev = adev; 1009 1010 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1011 &adev->dev->kobj, "ip_discovery"); 1012 if (res) { 1013 DRM_ERROR("Couldn't init and add ip_discovery/"); 1014 goto Err; 1015 } 1016 1017 die_kset = &adev->ip_top->die_kset; 1018 kobject_set_name(&die_kset->kobj, "%s", "die"); 1019 die_kset->kobj.parent = &adev->ip_top->kobj; 1020 die_kset->kobj.ktype = &die_kobj_ktype; 1021 res = kset_register(&adev->ip_top->die_kset); 1022 if (res) { 1023 DRM_ERROR("Couldn't register die_kset"); 1024 goto Err; 1025 } 1026 1027 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1028 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1029 ip_hw_instance_attrs[ii] = NULL; 1030 1031 res = amdgpu_discovery_sysfs_recurse(adev); 1032 1033 return res; 1034 Err: 1035 kobject_put(&adev->ip_top->kobj); 1036 return res; 1037 } 1038 1039 /* -------------------------------------------------- */ 1040 1041 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1042 1043 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1044 { 1045 struct list_head *el, *tmp; 1046 struct kset *hw_id_kset; 1047 1048 hw_id_kset = &ip_hw_id->hw_id_kset; 1049 spin_lock(&hw_id_kset->list_lock); 1050 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1051 list_del_init(el); 1052 spin_unlock(&hw_id_kset->list_lock); 1053 /* kobject is embedded in ip_hw_instance */ 1054 kobject_put(list_to_kobj(el)); 1055 spin_lock(&hw_id_kset->list_lock); 1056 } 1057 spin_unlock(&hw_id_kset->list_lock); 1058 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1059 } 1060 1061 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1062 { 1063 struct list_head *el, *tmp; 1064 struct kset *ip_kset; 1065 1066 ip_kset = &ip_die_entry->ip_kset; 1067 spin_lock(&ip_kset->list_lock); 1068 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1069 list_del_init(el); 1070 spin_unlock(&ip_kset->list_lock); 1071 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1072 spin_lock(&ip_kset->list_lock); 1073 } 1074 spin_unlock(&ip_kset->list_lock); 1075 kobject_put(&ip_die_entry->ip_kset.kobj); 1076 } 1077 1078 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1079 { 1080 struct list_head *el, *tmp; 1081 struct kset *die_kset; 1082 1083 die_kset = &adev->ip_top->die_kset; 1084 spin_lock(&die_kset->list_lock); 1085 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1086 list_del_init(el); 1087 spin_unlock(&die_kset->list_lock); 1088 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1089 spin_lock(&die_kset->list_lock); 1090 } 1091 spin_unlock(&die_kset->list_lock); 1092 kobject_put(&adev->ip_top->die_kset.kobj); 1093 kobject_put(&adev->ip_top->kobj); 1094 } 1095 1096 /* ================================================== */ 1097 1098 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1099 { 1100 struct binary_header *bhdr; 1101 struct ip_discovery_header *ihdr; 1102 struct die_header *dhdr; 1103 struct ip_v4 *ip; 1104 uint16_t die_offset; 1105 uint16_t ip_offset; 1106 uint16_t num_dies; 1107 uint16_t num_ips; 1108 uint8_t num_base_address; 1109 int hw_ip; 1110 int i, j, k; 1111 int r; 1112 1113 r = amdgpu_discovery_init(adev); 1114 if (r) { 1115 DRM_ERROR("amdgpu_discovery_init failed\n"); 1116 return r; 1117 } 1118 1119 adev->gfx.xcc_mask = 0; 1120 adev->sdma.sdma_mask = 0; 1121 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1122 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1123 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1124 num_dies = le16_to_cpu(ihdr->num_dies); 1125 1126 DRM_DEBUG("number of dies: %d\n", num_dies); 1127 1128 for (i = 0; i < num_dies; i++) { 1129 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1130 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1131 num_ips = le16_to_cpu(dhdr->num_ips); 1132 ip_offset = die_offset + sizeof(*dhdr); 1133 1134 if (le16_to_cpu(dhdr->die_id) != i) { 1135 DRM_ERROR("invalid die id %d, expected %d\n", 1136 le16_to_cpu(dhdr->die_id), i); 1137 return -EINVAL; 1138 } 1139 1140 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1141 le16_to_cpu(dhdr->die_id), num_ips); 1142 1143 for (j = 0; j < num_ips; j++) { 1144 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1145 1146 if (amdgpu_discovery_validate_ip(ip)) 1147 goto next_ip; 1148 1149 num_base_address = ip->num_base_address; 1150 1151 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1152 hw_id_names[le16_to_cpu(ip->hw_id)], 1153 le16_to_cpu(ip->hw_id), 1154 ip->instance_number, 1155 ip->major, ip->minor, 1156 ip->revision); 1157 1158 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1159 /* Bit [5:0]: original revision value 1160 * Bit [7:6]: en/decode capability: 1161 * 0b00 : VCN function normally 1162 * 0b10 : encode is disabled 1163 * 0b01 : decode is disabled 1164 */ 1165 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1166 ip->revision & 0xc0; 1167 ip->revision &= ~0xc0; 1168 if (adev->vcn.num_vcn_inst < AMDGPU_MAX_VCN_INSTANCES) 1169 adev->vcn.num_vcn_inst++; 1170 else 1171 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1172 adev->vcn.num_vcn_inst + 1, 1173 AMDGPU_MAX_VCN_INSTANCES); 1174 } 1175 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1176 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1177 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1178 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1179 if (adev->sdma.num_instances < 1180 AMDGPU_MAX_SDMA_INSTANCES) { 1181 adev->sdma.num_instances++; 1182 adev->sdma.sdma_mask |= 1183 (1U << ip->instance_number); 1184 } else { 1185 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1186 adev->sdma.num_instances + 1, 1187 AMDGPU_MAX_SDMA_INSTANCES); 1188 } 1189 } 1190 1191 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1192 adev->gmc.num_umc++; 1193 adev->umc.node_inst_num++; 1194 } 1195 1196 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1197 adev->gfx.xcc_mask |= 1198 (1U << ip->instance_number); 1199 1200 for (k = 0; k < num_base_address; k++) { 1201 /* 1202 * convert the endianness of base addresses in place, 1203 * so that we don't need to convert them when accessing adev->reg_offset. 1204 */ 1205 if (ihdr->base_addr_64_bit) 1206 /* Truncate the 64bit base address from ip discovery 1207 * and only store lower 32bit ip base in reg_offset[]. 1208 * Bits > 32 follows ASIC specific format, thus just 1209 * discard them and handle it within specific ASIC. 1210 * By this way reg_offset[] and related helpers can 1211 * stay unchanged. 1212 * The base address is in dwords, thus clear the 1213 * highest 2 bits to store. 1214 */ 1215 ip->base_address[k] = 1216 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1217 else 1218 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1219 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1220 } 1221 1222 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1223 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1224 hw_id_map[hw_ip] != 0) { 1225 DRM_DEBUG("set register base offset for %s\n", 1226 hw_id_names[le16_to_cpu(ip->hw_id)]); 1227 adev->reg_offset[hw_ip][ip->instance_number] = 1228 ip->base_address; 1229 /* Instance support is somewhat inconsistent. 1230 * SDMA is a good example. Sienna cichlid has 4 total 1231 * SDMA instances, each enumerated separately (HWIDs 1232 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1233 * but they are enumerated as multiple instances of the 1234 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1235 * example. On most chips there are multiple instances 1236 * with the same HWID. 1237 */ 1238 adev->ip_versions[hw_ip][ip->instance_number] = 1239 IP_VERSION(ip->major, ip->minor, ip->revision); 1240 } 1241 } 1242 1243 next_ip: 1244 if (ihdr->base_addr_64_bit) 1245 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1246 else 1247 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1248 } 1249 } 1250 1251 amdgpu_discovery_sysfs_init(adev); 1252 1253 return 0; 1254 } 1255 1256 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1257 { 1258 int vcn_harvest_count = 0; 1259 int umc_harvest_count = 0; 1260 1261 /* 1262 * Harvest table does not fit Navi1x and legacy GPUs, 1263 * so read harvest bit per IP data structure to set 1264 * harvest configuration. 1265 */ 1266 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) && 1267 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) { 1268 if ((adev->pdev->device == 0x731E && 1269 (adev->pdev->revision == 0xC6 || 1270 adev->pdev->revision == 0xC7)) || 1271 (adev->pdev->device == 0x7340 && 1272 adev->pdev->revision == 0xC9) || 1273 (adev->pdev->device == 0x7360 && 1274 adev->pdev->revision == 0xC7)) 1275 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1276 &vcn_harvest_count); 1277 } else { 1278 amdgpu_discovery_read_from_harvest_table(adev, 1279 &vcn_harvest_count, 1280 &umc_harvest_count); 1281 } 1282 1283 amdgpu_discovery_harvest_config_quirk(adev); 1284 1285 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1286 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1287 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1288 } 1289 1290 if (umc_harvest_count < adev->gmc.num_umc) { 1291 adev->gmc.num_umc -= umc_harvest_count; 1292 } 1293 } 1294 1295 union gc_info { 1296 struct gc_info_v1_0 v1; 1297 struct gc_info_v1_1 v1_1; 1298 struct gc_info_v1_2 v1_2; 1299 struct gc_info_v2_0 v2; 1300 }; 1301 1302 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1303 { 1304 struct binary_header *bhdr; 1305 union gc_info *gc_info; 1306 u16 offset; 1307 1308 if (!adev->mman.discovery_bin) { 1309 DRM_ERROR("ip discovery uninitialized\n"); 1310 return -EINVAL; 1311 } 1312 1313 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1314 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1315 1316 if (!offset) 1317 return 0; 1318 1319 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1320 1321 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1322 case 1: 1323 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1324 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1325 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1326 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1327 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1328 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1329 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1330 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1331 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1332 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1333 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1334 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1335 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1336 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1337 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1338 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1339 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1340 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1341 if (gc_info->v1.header.version_minor >= 1) { 1342 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1343 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1344 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1345 } 1346 if (gc_info->v1.header.version_minor >= 2) { 1347 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1348 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1349 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1350 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1351 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1352 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1353 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1354 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1355 } 1356 break; 1357 case 2: 1358 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1359 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1360 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1361 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1362 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1363 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1364 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1365 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1366 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1367 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1368 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1369 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1370 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1371 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1372 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1373 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1374 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1375 break; 1376 default: 1377 dev_err(adev->dev, 1378 "Unhandled GC info table %d.%d\n", 1379 le16_to_cpu(gc_info->v1.header.version_major), 1380 le16_to_cpu(gc_info->v1.header.version_minor)); 1381 return -EINVAL; 1382 } 1383 return 0; 1384 } 1385 1386 union mall_info { 1387 struct mall_info_v1_0 v1; 1388 }; 1389 1390 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1391 { 1392 struct binary_header *bhdr; 1393 union mall_info *mall_info; 1394 u32 u, mall_size_per_umc, m_s_present, half_use; 1395 u64 mall_size; 1396 u16 offset; 1397 1398 if (!adev->mman.discovery_bin) { 1399 DRM_ERROR("ip discovery uninitialized\n"); 1400 return -EINVAL; 1401 } 1402 1403 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1404 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1405 1406 if (!offset) 1407 return 0; 1408 1409 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1410 1411 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1412 case 1: 1413 mall_size = 0; 1414 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1415 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1416 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1417 for (u = 0; u < adev->gmc.num_umc; u++) { 1418 if (m_s_present & (1 << u)) 1419 mall_size += mall_size_per_umc * 2; 1420 else if (half_use & (1 << u)) 1421 mall_size += mall_size_per_umc / 2; 1422 else 1423 mall_size += mall_size_per_umc; 1424 } 1425 adev->gmc.mall_size = mall_size; 1426 break; 1427 default: 1428 dev_err(adev->dev, 1429 "Unhandled MALL info table %d.%d\n", 1430 le16_to_cpu(mall_info->v1.header.version_major), 1431 le16_to_cpu(mall_info->v1.header.version_minor)); 1432 return -EINVAL; 1433 } 1434 return 0; 1435 } 1436 1437 union vcn_info { 1438 struct vcn_info_v1_0 v1; 1439 }; 1440 1441 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1442 { 1443 struct binary_header *bhdr; 1444 union vcn_info *vcn_info; 1445 u16 offset; 1446 int v; 1447 1448 if (!adev->mman.discovery_bin) { 1449 DRM_ERROR("ip discovery uninitialized\n"); 1450 return -EINVAL; 1451 } 1452 1453 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1454 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1455 * but that may change in the future with new GPUs so keep this 1456 * check for defensive purposes. 1457 */ 1458 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1459 dev_err(adev->dev, "invalid vcn instances\n"); 1460 return -EINVAL; 1461 } 1462 1463 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1464 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1465 1466 if (!offset) 1467 return 0; 1468 1469 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1470 1471 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1472 case 1: 1473 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1474 * so this won't overflow. 1475 */ 1476 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1477 adev->vcn.vcn_codec_disable_mask[v] = 1478 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1479 } 1480 break; 1481 default: 1482 dev_err(adev->dev, 1483 "Unhandled VCN info table %d.%d\n", 1484 le16_to_cpu(vcn_info->v1.header.version_major), 1485 le16_to_cpu(vcn_info->v1.header.version_minor)); 1486 return -EINVAL; 1487 } 1488 return 0; 1489 } 1490 1491 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1492 { 1493 /* what IP to use for this? */ 1494 switch (adev->ip_versions[GC_HWIP][0]) { 1495 case IP_VERSION(9, 0, 1): 1496 case IP_VERSION(9, 1, 0): 1497 case IP_VERSION(9, 2, 1): 1498 case IP_VERSION(9, 2, 2): 1499 case IP_VERSION(9, 3, 0): 1500 case IP_VERSION(9, 4, 0): 1501 case IP_VERSION(9, 4, 1): 1502 case IP_VERSION(9, 4, 2): 1503 case IP_VERSION(9, 4, 3): 1504 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1505 break; 1506 case IP_VERSION(10, 1, 10): 1507 case IP_VERSION(10, 1, 1): 1508 case IP_VERSION(10, 1, 2): 1509 case IP_VERSION(10, 1, 3): 1510 case IP_VERSION(10, 1, 4): 1511 case IP_VERSION(10, 3, 0): 1512 case IP_VERSION(10, 3, 1): 1513 case IP_VERSION(10, 3, 2): 1514 case IP_VERSION(10, 3, 3): 1515 case IP_VERSION(10, 3, 4): 1516 case IP_VERSION(10, 3, 5): 1517 case IP_VERSION(10, 3, 6): 1518 case IP_VERSION(10, 3, 7): 1519 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1520 break; 1521 case IP_VERSION(11, 0, 0): 1522 case IP_VERSION(11, 0, 1): 1523 case IP_VERSION(11, 0, 2): 1524 case IP_VERSION(11, 0, 3): 1525 case IP_VERSION(11, 0, 4): 1526 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1527 break; 1528 default: 1529 dev_err(adev->dev, 1530 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1531 adev->ip_versions[GC_HWIP][0]); 1532 return -EINVAL; 1533 } 1534 return 0; 1535 } 1536 1537 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1538 { 1539 /* use GC or MMHUB IP version */ 1540 switch (adev->ip_versions[GC_HWIP][0]) { 1541 case IP_VERSION(9, 0, 1): 1542 case IP_VERSION(9, 1, 0): 1543 case IP_VERSION(9, 2, 1): 1544 case IP_VERSION(9, 2, 2): 1545 case IP_VERSION(9, 3, 0): 1546 case IP_VERSION(9, 4, 0): 1547 case IP_VERSION(9, 4, 1): 1548 case IP_VERSION(9, 4, 2): 1549 case IP_VERSION(9, 4, 3): 1550 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1551 break; 1552 case IP_VERSION(10, 1, 10): 1553 case IP_VERSION(10, 1, 1): 1554 case IP_VERSION(10, 1, 2): 1555 case IP_VERSION(10, 1, 3): 1556 case IP_VERSION(10, 1, 4): 1557 case IP_VERSION(10, 3, 0): 1558 case IP_VERSION(10, 3, 1): 1559 case IP_VERSION(10, 3, 2): 1560 case IP_VERSION(10, 3, 3): 1561 case IP_VERSION(10, 3, 4): 1562 case IP_VERSION(10, 3, 5): 1563 case IP_VERSION(10, 3, 6): 1564 case IP_VERSION(10, 3, 7): 1565 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1566 break; 1567 case IP_VERSION(11, 0, 0): 1568 case IP_VERSION(11, 0, 1): 1569 case IP_VERSION(11, 0, 2): 1570 case IP_VERSION(11, 0, 3): 1571 case IP_VERSION(11, 0, 4): 1572 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1573 break; 1574 default: 1575 dev_err(adev->dev, 1576 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1577 adev->ip_versions[GC_HWIP][0]); 1578 return -EINVAL; 1579 } 1580 return 0; 1581 } 1582 1583 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1584 { 1585 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1586 case IP_VERSION(4, 0, 0): 1587 case IP_VERSION(4, 0, 1): 1588 case IP_VERSION(4, 1, 0): 1589 case IP_VERSION(4, 1, 1): 1590 case IP_VERSION(4, 3, 0): 1591 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1592 break; 1593 case IP_VERSION(4, 2, 0): 1594 case IP_VERSION(4, 2, 1): 1595 case IP_VERSION(4, 4, 0): 1596 case IP_VERSION(4, 4, 2): 1597 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1598 break; 1599 case IP_VERSION(5, 0, 0): 1600 case IP_VERSION(5, 0, 1): 1601 case IP_VERSION(5, 0, 2): 1602 case IP_VERSION(5, 0, 3): 1603 case IP_VERSION(5, 2, 0): 1604 case IP_VERSION(5, 2, 1): 1605 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1606 break; 1607 case IP_VERSION(6, 0, 0): 1608 case IP_VERSION(6, 0, 1): 1609 case IP_VERSION(6, 0, 2): 1610 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1611 break; 1612 default: 1613 dev_err(adev->dev, 1614 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1615 adev->ip_versions[OSSSYS_HWIP][0]); 1616 return -EINVAL; 1617 } 1618 return 0; 1619 } 1620 1621 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1622 { 1623 switch (adev->ip_versions[MP0_HWIP][0]) { 1624 case IP_VERSION(9, 0, 0): 1625 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1626 break; 1627 case IP_VERSION(10, 0, 0): 1628 case IP_VERSION(10, 0, 1): 1629 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1630 break; 1631 case IP_VERSION(11, 0, 0): 1632 case IP_VERSION(11, 0, 2): 1633 case IP_VERSION(11, 0, 4): 1634 case IP_VERSION(11, 0, 5): 1635 case IP_VERSION(11, 0, 9): 1636 case IP_VERSION(11, 0, 7): 1637 case IP_VERSION(11, 0, 11): 1638 case IP_VERSION(11, 0, 12): 1639 case IP_VERSION(11, 0, 13): 1640 case IP_VERSION(11, 5, 0): 1641 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1642 break; 1643 case IP_VERSION(11, 0, 8): 1644 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1645 break; 1646 case IP_VERSION(11, 0, 3): 1647 case IP_VERSION(12, 0, 1): 1648 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1649 break; 1650 case IP_VERSION(13, 0, 0): 1651 case IP_VERSION(13, 0, 1): 1652 case IP_VERSION(13, 0, 2): 1653 case IP_VERSION(13, 0, 3): 1654 case IP_VERSION(13, 0, 5): 1655 case IP_VERSION(13, 0, 6): 1656 case IP_VERSION(13, 0, 7): 1657 case IP_VERSION(13, 0, 8): 1658 case IP_VERSION(13, 0, 10): 1659 case IP_VERSION(13, 0, 11): 1660 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1661 break; 1662 case IP_VERSION(13, 0, 4): 1663 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1664 break; 1665 default: 1666 dev_err(adev->dev, 1667 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1668 adev->ip_versions[MP0_HWIP][0]); 1669 return -EINVAL; 1670 } 1671 return 0; 1672 } 1673 1674 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1675 { 1676 switch (adev->ip_versions[MP1_HWIP][0]) { 1677 case IP_VERSION(9, 0, 0): 1678 case IP_VERSION(10, 0, 0): 1679 case IP_VERSION(10, 0, 1): 1680 case IP_VERSION(11, 0, 2): 1681 if (adev->asic_type == CHIP_ARCTURUS) 1682 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1683 else 1684 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1685 break; 1686 case IP_VERSION(11, 0, 0): 1687 case IP_VERSION(11, 0, 5): 1688 case IP_VERSION(11, 0, 9): 1689 case IP_VERSION(11, 0, 7): 1690 case IP_VERSION(11, 0, 8): 1691 case IP_VERSION(11, 0, 11): 1692 case IP_VERSION(11, 0, 12): 1693 case IP_VERSION(11, 0, 13): 1694 case IP_VERSION(11, 5, 0): 1695 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1696 break; 1697 case IP_VERSION(12, 0, 0): 1698 case IP_VERSION(12, 0, 1): 1699 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1700 break; 1701 case IP_VERSION(13, 0, 0): 1702 case IP_VERSION(13, 0, 1): 1703 case IP_VERSION(13, 0, 2): 1704 case IP_VERSION(13, 0, 3): 1705 case IP_VERSION(13, 0, 4): 1706 case IP_VERSION(13, 0, 5): 1707 case IP_VERSION(13, 0, 7): 1708 case IP_VERSION(13, 0, 8): 1709 case IP_VERSION(13, 0, 10): 1710 case IP_VERSION(13, 0, 11): 1711 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1712 break; 1713 default: 1714 dev_err(adev->dev, 1715 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1716 adev->ip_versions[MP1_HWIP][0]); 1717 return -EINVAL; 1718 } 1719 return 0; 1720 } 1721 1722 #if defined(CONFIG_DRM_AMD_DC) 1723 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1724 { 1725 amdgpu_device_set_sriov_virtual_display(adev); 1726 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1727 } 1728 #endif 1729 1730 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1731 { 1732 if (adev->enable_virtual_display) { 1733 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1734 return 0; 1735 } 1736 1737 if (!amdgpu_device_has_dc_support(adev)) 1738 return 0; 1739 1740 #if defined(CONFIG_DRM_AMD_DC) 1741 if (adev->ip_versions[DCE_HWIP][0]) { 1742 switch (adev->ip_versions[DCE_HWIP][0]) { 1743 case IP_VERSION(1, 0, 0): 1744 case IP_VERSION(1, 0, 1): 1745 case IP_VERSION(2, 0, 2): 1746 case IP_VERSION(2, 0, 0): 1747 case IP_VERSION(2, 0, 3): 1748 case IP_VERSION(2, 1, 0): 1749 case IP_VERSION(3, 0, 0): 1750 case IP_VERSION(3, 0, 2): 1751 case IP_VERSION(3, 0, 3): 1752 case IP_VERSION(3, 0, 1): 1753 case IP_VERSION(3, 1, 2): 1754 case IP_VERSION(3, 1, 3): 1755 case IP_VERSION(3, 1, 4): 1756 case IP_VERSION(3, 1, 5): 1757 case IP_VERSION(3, 1, 6): 1758 case IP_VERSION(3, 2, 0): 1759 case IP_VERSION(3, 2, 1): 1760 if (amdgpu_sriov_vf(adev)) 1761 amdgpu_discovery_set_sriov_display(adev); 1762 else 1763 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1764 break; 1765 default: 1766 dev_err(adev->dev, 1767 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1768 adev->ip_versions[DCE_HWIP][0]); 1769 return -EINVAL; 1770 } 1771 } else if (adev->ip_versions[DCI_HWIP][0]) { 1772 switch (adev->ip_versions[DCI_HWIP][0]) { 1773 case IP_VERSION(12, 0, 0): 1774 case IP_VERSION(12, 0, 1): 1775 case IP_VERSION(12, 1, 0): 1776 if (amdgpu_sriov_vf(adev)) 1777 amdgpu_discovery_set_sriov_display(adev); 1778 else 1779 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1780 break; 1781 default: 1782 dev_err(adev->dev, 1783 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1784 adev->ip_versions[DCI_HWIP][0]); 1785 return -EINVAL; 1786 } 1787 } 1788 #endif 1789 return 0; 1790 } 1791 1792 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1793 { 1794 switch (adev->ip_versions[GC_HWIP][0]) { 1795 case IP_VERSION(9, 0, 1): 1796 case IP_VERSION(9, 1, 0): 1797 case IP_VERSION(9, 2, 1): 1798 case IP_VERSION(9, 2, 2): 1799 case IP_VERSION(9, 3, 0): 1800 case IP_VERSION(9, 4, 0): 1801 case IP_VERSION(9, 4, 1): 1802 case IP_VERSION(9, 4, 2): 1803 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1804 break; 1805 case IP_VERSION(10, 1, 10): 1806 case IP_VERSION(10, 1, 2): 1807 case IP_VERSION(10, 1, 1): 1808 case IP_VERSION(10, 1, 3): 1809 case IP_VERSION(10, 1, 4): 1810 case IP_VERSION(10, 3, 0): 1811 case IP_VERSION(10, 3, 2): 1812 case IP_VERSION(10, 3, 1): 1813 case IP_VERSION(10, 3, 4): 1814 case IP_VERSION(10, 3, 5): 1815 case IP_VERSION(10, 3, 6): 1816 case IP_VERSION(10, 3, 3): 1817 case IP_VERSION(10, 3, 7): 1818 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1819 break; 1820 case IP_VERSION(11, 0, 0): 1821 case IP_VERSION(11, 0, 1): 1822 case IP_VERSION(11, 0, 2): 1823 case IP_VERSION(11, 0, 3): 1824 case IP_VERSION(11, 0, 4): 1825 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1826 break; 1827 default: 1828 dev_err(adev->dev, 1829 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1830 adev->ip_versions[GC_HWIP][0]); 1831 return -EINVAL; 1832 } 1833 return 0; 1834 } 1835 1836 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1837 { 1838 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1839 case IP_VERSION(4, 0, 0): 1840 case IP_VERSION(4, 0, 1): 1841 case IP_VERSION(4, 1, 0): 1842 case IP_VERSION(4, 1, 1): 1843 case IP_VERSION(4, 1, 2): 1844 case IP_VERSION(4, 2, 0): 1845 case IP_VERSION(4, 2, 2): 1846 case IP_VERSION(4, 4, 0): 1847 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1848 break; 1849 case IP_VERSION(4, 4, 2): 1850 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 1851 break; 1852 case IP_VERSION(5, 0, 0): 1853 case IP_VERSION(5, 0, 1): 1854 case IP_VERSION(5, 0, 2): 1855 case IP_VERSION(5, 0, 5): 1856 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1857 break; 1858 case IP_VERSION(5, 2, 0): 1859 case IP_VERSION(5, 2, 2): 1860 case IP_VERSION(5, 2, 4): 1861 case IP_VERSION(5, 2, 5): 1862 case IP_VERSION(5, 2, 6): 1863 case IP_VERSION(5, 2, 3): 1864 case IP_VERSION(5, 2, 1): 1865 case IP_VERSION(5, 2, 7): 1866 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1867 break; 1868 case IP_VERSION(6, 0, 0): 1869 case IP_VERSION(6, 0, 1): 1870 case IP_VERSION(6, 0, 2): 1871 case IP_VERSION(6, 0, 3): 1872 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1873 break; 1874 default: 1875 dev_err(adev->dev, 1876 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1877 adev->ip_versions[SDMA0_HWIP][0]); 1878 return -EINVAL; 1879 } 1880 return 0; 1881 } 1882 1883 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1884 { 1885 if (adev->ip_versions[VCE_HWIP][0]) { 1886 switch (adev->ip_versions[UVD_HWIP][0]) { 1887 case IP_VERSION(7, 0, 0): 1888 case IP_VERSION(7, 2, 0): 1889 /* UVD is not supported on vega20 SR-IOV */ 1890 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1891 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1892 break; 1893 default: 1894 dev_err(adev->dev, 1895 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1896 adev->ip_versions[UVD_HWIP][0]); 1897 return -EINVAL; 1898 } 1899 switch (adev->ip_versions[VCE_HWIP][0]) { 1900 case IP_VERSION(4, 0, 0): 1901 case IP_VERSION(4, 1, 0): 1902 /* VCE is not supported on vega20 SR-IOV */ 1903 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1904 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1905 break; 1906 default: 1907 dev_err(adev->dev, 1908 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1909 adev->ip_versions[VCE_HWIP][0]); 1910 return -EINVAL; 1911 } 1912 } else { 1913 switch (adev->ip_versions[UVD_HWIP][0]) { 1914 case IP_VERSION(1, 0, 0): 1915 case IP_VERSION(1, 0, 1): 1916 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1917 break; 1918 case IP_VERSION(2, 0, 0): 1919 case IP_VERSION(2, 0, 2): 1920 case IP_VERSION(2, 2, 0): 1921 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1922 if (!amdgpu_sriov_vf(adev)) 1923 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1924 break; 1925 case IP_VERSION(2, 0, 3): 1926 break; 1927 case IP_VERSION(2, 5, 0): 1928 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1929 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1930 break; 1931 case IP_VERSION(2, 6, 0): 1932 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1933 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1934 break; 1935 case IP_VERSION(3, 0, 0): 1936 case IP_VERSION(3, 0, 16): 1937 case IP_VERSION(3, 1, 1): 1938 case IP_VERSION(3, 1, 2): 1939 case IP_VERSION(3, 0, 2): 1940 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1941 if (!amdgpu_sriov_vf(adev)) 1942 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1943 break; 1944 case IP_VERSION(3, 0, 33): 1945 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1946 break; 1947 case IP_VERSION(4, 0, 0): 1948 case IP_VERSION(4, 0, 2): 1949 case IP_VERSION(4, 0, 4): 1950 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 1951 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 1952 break; 1953 case IP_VERSION(4, 0, 3): 1954 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 1955 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 1956 break; 1957 default: 1958 dev_err(adev->dev, 1959 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1960 adev->ip_versions[UVD_HWIP][0]); 1961 return -EINVAL; 1962 } 1963 } 1964 return 0; 1965 } 1966 1967 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1968 { 1969 switch (adev->ip_versions[GC_HWIP][0]) { 1970 case IP_VERSION(10, 1, 10): 1971 case IP_VERSION(10, 1, 1): 1972 case IP_VERSION(10, 1, 2): 1973 case IP_VERSION(10, 1, 3): 1974 case IP_VERSION(10, 1, 4): 1975 case IP_VERSION(10, 3, 0): 1976 case IP_VERSION(10, 3, 1): 1977 case IP_VERSION(10, 3, 2): 1978 case IP_VERSION(10, 3, 3): 1979 case IP_VERSION(10, 3, 4): 1980 case IP_VERSION(10, 3, 5): 1981 case IP_VERSION(10, 3, 6): 1982 if (amdgpu_mes) { 1983 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1984 adev->enable_mes = true; 1985 if (amdgpu_mes_kiq) 1986 adev->enable_mes_kiq = true; 1987 } 1988 break; 1989 case IP_VERSION(11, 0, 0): 1990 case IP_VERSION(11, 0, 1): 1991 case IP_VERSION(11, 0, 2): 1992 case IP_VERSION(11, 0, 3): 1993 case IP_VERSION(11, 0, 4): 1994 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 1995 adev->enable_mes = true; 1996 adev->enable_mes_kiq = true; 1997 break; 1998 default: 1999 break; 2000 } 2001 return 0; 2002 } 2003 2004 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2005 { 2006 switch (adev->ip_versions[GC_HWIP][0]) { 2007 case IP_VERSION(9, 4, 3): 2008 aqua_vanjaram_init_soc_config(adev); 2009 break; 2010 default: 2011 break; 2012 } 2013 } 2014 2015 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2016 { 2017 int r; 2018 2019 switch (adev->asic_type) { 2020 case CHIP_VEGA10: 2021 vega10_reg_base_init(adev); 2022 adev->sdma.num_instances = 2; 2023 adev->gmc.num_umc = 4; 2024 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2025 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2026 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2027 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2028 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2029 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2030 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2031 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2032 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2033 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2034 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2035 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2036 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2037 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2038 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2039 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2040 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2041 break; 2042 case CHIP_VEGA12: 2043 vega10_reg_base_init(adev); 2044 adev->sdma.num_instances = 2; 2045 adev->gmc.num_umc = 4; 2046 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2047 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2048 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2049 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2050 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2051 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2052 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2053 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2054 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2055 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2056 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2057 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2058 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2059 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2060 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2061 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2062 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2063 break; 2064 case CHIP_RAVEN: 2065 vega10_reg_base_init(adev); 2066 adev->sdma.num_instances = 1; 2067 adev->vcn.num_vcn_inst = 1; 2068 adev->gmc.num_umc = 2; 2069 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2070 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2071 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2072 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2073 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2074 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2075 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2076 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2077 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2078 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2079 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2080 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2081 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2082 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2083 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2084 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2085 } else { 2086 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2087 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2088 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2089 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2090 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2091 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2092 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2093 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2094 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2095 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2096 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2097 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2098 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2099 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2100 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2101 } 2102 break; 2103 case CHIP_VEGA20: 2104 vega20_reg_base_init(adev); 2105 adev->sdma.num_instances = 2; 2106 adev->gmc.num_umc = 8; 2107 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2108 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2109 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2110 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2111 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2112 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2113 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2114 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2115 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2116 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2117 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2118 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2119 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2120 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2121 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2122 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2123 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2124 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2125 break; 2126 case CHIP_ARCTURUS: 2127 arct_reg_base_init(adev); 2128 adev->sdma.num_instances = 8; 2129 adev->vcn.num_vcn_inst = 2; 2130 adev->gmc.num_umc = 8; 2131 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2132 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2133 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2134 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2135 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2136 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2137 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2138 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2139 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2140 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2141 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2142 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2143 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2144 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2145 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2146 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2147 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2148 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2149 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2150 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2151 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2152 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2153 break; 2154 case CHIP_ALDEBARAN: 2155 aldebaran_reg_base_init(adev); 2156 adev->sdma.num_instances = 5; 2157 adev->vcn.num_vcn_inst = 2; 2158 adev->gmc.num_umc = 4; 2159 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2160 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2161 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2162 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2163 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2164 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2165 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2166 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2167 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2168 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2169 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2170 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2171 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2172 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2173 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2174 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2175 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2176 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2177 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2178 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2179 break; 2180 default: 2181 r = amdgpu_discovery_reg_base_init(adev); 2182 if (r) 2183 return -EINVAL; 2184 2185 amdgpu_discovery_harvest_ip(adev); 2186 amdgpu_discovery_get_gfx_info(adev); 2187 amdgpu_discovery_get_mall_info(adev); 2188 amdgpu_discovery_get_vcn_info(adev); 2189 break; 2190 } 2191 2192 amdgpu_discovery_init_soc_config(adev); 2193 2194 switch (adev->ip_versions[GC_HWIP][0]) { 2195 case IP_VERSION(9, 0, 1): 2196 case IP_VERSION(9, 2, 1): 2197 case IP_VERSION(9, 4, 0): 2198 case IP_VERSION(9, 4, 1): 2199 case IP_VERSION(9, 4, 2): 2200 case IP_VERSION(9, 4, 3): 2201 adev->family = AMDGPU_FAMILY_AI; 2202 break; 2203 case IP_VERSION(9, 1, 0): 2204 case IP_VERSION(9, 2, 2): 2205 case IP_VERSION(9, 3, 0): 2206 adev->family = AMDGPU_FAMILY_RV; 2207 break; 2208 case IP_VERSION(10, 1, 10): 2209 case IP_VERSION(10, 1, 1): 2210 case IP_VERSION(10, 1, 2): 2211 case IP_VERSION(10, 1, 3): 2212 case IP_VERSION(10, 1, 4): 2213 case IP_VERSION(10, 3, 0): 2214 case IP_VERSION(10, 3, 2): 2215 case IP_VERSION(10, 3, 4): 2216 case IP_VERSION(10, 3, 5): 2217 adev->family = AMDGPU_FAMILY_NV; 2218 break; 2219 case IP_VERSION(10, 3, 1): 2220 adev->family = AMDGPU_FAMILY_VGH; 2221 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2222 break; 2223 case IP_VERSION(10, 3, 3): 2224 adev->family = AMDGPU_FAMILY_YC; 2225 break; 2226 case IP_VERSION(10, 3, 6): 2227 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2228 break; 2229 case IP_VERSION(10, 3, 7): 2230 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2231 break; 2232 case IP_VERSION(11, 0, 0): 2233 case IP_VERSION(11, 0, 2): 2234 case IP_VERSION(11, 0, 3): 2235 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2236 break; 2237 case IP_VERSION(11, 0, 1): 2238 case IP_VERSION(11, 0, 4): 2239 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2240 break; 2241 default: 2242 return -EINVAL; 2243 } 2244 2245 switch (adev->ip_versions[GC_HWIP][0]) { 2246 case IP_VERSION(9, 1, 0): 2247 case IP_VERSION(9, 2, 2): 2248 case IP_VERSION(9, 3, 0): 2249 case IP_VERSION(10, 1, 3): 2250 case IP_VERSION(10, 1, 4): 2251 case IP_VERSION(10, 3, 1): 2252 case IP_VERSION(10, 3, 3): 2253 case IP_VERSION(10, 3, 6): 2254 case IP_VERSION(10, 3, 7): 2255 case IP_VERSION(11, 0, 1): 2256 case IP_VERSION(11, 0, 4): 2257 adev->flags |= AMD_IS_APU; 2258 break; 2259 default: 2260 break; 2261 } 2262 2263 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2264 adev->gmc.xgmi.supported = true; 2265 2266 /* set NBIO version */ 2267 switch (adev->ip_versions[NBIO_HWIP][0]) { 2268 case IP_VERSION(6, 1, 0): 2269 case IP_VERSION(6, 2, 0): 2270 adev->nbio.funcs = &nbio_v6_1_funcs; 2271 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2272 break; 2273 case IP_VERSION(7, 0, 0): 2274 case IP_VERSION(7, 0, 1): 2275 case IP_VERSION(2, 5, 0): 2276 adev->nbio.funcs = &nbio_v7_0_funcs; 2277 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2278 break; 2279 case IP_VERSION(7, 4, 0): 2280 case IP_VERSION(7, 4, 1): 2281 case IP_VERSION(7, 4, 4): 2282 adev->nbio.funcs = &nbio_v7_4_funcs; 2283 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2284 break; 2285 case IP_VERSION(7, 9, 0): 2286 adev->nbio.funcs = &nbio_v7_9_funcs; 2287 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2288 break; 2289 case IP_VERSION(7, 2, 0): 2290 case IP_VERSION(7, 2, 1): 2291 case IP_VERSION(7, 3, 0): 2292 case IP_VERSION(7, 5, 0): 2293 case IP_VERSION(7, 5, 1): 2294 adev->nbio.funcs = &nbio_v7_2_funcs; 2295 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2296 break; 2297 case IP_VERSION(2, 1, 1): 2298 case IP_VERSION(2, 3, 0): 2299 case IP_VERSION(2, 3, 1): 2300 case IP_VERSION(2, 3, 2): 2301 case IP_VERSION(3, 3, 0): 2302 case IP_VERSION(3, 3, 1): 2303 case IP_VERSION(3, 3, 2): 2304 case IP_VERSION(3, 3, 3): 2305 adev->nbio.funcs = &nbio_v2_3_funcs; 2306 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2307 break; 2308 case IP_VERSION(4, 3, 0): 2309 case IP_VERSION(4, 3, 1): 2310 if (amdgpu_sriov_vf(adev)) 2311 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2312 else 2313 adev->nbio.funcs = &nbio_v4_3_funcs; 2314 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2315 break; 2316 case IP_VERSION(7, 7, 0): 2317 case IP_VERSION(7, 7, 1): 2318 adev->nbio.funcs = &nbio_v7_7_funcs; 2319 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2320 break; 2321 default: 2322 break; 2323 } 2324 2325 switch (adev->ip_versions[HDP_HWIP][0]) { 2326 case IP_VERSION(4, 0, 0): 2327 case IP_VERSION(4, 0, 1): 2328 case IP_VERSION(4, 1, 0): 2329 case IP_VERSION(4, 1, 1): 2330 case IP_VERSION(4, 1, 2): 2331 case IP_VERSION(4, 2, 0): 2332 case IP_VERSION(4, 2, 1): 2333 case IP_VERSION(4, 4, 0): 2334 case IP_VERSION(4, 4, 2): 2335 adev->hdp.funcs = &hdp_v4_0_funcs; 2336 break; 2337 case IP_VERSION(5, 0, 0): 2338 case IP_VERSION(5, 0, 1): 2339 case IP_VERSION(5, 0, 2): 2340 case IP_VERSION(5, 0, 3): 2341 case IP_VERSION(5, 0, 4): 2342 case IP_VERSION(5, 2, 0): 2343 adev->hdp.funcs = &hdp_v5_0_funcs; 2344 break; 2345 case IP_VERSION(5, 2, 1): 2346 adev->hdp.funcs = &hdp_v5_2_funcs; 2347 break; 2348 case IP_VERSION(6, 0, 0): 2349 case IP_VERSION(6, 0, 1): 2350 adev->hdp.funcs = &hdp_v6_0_funcs; 2351 break; 2352 default: 2353 break; 2354 } 2355 2356 switch (adev->ip_versions[DF_HWIP][0]) { 2357 case IP_VERSION(3, 6, 0): 2358 case IP_VERSION(3, 6, 1): 2359 case IP_VERSION(3, 6, 2): 2360 adev->df.funcs = &df_v3_6_funcs; 2361 break; 2362 case IP_VERSION(2, 1, 0): 2363 case IP_VERSION(2, 1, 1): 2364 case IP_VERSION(2, 5, 0): 2365 case IP_VERSION(3, 5, 1): 2366 case IP_VERSION(3, 5, 2): 2367 adev->df.funcs = &df_v1_7_funcs; 2368 break; 2369 case IP_VERSION(4, 3, 0): 2370 adev->df.funcs = &df_v4_3_funcs; 2371 break; 2372 default: 2373 break; 2374 } 2375 2376 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2377 case IP_VERSION(9, 0, 0): 2378 case IP_VERSION(9, 0, 1): 2379 case IP_VERSION(10, 0, 0): 2380 case IP_VERSION(10, 0, 1): 2381 case IP_VERSION(10, 0, 2): 2382 adev->smuio.funcs = &smuio_v9_0_funcs; 2383 break; 2384 case IP_VERSION(11, 0, 0): 2385 case IP_VERSION(11, 0, 2): 2386 case IP_VERSION(11, 0, 3): 2387 case IP_VERSION(11, 0, 4): 2388 case IP_VERSION(11, 0, 7): 2389 case IP_VERSION(11, 0, 8): 2390 adev->smuio.funcs = &smuio_v11_0_funcs; 2391 break; 2392 case IP_VERSION(11, 0, 6): 2393 case IP_VERSION(11, 0, 10): 2394 case IP_VERSION(11, 0, 11): 2395 case IP_VERSION(11, 5, 0): 2396 case IP_VERSION(13, 0, 1): 2397 case IP_VERSION(13, 0, 9): 2398 case IP_VERSION(13, 0, 10): 2399 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2400 break; 2401 case IP_VERSION(13, 0, 2): 2402 adev->smuio.funcs = &smuio_v13_0_funcs; 2403 break; 2404 case IP_VERSION(13, 0, 3): 2405 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2406 break; 2407 case IP_VERSION(13, 0, 6): 2408 case IP_VERSION(13, 0, 8): 2409 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2410 break; 2411 default: 2412 break; 2413 } 2414 2415 switch (adev->ip_versions[LSDMA_HWIP][0]) { 2416 case IP_VERSION(6, 0, 0): 2417 case IP_VERSION(6, 0, 1): 2418 case IP_VERSION(6, 0, 2): 2419 case IP_VERSION(6, 0, 3): 2420 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2421 break; 2422 default: 2423 break; 2424 } 2425 2426 r = amdgpu_discovery_set_common_ip_blocks(adev); 2427 if (r) 2428 return r; 2429 2430 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2431 if (r) 2432 return r; 2433 2434 /* For SR-IOV, PSP needs to be initialized before IH */ 2435 if (amdgpu_sriov_vf(adev)) { 2436 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2437 if (r) 2438 return r; 2439 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2440 if (r) 2441 return r; 2442 } else { 2443 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2444 if (r) 2445 return r; 2446 2447 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2448 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2449 if (r) 2450 return r; 2451 } 2452 } 2453 2454 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2455 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2456 if (r) 2457 return r; 2458 } 2459 2460 r = amdgpu_discovery_set_display_ip_blocks(adev); 2461 if (r) 2462 return r; 2463 2464 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2465 if (r) 2466 return r; 2467 2468 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2469 if (r) 2470 return r; 2471 2472 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2473 !amdgpu_sriov_vf(adev)) || 2474 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2475 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2476 if (r) 2477 return r; 2478 } 2479 2480 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2481 if (r) 2482 return r; 2483 2484 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2485 if (r) 2486 return r; 2487 2488 return 0; 2489 } 2490 2491