1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gfxhub_v2_0.h" 51 #include "mmhub_v2_0.h" 52 #include "nbio_v2_3.h" 53 #include "nbio_v7_2.h" 54 #include "hdp_v5_0.h" 55 #include "nv.h" 56 #include "navi10_ih.h" 57 #include "gfx_v10_0.h" 58 #include "sdma_v5_0.h" 59 #include "sdma_v5_2.h" 60 #include "vcn_v2_0.h" 61 #include "jpeg_v2_0.h" 62 #include "vcn_v3_0.h" 63 #include "jpeg_v3_0.h" 64 #include "amdgpu_vkms.h" 65 #include "mes_v10_1.h" 66 #include "smuio_v11_0.h" 67 #include "smuio_v11_0_6.h" 68 #include "smuio_v13_0.h" 69 70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 72 73 #define mmRCC_CONFIG_MEMSIZE 0xde3 74 #define mmMM_INDEX 0x0 75 #define mmMM_INDEX_HI 0x6 76 #define mmMM_DATA 0x1 77 78 static const char *hw_id_names[HW_ID_MAX] = { 79 [MP1_HWID] = "MP1", 80 [MP2_HWID] = "MP2", 81 [THM_HWID] = "THM", 82 [SMUIO_HWID] = "SMUIO", 83 [FUSE_HWID] = "FUSE", 84 [CLKA_HWID] = "CLKA", 85 [PWR_HWID] = "PWR", 86 [GC_HWID] = "GC", 87 [UVD_HWID] = "UVD", 88 [AUDIO_AZ_HWID] = "AUDIO_AZ", 89 [ACP_HWID] = "ACP", 90 [DCI_HWID] = "DCI", 91 [DMU_HWID] = "DMU", 92 [DCO_HWID] = "DCO", 93 [DIO_HWID] = "DIO", 94 [XDMA_HWID] = "XDMA", 95 [DCEAZ_HWID] = "DCEAZ", 96 [DAZ_HWID] = "DAZ", 97 [SDPMUX_HWID] = "SDPMUX", 98 [NTB_HWID] = "NTB", 99 [IOHC_HWID] = "IOHC", 100 [L2IMU_HWID] = "L2IMU", 101 [VCE_HWID] = "VCE", 102 [MMHUB_HWID] = "MMHUB", 103 [ATHUB_HWID] = "ATHUB", 104 [DBGU_NBIO_HWID] = "DBGU_NBIO", 105 [DFX_HWID] = "DFX", 106 [DBGU0_HWID] = "DBGU0", 107 [DBGU1_HWID] = "DBGU1", 108 [OSSSYS_HWID] = "OSSSYS", 109 [HDP_HWID] = "HDP", 110 [SDMA0_HWID] = "SDMA0", 111 [SDMA1_HWID] = "SDMA1", 112 [SDMA2_HWID] = "SDMA2", 113 [SDMA3_HWID] = "SDMA3", 114 [ISP_HWID] = "ISP", 115 [DBGU_IO_HWID] = "DBGU_IO", 116 [DF_HWID] = "DF", 117 [CLKB_HWID] = "CLKB", 118 [FCH_HWID] = "FCH", 119 [DFX_DAP_HWID] = "DFX_DAP", 120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 123 [L1IMU3_HWID] = "L1IMU3", 124 [L1IMU4_HWID] = "L1IMU4", 125 [L1IMU5_HWID] = "L1IMU5", 126 [L1IMU6_HWID] = "L1IMU6", 127 [L1IMU7_HWID] = "L1IMU7", 128 [L1IMU8_HWID] = "L1IMU8", 129 [L1IMU9_HWID] = "L1IMU9", 130 [L1IMU10_HWID] = "L1IMU10", 131 [L1IMU11_HWID] = "L1IMU11", 132 [L1IMU12_HWID] = "L1IMU12", 133 [L1IMU13_HWID] = "L1IMU13", 134 [L1IMU14_HWID] = "L1IMU14", 135 [L1IMU15_HWID] = "L1IMU15", 136 [WAFLC_HWID] = "WAFLC", 137 [FCH_USB_PD_HWID] = "FCH_USB_PD", 138 [PCIE_HWID] = "PCIE", 139 [PCS_HWID] = "PCS", 140 [DDCL_HWID] = "DDCL", 141 [SST_HWID] = "SST", 142 [IOAGR_HWID] = "IOAGR", 143 [NBIF_HWID] = "NBIF", 144 [IOAPIC_HWID] = "IOAPIC", 145 [SYSTEMHUB_HWID] = "SYSTEMHUB", 146 [NTBCCP_HWID] = "NTBCCP", 147 [UMC_HWID] = "UMC", 148 [SATA_HWID] = "SATA", 149 [USB_HWID] = "USB", 150 [CCXSEC_HWID] = "CCXSEC", 151 [XGMI_HWID] = "XGMI", 152 [XGBE_HWID] = "XGBE", 153 [MP0_HWID] = "MP0", 154 }; 155 156 static int hw_id_map[MAX_HWIP] = { 157 [GC_HWIP] = GC_HWID, 158 [HDP_HWIP] = HDP_HWID, 159 [SDMA0_HWIP] = SDMA0_HWID, 160 [SDMA1_HWIP] = SDMA1_HWID, 161 [SDMA2_HWIP] = SDMA2_HWID, 162 [SDMA3_HWIP] = SDMA3_HWID, 163 [MMHUB_HWIP] = MMHUB_HWID, 164 [ATHUB_HWIP] = ATHUB_HWID, 165 [NBIO_HWIP] = NBIF_HWID, 166 [MP0_HWIP] = MP0_HWID, 167 [MP1_HWIP] = MP1_HWID, 168 [UVD_HWIP] = UVD_HWID, 169 [VCE_HWIP] = VCE_HWID, 170 [DF_HWIP] = DF_HWID, 171 [DCE_HWIP] = DMU_HWID, 172 [OSSSYS_HWIP] = OSSSYS_HWID, 173 [SMUIO_HWIP] = SMUIO_HWID, 174 [PWR_HWIP] = PWR_HWID, 175 [NBIF_HWIP] = NBIF_HWID, 176 [THM_HWIP] = THM_HWID, 177 [CLK_HWIP] = CLKA_HWID, 178 [UMC_HWIP] = UMC_HWID, 179 [XGMI_HWIP] = XGMI_HWID, 180 [DCI_HWIP] = DCI_HWID, 181 }; 182 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 184 { 185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 187 188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 189 adev->mman.discovery_tmr_size, false); 190 return 0; 191 } 192 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 194 { 195 const struct firmware *fw; 196 const char *fw_name; 197 int r; 198 199 switch (amdgpu_discovery) { 200 case 2: 201 fw_name = FIRMWARE_IP_DISCOVERY; 202 break; 203 default: 204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 205 return -EINVAL; 206 } 207 208 r = request_firmware(&fw, fw_name, adev->dev); 209 if (r) { 210 dev_err(adev->dev, "can't load firmware \"%s\"\n", 211 fw_name); 212 return r; 213 } 214 215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 216 release_firmware(fw); 217 218 return 0; 219 } 220 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 222 { 223 uint16_t checksum = 0; 224 int i; 225 226 for (i = 0; i < size; i++) 227 checksum += data[i]; 228 229 return checksum; 230 } 231 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 233 uint16_t expected) 234 { 235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 236 } 237 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 239 { 240 struct binary_header *bhdr; 241 bhdr = (struct binary_header *)binary; 242 243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 244 } 245 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 247 { 248 /* 249 * So far, apply this quirk only on those Navy Flounder boards which 250 * have a bad harvest table of VCN config. 251 */ 252 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 253 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 254 switch (adev->pdev->revision) { 255 case 0xC1: 256 case 0xC2: 257 case 0xC3: 258 case 0xC5: 259 case 0xC7: 260 case 0xCF: 261 case 0xDF: 262 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 263 break; 264 default: 265 break; 266 } 267 } 268 } 269 270 static int amdgpu_discovery_init(struct amdgpu_device *adev) 271 { 272 struct table_info *info; 273 struct binary_header *bhdr; 274 struct ip_discovery_header *ihdr; 275 struct gpu_info_header *ghdr; 276 uint16_t offset; 277 uint16_t size; 278 uint16_t checksum; 279 int r; 280 281 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 282 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 283 if (!adev->mman.discovery_bin) 284 return -ENOMEM; 285 286 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 287 if (r) { 288 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 289 r = -EINVAL; 290 goto out; 291 } 292 293 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 294 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 295 /* retry read ip discovery binary from file */ 296 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 297 if (r) { 298 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 299 r = -EINVAL; 300 goto out; 301 } 302 /* check the ip discovery binary signature */ 303 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 304 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 305 r = -EINVAL; 306 goto out; 307 } 308 } 309 310 bhdr = (struct binary_header *)adev->mman.discovery_bin; 311 312 offset = offsetof(struct binary_header, binary_checksum) + 313 sizeof(bhdr->binary_checksum); 314 size = le16_to_cpu(bhdr->binary_size) - offset; 315 checksum = le16_to_cpu(bhdr->binary_checksum); 316 317 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 318 size, checksum)) { 319 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 320 r = -EINVAL; 321 goto out; 322 } 323 324 info = &bhdr->table_list[IP_DISCOVERY]; 325 offset = le16_to_cpu(info->offset); 326 checksum = le16_to_cpu(info->checksum); 327 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 328 329 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 330 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 331 r = -EINVAL; 332 goto out; 333 } 334 335 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 336 le16_to_cpu(ihdr->size), checksum)) { 337 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 338 r = -EINVAL; 339 goto out; 340 } 341 342 info = &bhdr->table_list[GC]; 343 offset = le16_to_cpu(info->offset); 344 checksum = le16_to_cpu(info->checksum); 345 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 346 347 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 348 le32_to_cpu(ghdr->size), checksum)) { 349 dev_err(adev->dev, "invalid gc data table checksum\n"); 350 r = -EINVAL; 351 goto out; 352 } 353 354 return 0; 355 356 out: 357 kfree(adev->mman.discovery_bin); 358 adev->mman.discovery_bin = NULL; 359 360 return r; 361 } 362 363 void amdgpu_discovery_fini(struct amdgpu_device *adev) 364 { 365 kfree(adev->mman.discovery_bin); 366 adev->mman.discovery_bin = NULL; 367 } 368 369 static int amdgpu_discovery_validate_ip(const struct ip *ip) 370 { 371 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 372 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 373 ip->number_instance); 374 return -EINVAL; 375 } 376 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 377 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 378 le16_to_cpu(ip->hw_id)); 379 return -EINVAL; 380 } 381 382 return 0; 383 } 384 385 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 386 { 387 struct binary_header *bhdr; 388 struct ip_discovery_header *ihdr; 389 struct die_header *dhdr; 390 struct ip *ip; 391 uint16_t die_offset; 392 uint16_t ip_offset; 393 uint16_t num_dies; 394 uint16_t num_ips; 395 uint8_t num_base_address; 396 int hw_ip; 397 int i, j, k; 398 int r; 399 400 r = amdgpu_discovery_init(adev); 401 if (r) { 402 DRM_ERROR("amdgpu_discovery_init failed\n"); 403 return r; 404 } 405 406 bhdr = (struct binary_header *)adev->mman.discovery_bin; 407 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 408 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 409 num_dies = le16_to_cpu(ihdr->num_dies); 410 411 DRM_DEBUG("number of dies: %d\n", num_dies); 412 413 for (i = 0; i < num_dies; i++) { 414 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 415 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 416 num_ips = le16_to_cpu(dhdr->num_ips); 417 ip_offset = die_offset + sizeof(*dhdr); 418 419 if (le16_to_cpu(dhdr->die_id) != i) { 420 DRM_ERROR("invalid die id %d, expected %d\n", 421 le16_to_cpu(dhdr->die_id), i); 422 return -EINVAL; 423 } 424 425 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 426 le16_to_cpu(dhdr->die_id), num_ips); 427 428 for (j = 0; j < num_ips; j++) { 429 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 430 431 if (amdgpu_discovery_validate_ip(ip)) 432 goto next_ip; 433 434 num_base_address = ip->num_base_address; 435 436 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 437 hw_id_names[le16_to_cpu(ip->hw_id)], 438 le16_to_cpu(ip->hw_id), 439 ip->number_instance, 440 ip->major, ip->minor, 441 ip->revision); 442 443 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 444 /* Bit [5:0]: original revision value 445 * Bit [7:6]: en/decode capability: 446 * 0b00 : VCN function normally 447 * 0b10 : encode is disabled 448 * 0b01 : decode is disabled 449 */ 450 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 451 ip->revision & 0xc0; 452 ip->revision &= ~0xc0; 453 adev->vcn.num_vcn_inst++; 454 } 455 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 456 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 457 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 458 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 459 adev->sdma.num_instances++; 460 461 for (k = 0; k < num_base_address; k++) { 462 /* 463 * convert the endianness of base addresses in place, 464 * so that we don't need to convert them when accessing adev->reg_offset. 465 */ 466 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 467 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 468 } 469 470 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 471 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 472 DRM_DEBUG("set register base offset for %s\n", 473 hw_id_names[le16_to_cpu(ip->hw_id)]); 474 adev->reg_offset[hw_ip][ip->number_instance] = 475 ip->base_address; 476 /* Instance support is somewhat inconsistent. 477 * SDMA is a good example. Sienna cichlid has 4 total 478 * SDMA instances, each enumerated separately (HWIDs 479 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 480 * but they are enumerated as multiple instances of the 481 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 482 * example. On most chips there are multiple instances 483 * with the same HWID. 484 */ 485 adev->ip_versions[hw_ip][ip->number_instance] = 486 IP_VERSION(ip->major, ip->minor, ip->revision); 487 } 488 } 489 490 next_ip: 491 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 492 } 493 } 494 495 return 0; 496 } 497 498 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 499 int *major, int *minor, int *revision) 500 { 501 struct binary_header *bhdr; 502 struct ip_discovery_header *ihdr; 503 struct die_header *dhdr; 504 struct ip *ip; 505 uint16_t die_offset; 506 uint16_t ip_offset; 507 uint16_t num_dies; 508 uint16_t num_ips; 509 int i, j; 510 511 if (!adev->mman.discovery_bin) { 512 DRM_ERROR("ip discovery uninitialized\n"); 513 return -EINVAL; 514 } 515 516 bhdr = (struct binary_header *)adev->mman.discovery_bin; 517 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 518 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 519 num_dies = le16_to_cpu(ihdr->num_dies); 520 521 for (i = 0; i < num_dies; i++) { 522 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 523 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 524 num_ips = le16_to_cpu(dhdr->num_ips); 525 ip_offset = die_offset + sizeof(*dhdr); 526 527 for (j = 0; j < num_ips; j++) { 528 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 529 530 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 531 if (major) 532 *major = ip->major; 533 if (minor) 534 *minor = ip->minor; 535 if (revision) 536 *revision = ip->revision; 537 return 0; 538 } 539 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 540 } 541 } 542 543 return -EINVAL; 544 } 545 546 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 547 { 548 struct binary_header *bhdr; 549 struct harvest_table *harvest_info; 550 int i, vcn_harvest_count = 0; 551 552 bhdr = (struct binary_header *)adev->mman.discovery_bin; 553 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + 554 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset)); 555 556 for (i = 0; i < 32; i++) { 557 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 558 break; 559 560 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 561 case VCN_HWID: 562 vcn_harvest_count++; 563 if (harvest_info->list[i].number_instance == 0) 564 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 565 else 566 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 567 break; 568 case DMU_HWID: 569 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 570 break; 571 default: 572 break; 573 } 574 } 575 576 amdgpu_discovery_harvest_config_quirk(adev); 577 578 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 579 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 580 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 581 } 582 if ((adev->pdev->device == 0x731E && 583 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) || 584 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) || 585 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) { 586 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 587 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 588 } 589 } 590 591 union gc_info { 592 struct gc_info_v1_0 v1; 593 struct gc_info_v2_0 v2; 594 }; 595 596 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 597 { 598 struct binary_header *bhdr; 599 union gc_info *gc_info; 600 601 if (!adev->mman.discovery_bin) { 602 DRM_ERROR("ip discovery uninitialized\n"); 603 return -EINVAL; 604 } 605 606 bhdr = (struct binary_header *)adev->mman.discovery_bin; 607 gc_info = (union gc_info *)(adev->mman.discovery_bin + 608 le16_to_cpu(bhdr->table_list[GC].offset)); 609 switch (gc_info->v1.header.version_major) { 610 case 1: 611 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 612 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 613 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 614 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 615 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 616 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 617 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 618 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 619 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 620 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 621 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 622 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 623 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 624 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 625 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 626 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 627 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 628 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 629 break; 630 case 2: 631 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 632 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 633 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 634 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 635 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 636 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 637 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 638 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 639 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 640 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 641 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 642 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 643 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 644 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 645 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 646 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 647 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 648 break; 649 default: 650 dev_err(adev->dev, 651 "Unhandled GC info table %d.%d\n", 652 gc_info->v1.header.version_major, 653 gc_info->v1.header.version_minor); 654 return -EINVAL; 655 } 656 return 0; 657 } 658 659 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 660 { 661 /* what IP to use for this? */ 662 switch (adev->ip_versions[GC_HWIP][0]) { 663 case IP_VERSION(9, 0, 1): 664 case IP_VERSION(9, 1, 0): 665 case IP_VERSION(9, 2, 1): 666 case IP_VERSION(9, 2, 2): 667 case IP_VERSION(9, 3, 0): 668 case IP_VERSION(9, 4, 0): 669 case IP_VERSION(9, 4, 1): 670 case IP_VERSION(9, 4, 2): 671 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 672 break; 673 case IP_VERSION(10, 1, 10): 674 case IP_VERSION(10, 1, 1): 675 case IP_VERSION(10, 1, 2): 676 case IP_VERSION(10, 1, 3): 677 case IP_VERSION(10, 3, 0): 678 case IP_VERSION(10, 3, 1): 679 case IP_VERSION(10, 3, 2): 680 case IP_VERSION(10, 3, 3): 681 case IP_VERSION(10, 3, 4): 682 case IP_VERSION(10, 3, 5): 683 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 684 break; 685 default: 686 dev_err(adev->dev, 687 "Failed to add common ip block(GC_HWIP:0x%x)\n", 688 adev->ip_versions[GC_HWIP][0]); 689 return -EINVAL; 690 } 691 return 0; 692 } 693 694 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 695 { 696 /* use GC or MMHUB IP version */ 697 switch (adev->ip_versions[GC_HWIP][0]) { 698 case IP_VERSION(9, 0, 1): 699 case IP_VERSION(9, 1, 0): 700 case IP_VERSION(9, 2, 1): 701 case IP_VERSION(9, 2, 2): 702 case IP_VERSION(9, 3, 0): 703 case IP_VERSION(9, 4, 0): 704 case IP_VERSION(9, 4, 1): 705 case IP_VERSION(9, 4, 2): 706 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 707 break; 708 case IP_VERSION(10, 1, 10): 709 case IP_VERSION(10, 1, 1): 710 case IP_VERSION(10, 1, 2): 711 case IP_VERSION(10, 1, 3): 712 case IP_VERSION(10, 3, 0): 713 case IP_VERSION(10, 3, 1): 714 case IP_VERSION(10, 3, 2): 715 case IP_VERSION(10, 3, 3): 716 case IP_VERSION(10, 3, 4): 717 case IP_VERSION(10, 3, 5): 718 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 719 break; 720 default: 721 dev_err(adev->dev, 722 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 723 adev->ip_versions[GC_HWIP][0]); 724 return -EINVAL; 725 } 726 return 0; 727 } 728 729 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 730 { 731 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 732 case IP_VERSION(4, 0, 0): 733 case IP_VERSION(4, 0, 1): 734 case IP_VERSION(4, 1, 0): 735 case IP_VERSION(4, 1, 1): 736 case IP_VERSION(4, 3, 0): 737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 738 break; 739 case IP_VERSION(4, 2, 0): 740 case IP_VERSION(4, 2, 1): 741 case IP_VERSION(4, 4, 0): 742 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 743 break; 744 case IP_VERSION(5, 0, 0): 745 case IP_VERSION(5, 0, 1): 746 case IP_VERSION(5, 0, 2): 747 case IP_VERSION(5, 0, 3): 748 case IP_VERSION(5, 2, 0): 749 case IP_VERSION(5, 2, 1): 750 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 751 break; 752 default: 753 dev_err(adev->dev, 754 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 755 adev->ip_versions[OSSSYS_HWIP][0]); 756 return -EINVAL; 757 } 758 return 0; 759 } 760 761 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 762 { 763 switch (adev->ip_versions[MP0_HWIP][0]) { 764 case IP_VERSION(9, 0, 0): 765 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 766 break; 767 case IP_VERSION(10, 0, 0): 768 case IP_VERSION(10, 0, 1): 769 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 770 break; 771 case IP_VERSION(11, 0, 0): 772 case IP_VERSION(11, 0, 2): 773 case IP_VERSION(11, 0, 4): 774 case IP_VERSION(11, 0, 5): 775 case IP_VERSION(11, 0, 9): 776 case IP_VERSION(11, 0, 7): 777 case IP_VERSION(11, 0, 11): 778 case IP_VERSION(11, 0, 12): 779 case IP_VERSION(11, 0, 13): 780 case IP_VERSION(11, 5, 0): 781 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 782 break; 783 case IP_VERSION(11, 0, 8): 784 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 785 break; 786 case IP_VERSION(11, 0, 3): 787 case IP_VERSION(12, 0, 1): 788 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 789 break; 790 case IP_VERSION(13, 0, 1): 791 case IP_VERSION(13, 0, 2): 792 case IP_VERSION(13, 0, 3): 793 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 794 break; 795 default: 796 dev_err(adev->dev, 797 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 798 adev->ip_versions[MP0_HWIP][0]); 799 return -EINVAL; 800 } 801 return 0; 802 } 803 804 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 805 { 806 switch (adev->ip_versions[MP1_HWIP][0]) { 807 case IP_VERSION(9, 0, 0): 808 case IP_VERSION(10, 0, 0): 809 case IP_VERSION(10, 0, 1): 810 case IP_VERSION(11, 0, 2): 811 if (adev->asic_type == CHIP_ARCTURUS) 812 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 813 else 814 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 815 break; 816 case IP_VERSION(11, 0, 0): 817 case IP_VERSION(11, 0, 5): 818 case IP_VERSION(11, 0, 9): 819 case IP_VERSION(11, 0, 7): 820 case IP_VERSION(11, 0, 8): 821 case IP_VERSION(11, 0, 11): 822 case IP_VERSION(11, 0, 12): 823 case IP_VERSION(11, 0, 13): 824 case IP_VERSION(11, 5, 0): 825 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 826 break; 827 case IP_VERSION(12, 0, 0): 828 case IP_VERSION(12, 0, 1): 829 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 830 break; 831 case IP_VERSION(13, 0, 1): 832 case IP_VERSION(13, 0, 2): 833 case IP_VERSION(13, 0, 3): 834 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 835 break; 836 default: 837 dev_err(adev->dev, 838 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 839 adev->ip_versions[MP1_HWIP][0]); 840 return -EINVAL; 841 } 842 return 0; 843 } 844 845 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 846 { 847 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 848 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 849 return 0; 850 } 851 852 if (!amdgpu_device_has_dc_support(adev)) 853 return 0; 854 855 #if defined(CONFIG_DRM_AMD_DC) 856 if (adev->ip_versions[DCE_HWIP][0]) { 857 switch (adev->ip_versions[DCE_HWIP][0]) { 858 case IP_VERSION(1, 0, 0): 859 case IP_VERSION(1, 0, 1): 860 case IP_VERSION(2, 0, 2): 861 case IP_VERSION(2, 0, 0): 862 case IP_VERSION(2, 0, 3): 863 case IP_VERSION(2, 1, 0): 864 case IP_VERSION(3, 0, 0): 865 case IP_VERSION(3, 0, 2): 866 case IP_VERSION(3, 0, 3): 867 case IP_VERSION(3, 0, 1): 868 case IP_VERSION(3, 1, 2): 869 case IP_VERSION(3, 1, 3): 870 amdgpu_device_ip_block_add(adev, &dm_ip_block); 871 break; 872 default: 873 dev_err(adev->dev, 874 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 875 adev->ip_versions[DCE_HWIP][0]); 876 return -EINVAL; 877 } 878 } else if (adev->ip_versions[DCI_HWIP][0]) { 879 switch (adev->ip_versions[DCI_HWIP][0]) { 880 case IP_VERSION(12, 0, 0): 881 case IP_VERSION(12, 0, 1): 882 case IP_VERSION(12, 1, 0): 883 amdgpu_device_ip_block_add(adev, &dm_ip_block); 884 break; 885 default: 886 dev_err(adev->dev, 887 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 888 adev->ip_versions[DCI_HWIP][0]); 889 return -EINVAL; 890 } 891 } 892 #endif 893 return 0; 894 } 895 896 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 897 { 898 switch (adev->ip_versions[GC_HWIP][0]) { 899 case IP_VERSION(9, 0, 1): 900 case IP_VERSION(9, 1, 0): 901 case IP_VERSION(9, 2, 1): 902 case IP_VERSION(9, 2, 2): 903 case IP_VERSION(9, 3, 0): 904 case IP_VERSION(9, 4, 0): 905 case IP_VERSION(9, 4, 1): 906 case IP_VERSION(9, 4, 2): 907 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 908 break; 909 case IP_VERSION(10, 1, 10): 910 case IP_VERSION(10, 1, 2): 911 case IP_VERSION(10, 1, 1): 912 case IP_VERSION(10, 1, 3): 913 case IP_VERSION(10, 3, 0): 914 case IP_VERSION(10, 3, 2): 915 case IP_VERSION(10, 3, 1): 916 case IP_VERSION(10, 3, 4): 917 case IP_VERSION(10, 3, 5): 918 case IP_VERSION(10, 3, 3): 919 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 920 break; 921 default: 922 dev_err(adev->dev, 923 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 924 adev->ip_versions[GC_HWIP][0]); 925 return -EINVAL; 926 } 927 return 0; 928 } 929 930 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 931 { 932 switch (adev->ip_versions[SDMA0_HWIP][0]) { 933 case IP_VERSION(4, 0, 0): 934 case IP_VERSION(4, 0, 1): 935 case IP_VERSION(4, 1, 0): 936 case IP_VERSION(4, 1, 1): 937 case IP_VERSION(4, 1, 2): 938 case IP_VERSION(4, 2, 0): 939 case IP_VERSION(4, 2, 2): 940 case IP_VERSION(4, 4, 0): 941 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 942 break; 943 case IP_VERSION(5, 0, 0): 944 case IP_VERSION(5, 0, 1): 945 case IP_VERSION(5, 0, 2): 946 case IP_VERSION(5, 0, 5): 947 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 948 break; 949 case IP_VERSION(5, 2, 0): 950 case IP_VERSION(5, 2, 2): 951 case IP_VERSION(5, 2, 4): 952 case IP_VERSION(5, 2, 5): 953 case IP_VERSION(5, 2, 3): 954 case IP_VERSION(5, 2, 1): 955 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 956 break; 957 default: 958 dev_err(adev->dev, 959 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 960 adev->ip_versions[SDMA0_HWIP][0]); 961 return -EINVAL; 962 } 963 return 0; 964 } 965 966 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 967 { 968 if (adev->ip_versions[VCE_HWIP][0]) { 969 switch (adev->ip_versions[UVD_HWIP][0]) { 970 case IP_VERSION(7, 0, 0): 971 case IP_VERSION(7, 2, 0): 972 /* UVD is not supported on vega20 SR-IOV */ 973 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 974 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 975 break; 976 default: 977 dev_err(adev->dev, 978 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 979 adev->ip_versions[UVD_HWIP][0]); 980 return -EINVAL; 981 } 982 switch (adev->ip_versions[VCE_HWIP][0]) { 983 case IP_VERSION(4, 0, 0): 984 case IP_VERSION(4, 1, 0): 985 /* VCE is not supported on vega20 SR-IOV */ 986 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 987 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 988 break; 989 default: 990 dev_err(adev->dev, 991 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 992 adev->ip_versions[VCE_HWIP][0]); 993 return -EINVAL; 994 } 995 } else { 996 switch (adev->ip_versions[UVD_HWIP][0]) { 997 case IP_VERSION(1, 0, 0): 998 case IP_VERSION(1, 0, 1): 999 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1000 break; 1001 case IP_VERSION(2, 0, 0): 1002 case IP_VERSION(2, 0, 2): 1003 case IP_VERSION(2, 2, 0): 1004 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1005 if (!amdgpu_sriov_vf(adev)) 1006 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1007 break; 1008 case IP_VERSION(2, 0, 3): 1009 break; 1010 case IP_VERSION(2, 5, 0): 1011 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1012 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1013 break; 1014 case IP_VERSION(2, 6, 0): 1015 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1016 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1017 break; 1018 case IP_VERSION(3, 0, 0): 1019 case IP_VERSION(3, 0, 16): 1020 case IP_VERSION(3, 1, 1): 1021 case IP_VERSION(3, 0, 2): 1022 case IP_VERSION(3, 0, 192): 1023 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1024 if (!amdgpu_sriov_vf(adev)) 1025 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1026 break; 1027 case IP_VERSION(3, 0, 33): 1028 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1029 break; 1030 default: 1031 dev_err(adev->dev, 1032 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1033 adev->ip_versions[UVD_HWIP][0]); 1034 return -EINVAL; 1035 } 1036 } 1037 return 0; 1038 } 1039 1040 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1041 { 1042 switch (adev->ip_versions[GC_HWIP][0]) { 1043 case IP_VERSION(10, 1, 10): 1044 case IP_VERSION(10, 1, 1): 1045 case IP_VERSION(10, 1, 2): 1046 case IP_VERSION(10, 1, 3): 1047 case IP_VERSION(10, 3, 0): 1048 case IP_VERSION(10, 3, 1): 1049 case IP_VERSION(10, 3, 2): 1050 case IP_VERSION(10, 3, 3): 1051 case IP_VERSION(10, 3, 4): 1052 case IP_VERSION(10, 3, 5): 1053 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1054 break; 1055 default: 1056 break; 1057 } 1058 return 0; 1059 } 1060 1061 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1062 { 1063 int r; 1064 1065 switch (adev->asic_type) { 1066 case CHIP_VEGA10: 1067 vega10_reg_base_init(adev); 1068 adev->sdma.num_instances = 2; 1069 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1070 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1071 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1072 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1073 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1074 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1075 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1076 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1077 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1078 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1079 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1080 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1081 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1082 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1083 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1084 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1085 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1086 break; 1087 case CHIP_VEGA12: 1088 vega10_reg_base_init(adev); 1089 adev->sdma.num_instances = 2; 1090 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1091 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1092 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1093 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1094 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1095 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1096 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1097 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1098 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1099 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1100 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1101 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1102 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1103 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1104 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1105 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1106 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1107 break; 1108 case CHIP_RAVEN: 1109 vega10_reg_base_init(adev); 1110 adev->sdma.num_instances = 1; 1111 adev->vcn.num_vcn_inst = 1; 1112 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1113 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1114 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1115 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1116 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1117 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1118 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1119 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1120 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1121 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1122 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1123 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1124 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1125 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1126 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1127 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1128 } else { 1129 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1130 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1131 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1132 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1133 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1134 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1135 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1136 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1137 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1138 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1139 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1140 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1141 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1142 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1143 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1144 } 1145 break; 1146 case CHIP_VEGA20: 1147 vega20_reg_base_init(adev); 1148 adev->sdma.num_instances = 2; 1149 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1150 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1151 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1152 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1153 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1154 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1155 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1156 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1157 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 1158 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 1159 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1160 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 1161 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 1162 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 1163 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 1164 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 1165 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 1166 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 1167 break; 1168 case CHIP_ARCTURUS: 1169 arct_reg_base_init(adev); 1170 adev->sdma.num_instances = 8; 1171 adev->vcn.num_vcn_inst = 2; 1172 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1173 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1174 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 1175 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 1176 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 1177 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 1178 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 1179 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 1180 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 1181 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 1182 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 1183 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 1184 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 1185 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 1186 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 1187 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 1188 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1189 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 1190 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 1191 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 1192 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 1193 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 1194 break; 1195 case CHIP_ALDEBARAN: 1196 aldebaran_reg_base_init(adev); 1197 adev->sdma.num_instances = 5; 1198 adev->vcn.num_vcn_inst = 2; 1199 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1200 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1201 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 1202 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 1203 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 1204 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 1205 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 1206 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 1207 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 1208 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 1209 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 1210 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 1211 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 1212 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 1213 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 1214 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 1215 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 1216 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 1217 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 1218 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 1219 break; 1220 default: 1221 r = amdgpu_discovery_reg_base_init(adev); 1222 if (r) 1223 return -EINVAL; 1224 1225 amdgpu_discovery_harvest_ip(adev); 1226 break; 1227 } 1228 1229 switch (adev->ip_versions[GC_HWIP][0]) { 1230 case IP_VERSION(9, 0, 1): 1231 case IP_VERSION(9, 2, 1): 1232 case IP_VERSION(9, 4, 0): 1233 case IP_VERSION(9, 4, 1): 1234 case IP_VERSION(9, 4, 2): 1235 adev->family = AMDGPU_FAMILY_AI; 1236 break; 1237 case IP_VERSION(9, 1, 0): 1238 case IP_VERSION(9, 2, 2): 1239 case IP_VERSION(9, 3, 0): 1240 adev->family = AMDGPU_FAMILY_RV; 1241 break; 1242 case IP_VERSION(10, 1, 10): 1243 case IP_VERSION(10, 1, 1): 1244 case IP_VERSION(10, 1, 2): 1245 case IP_VERSION(10, 1, 3): 1246 case IP_VERSION(10, 3, 0): 1247 case IP_VERSION(10, 3, 2): 1248 case IP_VERSION(10, 3, 4): 1249 case IP_VERSION(10, 3, 5): 1250 adev->family = AMDGPU_FAMILY_NV; 1251 break; 1252 case IP_VERSION(10, 3, 1): 1253 adev->family = AMDGPU_FAMILY_VGH; 1254 break; 1255 case IP_VERSION(10, 3, 3): 1256 adev->family = AMDGPU_FAMILY_YC; 1257 break; 1258 default: 1259 return -EINVAL; 1260 } 1261 1262 switch (adev->ip_versions[GC_HWIP][0]) { 1263 case IP_VERSION(9, 1, 0): 1264 case IP_VERSION(9, 2, 2): 1265 case IP_VERSION(9, 3, 0): 1266 case IP_VERSION(10, 1, 3): 1267 case IP_VERSION(10, 3, 1): 1268 case IP_VERSION(10, 3, 3): 1269 adev->flags |= AMD_IS_APU; 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 1276 adev->gmc.xgmi.supported = true; 1277 1278 /* set NBIO version */ 1279 switch (adev->ip_versions[NBIO_HWIP][0]) { 1280 case IP_VERSION(6, 1, 0): 1281 case IP_VERSION(6, 2, 0): 1282 adev->nbio.funcs = &nbio_v6_1_funcs; 1283 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 1284 break; 1285 case IP_VERSION(7, 0, 0): 1286 case IP_VERSION(7, 0, 1): 1287 case IP_VERSION(2, 5, 0): 1288 adev->nbio.funcs = &nbio_v7_0_funcs; 1289 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 1290 break; 1291 case IP_VERSION(7, 4, 0): 1292 case IP_VERSION(7, 4, 1): 1293 adev->nbio.funcs = &nbio_v7_4_funcs; 1294 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 1295 break; 1296 case IP_VERSION(7, 4, 4): 1297 adev->nbio.funcs = &nbio_v7_4_funcs; 1298 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 1299 break; 1300 case IP_VERSION(7, 2, 0): 1301 case IP_VERSION(7, 2, 1): 1302 case IP_VERSION(7, 5, 0): 1303 adev->nbio.funcs = &nbio_v7_2_funcs; 1304 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 1305 break; 1306 case IP_VERSION(2, 1, 1): 1307 case IP_VERSION(2, 3, 0): 1308 case IP_VERSION(2, 3, 1): 1309 case IP_VERSION(2, 3, 2): 1310 adev->nbio.funcs = &nbio_v2_3_funcs; 1311 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 1312 break; 1313 case IP_VERSION(3, 3, 0): 1314 case IP_VERSION(3, 3, 1): 1315 case IP_VERSION(3, 3, 2): 1316 case IP_VERSION(3, 3, 3): 1317 adev->nbio.funcs = &nbio_v2_3_funcs; 1318 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 switch (adev->ip_versions[HDP_HWIP][0]) { 1325 case IP_VERSION(4, 0, 0): 1326 case IP_VERSION(4, 0, 1): 1327 case IP_VERSION(4, 1, 0): 1328 case IP_VERSION(4, 1, 1): 1329 case IP_VERSION(4, 1, 2): 1330 case IP_VERSION(4, 2, 0): 1331 case IP_VERSION(4, 2, 1): 1332 case IP_VERSION(4, 4, 0): 1333 adev->hdp.funcs = &hdp_v4_0_funcs; 1334 break; 1335 case IP_VERSION(5, 0, 0): 1336 case IP_VERSION(5, 0, 1): 1337 case IP_VERSION(5, 0, 2): 1338 case IP_VERSION(5, 0, 3): 1339 case IP_VERSION(5, 0, 4): 1340 case IP_VERSION(5, 2, 0): 1341 adev->hdp.funcs = &hdp_v5_0_funcs; 1342 break; 1343 default: 1344 break; 1345 } 1346 1347 switch (adev->ip_versions[DF_HWIP][0]) { 1348 case IP_VERSION(3, 6, 0): 1349 case IP_VERSION(3, 6, 1): 1350 case IP_VERSION(3, 6, 2): 1351 adev->df.funcs = &df_v3_6_funcs; 1352 break; 1353 case IP_VERSION(2, 1, 0): 1354 case IP_VERSION(2, 1, 1): 1355 case IP_VERSION(2, 5, 0): 1356 case IP_VERSION(3, 5, 1): 1357 case IP_VERSION(3, 5, 2): 1358 adev->df.funcs = &df_v1_7_funcs; 1359 break; 1360 default: 1361 break; 1362 } 1363 1364 switch (adev->ip_versions[SMUIO_HWIP][0]) { 1365 case IP_VERSION(9, 0, 0): 1366 case IP_VERSION(9, 0, 1): 1367 case IP_VERSION(10, 0, 0): 1368 case IP_VERSION(10, 0, 1): 1369 case IP_VERSION(10, 0, 2): 1370 adev->smuio.funcs = &smuio_v9_0_funcs; 1371 break; 1372 case IP_VERSION(11, 0, 0): 1373 case IP_VERSION(11, 0, 2): 1374 case IP_VERSION(11, 0, 3): 1375 case IP_VERSION(11, 0, 4): 1376 case IP_VERSION(11, 0, 7): 1377 case IP_VERSION(11, 0, 8): 1378 adev->smuio.funcs = &smuio_v11_0_funcs; 1379 break; 1380 case IP_VERSION(11, 0, 6): 1381 case IP_VERSION(11, 0, 10): 1382 case IP_VERSION(11, 0, 11): 1383 case IP_VERSION(11, 5, 0): 1384 case IP_VERSION(13, 0, 1): 1385 adev->smuio.funcs = &smuio_v11_0_6_funcs; 1386 break; 1387 case IP_VERSION(13, 0, 2): 1388 adev->smuio.funcs = &smuio_v13_0_funcs; 1389 break; 1390 default: 1391 break; 1392 } 1393 1394 r = amdgpu_discovery_set_common_ip_blocks(adev); 1395 if (r) 1396 return r; 1397 1398 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 1399 if (r) 1400 return r; 1401 1402 /* For SR-IOV, PSP needs to be initialized before IH */ 1403 if (amdgpu_sriov_vf(adev)) { 1404 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1405 if (r) 1406 return r; 1407 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1408 if (r) 1409 return r; 1410 } else { 1411 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1412 if (r) 1413 return r; 1414 1415 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1416 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1417 if (r) 1418 return r; 1419 } 1420 } 1421 1422 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1423 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1424 if (r) 1425 return r; 1426 } 1427 1428 r = amdgpu_discovery_set_display_ip_blocks(adev); 1429 if (r) 1430 return r; 1431 1432 r = amdgpu_discovery_set_gc_ip_blocks(adev); 1433 if (r) 1434 return r; 1435 1436 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 1437 if (r) 1438 return r; 1439 1440 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 1441 !amdgpu_sriov_vf(adev)) { 1442 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1443 if (r) 1444 return r; 1445 } 1446 1447 r = amdgpu_discovery_set_mm_ip_blocks(adev); 1448 if (r) 1449 return r; 1450 1451 if (adev->enable_mes) { 1452 r = amdgpu_discovery_set_mes_ip_blocks(adev); 1453 if (r) 1454 return r; 1455 } 1456 1457 return 0; 1458 } 1459 1460