1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_discovery.h" 26 #include "soc15_hw_ip.h" 27 #include "discovery.h" 28 29 #define mmRCC_CONFIG_MEMSIZE 0xde3 30 #define mmMM_INDEX 0x0 31 #define mmMM_INDEX_HI 0x6 32 #define mmMM_DATA 0x1 33 #define HW_ID_MAX 300 34 35 const char *hw_id_names[HW_ID_MAX] = { 36 [MP1_HWID] = "MP1", 37 [MP2_HWID] = "MP2", 38 [THM_HWID] = "THM", 39 [SMUIO_HWID] = "SMUIO", 40 [FUSE_HWID] = "FUSE", 41 [CLKA_HWID] = "CLKA", 42 [PWR_HWID] = "PWR", 43 [GC_HWID] = "GC", 44 [UVD_HWID] = "UVD", 45 [AUDIO_AZ_HWID] = "AUDIO_AZ", 46 [ACP_HWID] = "ACP", 47 [DCI_HWID] = "DCI", 48 [DMU_HWID] = "DMU", 49 [DCO_HWID] = "DCO", 50 [DIO_HWID] = "DIO", 51 [XDMA_HWID] = "XDMA", 52 [DCEAZ_HWID] = "DCEAZ", 53 [DAZ_HWID] = "DAZ", 54 [SDPMUX_HWID] = "SDPMUX", 55 [NTB_HWID] = "NTB", 56 [IOHC_HWID] = "IOHC", 57 [L2IMU_HWID] = "L2IMU", 58 [VCE_HWID] = "VCE", 59 [MMHUB_HWID] = "MMHUB", 60 [ATHUB_HWID] = "ATHUB", 61 [DBGU_NBIO_HWID] = "DBGU_NBIO", 62 [DFX_HWID] = "DFX", 63 [DBGU0_HWID] = "DBGU0", 64 [DBGU1_HWID] = "DBGU1", 65 [OSSSYS_HWID] = "OSSSYS", 66 [HDP_HWID] = "HDP", 67 [SDMA0_HWID] = "SDMA0", 68 [SDMA1_HWID] = "SDMA1", 69 [ISP_HWID] = "ISP", 70 [DBGU_IO_HWID] = "DBGU_IO", 71 [DF_HWID] = "DF", 72 [CLKB_HWID] = "CLKB", 73 [FCH_HWID] = "FCH", 74 [DFX_DAP_HWID] = "DFX_DAP", 75 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 76 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 77 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 78 [L1IMU3_HWID] = "L1IMU3", 79 [L1IMU4_HWID] = "L1IMU4", 80 [L1IMU5_HWID] = "L1IMU5", 81 [L1IMU6_HWID] = "L1IMU6", 82 [L1IMU7_HWID] = "L1IMU7", 83 [L1IMU8_HWID] = "L1IMU8", 84 [L1IMU9_HWID] = "L1IMU9", 85 [L1IMU10_HWID] = "L1IMU10", 86 [L1IMU11_HWID] = "L1IMU11", 87 [L1IMU12_HWID] = "L1IMU12", 88 [L1IMU13_HWID] = "L1IMU13", 89 [L1IMU14_HWID] = "L1IMU14", 90 [L1IMU15_HWID] = "L1IMU15", 91 [WAFLC_HWID] = "WAFLC", 92 [FCH_USB_PD_HWID] = "FCH_USB_PD", 93 [PCIE_HWID] = "PCIE", 94 [PCS_HWID] = "PCS", 95 [DDCL_HWID] = "DDCL", 96 [SST_HWID] = "SST", 97 [IOAGR_HWID] = "IOAGR", 98 [NBIF_HWID] = "NBIF", 99 [IOAPIC_HWID] = "IOAPIC", 100 [SYSTEMHUB_HWID] = "SYSTEMHUB", 101 [NTBCCP_HWID] = "NTBCCP", 102 [UMC_HWID] = "UMC", 103 [SATA_HWID] = "SATA", 104 [USB_HWID] = "USB", 105 [CCXSEC_HWID] = "CCXSEC", 106 [XGMI_HWID] = "XGMI", 107 [XGBE_HWID] = "XGBE", 108 [MP0_HWID] = "MP0", 109 }; 110 111 static int hw_id_map[MAX_HWIP] = { 112 [GC_HWIP] = GC_HWID, 113 [HDP_HWIP] = HDP_HWID, 114 [SDMA0_HWIP] = SDMA0_HWID, 115 [SDMA1_HWIP] = SDMA1_HWID, 116 [MMHUB_HWIP] = MMHUB_HWID, 117 [ATHUB_HWIP] = ATHUB_HWID, 118 [NBIO_HWIP] = NBIF_HWID, 119 [MP0_HWIP] = MP0_HWID, 120 [MP1_HWIP] = MP1_HWID, 121 [UVD_HWIP] = UVD_HWID, 122 [VCE_HWIP] = VCE_HWID, 123 [DF_HWIP] = DF_HWID, 124 [DCE_HWIP] = DMU_HWID, 125 [OSSSYS_HWIP] = OSSSYS_HWID, 126 [SMUIO_HWIP] = SMUIO_HWID, 127 [PWR_HWIP] = PWR_HWID, 128 [NBIF_HWIP] = NBIF_HWID, 129 [THM_HWIP] = THM_HWID, 130 [CLK_HWIP] = CLKA_HWID, 131 }; 132 133 static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary) 134 { 135 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 136 uint64_t pos = vram_size - DISCOVERY_TMR_SIZE; 137 138 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, DISCOVERY_TMR_SIZE, false); 139 return 0; 140 } 141 142 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 143 { 144 uint16_t checksum = 0; 145 int i; 146 147 for (i = 0; i < size; i++) 148 checksum += data[i]; 149 150 return checksum; 151 } 152 153 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 154 uint16_t expected) 155 { 156 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 157 } 158 159 static int amdgpu_discovery_init(struct amdgpu_device *adev) 160 { 161 struct table_info *info; 162 struct binary_header *bhdr; 163 struct ip_discovery_header *ihdr; 164 struct gpu_info_header *ghdr; 165 uint16_t offset; 166 uint16_t size; 167 uint16_t checksum; 168 int r; 169 170 adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 171 if (!adev->discovery) 172 return -ENOMEM; 173 174 r = amdgpu_discovery_read_binary(adev, adev->discovery); 175 if (r) { 176 DRM_ERROR("failed to read ip discovery binary\n"); 177 goto out; 178 } 179 180 bhdr = (struct binary_header *)adev->discovery; 181 182 if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) { 183 DRM_ERROR("invalid ip discovery binary signature\n"); 184 r = -EINVAL; 185 goto out; 186 } 187 188 offset = offsetof(struct binary_header, binary_checksum) + 189 sizeof(bhdr->binary_checksum); 190 size = bhdr->binary_size - offset; 191 checksum = bhdr->binary_checksum; 192 193 if (!amdgpu_discovery_verify_checksum(adev->discovery + offset, 194 size, checksum)) { 195 DRM_ERROR("invalid ip discovery binary checksum\n"); 196 r = -EINVAL; 197 goto out; 198 } 199 200 info = &bhdr->table_list[IP_DISCOVERY]; 201 offset = le16_to_cpu(info->offset); 202 checksum = le16_to_cpu(info->checksum); 203 ihdr = (struct ip_discovery_header *)(adev->discovery + offset); 204 205 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 206 DRM_ERROR("invalid ip discovery data table signature\n"); 207 r = -EINVAL; 208 goto out; 209 } 210 211 if (!amdgpu_discovery_verify_checksum(adev->discovery + offset, 212 ihdr->size, checksum)) { 213 DRM_ERROR("invalid ip discovery data table checksum\n"); 214 r = -EINVAL; 215 goto out; 216 } 217 218 info = &bhdr->table_list[GC]; 219 offset = le16_to_cpu(info->offset); 220 checksum = le16_to_cpu(info->checksum); 221 ghdr = (struct gpu_info_header *)(adev->discovery + offset); 222 223 if (!amdgpu_discovery_verify_checksum(adev->discovery + offset, 224 ghdr->size, checksum)) { 225 DRM_ERROR("invalid gc data table checksum\n"); 226 r = -EINVAL; 227 goto out; 228 } 229 230 return 0; 231 232 out: 233 kfree(adev->discovery); 234 adev->discovery = NULL; 235 236 return r; 237 } 238 239 void amdgpu_discovery_fini(struct amdgpu_device *adev) 240 { 241 kfree(adev->discovery); 242 adev->discovery = NULL; 243 } 244 245 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 246 { 247 struct binary_header *bhdr; 248 struct ip_discovery_header *ihdr; 249 struct die_header *dhdr; 250 struct ip *ip; 251 uint16_t die_offset; 252 uint16_t ip_offset; 253 uint16_t num_dies; 254 uint16_t num_ips; 255 uint8_t num_base_address; 256 int hw_ip; 257 int i, j, k; 258 int r; 259 260 r = amdgpu_discovery_init(adev); 261 if (r) { 262 DRM_ERROR("amdgpu_discovery_init failed\n"); 263 return r; 264 } 265 266 bhdr = (struct binary_header *)adev->discovery; 267 ihdr = (struct ip_discovery_header *)(adev->discovery + 268 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 269 num_dies = le16_to_cpu(ihdr->num_dies); 270 271 DRM_DEBUG("number of dies: %d\n", num_dies); 272 273 for (i = 0; i < num_dies; i++) { 274 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 275 dhdr = (struct die_header *)(adev->discovery + die_offset); 276 num_ips = le16_to_cpu(dhdr->num_ips); 277 ip_offset = die_offset + sizeof(*dhdr); 278 279 if (le16_to_cpu(dhdr->die_id) != i) { 280 DRM_ERROR("invalid die id %d, expected %d\n", 281 le16_to_cpu(dhdr->die_id), i); 282 return -EINVAL; 283 } 284 285 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 286 le16_to_cpu(dhdr->die_id), num_ips); 287 288 for (j = 0; j < num_ips; j++) { 289 ip = (struct ip *)(adev->discovery + ip_offset); 290 num_base_address = ip->num_base_address; 291 292 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 293 hw_id_names[le16_to_cpu(ip->hw_id)], 294 le16_to_cpu(ip->hw_id), 295 ip->number_instance, 296 ip->major, ip->minor, 297 ip->revision); 298 299 for (k = 0; k < num_base_address; k++) { 300 /* 301 * convert the endianness of base addresses in place, 302 * so that we don't need to convert them when accessing adev->reg_offset. 303 */ 304 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 305 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 306 } 307 308 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 309 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 310 DRM_DEBUG("set register base offset for %s\n", 311 hw_id_names[le16_to_cpu(ip->hw_id)]); 312 adev->reg_offset[hw_ip][ip->number_instance] = 313 ip->base_address; 314 } 315 316 } 317 318 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 319 } 320 } 321 322 return 0; 323 } 324 325 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, 326 int *major, int *minor, int *revision) 327 { 328 struct binary_header *bhdr; 329 struct ip_discovery_header *ihdr; 330 struct die_header *dhdr; 331 struct ip *ip; 332 uint16_t die_offset; 333 uint16_t ip_offset; 334 uint16_t num_dies; 335 uint16_t num_ips; 336 int i, j; 337 338 if (!adev->discovery) { 339 DRM_ERROR("ip discovery uninitialized\n"); 340 return -EINVAL; 341 } 342 343 bhdr = (struct binary_header *)adev->discovery; 344 ihdr = (struct ip_discovery_header *)(adev->discovery + 345 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 346 num_dies = le16_to_cpu(ihdr->num_dies); 347 348 for (i = 0; i < num_dies; i++) { 349 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 350 dhdr = (struct die_header *)(adev->discovery + die_offset); 351 num_ips = le16_to_cpu(dhdr->num_ips); 352 ip_offset = die_offset + sizeof(*dhdr); 353 354 for (j = 0; j < num_ips; j++) { 355 ip = (struct ip *)(adev->discovery + ip_offset); 356 357 if (le16_to_cpu(ip->hw_id) == hw_id) { 358 if (major) 359 *major = ip->major; 360 if (minor) 361 *minor = ip->minor; 362 if (revision) 363 *revision = ip->revision; 364 return 0; 365 } 366 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 367 } 368 } 369 370 return -EINVAL; 371 } 372 373 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 374 { 375 struct binary_header *bhdr; 376 struct gc_info_v1_0 *gc_info; 377 378 if (!adev->discovery) { 379 DRM_ERROR("ip discovery uninitialized\n"); 380 return -EINVAL; 381 } 382 383 bhdr = (struct binary_header *)adev->discovery; 384 gc_info = (struct gc_info_v1_0 *)(adev->discovery + 385 le16_to_cpu(bhdr->table_list[GC].offset)); 386 387 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); 388 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + 389 le32_to_cpu(gc_info->gc_num_wgp1_per_sa)); 390 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); 391 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); 392 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); 393 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); 394 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); 395 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); 396 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); 397 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); 398 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size); 399 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd); 400 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu); 401 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size); 402 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) / 403 le32_to_cpu(gc_info->gc_num_sa_per_se); 404 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc); 405 406 return 0; 407 } 408