1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gfxhub_v2_0.h" 51 #include "mmhub_v2_0.h" 52 #include "nbio_v2_3.h" 53 #include "nbio_v7_2.h" 54 #include "hdp_v5_0.h" 55 #include "nv.h" 56 #include "navi10_ih.h" 57 #include "gfx_v10_0.h" 58 #include "sdma_v5_0.h" 59 #include "sdma_v5_2.h" 60 #include "vcn_v2_0.h" 61 #include "jpeg_v2_0.h" 62 #include "vcn_v3_0.h" 63 #include "jpeg_v3_0.h" 64 #include "amdgpu_vkms.h" 65 #include "mes_v10_1.h" 66 #include "smuio_v11_0.h" 67 #include "smuio_v11_0_6.h" 68 #include "smuio_v13_0.h" 69 70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 72 73 #define mmRCC_CONFIG_MEMSIZE 0xde3 74 #define mmMM_INDEX 0x0 75 #define mmMM_INDEX_HI 0x6 76 #define mmMM_DATA 0x1 77 78 static const char *hw_id_names[HW_ID_MAX] = { 79 [MP1_HWID] = "MP1", 80 [MP2_HWID] = "MP2", 81 [THM_HWID] = "THM", 82 [SMUIO_HWID] = "SMUIO", 83 [FUSE_HWID] = "FUSE", 84 [CLKA_HWID] = "CLKA", 85 [PWR_HWID] = "PWR", 86 [GC_HWID] = "GC", 87 [UVD_HWID] = "UVD", 88 [AUDIO_AZ_HWID] = "AUDIO_AZ", 89 [ACP_HWID] = "ACP", 90 [DCI_HWID] = "DCI", 91 [DMU_HWID] = "DMU", 92 [DCO_HWID] = "DCO", 93 [DIO_HWID] = "DIO", 94 [XDMA_HWID] = "XDMA", 95 [DCEAZ_HWID] = "DCEAZ", 96 [DAZ_HWID] = "DAZ", 97 [SDPMUX_HWID] = "SDPMUX", 98 [NTB_HWID] = "NTB", 99 [IOHC_HWID] = "IOHC", 100 [L2IMU_HWID] = "L2IMU", 101 [VCE_HWID] = "VCE", 102 [MMHUB_HWID] = "MMHUB", 103 [ATHUB_HWID] = "ATHUB", 104 [DBGU_NBIO_HWID] = "DBGU_NBIO", 105 [DFX_HWID] = "DFX", 106 [DBGU0_HWID] = "DBGU0", 107 [DBGU1_HWID] = "DBGU1", 108 [OSSSYS_HWID] = "OSSSYS", 109 [HDP_HWID] = "HDP", 110 [SDMA0_HWID] = "SDMA0", 111 [SDMA1_HWID] = "SDMA1", 112 [SDMA2_HWID] = "SDMA2", 113 [SDMA3_HWID] = "SDMA3", 114 [ISP_HWID] = "ISP", 115 [DBGU_IO_HWID] = "DBGU_IO", 116 [DF_HWID] = "DF", 117 [CLKB_HWID] = "CLKB", 118 [FCH_HWID] = "FCH", 119 [DFX_DAP_HWID] = "DFX_DAP", 120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 123 [L1IMU3_HWID] = "L1IMU3", 124 [L1IMU4_HWID] = "L1IMU4", 125 [L1IMU5_HWID] = "L1IMU5", 126 [L1IMU6_HWID] = "L1IMU6", 127 [L1IMU7_HWID] = "L1IMU7", 128 [L1IMU8_HWID] = "L1IMU8", 129 [L1IMU9_HWID] = "L1IMU9", 130 [L1IMU10_HWID] = "L1IMU10", 131 [L1IMU11_HWID] = "L1IMU11", 132 [L1IMU12_HWID] = "L1IMU12", 133 [L1IMU13_HWID] = "L1IMU13", 134 [L1IMU14_HWID] = "L1IMU14", 135 [L1IMU15_HWID] = "L1IMU15", 136 [WAFLC_HWID] = "WAFLC", 137 [FCH_USB_PD_HWID] = "FCH_USB_PD", 138 [PCIE_HWID] = "PCIE", 139 [PCS_HWID] = "PCS", 140 [DDCL_HWID] = "DDCL", 141 [SST_HWID] = "SST", 142 [IOAGR_HWID] = "IOAGR", 143 [NBIF_HWID] = "NBIF", 144 [IOAPIC_HWID] = "IOAPIC", 145 [SYSTEMHUB_HWID] = "SYSTEMHUB", 146 [NTBCCP_HWID] = "NTBCCP", 147 [UMC_HWID] = "UMC", 148 [SATA_HWID] = "SATA", 149 [USB_HWID] = "USB", 150 [CCXSEC_HWID] = "CCXSEC", 151 [XGMI_HWID] = "XGMI", 152 [XGBE_HWID] = "XGBE", 153 [MP0_HWID] = "MP0", 154 }; 155 156 static int hw_id_map[MAX_HWIP] = { 157 [GC_HWIP] = GC_HWID, 158 [HDP_HWIP] = HDP_HWID, 159 [SDMA0_HWIP] = SDMA0_HWID, 160 [SDMA1_HWIP] = SDMA1_HWID, 161 [SDMA2_HWIP] = SDMA2_HWID, 162 [SDMA3_HWIP] = SDMA3_HWID, 163 [MMHUB_HWIP] = MMHUB_HWID, 164 [ATHUB_HWIP] = ATHUB_HWID, 165 [NBIO_HWIP] = NBIF_HWID, 166 [MP0_HWIP] = MP0_HWID, 167 [MP1_HWIP] = MP1_HWID, 168 [UVD_HWIP] = UVD_HWID, 169 [VCE_HWIP] = VCE_HWID, 170 [DF_HWIP] = DF_HWID, 171 [DCE_HWIP] = DMU_HWID, 172 [OSSSYS_HWIP] = OSSSYS_HWID, 173 [SMUIO_HWIP] = SMUIO_HWID, 174 [PWR_HWIP] = PWR_HWID, 175 [NBIF_HWIP] = NBIF_HWID, 176 [THM_HWIP] = THM_HWID, 177 [CLK_HWIP] = CLKA_HWID, 178 [UMC_HWIP] = UMC_HWID, 179 [XGMI_HWIP] = XGMI_HWID, 180 [DCI_HWIP] = DCI_HWID, 181 }; 182 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 184 { 185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 187 188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 189 adev->mman.discovery_tmr_size, false); 190 return 0; 191 } 192 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 194 { 195 const struct firmware *fw; 196 const char *fw_name; 197 int r; 198 199 switch (amdgpu_discovery) { 200 case 2: 201 fw_name = FIRMWARE_IP_DISCOVERY; 202 break; 203 default: 204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 205 return -EINVAL; 206 } 207 208 r = request_firmware(&fw, fw_name, adev->dev); 209 if (r) { 210 dev_err(adev->dev, "can't load firmware \"%s\"\n", 211 fw_name); 212 return r; 213 } 214 215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 216 release_firmware(fw); 217 218 return 0; 219 } 220 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 222 { 223 uint16_t checksum = 0; 224 int i; 225 226 for (i = 0; i < size; i++) 227 checksum += data[i]; 228 229 return checksum; 230 } 231 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 233 uint16_t expected) 234 { 235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 236 } 237 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 239 { 240 struct binary_header *bhdr; 241 bhdr = (struct binary_header *)binary; 242 243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 244 } 245 246 static int amdgpu_discovery_init(struct amdgpu_device *adev) 247 { 248 struct table_info *info; 249 struct binary_header *bhdr; 250 struct ip_discovery_header *ihdr; 251 struct gpu_info_header *ghdr; 252 uint16_t offset; 253 uint16_t size; 254 uint16_t checksum; 255 int r; 256 257 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 258 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 259 if (!adev->mman.discovery_bin) 260 return -ENOMEM; 261 262 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 263 if (r) { 264 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 265 r = -EINVAL; 266 goto out; 267 } 268 269 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 270 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 271 /* retry read ip discovery binary from file */ 272 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 273 if (r) { 274 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 275 r = -EINVAL; 276 goto out; 277 } 278 /* check the ip discovery binary signature */ 279 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 280 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 281 r = -EINVAL; 282 goto out; 283 } 284 } 285 286 bhdr = (struct binary_header *)adev->mman.discovery_bin; 287 288 offset = offsetof(struct binary_header, binary_checksum) + 289 sizeof(bhdr->binary_checksum); 290 size = le16_to_cpu(bhdr->binary_size) - offset; 291 checksum = le16_to_cpu(bhdr->binary_checksum); 292 293 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 294 size, checksum)) { 295 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 296 r = -EINVAL; 297 goto out; 298 } 299 300 info = &bhdr->table_list[IP_DISCOVERY]; 301 offset = le16_to_cpu(info->offset); 302 checksum = le16_to_cpu(info->checksum); 303 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 304 305 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 306 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 307 r = -EINVAL; 308 goto out; 309 } 310 311 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 312 le16_to_cpu(ihdr->size), checksum)) { 313 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 314 r = -EINVAL; 315 goto out; 316 } 317 318 info = &bhdr->table_list[GC]; 319 offset = le16_to_cpu(info->offset); 320 checksum = le16_to_cpu(info->checksum); 321 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 322 323 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 324 le32_to_cpu(ghdr->size), checksum)) { 325 dev_err(adev->dev, "invalid gc data table checksum\n"); 326 r = -EINVAL; 327 goto out; 328 } 329 330 return 0; 331 332 out: 333 kfree(adev->mman.discovery_bin); 334 adev->mman.discovery_bin = NULL; 335 336 return r; 337 } 338 339 void amdgpu_discovery_fini(struct amdgpu_device *adev) 340 { 341 kfree(adev->mman.discovery_bin); 342 adev->mman.discovery_bin = NULL; 343 } 344 345 static int amdgpu_discovery_validate_ip(const struct ip *ip) 346 { 347 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 348 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 349 ip->number_instance); 350 return -EINVAL; 351 } 352 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 353 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 354 le16_to_cpu(ip->hw_id)); 355 return -EINVAL; 356 } 357 358 return 0; 359 } 360 361 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 362 { 363 struct binary_header *bhdr; 364 struct ip_discovery_header *ihdr; 365 struct die_header *dhdr; 366 struct ip *ip; 367 uint16_t die_offset; 368 uint16_t ip_offset; 369 uint16_t num_dies; 370 uint16_t num_ips; 371 uint8_t num_base_address; 372 int hw_ip; 373 int i, j, k; 374 int r; 375 376 r = amdgpu_discovery_init(adev); 377 if (r) { 378 DRM_ERROR("amdgpu_discovery_init failed\n"); 379 return r; 380 } 381 382 bhdr = (struct binary_header *)adev->mman.discovery_bin; 383 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 384 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 385 num_dies = le16_to_cpu(ihdr->num_dies); 386 387 DRM_DEBUG("number of dies: %d\n", num_dies); 388 389 for (i = 0; i < num_dies; i++) { 390 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 391 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 392 num_ips = le16_to_cpu(dhdr->num_ips); 393 ip_offset = die_offset + sizeof(*dhdr); 394 395 if (le16_to_cpu(dhdr->die_id) != i) { 396 DRM_ERROR("invalid die id %d, expected %d\n", 397 le16_to_cpu(dhdr->die_id), i); 398 return -EINVAL; 399 } 400 401 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 402 le16_to_cpu(dhdr->die_id), num_ips); 403 404 for (j = 0; j < num_ips; j++) { 405 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 406 407 if (amdgpu_discovery_validate_ip(ip)) 408 goto next_ip; 409 410 num_base_address = ip->num_base_address; 411 412 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 413 hw_id_names[le16_to_cpu(ip->hw_id)], 414 le16_to_cpu(ip->hw_id), 415 ip->number_instance, 416 ip->major, ip->minor, 417 ip->revision); 418 419 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 420 /* Bit [5:0]: original revision value 421 * Bit [7:6]: en/decode capability: 422 * 0b00 : VCN function normally 423 * 0b10 : encode is disabled 424 * 0b01 : decode is disabled 425 */ 426 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 427 ip->revision & 0xc0; 428 ip->revision &= ~0xc0; 429 adev->vcn.num_vcn_inst++; 430 } 431 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 432 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 433 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 434 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 435 adev->sdma.num_instances++; 436 437 for (k = 0; k < num_base_address; k++) { 438 /* 439 * convert the endianness of base addresses in place, 440 * so that we don't need to convert them when accessing adev->reg_offset. 441 */ 442 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 443 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 444 } 445 446 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 447 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 448 DRM_DEBUG("set register base offset for %s\n", 449 hw_id_names[le16_to_cpu(ip->hw_id)]); 450 adev->reg_offset[hw_ip][ip->number_instance] = 451 ip->base_address; 452 /* Instance support is somewhat inconsistent. 453 * SDMA is a good example. Sienna cichlid has 4 total 454 * SDMA instances, each enumerated separately (HWIDs 455 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 456 * but they are enumerated as multiple instances of the 457 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 458 * example. On most chips there are multiple instances 459 * with the same HWID. 460 */ 461 adev->ip_versions[hw_ip][ip->number_instance] = 462 IP_VERSION(ip->major, ip->minor, ip->revision); 463 } 464 } 465 466 next_ip: 467 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 468 } 469 } 470 471 return 0; 472 } 473 474 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 475 int *major, int *minor, int *revision) 476 { 477 struct binary_header *bhdr; 478 struct ip_discovery_header *ihdr; 479 struct die_header *dhdr; 480 struct ip *ip; 481 uint16_t die_offset; 482 uint16_t ip_offset; 483 uint16_t num_dies; 484 uint16_t num_ips; 485 int i, j; 486 487 if (!adev->mman.discovery_bin) { 488 DRM_ERROR("ip discovery uninitialized\n"); 489 return -EINVAL; 490 } 491 492 bhdr = (struct binary_header *)adev->mman.discovery_bin; 493 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 494 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 495 num_dies = le16_to_cpu(ihdr->num_dies); 496 497 for (i = 0; i < num_dies; i++) { 498 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 499 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 500 num_ips = le16_to_cpu(dhdr->num_ips); 501 ip_offset = die_offset + sizeof(*dhdr); 502 503 for (j = 0; j < num_ips; j++) { 504 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 505 506 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 507 if (major) 508 *major = ip->major; 509 if (minor) 510 *minor = ip->minor; 511 if (revision) 512 *revision = ip->revision; 513 return 0; 514 } 515 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 516 } 517 } 518 519 return -EINVAL; 520 } 521 522 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 523 { 524 struct binary_header *bhdr; 525 struct harvest_table *harvest_info; 526 int i, vcn_harvest_count = 0; 527 528 bhdr = (struct binary_header *)adev->mman.discovery_bin; 529 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + 530 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset)); 531 532 for (i = 0; i < 32; i++) { 533 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 534 break; 535 536 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 537 case VCN_HWID: 538 vcn_harvest_count++; 539 if (harvest_info->list[i].number_instance == 0) 540 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 541 else 542 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 543 break; 544 case DMU_HWID: 545 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 546 break; 547 default: 548 break; 549 } 550 } 551 /* some IP discovery tables on Navy Flounder don't have this set correctly */ 552 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 553 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) 554 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 555 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 556 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 557 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 558 } 559 if ((adev->pdev->device == 0x731E && 560 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) || 561 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) || 562 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) { 563 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 564 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 565 } 566 } 567 568 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 569 { 570 struct binary_header *bhdr; 571 struct gc_info_v1_0 *gc_info; 572 573 if (!adev->mman.discovery_bin) { 574 DRM_ERROR("ip discovery uninitialized\n"); 575 return -EINVAL; 576 } 577 578 bhdr = (struct binary_header *)adev->mman.discovery_bin; 579 gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin + 580 le16_to_cpu(bhdr->table_list[GC].offset)); 581 582 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); 583 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + 584 le32_to_cpu(gc_info->gc_num_wgp1_per_sa)); 585 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); 586 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); 587 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); 588 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); 589 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); 590 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); 591 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); 592 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); 593 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size); 594 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd); 595 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu); 596 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size); 597 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) / 598 le32_to_cpu(gc_info->gc_num_sa_per_se); 599 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc); 600 601 return 0; 602 } 603 604 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 605 { 606 /* what IP to use for this? */ 607 switch (adev->ip_versions[GC_HWIP][0]) { 608 case IP_VERSION(9, 0, 1): 609 case IP_VERSION(9, 1, 0): 610 case IP_VERSION(9, 2, 1): 611 case IP_VERSION(9, 2, 2): 612 case IP_VERSION(9, 3, 0): 613 case IP_VERSION(9, 4, 0): 614 case IP_VERSION(9, 4, 1): 615 case IP_VERSION(9, 4, 2): 616 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 617 break; 618 case IP_VERSION(10, 1, 10): 619 case IP_VERSION(10, 1, 1): 620 case IP_VERSION(10, 1, 2): 621 case IP_VERSION(10, 1, 3): 622 case IP_VERSION(10, 3, 0): 623 case IP_VERSION(10, 3, 1): 624 case IP_VERSION(10, 3, 2): 625 case IP_VERSION(10, 3, 3): 626 case IP_VERSION(10, 3, 4): 627 case IP_VERSION(10, 3, 5): 628 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 629 break; 630 default: 631 dev_err(adev->dev, 632 "Failed to add common ip block(GC_HWIP:0x%x)\n", 633 adev->ip_versions[GC_HWIP][0]); 634 return -EINVAL; 635 } 636 return 0; 637 } 638 639 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 640 { 641 /* use GC or MMHUB IP version */ 642 switch (adev->ip_versions[GC_HWIP][0]) { 643 case IP_VERSION(9, 0, 1): 644 case IP_VERSION(9, 1, 0): 645 case IP_VERSION(9, 2, 1): 646 case IP_VERSION(9, 2, 2): 647 case IP_VERSION(9, 3, 0): 648 case IP_VERSION(9, 4, 0): 649 case IP_VERSION(9, 4, 1): 650 case IP_VERSION(9, 4, 2): 651 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 652 break; 653 case IP_VERSION(10, 1, 10): 654 case IP_VERSION(10, 1, 1): 655 case IP_VERSION(10, 1, 2): 656 case IP_VERSION(10, 1, 3): 657 case IP_VERSION(10, 3, 0): 658 case IP_VERSION(10, 3, 1): 659 case IP_VERSION(10, 3, 2): 660 case IP_VERSION(10, 3, 3): 661 case IP_VERSION(10, 3, 4): 662 case IP_VERSION(10, 3, 5): 663 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 664 break; 665 default: 666 dev_err(adev->dev, 667 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 668 adev->ip_versions[GC_HWIP][0]); 669 return -EINVAL; 670 } 671 return 0; 672 } 673 674 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 675 { 676 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 677 case IP_VERSION(4, 0, 0): 678 case IP_VERSION(4, 0, 1): 679 case IP_VERSION(4, 1, 0): 680 case IP_VERSION(4, 1, 1): 681 case IP_VERSION(4, 3, 0): 682 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 683 break; 684 case IP_VERSION(4, 2, 0): 685 case IP_VERSION(4, 2, 1): 686 case IP_VERSION(4, 4, 0): 687 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 688 break; 689 case IP_VERSION(5, 0, 0): 690 case IP_VERSION(5, 0, 1): 691 case IP_VERSION(5, 0, 2): 692 case IP_VERSION(5, 0, 3): 693 case IP_VERSION(5, 2, 0): 694 case IP_VERSION(5, 2, 1): 695 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 696 break; 697 default: 698 dev_err(adev->dev, 699 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 700 adev->ip_versions[OSSSYS_HWIP][0]); 701 return -EINVAL; 702 } 703 return 0; 704 } 705 706 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 707 { 708 switch (adev->ip_versions[MP0_HWIP][0]) { 709 case IP_VERSION(9, 0, 0): 710 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 711 break; 712 case IP_VERSION(10, 0, 0): 713 case IP_VERSION(10, 0, 1): 714 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 715 break; 716 case IP_VERSION(11, 0, 0): 717 case IP_VERSION(11, 0, 2): 718 case IP_VERSION(11, 0, 4): 719 case IP_VERSION(11, 0, 5): 720 case IP_VERSION(11, 0, 9): 721 case IP_VERSION(11, 0, 7): 722 case IP_VERSION(11, 0, 11): 723 case IP_VERSION(11, 0, 12): 724 case IP_VERSION(11, 0, 13): 725 case IP_VERSION(11, 5, 0): 726 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 727 break; 728 case IP_VERSION(11, 0, 8): 729 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 730 break; 731 case IP_VERSION(11, 0, 3): 732 case IP_VERSION(12, 0, 1): 733 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 734 break; 735 case IP_VERSION(13, 0, 1): 736 case IP_VERSION(13, 0, 2): 737 case IP_VERSION(13, 0, 3): 738 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 739 break; 740 default: 741 dev_err(adev->dev, 742 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 743 adev->ip_versions[MP0_HWIP][0]); 744 return -EINVAL; 745 } 746 return 0; 747 } 748 749 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 750 { 751 switch (adev->ip_versions[MP1_HWIP][0]) { 752 case IP_VERSION(9, 0, 0): 753 case IP_VERSION(10, 0, 0): 754 case IP_VERSION(10, 0, 1): 755 case IP_VERSION(11, 0, 2): 756 if (adev->asic_type == CHIP_ARCTURUS) 757 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 758 else 759 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 760 break; 761 case IP_VERSION(11, 0, 0): 762 case IP_VERSION(11, 0, 5): 763 case IP_VERSION(11, 0, 9): 764 case IP_VERSION(11, 0, 7): 765 case IP_VERSION(11, 0, 8): 766 case IP_VERSION(11, 0, 11): 767 case IP_VERSION(11, 0, 12): 768 case IP_VERSION(11, 0, 13): 769 case IP_VERSION(11, 5, 0): 770 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 771 break; 772 case IP_VERSION(12, 0, 0): 773 case IP_VERSION(12, 0, 1): 774 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 775 break; 776 case IP_VERSION(13, 0, 1): 777 case IP_VERSION(13, 0, 2): 778 case IP_VERSION(13, 0, 3): 779 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 780 break; 781 default: 782 dev_err(adev->dev, 783 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 784 adev->ip_versions[MP1_HWIP][0]); 785 return -EINVAL; 786 } 787 return 0; 788 } 789 790 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 791 { 792 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 793 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 794 #if defined(CONFIG_DRM_AMD_DC) 795 } else if (adev->ip_versions[DCE_HWIP][0]) { 796 switch (adev->ip_versions[DCE_HWIP][0]) { 797 case IP_VERSION(1, 0, 0): 798 case IP_VERSION(1, 0, 1): 799 case IP_VERSION(2, 0, 2): 800 case IP_VERSION(2, 0, 0): 801 case IP_VERSION(2, 0, 3): 802 case IP_VERSION(2, 1, 0): 803 case IP_VERSION(3, 0, 0): 804 case IP_VERSION(3, 0, 2): 805 case IP_VERSION(3, 0, 3): 806 case IP_VERSION(3, 0, 1): 807 case IP_VERSION(3, 1, 2): 808 case IP_VERSION(3, 1, 3): 809 amdgpu_device_ip_block_add(adev, &dm_ip_block); 810 break; 811 default: 812 dev_err(adev->dev, 813 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 814 adev->ip_versions[DCE_HWIP][0]); 815 return -EINVAL; 816 } 817 } else if (adev->ip_versions[DCI_HWIP][0]) { 818 switch (adev->ip_versions[DCI_HWIP][0]) { 819 case IP_VERSION(12, 0, 0): 820 case IP_VERSION(12, 0, 1): 821 case IP_VERSION(12, 1, 0): 822 amdgpu_device_ip_block_add(adev, &dm_ip_block); 823 break; 824 default: 825 dev_err(adev->dev, 826 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 827 adev->ip_versions[DCI_HWIP][0]); 828 return -EINVAL; 829 } 830 #endif 831 } 832 return 0; 833 } 834 835 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 836 { 837 switch (adev->ip_versions[GC_HWIP][0]) { 838 case IP_VERSION(9, 0, 1): 839 case IP_VERSION(9, 1, 0): 840 case IP_VERSION(9, 2, 1): 841 case IP_VERSION(9, 2, 2): 842 case IP_VERSION(9, 3, 0): 843 case IP_VERSION(9, 4, 0): 844 case IP_VERSION(9, 4, 1): 845 case IP_VERSION(9, 4, 2): 846 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 847 break; 848 case IP_VERSION(10, 1, 10): 849 case IP_VERSION(10, 1, 2): 850 case IP_VERSION(10, 1, 1): 851 case IP_VERSION(10, 1, 3): 852 case IP_VERSION(10, 3, 0): 853 case IP_VERSION(10, 3, 2): 854 case IP_VERSION(10, 3, 1): 855 case IP_VERSION(10, 3, 4): 856 case IP_VERSION(10, 3, 5): 857 case IP_VERSION(10, 3, 3): 858 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 859 break; 860 default: 861 dev_err(adev->dev, 862 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 863 adev->ip_versions[GC_HWIP][0]); 864 return -EINVAL; 865 } 866 return 0; 867 } 868 869 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 870 { 871 switch (adev->ip_versions[SDMA0_HWIP][0]) { 872 case IP_VERSION(4, 0, 0): 873 case IP_VERSION(4, 0, 1): 874 case IP_VERSION(4, 1, 0): 875 case IP_VERSION(4, 1, 1): 876 case IP_VERSION(4, 1, 2): 877 case IP_VERSION(4, 2, 0): 878 case IP_VERSION(4, 2, 2): 879 case IP_VERSION(4, 4, 0): 880 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 881 break; 882 case IP_VERSION(5, 0, 0): 883 case IP_VERSION(5, 0, 1): 884 case IP_VERSION(5, 0, 2): 885 case IP_VERSION(5, 0, 5): 886 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 887 break; 888 case IP_VERSION(5, 2, 0): 889 case IP_VERSION(5, 2, 2): 890 case IP_VERSION(5, 2, 4): 891 case IP_VERSION(5, 2, 5): 892 case IP_VERSION(5, 2, 3): 893 case IP_VERSION(5, 2, 1): 894 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 895 break; 896 default: 897 dev_err(adev->dev, 898 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 899 adev->ip_versions[SDMA0_HWIP][0]); 900 return -EINVAL; 901 } 902 return 0; 903 } 904 905 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 906 { 907 if (adev->ip_versions[VCE_HWIP][0]) { 908 switch (adev->ip_versions[UVD_HWIP][0]) { 909 case IP_VERSION(7, 0, 0): 910 case IP_VERSION(7, 2, 0): 911 /* UVD is not supported on vega20 SR-IOV */ 912 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 913 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 914 break; 915 default: 916 dev_err(adev->dev, 917 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 918 adev->ip_versions[UVD_HWIP][0]); 919 return -EINVAL; 920 } 921 switch (adev->ip_versions[VCE_HWIP][0]) { 922 case IP_VERSION(4, 0, 0): 923 case IP_VERSION(4, 1, 0): 924 /* VCE is not supported on vega20 SR-IOV */ 925 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 926 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 927 break; 928 default: 929 dev_err(adev->dev, 930 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 931 adev->ip_versions[VCE_HWIP][0]); 932 return -EINVAL; 933 } 934 } else { 935 switch (adev->ip_versions[UVD_HWIP][0]) { 936 case IP_VERSION(1, 0, 0): 937 case IP_VERSION(1, 0, 1): 938 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 939 break; 940 case IP_VERSION(2, 0, 0): 941 case IP_VERSION(2, 0, 2): 942 case IP_VERSION(2, 2, 0): 943 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 944 if (!amdgpu_sriov_vf(adev)) 945 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 946 break; 947 case IP_VERSION(2, 0, 3): 948 break; 949 case IP_VERSION(2, 5, 0): 950 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 951 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 952 break; 953 case IP_VERSION(2, 6, 0): 954 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 955 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 956 break; 957 case IP_VERSION(3, 0, 0): 958 case IP_VERSION(3, 0, 16): 959 case IP_VERSION(3, 1, 1): 960 case IP_VERSION(3, 0, 2): 961 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 962 if (!amdgpu_sriov_vf(adev)) 963 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 964 break; 965 case IP_VERSION(3, 0, 33): 966 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 967 break; 968 default: 969 dev_err(adev->dev, 970 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 971 adev->ip_versions[UVD_HWIP][0]); 972 return -EINVAL; 973 } 974 } 975 return 0; 976 } 977 978 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 979 { 980 switch (adev->ip_versions[GC_HWIP][0]) { 981 case IP_VERSION(10, 1, 10): 982 case IP_VERSION(10, 1, 1): 983 case IP_VERSION(10, 1, 2): 984 case IP_VERSION(10, 1, 3): 985 case IP_VERSION(10, 3, 0): 986 case IP_VERSION(10, 3, 1): 987 case IP_VERSION(10, 3, 2): 988 case IP_VERSION(10, 3, 3): 989 case IP_VERSION(10, 3, 4): 990 case IP_VERSION(10, 3, 5): 991 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 992 break; 993 default: 994 break;; 995 } 996 return 0; 997 } 998 999 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1000 { 1001 int r; 1002 1003 switch (adev->asic_type) { 1004 case CHIP_VEGA10: 1005 vega10_reg_base_init(adev); 1006 adev->sdma.num_instances = 2; 1007 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1008 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1009 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1010 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1011 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1012 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1013 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1014 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1015 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1016 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1017 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1018 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1019 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1020 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1021 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1022 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1023 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1024 break; 1025 case CHIP_VEGA12: 1026 vega10_reg_base_init(adev); 1027 adev->sdma.num_instances = 2; 1028 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1029 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1030 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1031 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1032 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1033 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1034 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1035 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1036 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1037 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1038 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1039 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1040 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1041 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1042 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1043 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1044 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1045 break; 1046 case CHIP_RAVEN: 1047 vega10_reg_base_init(adev); 1048 adev->sdma.num_instances = 1; 1049 adev->vcn.num_vcn_inst = 1; 1050 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1051 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1052 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1053 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1054 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1055 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1056 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1057 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1058 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1059 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1060 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1061 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1062 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1063 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1064 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1065 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1066 } else { 1067 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1068 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1069 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1070 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1071 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1072 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1073 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1074 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1075 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1076 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1077 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1078 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1079 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1080 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1081 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1082 } 1083 break; 1084 case CHIP_VEGA20: 1085 vega20_reg_base_init(adev); 1086 adev->sdma.num_instances = 2; 1087 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1088 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1089 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1090 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1091 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1092 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1093 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1094 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1095 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 1096 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 1097 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1098 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 1099 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 1100 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 1101 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 1102 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 1103 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 1104 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 1105 break; 1106 case CHIP_ARCTURUS: 1107 arct_reg_base_init(adev); 1108 adev->sdma.num_instances = 8; 1109 adev->vcn.num_vcn_inst = 2; 1110 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1111 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1112 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 1113 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 1114 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 1115 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 1116 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 1117 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 1118 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 1119 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 1120 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 1121 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 1122 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 1123 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 1124 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 1125 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 1126 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1127 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 1128 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 1129 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 1130 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 1131 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 1132 break; 1133 case CHIP_ALDEBARAN: 1134 aldebaran_reg_base_init(adev); 1135 adev->sdma.num_instances = 5; 1136 adev->vcn.num_vcn_inst = 2; 1137 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1138 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1139 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 1140 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 1141 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 1142 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 1143 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 1144 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 1145 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 1146 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 1147 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 1148 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 1149 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 1150 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 1151 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 1152 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 1153 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 1154 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 1155 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 1156 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 1157 break; 1158 default: 1159 r = amdgpu_discovery_reg_base_init(adev); 1160 if (r) 1161 return -EINVAL; 1162 1163 amdgpu_discovery_harvest_ip(adev); 1164 1165 if (!adev->mman.discovery_bin) { 1166 DRM_ERROR("ip discovery uninitialized\n"); 1167 return -EINVAL; 1168 } 1169 break; 1170 } 1171 1172 switch (adev->ip_versions[GC_HWIP][0]) { 1173 case IP_VERSION(9, 0, 1): 1174 case IP_VERSION(9, 2, 1): 1175 case IP_VERSION(9, 4, 0): 1176 case IP_VERSION(9, 4, 1): 1177 case IP_VERSION(9, 4, 2): 1178 adev->family = AMDGPU_FAMILY_AI; 1179 break; 1180 case IP_VERSION(9, 1, 0): 1181 case IP_VERSION(9, 2, 2): 1182 case IP_VERSION(9, 3, 0): 1183 adev->family = AMDGPU_FAMILY_RV; 1184 break; 1185 case IP_VERSION(10, 1, 10): 1186 case IP_VERSION(10, 1, 1): 1187 case IP_VERSION(10, 1, 2): 1188 case IP_VERSION(10, 1, 3): 1189 case IP_VERSION(10, 3, 0): 1190 case IP_VERSION(10, 3, 2): 1191 case IP_VERSION(10, 3, 4): 1192 case IP_VERSION(10, 3, 5): 1193 adev->family = AMDGPU_FAMILY_NV; 1194 break; 1195 case IP_VERSION(10, 3, 1): 1196 adev->family = AMDGPU_FAMILY_VGH; 1197 break; 1198 case IP_VERSION(10, 3, 3): 1199 adev->family = AMDGPU_FAMILY_YC; 1200 break; 1201 default: 1202 return -EINVAL; 1203 } 1204 1205 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 1206 adev->gmc.xgmi.supported = true; 1207 1208 /* set NBIO version */ 1209 switch (adev->ip_versions[NBIO_HWIP][0]) { 1210 case IP_VERSION(6, 1, 0): 1211 case IP_VERSION(6, 2, 0): 1212 adev->nbio.funcs = &nbio_v6_1_funcs; 1213 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 1214 break; 1215 case IP_VERSION(7, 0, 0): 1216 case IP_VERSION(7, 0, 1): 1217 case IP_VERSION(2, 5, 0): 1218 adev->nbio.funcs = &nbio_v7_0_funcs; 1219 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 1220 break; 1221 case IP_VERSION(7, 4, 0): 1222 case IP_VERSION(7, 4, 1): 1223 adev->nbio.funcs = &nbio_v7_4_funcs; 1224 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 1225 break; 1226 case IP_VERSION(7, 4, 4): 1227 adev->nbio.funcs = &nbio_v7_4_funcs; 1228 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 1229 break; 1230 case IP_VERSION(7, 2, 0): 1231 case IP_VERSION(7, 2, 1): 1232 case IP_VERSION(7, 5, 0): 1233 adev->nbio.funcs = &nbio_v7_2_funcs; 1234 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 1235 break; 1236 case IP_VERSION(2, 1, 1): 1237 case IP_VERSION(2, 3, 0): 1238 case IP_VERSION(2, 3, 1): 1239 case IP_VERSION(2, 3, 2): 1240 adev->nbio.funcs = &nbio_v2_3_funcs; 1241 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 1242 break; 1243 case IP_VERSION(3, 3, 0): 1244 case IP_VERSION(3, 3, 1): 1245 case IP_VERSION(3, 3, 2): 1246 case IP_VERSION(3, 3, 3): 1247 adev->nbio.funcs = &nbio_v2_3_funcs; 1248 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 1249 break; 1250 default: 1251 break; 1252 } 1253 1254 switch (adev->ip_versions[HDP_HWIP][0]) { 1255 case IP_VERSION(4, 0, 0): 1256 case IP_VERSION(4, 0, 1): 1257 case IP_VERSION(4, 1, 0): 1258 case IP_VERSION(4, 1, 1): 1259 case IP_VERSION(4, 1, 2): 1260 case IP_VERSION(4, 2, 0): 1261 case IP_VERSION(4, 2, 1): 1262 case IP_VERSION(4, 4, 0): 1263 adev->hdp.funcs = &hdp_v4_0_funcs; 1264 break; 1265 case IP_VERSION(5, 0, 0): 1266 case IP_VERSION(5, 0, 1): 1267 case IP_VERSION(5, 0, 2): 1268 case IP_VERSION(5, 0, 3): 1269 case IP_VERSION(5, 0, 4): 1270 case IP_VERSION(5, 2, 0): 1271 adev->hdp.funcs = &hdp_v5_0_funcs; 1272 break; 1273 default: 1274 break; 1275 } 1276 1277 switch (adev->ip_versions[DF_HWIP][0]) { 1278 case IP_VERSION(3, 6, 0): 1279 case IP_VERSION(3, 6, 1): 1280 case IP_VERSION(3, 6, 2): 1281 adev->df.funcs = &df_v3_6_funcs; 1282 break; 1283 case IP_VERSION(2, 1, 0): 1284 case IP_VERSION(2, 1, 1): 1285 case IP_VERSION(2, 5, 0): 1286 case IP_VERSION(3, 5, 1): 1287 case IP_VERSION(3, 5, 2): 1288 adev->df.funcs = &df_v1_7_funcs; 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 switch (adev->ip_versions[SMUIO_HWIP][0]) { 1295 case IP_VERSION(9, 0, 0): 1296 case IP_VERSION(9, 0, 1): 1297 case IP_VERSION(10, 0, 0): 1298 case IP_VERSION(10, 0, 1): 1299 case IP_VERSION(10, 0, 2): 1300 adev->smuio.funcs = &smuio_v9_0_funcs; 1301 break; 1302 case IP_VERSION(11, 0, 0): 1303 case IP_VERSION(11, 0, 2): 1304 case IP_VERSION(11, 0, 3): 1305 case IP_VERSION(11, 0, 4): 1306 case IP_VERSION(11, 0, 7): 1307 case IP_VERSION(11, 0, 8): 1308 adev->smuio.funcs = &smuio_v11_0_funcs; 1309 break; 1310 case IP_VERSION(11, 0, 6): 1311 case IP_VERSION(11, 0, 10): 1312 case IP_VERSION(11, 0, 11): 1313 case IP_VERSION(11, 5, 0): 1314 case IP_VERSION(13, 0, 1): 1315 adev->smuio.funcs = &smuio_v11_0_6_funcs; 1316 break; 1317 case IP_VERSION(13, 0, 2): 1318 adev->smuio.funcs = &smuio_v13_0_funcs; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 r = amdgpu_discovery_set_common_ip_blocks(adev); 1325 if (r) 1326 return r; 1327 1328 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 1329 if (r) 1330 return r; 1331 1332 /* For SR-IOV, PSP needs to be initialized before IH */ 1333 if (amdgpu_sriov_vf(adev)) { 1334 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1335 if (r) 1336 return r; 1337 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1338 if (r) 1339 return r; 1340 } else { 1341 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1342 if (r) 1343 return r; 1344 1345 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1346 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1347 if (r) 1348 return r; 1349 } 1350 } 1351 1352 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1353 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1354 if (r) 1355 return r; 1356 } 1357 1358 r = amdgpu_discovery_set_display_ip_blocks(adev); 1359 if (r) 1360 return r; 1361 1362 r = amdgpu_discovery_set_gc_ip_blocks(adev); 1363 if (r) 1364 return r; 1365 1366 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 1367 if (r) 1368 return r; 1369 1370 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 1371 !amdgpu_sriov_vf(adev)) { 1372 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1373 if (r) 1374 return r; 1375 } 1376 1377 r = amdgpu_discovery_set_mm_ip_blocks(adev); 1378 if (r) 1379 return r; 1380 1381 if (adev->enable_mes) { 1382 r = amdgpu_discovery_set_mes_ip_blocks(adev); 1383 if (r) 1384 return r; 1385 } 1386 1387 return 0; 1388 } 1389 1390