1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "df_v4_3.h" 37 #include "nbio_v6_1.h" 38 #include "nbio_v7_0.h" 39 #include "nbio_v7_4.h" 40 #include "hdp_v4_0.h" 41 #include "vega10_ih.h" 42 #include "vega20_ih.h" 43 #include "sdma_v4_0.h" 44 #include "sdma_v4_4_2.h" 45 #include "uvd_v7_0.h" 46 #include "vce_v4_0.h" 47 #include "vcn_v1_0.h" 48 #include "vcn_v2_5.h" 49 #include "jpeg_v2_5.h" 50 #include "smuio_v9_0.h" 51 #include "gmc_v10_0.h" 52 #include "gmc_v11_0.h" 53 #include "gfxhub_v2_0.h" 54 #include "mmhub_v2_0.h" 55 #include "nbio_v2_3.h" 56 #include "nbio_v4_3.h" 57 #include "nbio_v7_2.h" 58 #include "nbio_v7_7.h" 59 #include "hdp_v5_0.h" 60 #include "hdp_v5_2.h" 61 #include "hdp_v6_0.h" 62 #include "nv.h" 63 #include "soc21.h" 64 #include "navi10_ih.h" 65 #include "ih_v6_0.h" 66 #include "gfx_v10_0.h" 67 #include "gfx_v11_0.h" 68 #include "sdma_v5_0.h" 69 #include "sdma_v5_2.h" 70 #include "sdma_v6_0.h" 71 #include "lsdma_v6_0.h" 72 #include "vcn_v2_0.h" 73 #include "jpeg_v2_0.h" 74 #include "vcn_v3_0.h" 75 #include "jpeg_v3_0.h" 76 #include "vcn_v4_0.h" 77 #include "jpeg_v4_0.h" 78 #include "amdgpu_vkms.h" 79 #include "mes_v10_1.h" 80 #include "mes_v11_0.h" 81 #include "smuio_v11_0.h" 82 #include "smuio_v11_0_6.h" 83 #include "smuio_v13_0.h" 84 #include "smuio_v13_0_6.h" 85 86 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 87 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 88 89 #define mmRCC_CONFIG_MEMSIZE 0xde3 90 #define mmMM_INDEX 0x0 91 #define mmMM_INDEX_HI 0x6 92 #define mmMM_DATA 0x1 93 94 static const char *hw_id_names[HW_ID_MAX] = { 95 [MP1_HWID] = "MP1", 96 [MP2_HWID] = "MP2", 97 [THM_HWID] = "THM", 98 [SMUIO_HWID] = "SMUIO", 99 [FUSE_HWID] = "FUSE", 100 [CLKA_HWID] = "CLKA", 101 [PWR_HWID] = "PWR", 102 [GC_HWID] = "GC", 103 [UVD_HWID] = "UVD", 104 [AUDIO_AZ_HWID] = "AUDIO_AZ", 105 [ACP_HWID] = "ACP", 106 [DCI_HWID] = "DCI", 107 [DMU_HWID] = "DMU", 108 [DCO_HWID] = "DCO", 109 [DIO_HWID] = "DIO", 110 [XDMA_HWID] = "XDMA", 111 [DCEAZ_HWID] = "DCEAZ", 112 [DAZ_HWID] = "DAZ", 113 [SDPMUX_HWID] = "SDPMUX", 114 [NTB_HWID] = "NTB", 115 [IOHC_HWID] = "IOHC", 116 [L2IMU_HWID] = "L2IMU", 117 [VCE_HWID] = "VCE", 118 [MMHUB_HWID] = "MMHUB", 119 [ATHUB_HWID] = "ATHUB", 120 [DBGU_NBIO_HWID] = "DBGU_NBIO", 121 [DFX_HWID] = "DFX", 122 [DBGU0_HWID] = "DBGU0", 123 [DBGU1_HWID] = "DBGU1", 124 [OSSSYS_HWID] = "OSSSYS", 125 [HDP_HWID] = "HDP", 126 [SDMA0_HWID] = "SDMA0", 127 [SDMA1_HWID] = "SDMA1", 128 [SDMA2_HWID] = "SDMA2", 129 [SDMA3_HWID] = "SDMA3", 130 [LSDMA_HWID] = "LSDMA", 131 [ISP_HWID] = "ISP", 132 [DBGU_IO_HWID] = "DBGU_IO", 133 [DF_HWID] = "DF", 134 [CLKB_HWID] = "CLKB", 135 [FCH_HWID] = "FCH", 136 [DFX_DAP_HWID] = "DFX_DAP", 137 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 138 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 139 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 140 [L1IMU3_HWID] = "L1IMU3", 141 [L1IMU4_HWID] = "L1IMU4", 142 [L1IMU5_HWID] = "L1IMU5", 143 [L1IMU6_HWID] = "L1IMU6", 144 [L1IMU7_HWID] = "L1IMU7", 145 [L1IMU8_HWID] = "L1IMU8", 146 [L1IMU9_HWID] = "L1IMU9", 147 [L1IMU10_HWID] = "L1IMU10", 148 [L1IMU11_HWID] = "L1IMU11", 149 [L1IMU12_HWID] = "L1IMU12", 150 [L1IMU13_HWID] = "L1IMU13", 151 [L1IMU14_HWID] = "L1IMU14", 152 [L1IMU15_HWID] = "L1IMU15", 153 [WAFLC_HWID] = "WAFLC", 154 [FCH_USB_PD_HWID] = "FCH_USB_PD", 155 [PCIE_HWID] = "PCIE", 156 [PCS_HWID] = "PCS", 157 [DDCL_HWID] = "DDCL", 158 [SST_HWID] = "SST", 159 [IOAGR_HWID] = "IOAGR", 160 [NBIF_HWID] = "NBIF", 161 [IOAPIC_HWID] = "IOAPIC", 162 [SYSTEMHUB_HWID] = "SYSTEMHUB", 163 [NTBCCP_HWID] = "NTBCCP", 164 [UMC_HWID] = "UMC", 165 [SATA_HWID] = "SATA", 166 [USB_HWID] = "USB", 167 [CCXSEC_HWID] = "CCXSEC", 168 [XGMI_HWID] = "XGMI", 169 [XGBE_HWID] = "XGBE", 170 [MP0_HWID] = "MP0", 171 }; 172 173 static int hw_id_map[MAX_HWIP] = { 174 [GC_HWIP] = GC_HWID, 175 [HDP_HWIP] = HDP_HWID, 176 [SDMA0_HWIP] = SDMA0_HWID, 177 [SDMA1_HWIP] = SDMA1_HWID, 178 [SDMA2_HWIP] = SDMA2_HWID, 179 [SDMA3_HWIP] = SDMA3_HWID, 180 [LSDMA_HWIP] = LSDMA_HWID, 181 [MMHUB_HWIP] = MMHUB_HWID, 182 [ATHUB_HWIP] = ATHUB_HWID, 183 [NBIO_HWIP] = NBIF_HWID, 184 [MP0_HWIP] = MP0_HWID, 185 [MP1_HWIP] = MP1_HWID, 186 [UVD_HWIP] = UVD_HWID, 187 [VCE_HWIP] = VCE_HWID, 188 [DF_HWIP] = DF_HWID, 189 [DCE_HWIP] = DMU_HWID, 190 [OSSSYS_HWIP] = OSSSYS_HWID, 191 [SMUIO_HWIP] = SMUIO_HWID, 192 [PWR_HWIP] = PWR_HWID, 193 [NBIF_HWIP] = NBIF_HWID, 194 [THM_HWIP] = THM_HWID, 195 [CLK_HWIP] = CLKA_HWID, 196 [UMC_HWIP] = UMC_HWID, 197 [XGMI_HWIP] = XGMI_HWID, 198 [DCI_HWIP] = DCI_HWID, 199 [PCIE_HWIP] = PCIE_HWID, 200 }; 201 202 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 203 { 204 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 205 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 206 207 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 208 adev->mman.discovery_tmr_size, false); 209 return 0; 210 } 211 212 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 213 { 214 const struct firmware *fw; 215 const char *fw_name; 216 int r; 217 218 switch (amdgpu_discovery) { 219 case 2: 220 fw_name = FIRMWARE_IP_DISCOVERY; 221 break; 222 default: 223 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 224 return -EINVAL; 225 } 226 227 r = request_firmware(&fw, fw_name, adev->dev); 228 if (r) { 229 dev_err(adev->dev, "can't load firmware \"%s\"\n", 230 fw_name); 231 return r; 232 } 233 234 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 235 release_firmware(fw); 236 237 return 0; 238 } 239 240 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 241 { 242 uint16_t checksum = 0; 243 int i; 244 245 for (i = 0; i < size; i++) 246 checksum += data[i]; 247 248 return checksum; 249 } 250 251 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 252 uint16_t expected) 253 { 254 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 255 } 256 257 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 258 { 259 struct binary_header *bhdr; 260 bhdr = (struct binary_header *)binary; 261 262 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 263 } 264 265 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 266 { 267 /* 268 * So far, apply this quirk only on those Navy Flounder boards which 269 * have a bad harvest table of VCN config. 270 */ 271 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 272 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 273 switch (adev->pdev->revision) { 274 case 0xC1: 275 case 0xC2: 276 case 0xC3: 277 case 0xC5: 278 case 0xC7: 279 case 0xCF: 280 case 0xDF: 281 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 282 break; 283 default: 284 break; 285 } 286 } 287 } 288 289 static int amdgpu_discovery_init(struct amdgpu_device *adev) 290 { 291 struct table_info *info; 292 struct binary_header *bhdr; 293 uint16_t offset; 294 uint16_t size; 295 uint16_t checksum; 296 int r; 297 298 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 299 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 300 if (!adev->mman.discovery_bin) 301 return -ENOMEM; 302 303 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 304 if (r) { 305 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 306 r = -EINVAL; 307 goto out; 308 } 309 310 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin) || amdgpu_discovery == 2) { 311 /* ignore the discovery binary from vram if discovery=2 in kernel module parameter */ 312 if (amdgpu_discovery == 2) 313 dev_info(adev->dev,"force read ip discovery binary from file"); 314 else 315 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 316 317 /* retry read ip discovery binary from file */ 318 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 319 if (r) { 320 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 321 r = -EINVAL; 322 goto out; 323 } 324 /* check the ip discovery binary signature */ 325 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 326 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 327 r = -EINVAL; 328 goto out; 329 } 330 } 331 332 bhdr = (struct binary_header *)adev->mman.discovery_bin; 333 334 offset = offsetof(struct binary_header, binary_checksum) + 335 sizeof(bhdr->binary_checksum); 336 size = le16_to_cpu(bhdr->binary_size) - offset; 337 checksum = le16_to_cpu(bhdr->binary_checksum); 338 339 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 340 size, checksum)) { 341 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 342 r = -EINVAL; 343 goto out; 344 } 345 346 info = &bhdr->table_list[IP_DISCOVERY]; 347 offset = le16_to_cpu(info->offset); 348 checksum = le16_to_cpu(info->checksum); 349 350 if (offset) { 351 struct ip_discovery_header *ihdr = 352 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 353 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 354 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 355 r = -EINVAL; 356 goto out; 357 } 358 359 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 360 le16_to_cpu(ihdr->size), checksum)) { 361 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 362 r = -EINVAL; 363 goto out; 364 } 365 } 366 367 info = &bhdr->table_list[GC]; 368 offset = le16_to_cpu(info->offset); 369 checksum = le16_to_cpu(info->checksum); 370 371 if (offset) { 372 struct gpu_info_header *ghdr = 373 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 374 375 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 376 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 377 r = -EINVAL; 378 goto out; 379 } 380 381 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 382 le32_to_cpu(ghdr->size), checksum)) { 383 dev_err(adev->dev, "invalid gc data table checksum\n"); 384 r = -EINVAL; 385 goto out; 386 } 387 } 388 389 info = &bhdr->table_list[HARVEST_INFO]; 390 offset = le16_to_cpu(info->offset); 391 checksum = le16_to_cpu(info->checksum); 392 393 if (offset) { 394 struct harvest_info_header *hhdr = 395 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 396 397 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 398 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 399 r = -EINVAL; 400 goto out; 401 } 402 403 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 404 sizeof(struct harvest_table), checksum)) { 405 dev_err(adev->dev, "invalid harvest data table checksum\n"); 406 r = -EINVAL; 407 goto out; 408 } 409 } 410 411 info = &bhdr->table_list[VCN_INFO]; 412 offset = le16_to_cpu(info->offset); 413 checksum = le16_to_cpu(info->checksum); 414 415 if (offset) { 416 struct vcn_info_header *vhdr = 417 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 418 419 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 420 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 421 r = -EINVAL; 422 goto out; 423 } 424 425 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 426 le32_to_cpu(vhdr->size_bytes), checksum)) { 427 dev_err(adev->dev, "invalid vcn data table checksum\n"); 428 r = -EINVAL; 429 goto out; 430 } 431 } 432 433 info = &bhdr->table_list[MALL_INFO]; 434 offset = le16_to_cpu(info->offset); 435 checksum = le16_to_cpu(info->checksum); 436 437 if (0 && offset) { 438 struct mall_info_header *mhdr = 439 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 440 441 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 442 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 443 r = -EINVAL; 444 goto out; 445 } 446 447 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 448 le32_to_cpu(mhdr->size_bytes), checksum)) { 449 dev_err(adev->dev, "invalid mall data table checksum\n"); 450 r = -EINVAL; 451 goto out; 452 } 453 } 454 455 return 0; 456 457 out: 458 kfree(adev->mman.discovery_bin); 459 adev->mman.discovery_bin = NULL; 460 461 return r; 462 } 463 464 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 465 466 void amdgpu_discovery_fini(struct amdgpu_device *adev) 467 { 468 amdgpu_discovery_sysfs_fini(adev); 469 kfree(adev->mman.discovery_bin); 470 adev->mman.discovery_bin = NULL; 471 } 472 473 static int amdgpu_discovery_validate_ip(const struct ip *ip) 474 { 475 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 476 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 477 ip->number_instance); 478 return -EINVAL; 479 } 480 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 481 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 482 le16_to_cpu(ip->hw_id)); 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488 489 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 490 uint32_t *vcn_harvest_count) 491 { 492 struct binary_header *bhdr; 493 struct ip_discovery_header *ihdr; 494 struct die_header *dhdr; 495 struct ip *ip; 496 uint16_t die_offset, ip_offset, num_dies, num_ips; 497 int i, j; 498 499 bhdr = (struct binary_header *)adev->mman.discovery_bin; 500 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 501 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 502 num_dies = le16_to_cpu(ihdr->num_dies); 503 504 /* scan harvest bit of all IP data structures */ 505 for (i = 0; i < num_dies; i++) { 506 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 507 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 508 num_ips = le16_to_cpu(dhdr->num_ips); 509 ip_offset = die_offset + sizeof(*dhdr); 510 511 for (j = 0; j < num_ips; j++) { 512 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 513 514 if (amdgpu_discovery_validate_ip(ip)) 515 goto next_ip; 516 517 if (le16_to_cpu(ip->harvest) == 1) { 518 switch (le16_to_cpu(ip->hw_id)) { 519 case VCN_HWID: 520 (*vcn_harvest_count)++; 521 if (ip->number_instance == 0) 522 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 523 else 524 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 525 break; 526 case DMU_HWID: 527 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 528 break; 529 default: 530 break; 531 } 532 } 533 next_ip: 534 ip_offset += struct_size(ip, base_address, ip->num_base_address); 535 } 536 } 537 } 538 539 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 540 uint32_t *vcn_harvest_count, 541 uint32_t *umc_harvest_count) 542 { 543 struct binary_header *bhdr; 544 struct harvest_table *harvest_info; 545 u16 offset; 546 int i; 547 uint32_t umc_harvest_config = 0; 548 549 bhdr = (struct binary_header *)adev->mman.discovery_bin; 550 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 551 552 if (!offset) { 553 dev_err(adev->dev, "invalid harvest table offset\n"); 554 return; 555 } 556 557 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 558 559 for (i = 0; i < 32; i++) { 560 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 561 break; 562 563 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 564 case VCN_HWID: 565 (*vcn_harvest_count)++; 566 if (harvest_info->list[i].number_instance == 0) 567 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 568 else 569 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 570 break; 571 case DMU_HWID: 572 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 573 break; 574 case UMC_HWID: 575 umc_harvest_config |= 576 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 577 (*umc_harvest_count)++; 578 break; 579 default: 580 break; 581 } 582 } 583 584 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 585 ~umc_harvest_config; 586 } 587 588 /* ================================================== */ 589 590 struct ip_hw_instance { 591 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 592 593 int hw_id; 594 u8 num_instance; 595 u8 major, minor, revision; 596 u8 harvest; 597 598 int num_base_addresses; 599 u32 base_addr[]; 600 }; 601 602 struct ip_hw_id { 603 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 604 int hw_id; 605 }; 606 607 struct ip_die_entry { 608 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 609 u16 num_ips; 610 }; 611 612 /* -------------------------------------------------- */ 613 614 struct ip_hw_instance_attr { 615 struct attribute attr; 616 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 617 }; 618 619 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 620 { 621 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 622 } 623 624 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 625 { 626 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 627 } 628 629 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 630 { 631 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 632 } 633 634 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 635 { 636 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 637 } 638 639 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 640 { 641 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 642 } 643 644 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 645 { 646 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 647 } 648 649 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 650 { 651 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 652 } 653 654 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 655 { 656 ssize_t res, at; 657 int ii; 658 659 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 660 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 661 */ 662 if (at + 12 > PAGE_SIZE) 663 break; 664 res = sysfs_emit_at(buf, at, "0x%08X\n", 665 ip_hw_instance->base_addr[ii]); 666 if (res <= 0) 667 break; 668 at += res; 669 } 670 671 return res < 0 ? res : at; 672 } 673 674 static struct ip_hw_instance_attr ip_hw_attr[] = { 675 __ATTR_RO(hw_id), 676 __ATTR_RO(num_instance), 677 __ATTR_RO(major), 678 __ATTR_RO(minor), 679 __ATTR_RO(revision), 680 __ATTR_RO(harvest), 681 __ATTR_RO(num_base_addresses), 682 __ATTR_RO(base_addr), 683 }; 684 685 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 686 ATTRIBUTE_GROUPS(ip_hw_instance); 687 688 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 689 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 690 691 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 692 struct attribute *attr, 693 char *buf) 694 { 695 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 696 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 697 698 if (!ip_hw_attr->show) 699 return -EIO; 700 701 return ip_hw_attr->show(ip_hw_instance, buf); 702 } 703 704 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 705 .show = ip_hw_instance_attr_show, 706 }; 707 708 static void ip_hw_instance_release(struct kobject *kobj) 709 { 710 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 711 712 kfree(ip_hw_instance); 713 } 714 715 static const struct kobj_type ip_hw_instance_ktype = { 716 .release = ip_hw_instance_release, 717 .sysfs_ops = &ip_hw_instance_sysfs_ops, 718 .default_groups = ip_hw_instance_groups, 719 }; 720 721 /* -------------------------------------------------- */ 722 723 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 724 725 static void ip_hw_id_release(struct kobject *kobj) 726 { 727 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 728 729 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 730 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 731 kfree(ip_hw_id); 732 } 733 734 static const struct kobj_type ip_hw_id_ktype = { 735 .release = ip_hw_id_release, 736 .sysfs_ops = &kobj_sysfs_ops, 737 }; 738 739 /* -------------------------------------------------- */ 740 741 static void die_kobj_release(struct kobject *kobj); 742 static void ip_disc_release(struct kobject *kobj); 743 744 struct ip_die_entry_attribute { 745 struct attribute attr; 746 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 747 }; 748 749 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 750 751 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 752 { 753 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 754 } 755 756 /* If there are more ip_die_entry attrs, other than the number of IPs, 757 * we can make this intro an array of attrs, and then initialize 758 * ip_die_entry_attrs in a loop. 759 */ 760 static struct ip_die_entry_attribute num_ips_attr = 761 __ATTR_RO(num_ips); 762 763 static struct attribute *ip_die_entry_attrs[] = { 764 &num_ips_attr.attr, 765 NULL, 766 }; 767 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 768 769 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 770 771 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 772 struct attribute *attr, 773 char *buf) 774 { 775 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 776 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 777 778 if (!ip_die_entry_attr->show) 779 return -EIO; 780 781 return ip_die_entry_attr->show(ip_die_entry, buf); 782 } 783 784 static void ip_die_entry_release(struct kobject *kobj) 785 { 786 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 787 788 if (!list_empty(&ip_die_entry->ip_kset.list)) 789 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 790 kfree(ip_die_entry); 791 } 792 793 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 794 .show = ip_die_entry_attr_show, 795 }; 796 797 static const struct kobj_type ip_die_entry_ktype = { 798 .release = ip_die_entry_release, 799 .sysfs_ops = &ip_die_entry_sysfs_ops, 800 .default_groups = ip_die_entry_groups, 801 }; 802 803 static const struct kobj_type die_kobj_ktype = { 804 .release = die_kobj_release, 805 .sysfs_ops = &kobj_sysfs_ops, 806 }; 807 808 static const struct kobj_type ip_discovery_ktype = { 809 .release = ip_disc_release, 810 .sysfs_ops = &kobj_sysfs_ops, 811 }; 812 813 struct ip_discovery_top { 814 struct kobject kobj; /* ip_discovery/ */ 815 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 816 struct amdgpu_device *adev; 817 }; 818 819 static void die_kobj_release(struct kobject *kobj) 820 { 821 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 822 struct ip_discovery_top, 823 die_kset); 824 if (!list_empty(&ip_top->die_kset.list)) 825 DRM_ERROR("ip_top->die_kset is not empty"); 826 } 827 828 static void ip_disc_release(struct kobject *kobj) 829 { 830 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 831 kobj); 832 struct amdgpu_device *adev = ip_top->adev; 833 834 adev->ip_top = NULL; 835 kfree(ip_top); 836 } 837 838 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 839 struct ip_die_entry *ip_die_entry, 840 const size_t _ip_offset, const int num_ips) 841 { 842 int ii, jj, kk, res; 843 844 DRM_DEBUG("num_ips:%d", num_ips); 845 846 /* Find all IPs of a given HW ID, and add their instance to 847 * #die/#hw_id/#instance/<attributes> 848 */ 849 for (ii = 0; ii < HW_ID_MAX; ii++) { 850 struct ip_hw_id *ip_hw_id = NULL; 851 size_t ip_offset = _ip_offset; 852 853 for (jj = 0; jj < num_ips; jj++) { 854 struct ip *ip; 855 struct ip_hw_instance *ip_hw_instance; 856 857 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 858 if (amdgpu_discovery_validate_ip(ip) || 859 le16_to_cpu(ip->hw_id) != ii) 860 goto next_ip; 861 862 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 863 864 /* We have a hw_id match; register the hw 865 * block if not yet registered. 866 */ 867 if (!ip_hw_id) { 868 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 869 if (!ip_hw_id) 870 return -ENOMEM; 871 ip_hw_id->hw_id = ii; 872 873 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 874 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 875 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 876 res = kset_register(&ip_hw_id->hw_id_kset); 877 if (res) { 878 DRM_ERROR("Couldn't register ip_hw_id kset"); 879 kfree(ip_hw_id); 880 return res; 881 } 882 if (hw_id_names[ii]) { 883 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 884 &ip_hw_id->hw_id_kset.kobj, 885 hw_id_names[ii]); 886 if (res) { 887 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 888 hw_id_names[ii], 889 kobject_name(&ip_die_entry->ip_kset.kobj)); 890 } 891 } 892 } 893 894 /* Now register its instance. 895 */ 896 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 897 base_addr, 898 ip->num_base_address), 899 GFP_KERNEL); 900 if (!ip_hw_instance) { 901 DRM_ERROR("no memory for ip_hw_instance"); 902 return -ENOMEM; 903 } 904 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 905 ip_hw_instance->num_instance = ip->number_instance; 906 ip_hw_instance->major = ip->major; 907 ip_hw_instance->minor = ip->minor; 908 ip_hw_instance->revision = ip->revision; 909 ip_hw_instance->harvest = ip->harvest; 910 ip_hw_instance->num_base_addresses = ip->num_base_address; 911 912 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 913 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 914 915 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 916 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 917 res = kobject_add(&ip_hw_instance->kobj, NULL, 918 "%d", ip_hw_instance->num_instance); 919 next_ip: 920 ip_offset += struct_size(ip, base_address, ip->num_base_address); 921 } 922 } 923 924 return 0; 925 } 926 927 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 928 { 929 struct binary_header *bhdr; 930 struct ip_discovery_header *ihdr; 931 struct die_header *dhdr; 932 struct kset *die_kset = &adev->ip_top->die_kset; 933 u16 num_dies, die_offset, num_ips; 934 size_t ip_offset; 935 int ii, res; 936 937 bhdr = (struct binary_header *)adev->mman.discovery_bin; 938 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 939 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 940 num_dies = le16_to_cpu(ihdr->num_dies); 941 942 DRM_DEBUG("number of dies: %d\n", num_dies); 943 944 for (ii = 0; ii < num_dies; ii++) { 945 struct ip_die_entry *ip_die_entry; 946 947 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 948 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 949 num_ips = le16_to_cpu(dhdr->num_ips); 950 ip_offset = die_offset + sizeof(*dhdr); 951 952 /* Add the die to the kset. 953 * 954 * dhdr->die_id == ii, which was checked in 955 * amdgpu_discovery_reg_base_init(). 956 */ 957 958 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 959 if (!ip_die_entry) 960 return -ENOMEM; 961 962 ip_die_entry->num_ips = num_ips; 963 964 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 965 ip_die_entry->ip_kset.kobj.kset = die_kset; 966 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 967 res = kset_register(&ip_die_entry->ip_kset); 968 if (res) { 969 DRM_ERROR("Couldn't register ip_die_entry kset"); 970 kfree(ip_die_entry); 971 return res; 972 } 973 974 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 975 } 976 977 return 0; 978 } 979 980 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 981 { 982 struct kset *die_kset; 983 int res, ii; 984 985 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 986 if (!adev->ip_top) 987 return -ENOMEM; 988 989 adev->ip_top->adev = adev; 990 991 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 992 &adev->dev->kobj, "ip_discovery"); 993 if (res) { 994 DRM_ERROR("Couldn't init and add ip_discovery/"); 995 goto Err; 996 } 997 998 die_kset = &adev->ip_top->die_kset; 999 kobject_set_name(&die_kset->kobj, "%s", "die"); 1000 die_kset->kobj.parent = &adev->ip_top->kobj; 1001 die_kset->kobj.ktype = &die_kobj_ktype; 1002 res = kset_register(&adev->ip_top->die_kset); 1003 if (res) { 1004 DRM_ERROR("Couldn't register die_kset"); 1005 goto Err; 1006 } 1007 1008 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1009 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1010 ip_hw_instance_attrs[ii] = NULL; 1011 1012 res = amdgpu_discovery_sysfs_recurse(adev); 1013 1014 return res; 1015 Err: 1016 kobject_put(&adev->ip_top->kobj); 1017 return res; 1018 } 1019 1020 /* -------------------------------------------------- */ 1021 1022 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1023 1024 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1025 { 1026 struct list_head *el, *tmp; 1027 struct kset *hw_id_kset; 1028 1029 hw_id_kset = &ip_hw_id->hw_id_kset; 1030 spin_lock(&hw_id_kset->list_lock); 1031 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1032 list_del_init(el); 1033 spin_unlock(&hw_id_kset->list_lock); 1034 /* kobject is embedded in ip_hw_instance */ 1035 kobject_put(list_to_kobj(el)); 1036 spin_lock(&hw_id_kset->list_lock); 1037 } 1038 spin_unlock(&hw_id_kset->list_lock); 1039 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1040 } 1041 1042 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1043 { 1044 struct list_head *el, *tmp; 1045 struct kset *ip_kset; 1046 1047 ip_kset = &ip_die_entry->ip_kset; 1048 spin_lock(&ip_kset->list_lock); 1049 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1050 list_del_init(el); 1051 spin_unlock(&ip_kset->list_lock); 1052 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1053 spin_lock(&ip_kset->list_lock); 1054 } 1055 spin_unlock(&ip_kset->list_lock); 1056 kobject_put(&ip_die_entry->ip_kset.kobj); 1057 } 1058 1059 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1060 { 1061 struct list_head *el, *tmp; 1062 struct kset *die_kset; 1063 1064 die_kset = &adev->ip_top->die_kset; 1065 spin_lock(&die_kset->list_lock); 1066 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1067 list_del_init(el); 1068 spin_unlock(&die_kset->list_lock); 1069 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1070 spin_lock(&die_kset->list_lock); 1071 } 1072 spin_unlock(&die_kset->list_lock); 1073 kobject_put(&adev->ip_top->die_kset.kobj); 1074 kobject_put(&adev->ip_top->kobj); 1075 } 1076 1077 /* ================================================== */ 1078 1079 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1080 { 1081 struct binary_header *bhdr; 1082 struct ip_discovery_header *ihdr; 1083 struct die_header *dhdr; 1084 struct ip *ip; 1085 uint16_t die_offset; 1086 uint16_t ip_offset; 1087 uint16_t num_dies; 1088 uint16_t num_ips; 1089 uint8_t num_base_address; 1090 int hw_ip; 1091 int i, j, k; 1092 int r; 1093 1094 r = amdgpu_discovery_init(adev); 1095 if (r) { 1096 DRM_ERROR("amdgpu_discovery_init failed\n"); 1097 return r; 1098 } 1099 1100 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1101 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1102 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1103 num_dies = le16_to_cpu(ihdr->num_dies); 1104 1105 DRM_DEBUG("number of dies: %d\n", num_dies); 1106 1107 for (i = 0; i < num_dies; i++) { 1108 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1109 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1110 num_ips = le16_to_cpu(dhdr->num_ips); 1111 ip_offset = die_offset + sizeof(*dhdr); 1112 1113 if (le16_to_cpu(dhdr->die_id) != i) { 1114 DRM_ERROR("invalid die id %d, expected %d\n", 1115 le16_to_cpu(dhdr->die_id), i); 1116 return -EINVAL; 1117 } 1118 1119 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1120 le16_to_cpu(dhdr->die_id), num_ips); 1121 1122 for (j = 0; j < num_ips; j++) { 1123 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1124 1125 if (amdgpu_discovery_validate_ip(ip)) 1126 goto next_ip; 1127 1128 num_base_address = ip->num_base_address; 1129 1130 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1131 hw_id_names[le16_to_cpu(ip->hw_id)], 1132 le16_to_cpu(ip->hw_id), 1133 ip->number_instance, 1134 ip->major, ip->minor, 1135 ip->revision); 1136 1137 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1138 /* Bit [5:0]: original revision value 1139 * Bit [7:6]: en/decode capability: 1140 * 0b00 : VCN function normally 1141 * 0b10 : encode is disabled 1142 * 0b01 : decode is disabled 1143 */ 1144 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1145 ip->revision & 0xc0; 1146 ip->revision &= ~0xc0; 1147 if (adev->vcn.num_vcn_inst < AMDGPU_MAX_VCN_INSTANCES) 1148 adev->vcn.num_vcn_inst++; 1149 else 1150 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1151 adev->vcn.num_vcn_inst + 1, 1152 AMDGPU_MAX_VCN_INSTANCES); 1153 } 1154 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1155 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1156 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1157 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1158 if (adev->sdma.num_instances < AMDGPU_MAX_SDMA_INSTANCES) 1159 adev->sdma.num_instances++; 1160 else 1161 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1162 adev->sdma.num_instances + 1, 1163 AMDGPU_MAX_SDMA_INSTANCES); 1164 } 1165 1166 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1167 adev->gmc.num_umc++; 1168 adev->umc.node_inst_num++; 1169 } 1170 1171 for (k = 0; k < num_base_address; k++) { 1172 /* 1173 * convert the endianness of base addresses in place, 1174 * so that we don't need to convert them when accessing adev->reg_offset. 1175 */ 1176 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1177 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1178 } 1179 1180 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1181 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1182 DRM_DEBUG("set register base offset for %s\n", 1183 hw_id_names[le16_to_cpu(ip->hw_id)]); 1184 adev->reg_offset[hw_ip][ip->number_instance] = 1185 ip->base_address; 1186 /* Instance support is somewhat inconsistent. 1187 * SDMA is a good example. Sienna cichlid has 4 total 1188 * SDMA instances, each enumerated separately (HWIDs 1189 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1190 * but they are enumerated as multiple instances of the 1191 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1192 * example. On most chips there are multiple instances 1193 * with the same HWID. 1194 */ 1195 adev->ip_versions[hw_ip][ip->number_instance] = 1196 IP_VERSION(ip->major, ip->minor, ip->revision); 1197 } 1198 } 1199 1200 next_ip: 1201 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1202 } 1203 } 1204 1205 amdgpu_discovery_sysfs_init(adev); 1206 1207 return 0; 1208 } 1209 1210 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1211 int *major, int *minor, int *revision) 1212 { 1213 struct binary_header *bhdr; 1214 struct ip_discovery_header *ihdr; 1215 struct die_header *dhdr; 1216 struct ip *ip; 1217 uint16_t die_offset; 1218 uint16_t ip_offset; 1219 uint16_t num_dies; 1220 uint16_t num_ips; 1221 int i, j; 1222 1223 if (!adev->mman.discovery_bin) { 1224 DRM_ERROR("ip discovery uninitialized\n"); 1225 return -EINVAL; 1226 } 1227 1228 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1229 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1230 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1231 num_dies = le16_to_cpu(ihdr->num_dies); 1232 1233 for (i = 0; i < num_dies; i++) { 1234 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1235 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1236 num_ips = le16_to_cpu(dhdr->num_ips); 1237 ip_offset = die_offset + sizeof(*dhdr); 1238 1239 for (j = 0; j < num_ips; j++) { 1240 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1241 1242 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1243 if (major) 1244 *major = ip->major; 1245 if (minor) 1246 *minor = ip->minor; 1247 if (revision) 1248 *revision = ip->revision; 1249 return 0; 1250 } 1251 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1252 } 1253 } 1254 1255 return -EINVAL; 1256 } 1257 1258 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1259 { 1260 int vcn_harvest_count = 0; 1261 int umc_harvest_count = 0; 1262 1263 /* 1264 * Harvest table does not fit Navi1x and legacy GPUs, 1265 * so read harvest bit per IP data structure to set 1266 * harvest configuration. 1267 */ 1268 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1269 if ((adev->pdev->device == 0x731E && 1270 (adev->pdev->revision == 0xC6 || 1271 adev->pdev->revision == 0xC7)) || 1272 (adev->pdev->device == 0x7340 && 1273 adev->pdev->revision == 0xC9) || 1274 (adev->pdev->device == 0x7360 && 1275 adev->pdev->revision == 0xC7)) 1276 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1277 &vcn_harvest_count); 1278 } else { 1279 amdgpu_discovery_read_from_harvest_table(adev, 1280 &vcn_harvest_count, 1281 &umc_harvest_count); 1282 } 1283 1284 amdgpu_discovery_harvest_config_quirk(adev); 1285 1286 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1287 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1288 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1289 } 1290 1291 if (umc_harvest_count < adev->gmc.num_umc) { 1292 adev->gmc.num_umc -= umc_harvest_count; 1293 } 1294 } 1295 1296 union gc_info { 1297 struct gc_info_v1_0 v1; 1298 struct gc_info_v1_1 v1_1; 1299 struct gc_info_v1_2 v1_2; 1300 struct gc_info_v2_0 v2; 1301 }; 1302 1303 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1304 { 1305 struct binary_header *bhdr; 1306 union gc_info *gc_info; 1307 u16 offset; 1308 1309 if (!adev->mman.discovery_bin) { 1310 DRM_ERROR("ip discovery uninitialized\n"); 1311 return -EINVAL; 1312 } 1313 1314 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1315 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1316 1317 if (!offset) 1318 return 0; 1319 1320 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1321 1322 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1323 case 1: 1324 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1325 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1326 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1327 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1328 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1329 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1330 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1331 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1332 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1333 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1334 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1335 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1336 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1337 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1338 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1339 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1340 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1341 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1342 if (gc_info->v1.header.version_minor >= 1) { 1343 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1344 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1345 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1346 } 1347 if (gc_info->v1.header.version_minor >= 2) { 1348 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1349 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1350 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1351 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1352 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1353 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1354 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1355 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1356 } 1357 break; 1358 case 2: 1359 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1360 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1361 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1362 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1363 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1364 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1365 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1366 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1367 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1368 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1369 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1370 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1371 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1372 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1373 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1374 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1375 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1376 break; 1377 default: 1378 dev_err(adev->dev, 1379 "Unhandled GC info table %d.%d\n", 1380 le16_to_cpu(gc_info->v1.header.version_major), 1381 le16_to_cpu(gc_info->v1.header.version_minor)); 1382 return -EINVAL; 1383 } 1384 return 0; 1385 } 1386 1387 union mall_info { 1388 struct mall_info_v1_0 v1; 1389 }; 1390 1391 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1392 { 1393 struct binary_header *bhdr; 1394 union mall_info *mall_info; 1395 u32 u, mall_size_per_umc, m_s_present, half_use; 1396 u64 mall_size; 1397 u16 offset; 1398 1399 if (!adev->mman.discovery_bin) { 1400 DRM_ERROR("ip discovery uninitialized\n"); 1401 return -EINVAL; 1402 } 1403 1404 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1405 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1406 1407 if (!offset) 1408 return 0; 1409 1410 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1411 1412 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1413 case 1: 1414 mall_size = 0; 1415 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1416 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1417 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1418 for (u = 0; u < adev->gmc.num_umc; u++) { 1419 if (m_s_present & (1 << u)) 1420 mall_size += mall_size_per_umc * 2; 1421 else if (half_use & (1 << u)) 1422 mall_size += mall_size_per_umc / 2; 1423 else 1424 mall_size += mall_size_per_umc; 1425 } 1426 adev->gmc.mall_size = mall_size; 1427 break; 1428 default: 1429 dev_err(adev->dev, 1430 "Unhandled MALL info table %d.%d\n", 1431 le16_to_cpu(mall_info->v1.header.version_major), 1432 le16_to_cpu(mall_info->v1.header.version_minor)); 1433 return -EINVAL; 1434 } 1435 return 0; 1436 } 1437 1438 union vcn_info { 1439 struct vcn_info_v1_0 v1; 1440 }; 1441 1442 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1443 { 1444 struct binary_header *bhdr; 1445 union vcn_info *vcn_info; 1446 u16 offset; 1447 int v; 1448 1449 if (!adev->mman.discovery_bin) { 1450 DRM_ERROR("ip discovery uninitialized\n"); 1451 return -EINVAL; 1452 } 1453 1454 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1455 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1456 * but that may change in the future with new GPUs so keep this 1457 * check for defensive purposes. 1458 */ 1459 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1460 dev_err(adev->dev, "invalid vcn instances\n"); 1461 return -EINVAL; 1462 } 1463 1464 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1465 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1466 1467 if (!offset) 1468 return 0; 1469 1470 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1471 1472 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1473 case 1: 1474 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1475 * so this won't overflow. 1476 */ 1477 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1478 adev->vcn.vcn_codec_disable_mask[v] = 1479 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1480 } 1481 break; 1482 default: 1483 dev_err(adev->dev, 1484 "Unhandled VCN info table %d.%d\n", 1485 le16_to_cpu(vcn_info->v1.header.version_major), 1486 le16_to_cpu(vcn_info->v1.header.version_minor)); 1487 return -EINVAL; 1488 } 1489 return 0; 1490 } 1491 1492 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1493 { 1494 /* what IP to use for this? */ 1495 switch (adev->ip_versions[GC_HWIP][0]) { 1496 case IP_VERSION(9, 0, 1): 1497 case IP_VERSION(9, 1, 0): 1498 case IP_VERSION(9, 2, 1): 1499 case IP_VERSION(9, 2, 2): 1500 case IP_VERSION(9, 3, 0): 1501 case IP_VERSION(9, 4, 0): 1502 case IP_VERSION(9, 4, 1): 1503 case IP_VERSION(9, 4, 2): 1504 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1505 break; 1506 case IP_VERSION(10, 1, 10): 1507 case IP_VERSION(10, 1, 1): 1508 case IP_VERSION(10, 1, 2): 1509 case IP_VERSION(10, 1, 3): 1510 case IP_VERSION(10, 1, 4): 1511 case IP_VERSION(10, 3, 0): 1512 case IP_VERSION(10, 3, 1): 1513 case IP_VERSION(10, 3, 2): 1514 case IP_VERSION(10, 3, 3): 1515 case IP_VERSION(10, 3, 4): 1516 case IP_VERSION(10, 3, 5): 1517 case IP_VERSION(10, 3, 6): 1518 case IP_VERSION(10, 3, 7): 1519 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1520 break; 1521 case IP_VERSION(11, 0, 0): 1522 case IP_VERSION(11, 0, 1): 1523 case IP_VERSION(11, 0, 2): 1524 case IP_VERSION(11, 0, 3): 1525 case IP_VERSION(11, 0, 4): 1526 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1527 break; 1528 default: 1529 dev_err(adev->dev, 1530 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1531 adev->ip_versions[GC_HWIP][0]); 1532 return -EINVAL; 1533 } 1534 return 0; 1535 } 1536 1537 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1538 { 1539 /* use GC or MMHUB IP version */ 1540 switch (adev->ip_versions[GC_HWIP][0]) { 1541 case IP_VERSION(9, 0, 1): 1542 case IP_VERSION(9, 1, 0): 1543 case IP_VERSION(9, 2, 1): 1544 case IP_VERSION(9, 2, 2): 1545 case IP_VERSION(9, 3, 0): 1546 case IP_VERSION(9, 4, 0): 1547 case IP_VERSION(9, 4, 1): 1548 case IP_VERSION(9, 4, 2): 1549 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1550 break; 1551 case IP_VERSION(10, 1, 10): 1552 case IP_VERSION(10, 1, 1): 1553 case IP_VERSION(10, 1, 2): 1554 case IP_VERSION(10, 1, 3): 1555 case IP_VERSION(10, 1, 4): 1556 case IP_VERSION(10, 3, 0): 1557 case IP_VERSION(10, 3, 1): 1558 case IP_VERSION(10, 3, 2): 1559 case IP_VERSION(10, 3, 3): 1560 case IP_VERSION(10, 3, 4): 1561 case IP_VERSION(10, 3, 5): 1562 case IP_VERSION(10, 3, 6): 1563 case IP_VERSION(10, 3, 7): 1564 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1565 break; 1566 case IP_VERSION(11, 0, 0): 1567 case IP_VERSION(11, 0, 1): 1568 case IP_VERSION(11, 0, 2): 1569 case IP_VERSION(11, 0, 3): 1570 case IP_VERSION(11, 0, 4): 1571 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1572 break; 1573 default: 1574 dev_err(adev->dev, 1575 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1576 adev->ip_versions[GC_HWIP][0]); 1577 return -EINVAL; 1578 } 1579 return 0; 1580 } 1581 1582 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1583 { 1584 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1585 case IP_VERSION(4, 0, 0): 1586 case IP_VERSION(4, 0, 1): 1587 case IP_VERSION(4, 1, 0): 1588 case IP_VERSION(4, 1, 1): 1589 case IP_VERSION(4, 3, 0): 1590 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1591 break; 1592 case IP_VERSION(4, 2, 0): 1593 case IP_VERSION(4, 2, 1): 1594 case IP_VERSION(4, 4, 0): 1595 case IP_VERSION(4, 4, 2): 1596 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1597 break; 1598 case IP_VERSION(5, 0, 0): 1599 case IP_VERSION(5, 0, 1): 1600 case IP_VERSION(5, 0, 2): 1601 case IP_VERSION(5, 0, 3): 1602 case IP_VERSION(5, 2, 0): 1603 case IP_VERSION(5, 2, 1): 1604 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1605 break; 1606 case IP_VERSION(6, 0, 0): 1607 case IP_VERSION(6, 0, 1): 1608 case IP_VERSION(6, 0, 2): 1609 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1610 break; 1611 default: 1612 dev_err(adev->dev, 1613 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1614 adev->ip_versions[OSSSYS_HWIP][0]); 1615 return -EINVAL; 1616 } 1617 return 0; 1618 } 1619 1620 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1621 { 1622 switch (adev->ip_versions[MP0_HWIP][0]) { 1623 case IP_VERSION(9, 0, 0): 1624 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1625 break; 1626 case IP_VERSION(10, 0, 0): 1627 case IP_VERSION(10, 0, 1): 1628 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1629 break; 1630 case IP_VERSION(11, 0, 0): 1631 case IP_VERSION(11, 0, 2): 1632 case IP_VERSION(11, 0, 4): 1633 case IP_VERSION(11, 0, 5): 1634 case IP_VERSION(11, 0, 9): 1635 case IP_VERSION(11, 0, 7): 1636 case IP_VERSION(11, 0, 11): 1637 case IP_VERSION(11, 0, 12): 1638 case IP_VERSION(11, 0, 13): 1639 case IP_VERSION(11, 5, 0): 1640 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1641 break; 1642 case IP_VERSION(11, 0, 8): 1643 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1644 break; 1645 case IP_VERSION(11, 0, 3): 1646 case IP_VERSION(12, 0, 1): 1647 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1648 break; 1649 case IP_VERSION(13, 0, 0): 1650 case IP_VERSION(13, 0, 1): 1651 case IP_VERSION(13, 0, 2): 1652 case IP_VERSION(13, 0, 3): 1653 case IP_VERSION(13, 0, 5): 1654 case IP_VERSION(13, 0, 6): 1655 case IP_VERSION(13, 0, 7): 1656 case IP_VERSION(13, 0, 8): 1657 case IP_VERSION(13, 0, 10): 1658 case IP_VERSION(13, 0, 11): 1659 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1660 break; 1661 case IP_VERSION(13, 0, 4): 1662 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1663 break; 1664 default: 1665 dev_err(adev->dev, 1666 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1667 adev->ip_versions[MP0_HWIP][0]); 1668 return -EINVAL; 1669 } 1670 return 0; 1671 } 1672 1673 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1674 { 1675 switch (adev->ip_versions[MP1_HWIP][0]) { 1676 case IP_VERSION(9, 0, 0): 1677 case IP_VERSION(10, 0, 0): 1678 case IP_VERSION(10, 0, 1): 1679 case IP_VERSION(11, 0, 2): 1680 if (adev->asic_type == CHIP_ARCTURUS) 1681 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1682 else 1683 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1684 break; 1685 case IP_VERSION(11, 0, 0): 1686 case IP_VERSION(11, 0, 5): 1687 case IP_VERSION(11, 0, 9): 1688 case IP_VERSION(11, 0, 7): 1689 case IP_VERSION(11, 0, 8): 1690 case IP_VERSION(11, 0, 11): 1691 case IP_VERSION(11, 0, 12): 1692 case IP_VERSION(11, 0, 13): 1693 case IP_VERSION(11, 5, 0): 1694 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1695 break; 1696 case IP_VERSION(12, 0, 0): 1697 case IP_VERSION(12, 0, 1): 1698 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1699 break; 1700 case IP_VERSION(13, 0, 0): 1701 case IP_VERSION(13, 0, 1): 1702 case IP_VERSION(13, 0, 2): 1703 case IP_VERSION(13, 0, 3): 1704 case IP_VERSION(13, 0, 4): 1705 case IP_VERSION(13, 0, 5): 1706 case IP_VERSION(13, 0, 7): 1707 case IP_VERSION(13, 0, 8): 1708 case IP_VERSION(13, 0, 10): 1709 case IP_VERSION(13, 0, 11): 1710 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1711 break; 1712 default: 1713 dev_err(adev->dev, 1714 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1715 adev->ip_versions[MP1_HWIP][0]); 1716 return -EINVAL; 1717 } 1718 return 0; 1719 } 1720 1721 #if defined(CONFIG_DRM_AMD_DC) 1722 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1723 { 1724 amdgpu_device_set_sriov_virtual_display(adev); 1725 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1726 } 1727 #endif 1728 1729 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1730 { 1731 if (adev->enable_virtual_display) { 1732 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1733 return 0; 1734 } 1735 1736 if (!amdgpu_device_has_dc_support(adev)) 1737 return 0; 1738 1739 #if defined(CONFIG_DRM_AMD_DC) 1740 if (adev->ip_versions[DCE_HWIP][0]) { 1741 switch (adev->ip_versions[DCE_HWIP][0]) { 1742 case IP_VERSION(1, 0, 0): 1743 case IP_VERSION(1, 0, 1): 1744 case IP_VERSION(2, 0, 2): 1745 case IP_VERSION(2, 0, 0): 1746 case IP_VERSION(2, 0, 3): 1747 case IP_VERSION(2, 1, 0): 1748 case IP_VERSION(3, 0, 0): 1749 case IP_VERSION(3, 0, 2): 1750 case IP_VERSION(3, 0, 3): 1751 case IP_VERSION(3, 0, 1): 1752 case IP_VERSION(3, 1, 2): 1753 case IP_VERSION(3, 1, 3): 1754 case IP_VERSION(3, 1, 4): 1755 case IP_VERSION(3, 1, 5): 1756 case IP_VERSION(3, 1, 6): 1757 case IP_VERSION(3, 2, 0): 1758 case IP_VERSION(3, 2, 1): 1759 if (amdgpu_sriov_vf(adev)) 1760 amdgpu_discovery_set_sriov_display(adev); 1761 else 1762 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1763 break; 1764 default: 1765 dev_err(adev->dev, 1766 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1767 adev->ip_versions[DCE_HWIP][0]); 1768 return -EINVAL; 1769 } 1770 } else if (adev->ip_versions[DCI_HWIP][0]) { 1771 switch (adev->ip_versions[DCI_HWIP][0]) { 1772 case IP_VERSION(12, 0, 0): 1773 case IP_VERSION(12, 0, 1): 1774 case IP_VERSION(12, 1, 0): 1775 if (amdgpu_sriov_vf(adev)) 1776 amdgpu_discovery_set_sriov_display(adev); 1777 else 1778 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1779 break; 1780 default: 1781 dev_err(adev->dev, 1782 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1783 adev->ip_versions[DCI_HWIP][0]); 1784 return -EINVAL; 1785 } 1786 } 1787 #endif 1788 return 0; 1789 } 1790 1791 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1792 { 1793 switch (adev->ip_versions[GC_HWIP][0]) { 1794 case IP_VERSION(9, 0, 1): 1795 case IP_VERSION(9, 1, 0): 1796 case IP_VERSION(9, 2, 1): 1797 case IP_VERSION(9, 2, 2): 1798 case IP_VERSION(9, 3, 0): 1799 case IP_VERSION(9, 4, 0): 1800 case IP_VERSION(9, 4, 1): 1801 case IP_VERSION(9, 4, 2): 1802 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1803 break; 1804 case IP_VERSION(10, 1, 10): 1805 case IP_VERSION(10, 1, 2): 1806 case IP_VERSION(10, 1, 1): 1807 case IP_VERSION(10, 1, 3): 1808 case IP_VERSION(10, 1, 4): 1809 case IP_VERSION(10, 3, 0): 1810 case IP_VERSION(10, 3, 2): 1811 case IP_VERSION(10, 3, 1): 1812 case IP_VERSION(10, 3, 4): 1813 case IP_VERSION(10, 3, 5): 1814 case IP_VERSION(10, 3, 6): 1815 case IP_VERSION(10, 3, 3): 1816 case IP_VERSION(10, 3, 7): 1817 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1818 break; 1819 case IP_VERSION(11, 0, 0): 1820 case IP_VERSION(11, 0, 1): 1821 case IP_VERSION(11, 0, 2): 1822 case IP_VERSION(11, 0, 3): 1823 case IP_VERSION(11, 0, 4): 1824 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1825 break; 1826 default: 1827 dev_err(adev->dev, 1828 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1829 adev->ip_versions[GC_HWIP][0]); 1830 return -EINVAL; 1831 } 1832 return 0; 1833 } 1834 1835 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1836 { 1837 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1838 case IP_VERSION(4, 0, 0): 1839 case IP_VERSION(4, 0, 1): 1840 case IP_VERSION(4, 1, 0): 1841 case IP_VERSION(4, 1, 1): 1842 case IP_VERSION(4, 1, 2): 1843 case IP_VERSION(4, 2, 0): 1844 case IP_VERSION(4, 2, 2): 1845 case IP_VERSION(4, 4, 0): 1846 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1847 break; 1848 case IP_VERSION(4, 4, 2): 1849 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 1850 break; 1851 case IP_VERSION(5, 0, 0): 1852 case IP_VERSION(5, 0, 1): 1853 case IP_VERSION(5, 0, 2): 1854 case IP_VERSION(5, 0, 5): 1855 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1856 break; 1857 case IP_VERSION(5, 2, 0): 1858 case IP_VERSION(5, 2, 2): 1859 case IP_VERSION(5, 2, 4): 1860 case IP_VERSION(5, 2, 5): 1861 case IP_VERSION(5, 2, 6): 1862 case IP_VERSION(5, 2, 3): 1863 case IP_VERSION(5, 2, 1): 1864 case IP_VERSION(5, 2, 7): 1865 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1866 break; 1867 case IP_VERSION(6, 0, 0): 1868 case IP_VERSION(6, 0, 1): 1869 case IP_VERSION(6, 0, 2): 1870 case IP_VERSION(6, 0, 3): 1871 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1872 break; 1873 default: 1874 dev_err(adev->dev, 1875 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1876 adev->ip_versions[SDMA0_HWIP][0]); 1877 return -EINVAL; 1878 } 1879 return 0; 1880 } 1881 1882 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1883 { 1884 if (adev->ip_versions[VCE_HWIP][0]) { 1885 switch (adev->ip_versions[UVD_HWIP][0]) { 1886 case IP_VERSION(7, 0, 0): 1887 case IP_VERSION(7, 2, 0): 1888 /* UVD is not supported on vega20 SR-IOV */ 1889 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1890 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1891 break; 1892 default: 1893 dev_err(adev->dev, 1894 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1895 adev->ip_versions[UVD_HWIP][0]); 1896 return -EINVAL; 1897 } 1898 switch (adev->ip_versions[VCE_HWIP][0]) { 1899 case IP_VERSION(4, 0, 0): 1900 case IP_VERSION(4, 1, 0): 1901 /* VCE is not supported on vega20 SR-IOV */ 1902 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1903 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1904 break; 1905 default: 1906 dev_err(adev->dev, 1907 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1908 adev->ip_versions[VCE_HWIP][0]); 1909 return -EINVAL; 1910 } 1911 } else { 1912 switch (adev->ip_versions[UVD_HWIP][0]) { 1913 case IP_VERSION(1, 0, 0): 1914 case IP_VERSION(1, 0, 1): 1915 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1916 break; 1917 case IP_VERSION(2, 0, 0): 1918 case IP_VERSION(2, 0, 2): 1919 case IP_VERSION(2, 2, 0): 1920 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1921 if (!amdgpu_sriov_vf(adev)) 1922 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1923 break; 1924 case IP_VERSION(2, 0, 3): 1925 break; 1926 case IP_VERSION(2, 5, 0): 1927 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1928 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1929 break; 1930 case IP_VERSION(2, 6, 0): 1931 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1932 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1933 break; 1934 case IP_VERSION(3, 0, 0): 1935 case IP_VERSION(3, 0, 16): 1936 case IP_VERSION(3, 1, 1): 1937 case IP_VERSION(3, 1, 2): 1938 case IP_VERSION(3, 0, 2): 1939 case IP_VERSION(3, 0, 192): 1940 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1941 if (!amdgpu_sriov_vf(adev)) 1942 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1943 break; 1944 case IP_VERSION(3, 0, 33): 1945 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1946 break; 1947 case IP_VERSION(4, 0, 0): 1948 case IP_VERSION(4, 0, 2): 1949 case IP_VERSION(4, 0, 4): 1950 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 1951 if (!amdgpu_sriov_vf(adev)) 1952 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 1953 break; 1954 default: 1955 dev_err(adev->dev, 1956 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1957 adev->ip_versions[UVD_HWIP][0]); 1958 return -EINVAL; 1959 } 1960 } 1961 return 0; 1962 } 1963 1964 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1965 { 1966 switch (adev->ip_versions[GC_HWIP][0]) { 1967 case IP_VERSION(10, 1, 10): 1968 case IP_VERSION(10, 1, 1): 1969 case IP_VERSION(10, 1, 2): 1970 case IP_VERSION(10, 1, 3): 1971 case IP_VERSION(10, 1, 4): 1972 case IP_VERSION(10, 3, 0): 1973 case IP_VERSION(10, 3, 1): 1974 case IP_VERSION(10, 3, 2): 1975 case IP_VERSION(10, 3, 3): 1976 case IP_VERSION(10, 3, 4): 1977 case IP_VERSION(10, 3, 5): 1978 case IP_VERSION(10, 3, 6): 1979 if (amdgpu_mes) { 1980 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1981 adev->enable_mes = true; 1982 if (amdgpu_mes_kiq) 1983 adev->enable_mes_kiq = true; 1984 } 1985 break; 1986 case IP_VERSION(11, 0, 0): 1987 case IP_VERSION(11, 0, 1): 1988 case IP_VERSION(11, 0, 2): 1989 case IP_VERSION(11, 0, 3): 1990 case IP_VERSION(11, 0, 4): 1991 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 1992 adev->enable_mes = true; 1993 adev->enable_mes_kiq = true; 1994 break; 1995 default: 1996 break; 1997 } 1998 return 0; 1999 } 2000 2001 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2002 { 2003 int r; 2004 2005 switch (adev->asic_type) { 2006 case CHIP_VEGA10: 2007 vega10_reg_base_init(adev); 2008 adev->sdma.num_instances = 2; 2009 adev->gmc.num_umc = 4; 2010 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2011 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2012 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2013 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2014 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2015 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2016 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2017 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2018 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2019 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2020 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2021 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2022 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2023 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2024 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2025 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2026 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2027 break; 2028 case CHIP_VEGA12: 2029 vega10_reg_base_init(adev); 2030 adev->sdma.num_instances = 2; 2031 adev->gmc.num_umc = 4; 2032 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2033 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2034 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2035 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2036 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2037 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2038 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2039 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2040 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2041 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2042 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2043 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2044 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2045 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2046 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2047 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2048 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2049 break; 2050 case CHIP_RAVEN: 2051 vega10_reg_base_init(adev); 2052 adev->sdma.num_instances = 1; 2053 adev->vcn.num_vcn_inst = 1; 2054 adev->gmc.num_umc = 2; 2055 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2056 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2057 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2058 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2059 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2060 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2061 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2062 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2063 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2064 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2065 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2066 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2067 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2068 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2069 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2070 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2071 } else { 2072 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2073 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2074 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2075 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2076 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2077 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2078 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2079 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2080 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2081 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2082 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2083 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2084 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2085 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2086 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2087 } 2088 break; 2089 case CHIP_VEGA20: 2090 vega20_reg_base_init(adev); 2091 adev->sdma.num_instances = 2; 2092 adev->gmc.num_umc = 8; 2093 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2094 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2095 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2096 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2097 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2098 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2099 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2100 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2101 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2102 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2103 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2104 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2105 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2106 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2107 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2108 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2109 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2110 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2111 break; 2112 case CHIP_ARCTURUS: 2113 arct_reg_base_init(adev); 2114 adev->sdma.num_instances = 8; 2115 adev->vcn.num_vcn_inst = 2; 2116 adev->gmc.num_umc = 8; 2117 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2118 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2119 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2120 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2121 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2122 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2123 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2124 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2125 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2126 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2127 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2128 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2129 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2130 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2131 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2132 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2133 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2134 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2135 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2136 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2137 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2138 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2139 break; 2140 case CHIP_ALDEBARAN: 2141 aldebaran_reg_base_init(adev); 2142 adev->sdma.num_instances = 5; 2143 adev->vcn.num_vcn_inst = 2; 2144 adev->gmc.num_umc = 4; 2145 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2146 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2147 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2148 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2149 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2150 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2151 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2152 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2153 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2154 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2155 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2156 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2157 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2158 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2159 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2160 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2161 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2162 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2163 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2164 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2165 break; 2166 default: 2167 r = amdgpu_discovery_reg_base_init(adev); 2168 if (r) 2169 return -EINVAL; 2170 2171 amdgpu_discovery_harvest_ip(adev); 2172 amdgpu_discovery_get_gfx_info(adev); 2173 amdgpu_discovery_get_mall_info(adev); 2174 amdgpu_discovery_get_vcn_info(adev); 2175 break; 2176 } 2177 2178 switch (adev->ip_versions[GC_HWIP][0]) { 2179 case IP_VERSION(9, 0, 1): 2180 case IP_VERSION(9, 2, 1): 2181 case IP_VERSION(9, 4, 0): 2182 case IP_VERSION(9, 4, 1): 2183 case IP_VERSION(9, 4, 2): 2184 adev->family = AMDGPU_FAMILY_AI; 2185 break; 2186 case IP_VERSION(9, 1, 0): 2187 case IP_VERSION(9, 2, 2): 2188 case IP_VERSION(9, 3, 0): 2189 adev->family = AMDGPU_FAMILY_RV; 2190 break; 2191 case IP_VERSION(10, 1, 10): 2192 case IP_VERSION(10, 1, 1): 2193 case IP_VERSION(10, 1, 2): 2194 case IP_VERSION(10, 1, 3): 2195 case IP_VERSION(10, 1, 4): 2196 case IP_VERSION(10, 3, 0): 2197 case IP_VERSION(10, 3, 2): 2198 case IP_VERSION(10, 3, 4): 2199 case IP_VERSION(10, 3, 5): 2200 adev->family = AMDGPU_FAMILY_NV; 2201 break; 2202 case IP_VERSION(10, 3, 1): 2203 adev->family = AMDGPU_FAMILY_VGH; 2204 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2205 break; 2206 case IP_VERSION(10, 3, 3): 2207 adev->family = AMDGPU_FAMILY_YC; 2208 break; 2209 case IP_VERSION(10, 3, 6): 2210 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2211 break; 2212 case IP_VERSION(10, 3, 7): 2213 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2214 break; 2215 case IP_VERSION(11, 0, 0): 2216 case IP_VERSION(11, 0, 2): 2217 case IP_VERSION(11, 0, 3): 2218 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2219 break; 2220 case IP_VERSION(11, 0, 1): 2221 case IP_VERSION(11, 0, 4): 2222 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2223 break; 2224 default: 2225 return -EINVAL; 2226 } 2227 2228 switch (adev->ip_versions[GC_HWIP][0]) { 2229 case IP_VERSION(9, 1, 0): 2230 case IP_VERSION(9, 2, 2): 2231 case IP_VERSION(9, 3, 0): 2232 case IP_VERSION(10, 1, 3): 2233 case IP_VERSION(10, 1, 4): 2234 case IP_VERSION(10, 3, 1): 2235 case IP_VERSION(10, 3, 3): 2236 case IP_VERSION(10, 3, 6): 2237 case IP_VERSION(10, 3, 7): 2238 case IP_VERSION(11, 0, 1): 2239 case IP_VERSION(11, 0, 4): 2240 adev->flags |= AMD_IS_APU; 2241 break; 2242 default: 2243 break; 2244 } 2245 2246 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2247 adev->gmc.xgmi.supported = true; 2248 2249 /* set NBIO version */ 2250 switch (adev->ip_versions[NBIO_HWIP][0]) { 2251 case IP_VERSION(6, 1, 0): 2252 case IP_VERSION(6, 2, 0): 2253 adev->nbio.funcs = &nbio_v6_1_funcs; 2254 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2255 break; 2256 case IP_VERSION(7, 0, 0): 2257 case IP_VERSION(7, 0, 1): 2258 case IP_VERSION(2, 5, 0): 2259 adev->nbio.funcs = &nbio_v7_0_funcs; 2260 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2261 break; 2262 case IP_VERSION(7, 4, 0): 2263 case IP_VERSION(7, 4, 1): 2264 case IP_VERSION(7, 4, 4): 2265 adev->nbio.funcs = &nbio_v7_4_funcs; 2266 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2267 break; 2268 case IP_VERSION(7, 2, 0): 2269 case IP_VERSION(7, 2, 1): 2270 case IP_VERSION(7, 3, 0): 2271 case IP_VERSION(7, 5, 0): 2272 case IP_VERSION(7, 5, 1): 2273 adev->nbio.funcs = &nbio_v7_2_funcs; 2274 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2275 break; 2276 case IP_VERSION(2, 1, 1): 2277 case IP_VERSION(2, 3, 0): 2278 case IP_VERSION(2, 3, 1): 2279 case IP_VERSION(2, 3, 2): 2280 case IP_VERSION(3, 3, 0): 2281 case IP_VERSION(3, 3, 1): 2282 case IP_VERSION(3, 3, 2): 2283 case IP_VERSION(3, 3, 3): 2284 adev->nbio.funcs = &nbio_v2_3_funcs; 2285 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2286 break; 2287 case IP_VERSION(4, 3, 0): 2288 case IP_VERSION(4, 3, 1): 2289 if (amdgpu_sriov_vf(adev)) 2290 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2291 else 2292 adev->nbio.funcs = &nbio_v4_3_funcs; 2293 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2294 break; 2295 case IP_VERSION(7, 7, 0): 2296 case IP_VERSION(7, 7, 1): 2297 adev->nbio.funcs = &nbio_v7_7_funcs; 2298 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2299 break; 2300 default: 2301 break; 2302 } 2303 2304 switch (adev->ip_versions[HDP_HWIP][0]) { 2305 case IP_VERSION(4, 0, 0): 2306 case IP_VERSION(4, 0, 1): 2307 case IP_VERSION(4, 1, 0): 2308 case IP_VERSION(4, 1, 1): 2309 case IP_VERSION(4, 1, 2): 2310 case IP_VERSION(4, 2, 0): 2311 case IP_VERSION(4, 2, 1): 2312 case IP_VERSION(4, 4, 0): 2313 case IP_VERSION(4, 4, 2): 2314 adev->hdp.funcs = &hdp_v4_0_funcs; 2315 break; 2316 case IP_VERSION(5, 0, 0): 2317 case IP_VERSION(5, 0, 1): 2318 case IP_VERSION(5, 0, 2): 2319 case IP_VERSION(5, 0, 3): 2320 case IP_VERSION(5, 0, 4): 2321 case IP_VERSION(5, 2, 0): 2322 adev->hdp.funcs = &hdp_v5_0_funcs; 2323 break; 2324 case IP_VERSION(5, 2, 1): 2325 adev->hdp.funcs = &hdp_v5_2_funcs; 2326 break; 2327 case IP_VERSION(6, 0, 0): 2328 case IP_VERSION(6, 0, 1): 2329 adev->hdp.funcs = &hdp_v6_0_funcs; 2330 break; 2331 default: 2332 break; 2333 } 2334 2335 switch (adev->ip_versions[DF_HWIP][0]) { 2336 case IP_VERSION(3, 6, 0): 2337 case IP_VERSION(3, 6, 1): 2338 case IP_VERSION(3, 6, 2): 2339 adev->df.funcs = &df_v3_6_funcs; 2340 break; 2341 case IP_VERSION(2, 1, 0): 2342 case IP_VERSION(2, 1, 1): 2343 case IP_VERSION(2, 5, 0): 2344 case IP_VERSION(3, 5, 1): 2345 case IP_VERSION(3, 5, 2): 2346 adev->df.funcs = &df_v1_7_funcs; 2347 break; 2348 case IP_VERSION(4, 3, 0): 2349 adev->df.funcs = &df_v4_3_funcs; 2350 break; 2351 default: 2352 break; 2353 } 2354 2355 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2356 case IP_VERSION(9, 0, 0): 2357 case IP_VERSION(9, 0, 1): 2358 case IP_VERSION(10, 0, 0): 2359 case IP_VERSION(10, 0, 1): 2360 case IP_VERSION(10, 0, 2): 2361 adev->smuio.funcs = &smuio_v9_0_funcs; 2362 break; 2363 case IP_VERSION(11, 0, 0): 2364 case IP_VERSION(11, 0, 2): 2365 case IP_VERSION(11, 0, 3): 2366 case IP_VERSION(11, 0, 4): 2367 case IP_VERSION(11, 0, 7): 2368 case IP_VERSION(11, 0, 8): 2369 adev->smuio.funcs = &smuio_v11_0_funcs; 2370 break; 2371 case IP_VERSION(11, 0, 6): 2372 case IP_VERSION(11, 0, 10): 2373 case IP_VERSION(11, 0, 11): 2374 case IP_VERSION(11, 5, 0): 2375 case IP_VERSION(13, 0, 1): 2376 case IP_VERSION(13, 0, 9): 2377 case IP_VERSION(13, 0, 10): 2378 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2379 break; 2380 case IP_VERSION(13, 0, 2): 2381 adev->smuio.funcs = &smuio_v13_0_funcs; 2382 break; 2383 case IP_VERSION(13, 0, 6): 2384 case IP_VERSION(13, 0, 8): 2385 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2386 break; 2387 default: 2388 break; 2389 } 2390 2391 switch (adev->ip_versions[LSDMA_HWIP][0]) { 2392 case IP_VERSION(6, 0, 0): 2393 case IP_VERSION(6, 0, 1): 2394 case IP_VERSION(6, 0, 2): 2395 case IP_VERSION(6, 0, 3): 2396 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2397 break; 2398 default: 2399 break; 2400 } 2401 2402 r = amdgpu_discovery_set_common_ip_blocks(adev); 2403 if (r) 2404 return r; 2405 2406 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2407 if (r) 2408 return r; 2409 2410 /* For SR-IOV, PSP needs to be initialized before IH */ 2411 if (amdgpu_sriov_vf(adev)) { 2412 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2413 if (r) 2414 return r; 2415 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2416 if (r) 2417 return r; 2418 } else { 2419 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2420 if (r) 2421 return r; 2422 2423 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2424 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2425 if (r) 2426 return r; 2427 } 2428 } 2429 2430 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2431 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2432 if (r) 2433 return r; 2434 } 2435 2436 r = amdgpu_discovery_set_display_ip_blocks(adev); 2437 if (r) 2438 return r; 2439 2440 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2441 if (r) 2442 return r; 2443 2444 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2445 if (r) 2446 return r; 2447 2448 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2449 !amdgpu_sriov_vf(adev)) || 2450 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2451 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2452 if (r) 2453 return r; 2454 } 2455 2456 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2457 if (r) 2458 return r; 2459 2460 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2461 if (r) 2462 return r; 2463 2464 return 0; 2465 } 2466 2467