1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "df_v4_3.h" 37 #include "nbio_v6_1.h" 38 #include "nbio_v7_0.h" 39 #include "nbio_v7_4.h" 40 #include "nbio_v7_9.h" 41 #include "hdp_v4_0.h" 42 #include "vega10_ih.h" 43 #include "vega20_ih.h" 44 #include "sdma_v4_0.h" 45 #include "sdma_v4_4_2.h" 46 #include "uvd_v7_0.h" 47 #include "vce_v4_0.h" 48 #include "vcn_v1_0.h" 49 #include "vcn_v2_5.h" 50 #include "jpeg_v2_5.h" 51 #include "smuio_v9_0.h" 52 #include "gmc_v10_0.h" 53 #include "gmc_v11_0.h" 54 #include "gfxhub_v2_0.h" 55 #include "mmhub_v2_0.h" 56 #include "nbio_v2_3.h" 57 #include "nbio_v4_3.h" 58 #include "nbio_v7_2.h" 59 #include "nbio_v7_7.h" 60 #include "hdp_v5_0.h" 61 #include "hdp_v5_2.h" 62 #include "hdp_v6_0.h" 63 #include "nv.h" 64 #include "soc21.h" 65 #include "navi10_ih.h" 66 #include "ih_v6_0.h" 67 #include "gfx_v10_0.h" 68 #include "gfx_v11_0.h" 69 #include "sdma_v5_0.h" 70 #include "sdma_v5_2.h" 71 #include "sdma_v6_0.h" 72 #include "lsdma_v6_0.h" 73 #include "vcn_v2_0.h" 74 #include "jpeg_v2_0.h" 75 #include "vcn_v3_0.h" 76 #include "jpeg_v3_0.h" 77 #include "vcn_v4_0.h" 78 #include "jpeg_v4_0.h" 79 #include "amdgpu_vkms.h" 80 #include "mes_v10_1.h" 81 #include "mes_v11_0.h" 82 #include "smuio_v11_0.h" 83 #include "smuio_v11_0_6.h" 84 #include "smuio_v13_0.h" 85 #include "smuio_v13_0_6.h" 86 87 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 88 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 89 90 #define mmRCC_CONFIG_MEMSIZE 0xde3 91 #define mmMM_INDEX 0x0 92 #define mmMM_INDEX_HI 0x6 93 #define mmMM_DATA 0x1 94 95 static const char *hw_id_names[HW_ID_MAX] = { 96 [MP1_HWID] = "MP1", 97 [MP2_HWID] = "MP2", 98 [THM_HWID] = "THM", 99 [SMUIO_HWID] = "SMUIO", 100 [FUSE_HWID] = "FUSE", 101 [CLKA_HWID] = "CLKA", 102 [PWR_HWID] = "PWR", 103 [GC_HWID] = "GC", 104 [UVD_HWID] = "UVD", 105 [AUDIO_AZ_HWID] = "AUDIO_AZ", 106 [ACP_HWID] = "ACP", 107 [DCI_HWID] = "DCI", 108 [DMU_HWID] = "DMU", 109 [DCO_HWID] = "DCO", 110 [DIO_HWID] = "DIO", 111 [XDMA_HWID] = "XDMA", 112 [DCEAZ_HWID] = "DCEAZ", 113 [DAZ_HWID] = "DAZ", 114 [SDPMUX_HWID] = "SDPMUX", 115 [NTB_HWID] = "NTB", 116 [IOHC_HWID] = "IOHC", 117 [L2IMU_HWID] = "L2IMU", 118 [VCE_HWID] = "VCE", 119 [MMHUB_HWID] = "MMHUB", 120 [ATHUB_HWID] = "ATHUB", 121 [DBGU_NBIO_HWID] = "DBGU_NBIO", 122 [DFX_HWID] = "DFX", 123 [DBGU0_HWID] = "DBGU0", 124 [DBGU1_HWID] = "DBGU1", 125 [OSSSYS_HWID] = "OSSSYS", 126 [HDP_HWID] = "HDP", 127 [SDMA0_HWID] = "SDMA0", 128 [SDMA1_HWID] = "SDMA1", 129 [SDMA2_HWID] = "SDMA2", 130 [SDMA3_HWID] = "SDMA3", 131 [LSDMA_HWID] = "LSDMA", 132 [ISP_HWID] = "ISP", 133 [DBGU_IO_HWID] = "DBGU_IO", 134 [DF_HWID] = "DF", 135 [CLKB_HWID] = "CLKB", 136 [FCH_HWID] = "FCH", 137 [DFX_DAP_HWID] = "DFX_DAP", 138 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 139 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 140 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 141 [L1IMU3_HWID] = "L1IMU3", 142 [L1IMU4_HWID] = "L1IMU4", 143 [L1IMU5_HWID] = "L1IMU5", 144 [L1IMU6_HWID] = "L1IMU6", 145 [L1IMU7_HWID] = "L1IMU7", 146 [L1IMU8_HWID] = "L1IMU8", 147 [L1IMU9_HWID] = "L1IMU9", 148 [L1IMU10_HWID] = "L1IMU10", 149 [L1IMU11_HWID] = "L1IMU11", 150 [L1IMU12_HWID] = "L1IMU12", 151 [L1IMU13_HWID] = "L1IMU13", 152 [L1IMU14_HWID] = "L1IMU14", 153 [L1IMU15_HWID] = "L1IMU15", 154 [WAFLC_HWID] = "WAFLC", 155 [FCH_USB_PD_HWID] = "FCH_USB_PD", 156 [PCIE_HWID] = "PCIE", 157 [PCS_HWID] = "PCS", 158 [DDCL_HWID] = "DDCL", 159 [SST_HWID] = "SST", 160 [IOAGR_HWID] = "IOAGR", 161 [NBIF_HWID] = "NBIF", 162 [IOAPIC_HWID] = "IOAPIC", 163 [SYSTEMHUB_HWID] = "SYSTEMHUB", 164 [NTBCCP_HWID] = "NTBCCP", 165 [UMC_HWID] = "UMC", 166 [SATA_HWID] = "SATA", 167 [USB_HWID] = "USB", 168 [CCXSEC_HWID] = "CCXSEC", 169 [XGMI_HWID] = "XGMI", 170 [XGBE_HWID] = "XGBE", 171 [MP0_HWID] = "MP0", 172 }; 173 174 static int hw_id_map[MAX_HWIP] = { 175 [GC_HWIP] = GC_HWID, 176 [HDP_HWIP] = HDP_HWID, 177 [SDMA0_HWIP] = SDMA0_HWID, 178 [SDMA1_HWIP] = SDMA1_HWID, 179 [SDMA2_HWIP] = SDMA2_HWID, 180 [SDMA3_HWIP] = SDMA3_HWID, 181 [LSDMA_HWIP] = LSDMA_HWID, 182 [MMHUB_HWIP] = MMHUB_HWID, 183 [ATHUB_HWIP] = ATHUB_HWID, 184 [NBIO_HWIP] = NBIF_HWID, 185 [MP0_HWIP] = MP0_HWID, 186 [MP1_HWIP] = MP1_HWID, 187 [UVD_HWIP] = UVD_HWID, 188 [VCE_HWIP] = VCE_HWID, 189 [DF_HWIP] = DF_HWID, 190 [DCE_HWIP] = DMU_HWID, 191 [OSSSYS_HWIP] = OSSSYS_HWID, 192 [SMUIO_HWIP] = SMUIO_HWID, 193 [PWR_HWIP] = PWR_HWID, 194 [NBIF_HWIP] = NBIF_HWID, 195 [THM_HWIP] = THM_HWID, 196 [CLK_HWIP] = CLKA_HWID, 197 [UMC_HWIP] = UMC_HWID, 198 [XGMI_HWIP] = XGMI_HWID, 199 [DCI_HWIP] = DCI_HWID, 200 [PCIE_HWIP] = PCIE_HWID, 201 }; 202 203 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 204 { 205 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 206 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 207 208 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 209 adev->mman.discovery_tmr_size, false); 210 return 0; 211 } 212 213 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 214 { 215 const struct firmware *fw; 216 const char *fw_name; 217 int r; 218 219 switch (amdgpu_discovery) { 220 case 2: 221 fw_name = FIRMWARE_IP_DISCOVERY; 222 break; 223 default: 224 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 225 return -EINVAL; 226 } 227 228 r = request_firmware(&fw, fw_name, adev->dev); 229 if (r) { 230 dev_err(adev->dev, "can't load firmware \"%s\"\n", 231 fw_name); 232 return r; 233 } 234 235 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 236 release_firmware(fw); 237 238 return 0; 239 } 240 241 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 242 { 243 uint16_t checksum = 0; 244 int i; 245 246 for (i = 0; i < size; i++) 247 checksum += data[i]; 248 249 return checksum; 250 } 251 252 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 253 uint16_t expected) 254 { 255 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 256 } 257 258 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 259 { 260 struct binary_header *bhdr; 261 bhdr = (struct binary_header *)binary; 262 263 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 264 } 265 266 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 267 { 268 /* 269 * So far, apply this quirk only on those Navy Flounder boards which 270 * have a bad harvest table of VCN config. 271 */ 272 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 273 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 274 switch (adev->pdev->revision) { 275 case 0xC1: 276 case 0xC2: 277 case 0xC3: 278 case 0xC5: 279 case 0xC7: 280 case 0xCF: 281 case 0xDF: 282 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 283 break; 284 default: 285 break; 286 } 287 } 288 } 289 290 static int amdgpu_discovery_init(struct amdgpu_device *adev) 291 { 292 struct table_info *info; 293 struct binary_header *bhdr; 294 uint16_t offset; 295 uint16_t size; 296 uint16_t checksum; 297 int r; 298 299 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 300 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 301 if (!adev->mman.discovery_bin) 302 return -ENOMEM; 303 304 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 305 if (r) { 306 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 307 r = -EINVAL; 308 goto out; 309 } 310 311 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin) || amdgpu_discovery == 2) { 312 /* ignore the discovery binary from vram if discovery=2 in kernel module parameter */ 313 if (amdgpu_discovery == 2) 314 dev_info(adev->dev, "force read ip discovery binary from file"); 315 else 316 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 317 318 /* retry read ip discovery binary from file */ 319 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 320 if (r) { 321 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 322 r = -EINVAL; 323 goto out; 324 } 325 /* check the ip discovery binary signature */ 326 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 327 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 328 r = -EINVAL; 329 goto out; 330 } 331 } 332 333 bhdr = (struct binary_header *)adev->mman.discovery_bin; 334 335 offset = offsetof(struct binary_header, binary_checksum) + 336 sizeof(bhdr->binary_checksum); 337 size = le16_to_cpu(bhdr->binary_size) - offset; 338 checksum = le16_to_cpu(bhdr->binary_checksum); 339 340 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 341 size, checksum)) { 342 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 343 r = -EINVAL; 344 goto out; 345 } 346 347 info = &bhdr->table_list[IP_DISCOVERY]; 348 offset = le16_to_cpu(info->offset); 349 checksum = le16_to_cpu(info->checksum); 350 351 if (offset) { 352 struct ip_discovery_header *ihdr = 353 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 354 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 355 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 356 r = -EINVAL; 357 goto out; 358 } 359 360 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 361 le16_to_cpu(ihdr->size), checksum)) { 362 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 363 r = -EINVAL; 364 goto out; 365 } 366 } 367 368 info = &bhdr->table_list[GC]; 369 offset = le16_to_cpu(info->offset); 370 checksum = le16_to_cpu(info->checksum); 371 372 if (offset) { 373 struct gpu_info_header *ghdr = 374 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 375 376 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 377 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 378 r = -EINVAL; 379 goto out; 380 } 381 382 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 383 le32_to_cpu(ghdr->size), checksum)) { 384 dev_err(adev->dev, "invalid gc data table checksum\n"); 385 r = -EINVAL; 386 goto out; 387 } 388 } 389 390 info = &bhdr->table_list[HARVEST_INFO]; 391 offset = le16_to_cpu(info->offset); 392 checksum = le16_to_cpu(info->checksum); 393 394 if (offset) { 395 struct harvest_info_header *hhdr = 396 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 397 398 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 399 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 400 r = -EINVAL; 401 goto out; 402 } 403 404 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 405 sizeof(struct harvest_table), checksum)) { 406 dev_err(adev->dev, "invalid harvest data table checksum\n"); 407 r = -EINVAL; 408 goto out; 409 } 410 } 411 412 info = &bhdr->table_list[VCN_INFO]; 413 offset = le16_to_cpu(info->offset); 414 checksum = le16_to_cpu(info->checksum); 415 416 if (offset) { 417 struct vcn_info_header *vhdr = 418 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 419 420 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 421 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 422 r = -EINVAL; 423 goto out; 424 } 425 426 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 427 le32_to_cpu(vhdr->size_bytes), checksum)) { 428 dev_err(adev->dev, "invalid vcn data table checksum\n"); 429 r = -EINVAL; 430 goto out; 431 } 432 } 433 434 info = &bhdr->table_list[MALL_INFO]; 435 offset = le16_to_cpu(info->offset); 436 checksum = le16_to_cpu(info->checksum); 437 438 if (0 && offset) { 439 struct mall_info_header *mhdr = 440 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 441 442 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 443 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 444 r = -EINVAL; 445 goto out; 446 } 447 448 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 449 le32_to_cpu(mhdr->size_bytes), checksum)) { 450 dev_err(adev->dev, "invalid mall data table checksum\n"); 451 r = -EINVAL; 452 goto out; 453 } 454 } 455 456 return 0; 457 458 out: 459 kfree(adev->mman.discovery_bin); 460 adev->mman.discovery_bin = NULL; 461 462 return r; 463 } 464 465 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 466 467 void amdgpu_discovery_fini(struct amdgpu_device *adev) 468 { 469 amdgpu_discovery_sysfs_fini(adev); 470 kfree(adev->mman.discovery_bin); 471 adev->mman.discovery_bin = NULL; 472 } 473 474 static int amdgpu_discovery_validate_ip(const struct ip *ip) 475 { 476 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 477 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 478 ip->number_instance); 479 return -EINVAL; 480 } 481 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 482 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 483 le16_to_cpu(ip->hw_id)); 484 return -EINVAL; 485 } 486 487 return 0; 488 } 489 490 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 491 uint32_t *vcn_harvest_count) 492 { 493 struct binary_header *bhdr; 494 struct ip_discovery_header *ihdr; 495 struct die_header *dhdr; 496 struct ip *ip; 497 uint16_t die_offset, ip_offset, num_dies, num_ips; 498 int i, j; 499 500 bhdr = (struct binary_header *)adev->mman.discovery_bin; 501 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 502 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 503 num_dies = le16_to_cpu(ihdr->num_dies); 504 505 /* scan harvest bit of all IP data structures */ 506 for (i = 0; i < num_dies; i++) { 507 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 508 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 509 num_ips = le16_to_cpu(dhdr->num_ips); 510 ip_offset = die_offset + sizeof(*dhdr); 511 512 for (j = 0; j < num_ips; j++) { 513 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 514 515 if (amdgpu_discovery_validate_ip(ip)) 516 goto next_ip; 517 518 if (le16_to_cpu(ip->harvest) == 1) { 519 switch (le16_to_cpu(ip->hw_id)) { 520 case VCN_HWID: 521 (*vcn_harvest_count)++; 522 if (ip->number_instance == 0) 523 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 524 else 525 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 526 break; 527 case DMU_HWID: 528 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 529 break; 530 default: 531 break; 532 } 533 } 534 next_ip: 535 ip_offset += struct_size(ip, base_address, ip->num_base_address); 536 } 537 } 538 } 539 540 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 541 uint32_t *vcn_harvest_count, 542 uint32_t *umc_harvest_count) 543 { 544 struct binary_header *bhdr; 545 struct harvest_table *harvest_info; 546 u16 offset; 547 int i; 548 uint32_t umc_harvest_config = 0; 549 550 bhdr = (struct binary_header *)adev->mman.discovery_bin; 551 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 552 553 if (!offset) { 554 dev_err(adev->dev, "invalid harvest table offset\n"); 555 return; 556 } 557 558 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 559 560 for (i = 0; i < 32; i++) { 561 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 562 break; 563 564 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 565 case VCN_HWID: 566 (*vcn_harvest_count)++; 567 if (harvest_info->list[i].number_instance == 0) 568 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 569 else 570 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 571 break; 572 case DMU_HWID: 573 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 574 break; 575 case UMC_HWID: 576 umc_harvest_config |= 577 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 578 (*umc_harvest_count)++; 579 break; 580 default: 581 break; 582 } 583 } 584 585 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 586 ~umc_harvest_config; 587 } 588 589 /* ================================================== */ 590 591 struct ip_hw_instance { 592 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 593 594 int hw_id; 595 u8 num_instance; 596 u8 major, minor, revision; 597 u8 harvest; 598 599 int num_base_addresses; 600 u32 base_addr[]; 601 }; 602 603 struct ip_hw_id { 604 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 605 int hw_id; 606 }; 607 608 struct ip_die_entry { 609 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 610 u16 num_ips; 611 }; 612 613 /* -------------------------------------------------- */ 614 615 struct ip_hw_instance_attr { 616 struct attribute attr; 617 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 618 }; 619 620 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 621 { 622 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 623 } 624 625 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 626 { 627 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 628 } 629 630 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 631 { 632 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 633 } 634 635 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 636 { 637 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 638 } 639 640 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 641 { 642 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 643 } 644 645 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 646 { 647 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 648 } 649 650 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 651 { 652 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 653 } 654 655 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 656 { 657 ssize_t res, at; 658 int ii; 659 660 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 661 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 662 */ 663 if (at + 12 > PAGE_SIZE) 664 break; 665 res = sysfs_emit_at(buf, at, "0x%08X\n", 666 ip_hw_instance->base_addr[ii]); 667 if (res <= 0) 668 break; 669 at += res; 670 } 671 672 return res < 0 ? res : at; 673 } 674 675 static struct ip_hw_instance_attr ip_hw_attr[] = { 676 __ATTR_RO(hw_id), 677 __ATTR_RO(num_instance), 678 __ATTR_RO(major), 679 __ATTR_RO(minor), 680 __ATTR_RO(revision), 681 __ATTR_RO(harvest), 682 __ATTR_RO(num_base_addresses), 683 __ATTR_RO(base_addr), 684 }; 685 686 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 687 ATTRIBUTE_GROUPS(ip_hw_instance); 688 689 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 690 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 691 692 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 693 struct attribute *attr, 694 char *buf) 695 { 696 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 697 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 698 699 if (!ip_hw_attr->show) 700 return -EIO; 701 702 return ip_hw_attr->show(ip_hw_instance, buf); 703 } 704 705 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 706 .show = ip_hw_instance_attr_show, 707 }; 708 709 static void ip_hw_instance_release(struct kobject *kobj) 710 { 711 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 712 713 kfree(ip_hw_instance); 714 } 715 716 static const struct kobj_type ip_hw_instance_ktype = { 717 .release = ip_hw_instance_release, 718 .sysfs_ops = &ip_hw_instance_sysfs_ops, 719 .default_groups = ip_hw_instance_groups, 720 }; 721 722 /* -------------------------------------------------- */ 723 724 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 725 726 static void ip_hw_id_release(struct kobject *kobj) 727 { 728 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 729 730 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 731 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 732 kfree(ip_hw_id); 733 } 734 735 static const struct kobj_type ip_hw_id_ktype = { 736 .release = ip_hw_id_release, 737 .sysfs_ops = &kobj_sysfs_ops, 738 }; 739 740 /* -------------------------------------------------- */ 741 742 static void die_kobj_release(struct kobject *kobj); 743 static void ip_disc_release(struct kobject *kobj); 744 745 struct ip_die_entry_attribute { 746 struct attribute attr; 747 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 748 }; 749 750 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 751 752 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 753 { 754 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 755 } 756 757 /* If there are more ip_die_entry attrs, other than the number of IPs, 758 * we can make this intro an array of attrs, and then initialize 759 * ip_die_entry_attrs in a loop. 760 */ 761 static struct ip_die_entry_attribute num_ips_attr = 762 __ATTR_RO(num_ips); 763 764 static struct attribute *ip_die_entry_attrs[] = { 765 &num_ips_attr.attr, 766 NULL, 767 }; 768 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 769 770 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 771 772 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 773 struct attribute *attr, 774 char *buf) 775 { 776 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 777 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 778 779 if (!ip_die_entry_attr->show) 780 return -EIO; 781 782 return ip_die_entry_attr->show(ip_die_entry, buf); 783 } 784 785 static void ip_die_entry_release(struct kobject *kobj) 786 { 787 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 788 789 if (!list_empty(&ip_die_entry->ip_kset.list)) 790 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 791 kfree(ip_die_entry); 792 } 793 794 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 795 .show = ip_die_entry_attr_show, 796 }; 797 798 static const struct kobj_type ip_die_entry_ktype = { 799 .release = ip_die_entry_release, 800 .sysfs_ops = &ip_die_entry_sysfs_ops, 801 .default_groups = ip_die_entry_groups, 802 }; 803 804 static const struct kobj_type die_kobj_ktype = { 805 .release = die_kobj_release, 806 .sysfs_ops = &kobj_sysfs_ops, 807 }; 808 809 static const struct kobj_type ip_discovery_ktype = { 810 .release = ip_disc_release, 811 .sysfs_ops = &kobj_sysfs_ops, 812 }; 813 814 struct ip_discovery_top { 815 struct kobject kobj; /* ip_discovery/ */ 816 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 817 struct amdgpu_device *adev; 818 }; 819 820 static void die_kobj_release(struct kobject *kobj) 821 { 822 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 823 struct ip_discovery_top, 824 die_kset); 825 if (!list_empty(&ip_top->die_kset.list)) 826 DRM_ERROR("ip_top->die_kset is not empty"); 827 } 828 829 static void ip_disc_release(struct kobject *kobj) 830 { 831 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 832 kobj); 833 struct amdgpu_device *adev = ip_top->adev; 834 835 adev->ip_top = NULL; 836 kfree(ip_top); 837 } 838 839 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 840 struct ip_die_entry *ip_die_entry, 841 const size_t _ip_offset, const int num_ips) 842 { 843 int ii, jj, kk, res; 844 845 DRM_DEBUG("num_ips:%d", num_ips); 846 847 /* Find all IPs of a given HW ID, and add their instance to 848 * #die/#hw_id/#instance/<attributes> 849 */ 850 for (ii = 0; ii < HW_ID_MAX; ii++) { 851 struct ip_hw_id *ip_hw_id = NULL; 852 size_t ip_offset = _ip_offset; 853 854 for (jj = 0; jj < num_ips; jj++) { 855 struct ip *ip; 856 struct ip_hw_instance *ip_hw_instance; 857 858 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 859 if (amdgpu_discovery_validate_ip(ip) || 860 le16_to_cpu(ip->hw_id) != ii) 861 goto next_ip; 862 863 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 864 865 /* We have a hw_id match; register the hw 866 * block if not yet registered. 867 */ 868 if (!ip_hw_id) { 869 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 870 if (!ip_hw_id) 871 return -ENOMEM; 872 ip_hw_id->hw_id = ii; 873 874 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 875 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 876 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 877 res = kset_register(&ip_hw_id->hw_id_kset); 878 if (res) { 879 DRM_ERROR("Couldn't register ip_hw_id kset"); 880 kfree(ip_hw_id); 881 return res; 882 } 883 if (hw_id_names[ii]) { 884 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 885 &ip_hw_id->hw_id_kset.kobj, 886 hw_id_names[ii]); 887 if (res) { 888 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 889 hw_id_names[ii], 890 kobject_name(&ip_die_entry->ip_kset.kobj)); 891 } 892 } 893 } 894 895 /* Now register its instance. 896 */ 897 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 898 base_addr, 899 ip->num_base_address), 900 GFP_KERNEL); 901 if (!ip_hw_instance) { 902 DRM_ERROR("no memory for ip_hw_instance"); 903 return -ENOMEM; 904 } 905 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 906 ip_hw_instance->num_instance = ip->number_instance; 907 ip_hw_instance->major = ip->major; 908 ip_hw_instance->minor = ip->minor; 909 ip_hw_instance->revision = ip->revision; 910 ip_hw_instance->harvest = ip->harvest; 911 ip_hw_instance->num_base_addresses = ip->num_base_address; 912 913 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 914 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 915 916 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 917 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 918 res = kobject_add(&ip_hw_instance->kobj, NULL, 919 "%d", ip_hw_instance->num_instance); 920 next_ip: 921 ip_offset += struct_size(ip, base_address, ip->num_base_address); 922 } 923 } 924 925 return 0; 926 } 927 928 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 929 { 930 struct binary_header *bhdr; 931 struct ip_discovery_header *ihdr; 932 struct die_header *dhdr; 933 struct kset *die_kset = &adev->ip_top->die_kset; 934 u16 num_dies, die_offset, num_ips; 935 size_t ip_offset; 936 int ii, res; 937 938 bhdr = (struct binary_header *)adev->mman.discovery_bin; 939 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 940 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 941 num_dies = le16_to_cpu(ihdr->num_dies); 942 943 DRM_DEBUG("number of dies: %d\n", num_dies); 944 945 for (ii = 0; ii < num_dies; ii++) { 946 struct ip_die_entry *ip_die_entry; 947 948 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 949 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 950 num_ips = le16_to_cpu(dhdr->num_ips); 951 ip_offset = die_offset + sizeof(*dhdr); 952 953 /* Add the die to the kset. 954 * 955 * dhdr->die_id == ii, which was checked in 956 * amdgpu_discovery_reg_base_init(). 957 */ 958 959 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 960 if (!ip_die_entry) 961 return -ENOMEM; 962 963 ip_die_entry->num_ips = num_ips; 964 965 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 966 ip_die_entry->ip_kset.kobj.kset = die_kset; 967 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 968 res = kset_register(&ip_die_entry->ip_kset); 969 if (res) { 970 DRM_ERROR("Couldn't register ip_die_entry kset"); 971 kfree(ip_die_entry); 972 return res; 973 } 974 975 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 976 } 977 978 return 0; 979 } 980 981 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 982 { 983 struct kset *die_kset; 984 int res, ii; 985 986 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 987 if (!adev->ip_top) 988 return -ENOMEM; 989 990 adev->ip_top->adev = adev; 991 992 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 993 &adev->dev->kobj, "ip_discovery"); 994 if (res) { 995 DRM_ERROR("Couldn't init and add ip_discovery/"); 996 goto Err; 997 } 998 999 die_kset = &adev->ip_top->die_kset; 1000 kobject_set_name(&die_kset->kobj, "%s", "die"); 1001 die_kset->kobj.parent = &adev->ip_top->kobj; 1002 die_kset->kobj.ktype = &die_kobj_ktype; 1003 res = kset_register(&adev->ip_top->die_kset); 1004 if (res) { 1005 DRM_ERROR("Couldn't register die_kset"); 1006 goto Err; 1007 } 1008 1009 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1010 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1011 ip_hw_instance_attrs[ii] = NULL; 1012 1013 res = amdgpu_discovery_sysfs_recurse(adev); 1014 1015 return res; 1016 Err: 1017 kobject_put(&adev->ip_top->kobj); 1018 return res; 1019 } 1020 1021 /* -------------------------------------------------- */ 1022 1023 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1024 1025 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1026 { 1027 struct list_head *el, *tmp; 1028 struct kset *hw_id_kset; 1029 1030 hw_id_kset = &ip_hw_id->hw_id_kset; 1031 spin_lock(&hw_id_kset->list_lock); 1032 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1033 list_del_init(el); 1034 spin_unlock(&hw_id_kset->list_lock); 1035 /* kobject is embedded in ip_hw_instance */ 1036 kobject_put(list_to_kobj(el)); 1037 spin_lock(&hw_id_kset->list_lock); 1038 } 1039 spin_unlock(&hw_id_kset->list_lock); 1040 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1041 } 1042 1043 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1044 { 1045 struct list_head *el, *tmp; 1046 struct kset *ip_kset; 1047 1048 ip_kset = &ip_die_entry->ip_kset; 1049 spin_lock(&ip_kset->list_lock); 1050 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1051 list_del_init(el); 1052 spin_unlock(&ip_kset->list_lock); 1053 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1054 spin_lock(&ip_kset->list_lock); 1055 } 1056 spin_unlock(&ip_kset->list_lock); 1057 kobject_put(&ip_die_entry->ip_kset.kobj); 1058 } 1059 1060 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1061 { 1062 struct list_head *el, *tmp; 1063 struct kset *die_kset; 1064 1065 die_kset = &adev->ip_top->die_kset; 1066 spin_lock(&die_kset->list_lock); 1067 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1068 list_del_init(el); 1069 spin_unlock(&die_kset->list_lock); 1070 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1071 spin_lock(&die_kset->list_lock); 1072 } 1073 spin_unlock(&die_kset->list_lock); 1074 kobject_put(&adev->ip_top->die_kset.kobj); 1075 kobject_put(&adev->ip_top->kobj); 1076 } 1077 1078 /* ================================================== */ 1079 1080 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1081 { 1082 struct binary_header *bhdr; 1083 struct ip_discovery_header *ihdr; 1084 struct die_header *dhdr; 1085 struct ip *ip; 1086 uint16_t die_offset; 1087 uint16_t ip_offset; 1088 uint16_t num_dies; 1089 uint16_t num_ips; 1090 uint8_t num_base_address; 1091 int hw_ip; 1092 int i, j, k; 1093 int r; 1094 1095 r = amdgpu_discovery_init(adev); 1096 if (r) { 1097 DRM_ERROR("amdgpu_discovery_init failed\n"); 1098 return r; 1099 } 1100 1101 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1102 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1103 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1104 num_dies = le16_to_cpu(ihdr->num_dies); 1105 1106 DRM_DEBUG("number of dies: %d\n", num_dies); 1107 1108 for (i = 0; i < num_dies; i++) { 1109 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1110 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1111 num_ips = le16_to_cpu(dhdr->num_ips); 1112 ip_offset = die_offset + sizeof(*dhdr); 1113 1114 if (le16_to_cpu(dhdr->die_id) != i) { 1115 DRM_ERROR("invalid die id %d, expected %d\n", 1116 le16_to_cpu(dhdr->die_id), i); 1117 return -EINVAL; 1118 } 1119 1120 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1121 le16_to_cpu(dhdr->die_id), num_ips); 1122 1123 for (j = 0; j < num_ips; j++) { 1124 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1125 1126 if (amdgpu_discovery_validate_ip(ip)) 1127 goto next_ip; 1128 1129 num_base_address = ip->num_base_address; 1130 1131 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1132 hw_id_names[le16_to_cpu(ip->hw_id)], 1133 le16_to_cpu(ip->hw_id), 1134 ip->number_instance, 1135 ip->major, ip->minor, 1136 ip->revision); 1137 1138 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1139 /* Bit [5:0]: original revision value 1140 * Bit [7:6]: en/decode capability: 1141 * 0b00 : VCN function normally 1142 * 0b10 : encode is disabled 1143 * 0b01 : decode is disabled 1144 */ 1145 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1146 ip->revision & 0xc0; 1147 ip->revision &= ~0xc0; 1148 if (adev->vcn.num_vcn_inst < AMDGPU_MAX_VCN_INSTANCES) 1149 adev->vcn.num_vcn_inst++; 1150 else 1151 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1152 adev->vcn.num_vcn_inst + 1, 1153 AMDGPU_MAX_VCN_INSTANCES); 1154 } 1155 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1156 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1157 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1158 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1159 if (adev->sdma.num_instances < AMDGPU_MAX_SDMA_INSTANCES) 1160 adev->sdma.num_instances++; 1161 else 1162 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1163 adev->sdma.num_instances + 1, 1164 AMDGPU_MAX_SDMA_INSTANCES); 1165 } 1166 1167 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1168 adev->gmc.num_umc++; 1169 adev->umc.node_inst_num++; 1170 } 1171 1172 for (k = 0; k < num_base_address; k++) { 1173 /* 1174 * convert the endianness of base addresses in place, 1175 * so that we don't need to convert them when accessing adev->reg_offset. 1176 */ 1177 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1178 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1179 } 1180 1181 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1182 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1183 DRM_DEBUG("set register base offset for %s\n", 1184 hw_id_names[le16_to_cpu(ip->hw_id)]); 1185 adev->reg_offset[hw_ip][ip->number_instance] = 1186 ip->base_address; 1187 /* Instance support is somewhat inconsistent. 1188 * SDMA is a good example. Sienna cichlid has 4 total 1189 * SDMA instances, each enumerated separately (HWIDs 1190 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1191 * but they are enumerated as multiple instances of the 1192 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1193 * example. On most chips there are multiple instances 1194 * with the same HWID. 1195 */ 1196 adev->ip_versions[hw_ip][ip->number_instance] = 1197 IP_VERSION(ip->major, ip->minor, ip->revision); 1198 } 1199 } 1200 1201 next_ip: 1202 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1203 } 1204 } 1205 1206 amdgpu_discovery_sysfs_init(adev); 1207 1208 return 0; 1209 } 1210 1211 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1212 { 1213 int vcn_harvest_count = 0; 1214 int umc_harvest_count = 0; 1215 1216 /* 1217 * Harvest table does not fit Navi1x and legacy GPUs, 1218 * so read harvest bit per IP data structure to set 1219 * harvest configuration. 1220 */ 1221 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1222 if ((adev->pdev->device == 0x731E && 1223 (adev->pdev->revision == 0xC6 || 1224 adev->pdev->revision == 0xC7)) || 1225 (adev->pdev->device == 0x7340 && 1226 adev->pdev->revision == 0xC9) || 1227 (adev->pdev->device == 0x7360 && 1228 adev->pdev->revision == 0xC7)) 1229 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1230 &vcn_harvest_count); 1231 } else { 1232 amdgpu_discovery_read_from_harvest_table(adev, 1233 &vcn_harvest_count, 1234 &umc_harvest_count); 1235 } 1236 1237 amdgpu_discovery_harvest_config_quirk(adev); 1238 1239 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1240 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1241 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1242 } 1243 1244 if (umc_harvest_count < adev->gmc.num_umc) { 1245 adev->gmc.num_umc -= umc_harvest_count; 1246 } 1247 } 1248 1249 union gc_info { 1250 struct gc_info_v1_0 v1; 1251 struct gc_info_v1_1 v1_1; 1252 struct gc_info_v1_2 v1_2; 1253 struct gc_info_v2_0 v2; 1254 }; 1255 1256 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1257 { 1258 struct binary_header *bhdr; 1259 union gc_info *gc_info; 1260 u16 offset; 1261 1262 if (!adev->mman.discovery_bin) { 1263 DRM_ERROR("ip discovery uninitialized\n"); 1264 return -EINVAL; 1265 } 1266 1267 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1268 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1269 1270 if (!offset) 1271 return 0; 1272 1273 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1274 1275 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1276 case 1: 1277 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1278 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1279 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1280 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1281 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1282 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1283 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1284 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1285 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1286 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1287 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1288 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1289 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1290 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1291 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1292 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1293 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1294 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1295 if (gc_info->v1.header.version_minor >= 1) { 1296 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1297 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1298 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1299 } 1300 if (gc_info->v1.header.version_minor >= 2) { 1301 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1302 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1303 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1304 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1305 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1306 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1307 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1308 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1309 } 1310 break; 1311 case 2: 1312 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1313 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1314 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1315 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1316 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1317 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1318 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1319 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1320 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1321 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1322 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1323 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1324 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1325 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1326 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1327 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1328 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1329 break; 1330 default: 1331 dev_err(adev->dev, 1332 "Unhandled GC info table %d.%d\n", 1333 le16_to_cpu(gc_info->v1.header.version_major), 1334 le16_to_cpu(gc_info->v1.header.version_minor)); 1335 return -EINVAL; 1336 } 1337 return 0; 1338 } 1339 1340 union mall_info { 1341 struct mall_info_v1_0 v1; 1342 }; 1343 1344 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1345 { 1346 struct binary_header *bhdr; 1347 union mall_info *mall_info; 1348 u32 u, mall_size_per_umc, m_s_present, half_use; 1349 u64 mall_size; 1350 u16 offset; 1351 1352 if (!adev->mman.discovery_bin) { 1353 DRM_ERROR("ip discovery uninitialized\n"); 1354 return -EINVAL; 1355 } 1356 1357 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1358 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1359 1360 if (!offset) 1361 return 0; 1362 1363 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1364 1365 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1366 case 1: 1367 mall_size = 0; 1368 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1369 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1370 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1371 for (u = 0; u < adev->gmc.num_umc; u++) { 1372 if (m_s_present & (1 << u)) 1373 mall_size += mall_size_per_umc * 2; 1374 else if (half_use & (1 << u)) 1375 mall_size += mall_size_per_umc / 2; 1376 else 1377 mall_size += mall_size_per_umc; 1378 } 1379 adev->gmc.mall_size = mall_size; 1380 break; 1381 default: 1382 dev_err(adev->dev, 1383 "Unhandled MALL info table %d.%d\n", 1384 le16_to_cpu(mall_info->v1.header.version_major), 1385 le16_to_cpu(mall_info->v1.header.version_minor)); 1386 return -EINVAL; 1387 } 1388 return 0; 1389 } 1390 1391 union vcn_info { 1392 struct vcn_info_v1_0 v1; 1393 }; 1394 1395 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1396 { 1397 struct binary_header *bhdr; 1398 union vcn_info *vcn_info; 1399 u16 offset; 1400 int v; 1401 1402 if (!adev->mman.discovery_bin) { 1403 DRM_ERROR("ip discovery uninitialized\n"); 1404 return -EINVAL; 1405 } 1406 1407 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1408 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1409 * but that may change in the future with new GPUs so keep this 1410 * check for defensive purposes. 1411 */ 1412 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1413 dev_err(adev->dev, "invalid vcn instances\n"); 1414 return -EINVAL; 1415 } 1416 1417 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1418 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1419 1420 if (!offset) 1421 return 0; 1422 1423 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1424 1425 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1426 case 1: 1427 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1428 * so this won't overflow. 1429 */ 1430 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1431 adev->vcn.vcn_codec_disable_mask[v] = 1432 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1433 } 1434 break; 1435 default: 1436 dev_err(adev->dev, 1437 "Unhandled VCN info table %d.%d\n", 1438 le16_to_cpu(vcn_info->v1.header.version_major), 1439 le16_to_cpu(vcn_info->v1.header.version_minor)); 1440 return -EINVAL; 1441 } 1442 return 0; 1443 } 1444 1445 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1446 { 1447 /* what IP to use for this? */ 1448 switch (adev->ip_versions[GC_HWIP][0]) { 1449 case IP_VERSION(9, 0, 1): 1450 case IP_VERSION(9, 1, 0): 1451 case IP_VERSION(9, 2, 1): 1452 case IP_VERSION(9, 2, 2): 1453 case IP_VERSION(9, 3, 0): 1454 case IP_VERSION(9, 4, 0): 1455 case IP_VERSION(9, 4, 1): 1456 case IP_VERSION(9, 4, 2): 1457 case IP_VERSION(9, 4, 3): 1458 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1459 break; 1460 case IP_VERSION(10, 1, 10): 1461 case IP_VERSION(10, 1, 1): 1462 case IP_VERSION(10, 1, 2): 1463 case IP_VERSION(10, 1, 3): 1464 case IP_VERSION(10, 1, 4): 1465 case IP_VERSION(10, 3, 0): 1466 case IP_VERSION(10, 3, 1): 1467 case IP_VERSION(10, 3, 2): 1468 case IP_VERSION(10, 3, 3): 1469 case IP_VERSION(10, 3, 4): 1470 case IP_VERSION(10, 3, 5): 1471 case IP_VERSION(10, 3, 6): 1472 case IP_VERSION(10, 3, 7): 1473 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1474 break; 1475 case IP_VERSION(11, 0, 0): 1476 case IP_VERSION(11, 0, 1): 1477 case IP_VERSION(11, 0, 2): 1478 case IP_VERSION(11, 0, 3): 1479 case IP_VERSION(11, 0, 4): 1480 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1481 break; 1482 default: 1483 dev_err(adev->dev, 1484 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1485 adev->ip_versions[GC_HWIP][0]); 1486 return -EINVAL; 1487 } 1488 return 0; 1489 } 1490 1491 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1492 { 1493 /* use GC or MMHUB IP version */ 1494 switch (adev->ip_versions[GC_HWIP][0]) { 1495 case IP_VERSION(9, 0, 1): 1496 case IP_VERSION(9, 1, 0): 1497 case IP_VERSION(9, 2, 1): 1498 case IP_VERSION(9, 2, 2): 1499 case IP_VERSION(9, 3, 0): 1500 case IP_VERSION(9, 4, 0): 1501 case IP_VERSION(9, 4, 1): 1502 case IP_VERSION(9, 4, 2): 1503 case IP_VERSION(9, 4, 3): 1504 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1505 break; 1506 case IP_VERSION(10, 1, 10): 1507 case IP_VERSION(10, 1, 1): 1508 case IP_VERSION(10, 1, 2): 1509 case IP_VERSION(10, 1, 3): 1510 case IP_VERSION(10, 1, 4): 1511 case IP_VERSION(10, 3, 0): 1512 case IP_VERSION(10, 3, 1): 1513 case IP_VERSION(10, 3, 2): 1514 case IP_VERSION(10, 3, 3): 1515 case IP_VERSION(10, 3, 4): 1516 case IP_VERSION(10, 3, 5): 1517 case IP_VERSION(10, 3, 6): 1518 case IP_VERSION(10, 3, 7): 1519 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1520 break; 1521 case IP_VERSION(11, 0, 0): 1522 case IP_VERSION(11, 0, 1): 1523 case IP_VERSION(11, 0, 2): 1524 case IP_VERSION(11, 0, 3): 1525 case IP_VERSION(11, 0, 4): 1526 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1527 break; 1528 default: 1529 dev_err(adev->dev, 1530 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1531 adev->ip_versions[GC_HWIP][0]); 1532 return -EINVAL; 1533 } 1534 return 0; 1535 } 1536 1537 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1538 { 1539 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1540 case IP_VERSION(4, 0, 0): 1541 case IP_VERSION(4, 0, 1): 1542 case IP_VERSION(4, 1, 0): 1543 case IP_VERSION(4, 1, 1): 1544 case IP_VERSION(4, 3, 0): 1545 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1546 break; 1547 case IP_VERSION(4, 2, 0): 1548 case IP_VERSION(4, 2, 1): 1549 case IP_VERSION(4, 4, 0): 1550 case IP_VERSION(4, 4, 2): 1551 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1552 break; 1553 case IP_VERSION(5, 0, 0): 1554 case IP_VERSION(5, 0, 1): 1555 case IP_VERSION(5, 0, 2): 1556 case IP_VERSION(5, 0, 3): 1557 case IP_VERSION(5, 2, 0): 1558 case IP_VERSION(5, 2, 1): 1559 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1560 break; 1561 case IP_VERSION(6, 0, 0): 1562 case IP_VERSION(6, 0, 1): 1563 case IP_VERSION(6, 0, 2): 1564 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1565 break; 1566 default: 1567 dev_err(adev->dev, 1568 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1569 adev->ip_versions[OSSSYS_HWIP][0]); 1570 return -EINVAL; 1571 } 1572 return 0; 1573 } 1574 1575 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1576 { 1577 switch (adev->ip_versions[MP0_HWIP][0]) { 1578 case IP_VERSION(9, 0, 0): 1579 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1580 break; 1581 case IP_VERSION(10, 0, 0): 1582 case IP_VERSION(10, 0, 1): 1583 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1584 break; 1585 case IP_VERSION(11, 0, 0): 1586 case IP_VERSION(11, 0, 2): 1587 case IP_VERSION(11, 0, 4): 1588 case IP_VERSION(11, 0, 5): 1589 case IP_VERSION(11, 0, 9): 1590 case IP_VERSION(11, 0, 7): 1591 case IP_VERSION(11, 0, 11): 1592 case IP_VERSION(11, 0, 12): 1593 case IP_VERSION(11, 0, 13): 1594 case IP_VERSION(11, 5, 0): 1595 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1596 break; 1597 case IP_VERSION(11, 0, 8): 1598 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1599 break; 1600 case IP_VERSION(11, 0, 3): 1601 case IP_VERSION(12, 0, 1): 1602 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1603 break; 1604 case IP_VERSION(13, 0, 0): 1605 case IP_VERSION(13, 0, 1): 1606 case IP_VERSION(13, 0, 2): 1607 case IP_VERSION(13, 0, 3): 1608 case IP_VERSION(13, 0, 5): 1609 case IP_VERSION(13, 0, 6): 1610 case IP_VERSION(13, 0, 7): 1611 case IP_VERSION(13, 0, 8): 1612 case IP_VERSION(13, 0, 10): 1613 case IP_VERSION(13, 0, 11): 1614 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1615 break; 1616 case IP_VERSION(13, 0, 4): 1617 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1618 break; 1619 default: 1620 dev_err(adev->dev, 1621 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1622 adev->ip_versions[MP0_HWIP][0]); 1623 return -EINVAL; 1624 } 1625 return 0; 1626 } 1627 1628 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1629 { 1630 switch (adev->ip_versions[MP1_HWIP][0]) { 1631 case IP_VERSION(9, 0, 0): 1632 case IP_VERSION(10, 0, 0): 1633 case IP_VERSION(10, 0, 1): 1634 case IP_VERSION(11, 0, 2): 1635 if (adev->asic_type == CHIP_ARCTURUS) 1636 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1637 else 1638 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1639 break; 1640 case IP_VERSION(11, 0, 0): 1641 case IP_VERSION(11, 0, 5): 1642 case IP_VERSION(11, 0, 9): 1643 case IP_VERSION(11, 0, 7): 1644 case IP_VERSION(11, 0, 8): 1645 case IP_VERSION(11, 0, 11): 1646 case IP_VERSION(11, 0, 12): 1647 case IP_VERSION(11, 0, 13): 1648 case IP_VERSION(11, 5, 0): 1649 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1650 break; 1651 case IP_VERSION(12, 0, 0): 1652 case IP_VERSION(12, 0, 1): 1653 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1654 break; 1655 case IP_VERSION(13, 0, 0): 1656 case IP_VERSION(13, 0, 1): 1657 case IP_VERSION(13, 0, 2): 1658 case IP_VERSION(13, 0, 3): 1659 case IP_VERSION(13, 0, 4): 1660 case IP_VERSION(13, 0, 5): 1661 case IP_VERSION(13, 0, 7): 1662 case IP_VERSION(13, 0, 8): 1663 case IP_VERSION(13, 0, 10): 1664 case IP_VERSION(13, 0, 11): 1665 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1666 break; 1667 default: 1668 dev_err(adev->dev, 1669 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1670 adev->ip_versions[MP1_HWIP][0]); 1671 return -EINVAL; 1672 } 1673 return 0; 1674 } 1675 1676 #if defined(CONFIG_DRM_AMD_DC) 1677 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1678 { 1679 amdgpu_device_set_sriov_virtual_display(adev); 1680 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1681 } 1682 #endif 1683 1684 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1685 { 1686 if (adev->enable_virtual_display) { 1687 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1688 return 0; 1689 } 1690 1691 if (!amdgpu_device_has_dc_support(adev)) 1692 return 0; 1693 1694 #if defined(CONFIG_DRM_AMD_DC) 1695 if (adev->ip_versions[DCE_HWIP][0]) { 1696 switch (adev->ip_versions[DCE_HWIP][0]) { 1697 case IP_VERSION(1, 0, 0): 1698 case IP_VERSION(1, 0, 1): 1699 case IP_VERSION(2, 0, 2): 1700 case IP_VERSION(2, 0, 0): 1701 case IP_VERSION(2, 0, 3): 1702 case IP_VERSION(2, 1, 0): 1703 case IP_VERSION(3, 0, 0): 1704 case IP_VERSION(3, 0, 2): 1705 case IP_VERSION(3, 0, 3): 1706 case IP_VERSION(3, 0, 1): 1707 case IP_VERSION(3, 1, 2): 1708 case IP_VERSION(3, 1, 3): 1709 case IP_VERSION(3, 1, 4): 1710 case IP_VERSION(3, 1, 5): 1711 case IP_VERSION(3, 1, 6): 1712 case IP_VERSION(3, 2, 0): 1713 case IP_VERSION(3, 2, 1): 1714 if (amdgpu_sriov_vf(adev)) 1715 amdgpu_discovery_set_sriov_display(adev); 1716 else 1717 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1718 break; 1719 default: 1720 dev_err(adev->dev, 1721 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1722 adev->ip_versions[DCE_HWIP][0]); 1723 return -EINVAL; 1724 } 1725 } else if (adev->ip_versions[DCI_HWIP][0]) { 1726 switch (adev->ip_versions[DCI_HWIP][0]) { 1727 case IP_VERSION(12, 0, 0): 1728 case IP_VERSION(12, 0, 1): 1729 case IP_VERSION(12, 1, 0): 1730 if (amdgpu_sriov_vf(adev)) 1731 amdgpu_discovery_set_sriov_display(adev); 1732 else 1733 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1734 break; 1735 default: 1736 dev_err(adev->dev, 1737 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1738 adev->ip_versions[DCI_HWIP][0]); 1739 return -EINVAL; 1740 } 1741 } 1742 #endif 1743 return 0; 1744 } 1745 1746 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1747 { 1748 switch (adev->ip_versions[GC_HWIP][0]) { 1749 case IP_VERSION(9, 0, 1): 1750 case IP_VERSION(9, 1, 0): 1751 case IP_VERSION(9, 2, 1): 1752 case IP_VERSION(9, 2, 2): 1753 case IP_VERSION(9, 3, 0): 1754 case IP_VERSION(9, 4, 0): 1755 case IP_VERSION(9, 4, 1): 1756 case IP_VERSION(9, 4, 2): 1757 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1758 break; 1759 case IP_VERSION(10, 1, 10): 1760 case IP_VERSION(10, 1, 2): 1761 case IP_VERSION(10, 1, 1): 1762 case IP_VERSION(10, 1, 3): 1763 case IP_VERSION(10, 1, 4): 1764 case IP_VERSION(10, 3, 0): 1765 case IP_VERSION(10, 3, 2): 1766 case IP_VERSION(10, 3, 1): 1767 case IP_VERSION(10, 3, 4): 1768 case IP_VERSION(10, 3, 5): 1769 case IP_VERSION(10, 3, 6): 1770 case IP_VERSION(10, 3, 3): 1771 case IP_VERSION(10, 3, 7): 1772 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1773 break; 1774 case IP_VERSION(11, 0, 0): 1775 case IP_VERSION(11, 0, 1): 1776 case IP_VERSION(11, 0, 2): 1777 case IP_VERSION(11, 0, 3): 1778 case IP_VERSION(11, 0, 4): 1779 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1780 break; 1781 default: 1782 dev_err(adev->dev, 1783 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1784 adev->ip_versions[GC_HWIP][0]); 1785 return -EINVAL; 1786 } 1787 return 0; 1788 } 1789 1790 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1791 { 1792 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1793 case IP_VERSION(4, 0, 0): 1794 case IP_VERSION(4, 0, 1): 1795 case IP_VERSION(4, 1, 0): 1796 case IP_VERSION(4, 1, 1): 1797 case IP_VERSION(4, 1, 2): 1798 case IP_VERSION(4, 2, 0): 1799 case IP_VERSION(4, 2, 2): 1800 case IP_VERSION(4, 4, 0): 1801 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1802 break; 1803 case IP_VERSION(4, 4, 2): 1804 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 1805 break; 1806 case IP_VERSION(5, 0, 0): 1807 case IP_VERSION(5, 0, 1): 1808 case IP_VERSION(5, 0, 2): 1809 case IP_VERSION(5, 0, 5): 1810 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1811 break; 1812 case IP_VERSION(5, 2, 0): 1813 case IP_VERSION(5, 2, 2): 1814 case IP_VERSION(5, 2, 4): 1815 case IP_VERSION(5, 2, 5): 1816 case IP_VERSION(5, 2, 6): 1817 case IP_VERSION(5, 2, 3): 1818 case IP_VERSION(5, 2, 1): 1819 case IP_VERSION(5, 2, 7): 1820 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1821 break; 1822 case IP_VERSION(6, 0, 0): 1823 case IP_VERSION(6, 0, 1): 1824 case IP_VERSION(6, 0, 2): 1825 case IP_VERSION(6, 0, 3): 1826 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1827 break; 1828 default: 1829 dev_err(adev->dev, 1830 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1831 adev->ip_versions[SDMA0_HWIP][0]); 1832 return -EINVAL; 1833 } 1834 return 0; 1835 } 1836 1837 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1838 { 1839 if (adev->ip_versions[VCE_HWIP][0]) { 1840 switch (adev->ip_versions[UVD_HWIP][0]) { 1841 case IP_VERSION(7, 0, 0): 1842 case IP_VERSION(7, 2, 0): 1843 /* UVD is not supported on vega20 SR-IOV */ 1844 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1845 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1846 break; 1847 default: 1848 dev_err(adev->dev, 1849 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1850 adev->ip_versions[UVD_HWIP][0]); 1851 return -EINVAL; 1852 } 1853 switch (adev->ip_versions[VCE_HWIP][0]) { 1854 case IP_VERSION(4, 0, 0): 1855 case IP_VERSION(4, 1, 0): 1856 /* VCE is not supported on vega20 SR-IOV */ 1857 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1858 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1859 break; 1860 default: 1861 dev_err(adev->dev, 1862 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1863 adev->ip_versions[VCE_HWIP][0]); 1864 return -EINVAL; 1865 } 1866 } else { 1867 switch (adev->ip_versions[UVD_HWIP][0]) { 1868 case IP_VERSION(1, 0, 0): 1869 case IP_VERSION(1, 0, 1): 1870 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1871 break; 1872 case IP_VERSION(2, 0, 0): 1873 case IP_VERSION(2, 0, 2): 1874 case IP_VERSION(2, 2, 0): 1875 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1876 if (!amdgpu_sriov_vf(adev)) 1877 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1878 break; 1879 case IP_VERSION(2, 0, 3): 1880 break; 1881 case IP_VERSION(2, 5, 0): 1882 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1883 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1884 break; 1885 case IP_VERSION(2, 6, 0): 1886 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1887 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1888 break; 1889 case IP_VERSION(3, 0, 0): 1890 case IP_VERSION(3, 0, 16): 1891 case IP_VERSION(3, 1, 1): 1892 case IP_VERSION(3, 1, 2): 1893 case IP_VERSION(3, 0, 2): 1894 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1895 if (!amdgpu_sriov_vf(adev)) 1896 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1897 break; 1898 case IP_VERSION(3, 0, 33): 1899 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1900 break; 1901 case IP_VERSION(4, 0, 0): 1902 case IP_VERSION(4, 0, 2): 1903 case IP_VERSION(4, 0, 4): 1904 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 1905 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 1906 return 0; 1907 default: 1908 dev_err(adev->dev, 1909 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1910 adev->ip_versions[UVD_HWIP][0]); 1911 return -EINVAL; 1912 } 1913 } 1914 return 0; 1915 } 1916 1917 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1918 { 1919 switch (adev->ip_versions[GC_HWIP][0]) { 1920 case IP_VERSION(10, 1, 10): 1921 case IP_VERSION(10, 1, 1): 1922 case IP_VERSION(10, 1, 2): 1923 case IP_VERSION(10, 1, 3): 1924 case IP_VERSION(10, 1, 4): 1925 case IP_VERSION(10, 3, 0): 1926 case IP_VERSION(10, 3, 1): 1927 case IP_VERSION(10, 3, 2): 1928 case IP_VERSION(10, 3, 3): 1929 case IP_VERSION(10, 3, 4): 1930 case IP_VERSION(10, 3, 5): 1931 case IP_VERSION(10, 3, 6): 1932 if (amdgpu_mes) { 1933 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1934 adev->enable_mes = true; 1935 if (amdgpu_mes_kiq) 1936 adev->enable_mes_kiq = true; 1937 } 1938 break; 1939 case IP_VERSION(11, 0, 0): 1940 case IP_VERSION(11, 0, 1): 1941 case IP_VERSION(11, 0, 2): 1942 case IP_VERSION(11, 0, 3): 1943 case IP_VERSION(11, 0, 4): 1944 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 1945 adev->enable_mes = true; 1946 adev->enable_mes_kiq = true; 1947 break; 1948 default: 1949 break; 1950 } 1951 return 0; 1952 } 1953 1954 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1955 { 1956 int r; 1957 1958 switch (adev->asic_type) { 1959 case CHIP_VEGA10: 1960 vega10_reg_base_init(adev); 1961 adev->sdma.num_instances = 2; 1962 adev->gmc.num_umc = 4; 1963 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1964 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1965 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1966 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1967 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1968 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1969 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1970 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1971 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1972 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1973 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1974 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1975 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1976 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1977 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1978 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1979 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1980 break; 1981 case CHIP_VEGA12: 1982 vega10_reg_base_init(adev); 1983 adev->sdma.num_instances = 2; 1984 adev->gmc.num_umc = 4; 1985 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1986 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1987 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1988 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1989 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1990 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1991 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1992 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1993 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1994 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1995 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1996 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1997 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1998 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1999 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2000 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2001 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2002 break; 2003 case CHIP_RAVEN: 2004 vega10_reg_base_init(adev); 2005 adev->sdma.num_instances = 1; 2006 adev->vcn.num_vcn_inst = 1; 2007 adev->gmc.num_umc = 2; 2008 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2009 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2010 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2011 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2012 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2013 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2014 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2015 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2016 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2017 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2018 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2019 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2020 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2021 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2022 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2023 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2024 } else { 2025 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2026 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2027 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2028 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2029 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2030 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2031 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2032 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2033 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2034 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2035 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2036 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2037 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2038 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2039 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2040 } 2041 break; 2042 case CHIP_VEGA20: 2043 vega20_reg_base_init(adev); 2044 adev->sdma.num_instances = 2; 2045 adev->gmc.num_umc = 8; 2046 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2047 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2048 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2049 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2050 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2051 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2052 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2053 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2054 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2055 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2056 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2057 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2058 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2059 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2060 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2061 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2062 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2063 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2064 break; 2065 case CHIP_ARCTURUS: 2066 arct_reg_base_init(adev); 2067 adev->sdma.num_instances = 8; 2068 adev->vcn.num_vcn_inst = 2; 2069 adev->gmc.num_umc = 8; 2070 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2071 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2072 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2073 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2074 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2075 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2076 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2077 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2078 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2079 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2080 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2081 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2082 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2083 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2084 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2085 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2086 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2087 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2088 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2089 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2090 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2091 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2092 break; 2093 case CHIP_ALDEBARAN: 2094 aldebaran_reg_base_init(adev); 2095 adev->sdma.num_instances = 5; 2096 adev->vcn.num_vcn_inst = 2; 2097 adev->gmc.num_umc = 4; 2098 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2099 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2100 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2101 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2102 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2103 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2104 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2105 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2106 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2107 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2108 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2109 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2110 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2111 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2112 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2113 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2114 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2115 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2116 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2117 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2118 break; 2119 default: 2120 r = amdgpu_discovery_reg_base_init(adev); 2121 if (r) 2122 return -EINVAL; 2123 2124 amdgpu_discovery_harvest_ip(adev); 2125 amdgpu_discovery_get_gfx_info(adev); 2126 amdgpu_discovery_get_mall_info(adev); 2127 amdgpu_discovery_get_vcn_info(adev); 2128 break; 2129 } 2130 2131 switch (adev->ip_versions[GC_HWIP][0]) { 2132 case IP_VERSION(9, 0, 1): 2133 case IP_VERSION(9, 2, 1): 2134 case IP_VERSION(9, 4, 0): 2135 case IP_VERSION(9, 4, 1): 2136 case IP_VERSION(9, 4, 2): 2137 case IP_VERSION(9, 4, 3): 2138 adev->family = AMDGPU_FAMILY_AI; 2139 break; 2140 case IP_VERSION(9, 1, 0): 2141 case IP_VERSION(9, 2, 2): 2142 case IP_VERSION(9, 3, 0): 2143 adev->family = AMDGPU_FAMILY_RV; 2144 break; 2145 case IP_VERSION(10, 1, 10): 2146 case IP_VERSION(10, 1, 1): 2147 case IP_VERSION(10, 1, 2): 2148 case IP_VERSION(10, 1, 3): 2149 case IP_VERSION(10, 1, 4): 2150 case IP_VERSION(10, 3, 0): 2151 case IP_VERSION(10, 3, 2): 2152 case IP_VERSION(10, 3, 4): 2153 case IP_VERSION(10, 3, 5): 2154 adev->family = AMDGPU_FAMILY_NV; 2155 break; 2156 case IP_VERSION(10, 3, 1): 2157 adev->family = AMDGPU_FAMILY_VGH; 2158 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2159 break; 2160 case IP_VERSION(10, 3, 3): 2161 adev->family = AMDGPU_FAMILY_YC; 2162 break; 2163 case IP_VERSION(10, 3, 6): 2164 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2165 break; 2166 case IP_VERSION(10, 3, 7): 2167 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2168 break; 2169 case IP_VERSION(11, 0, 0): 2170 case IP_VERSION(11, 0, 2): 2171 case IP_VERSION(11, 0, 3): 2172 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2173 break; 2174 case IP_VERSION(11, 0, 1): 2175 case IP_VERSION(11, 0, 4): 2176 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2177 break; 2178 default: 2179 return -EINVAL; 2180 } 2181 2182 switch (adev->ip_versions[GC_HWIP][0]) { 2183 case IP_VERSION(9, 1, 0): 2184 case IP_VERSION(9, 2, 2): 2185 case IP_VERSION(9, 3, 0): 2186 case IP_VERSION(10, 1, 3): 2187 case IP_VERSION(10, 1, 4): 2188 case IP_VERSION(10, 3, 1): 2189 case IP_VERSION(10, 3, 3): 2190 case IP_VERSION(10, 3, 6): 2191 case IP_VERSION(10, 3, 7): 2192 case IP_VERSION(11, 0, 1): 2193 case IP_VERSION(11, 0, 4): 2194 adev->flags |= AMD_IS_APU; 2195 break; 2196 default: 2197 break; 2198 } 2199 2200 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2201 adev->gmc.xgmi.supported = true; 2202 2203 /* set NBIO version */ 2204 switch (adev->ip_versions[NBIO_HWIP][0]) { 2205 case IP_VERSION(6, 1, 0): 2206 case IP_VERSION(6, 2, 0): 2207 adev->nbio.funcs = &nbio_v6_1_funcs; 2208 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2209 break; 2210 case IP_VERSION(7, 0, 0): 2211 case IP_VERSION(7, 0, 1): 2212 case IP_VERSION(2, 5, 0): 2213 adev->nbio.funcs = &nbio_v7_0_funcs; 2214 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2215 break; 2216 case IP_VERSION(7, 4, 0): 2217 case IP_VERSION(7, 4, 1): 2218 case IP_VERSION(7, 4, 4): 2219 adev->nbio.funcs = &nbio_v7_4_funcs; 2220 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2221 break; 2222 case IP_VERSION(7, 9, 0): 2223 adev->nbio.funcs = &nbio_v7_9_funcs; 2224 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2225 break; 2226 case IP_VERSION(7, 2, 0): 2227 case IP_VERSION(7, 2, 1): 2228 case IP_VERSION(7, 3, 0): 2229 case IP_VERSION(7, 5, 0): 2230 case IP_VERSION(7, 5, 1): 2231 adev->nbio.funcs = &nbio_v7_2_funcs; 2232 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2233 break; 2234 case IP_VERSION(2, 1, 1): 2235 case IP_VERSION(2, 3, 0): 2236 case IP_VERSION(2, 3, 1): 2237 case IP_VERSION(2, 3, 2): 2238 case IP_VERSION(3, 3, 0): 2239 case IP_VERSION(3, 3, 1): 2240 case IP_VERSION(3, 3, 2): 2241 case IP_VERSION(3, 3, 3): 2242 adev->nbio.funcs = &nbio_v2_3_funcs; 2243 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2244 break; 2245 case IP_VERSION(4, 3, 0): 2246 case IP_VERSION(4, 3, 1): 2247 if (amdgpu_sriov_vf(adev)) 2248 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2249 else 2250 adev->nbio.funcs = &nbio_v4_3_funcs; 2251 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2252 break; 2253 case IP_VERSION(7, 7, 0): 2254 case IP_VERSION(7, 7, 1): 2255 adev->nbio.funcs = &nbio_v7_7_funcs; 2256 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2257 break; 2258 default: 2259 break; 2260 } 2261 2262 switch (adev->ip_versions[HDP_HWIP][0]) { 2263 case IP_VERSION(4, 0, 0): 2264 case IP_VERSION(4, 0, 1): 2265 case IP_VERSION(4, 1, 0): 2266 case IP_VERSION(4, 1, 1): 2267 case IP_VERSION(4, 1, 2): 2268 case IP_VERSION(4, 2, 0): 2269 case IP_VERSION(4, 2, 1): 2270 case IP_VERSION(4, 4, 0): 2271 case IP_VERSION(4, 4, 2): 2272 adev->hdp.funcs = &hdp_v4_0_funcs; 2273 break; 2274 case IP_VERSION(5, 0, 0): 2275 case IP_VERSION(5, 0, 1): 2276 case IP_VERSION(5, 0, 2): 2277 case IP_VERSION(5, 0, 3): 2278 case IP_VERSION(5, 0, 4): 2279 case IP_VERSION(5, 2, 0): 2280 adev->hdp.funcs = &hdp_v5_0_funcs; 2281 break; 2282 case IP_VERSION(5, 2, 1): 2283 adev->hdp.funcs = &hdp_v5_2_funcs; 2284 break; 2285 case IP_VERSION(6, 0, 0): 2286 case IP_VERSION(6, 0, 1): 2287 adev->hdp.funcs = &hdp_v6_0_funcs; 2288 break; 2289 default: 2290 break; 2291 } 2292 2293 switch (adev->ip_versions[DF_HWIP][0]) { 2294 case IP_VERSION(3, 6, 0): 2295 case IP_VERSION(3, 6, 1): 2296 case IP_VERSION(3, 6, 2): 2297 adev->df.funcs = &df_v3_6_funcs; 2298 break; 2299 case IP_VERSION(2, 1, 0): 2300 case IP_VERSION(2, 1, 1): 2301 case IP_VERSION(2, 5, 0): 2302 case IP_VERSION(3, 5, 1): 2303 case IP_VERSION(3, 5, 2): 2304 adev->df.funcs = &df_v1_7_funcs; 2305 break; 2306 case IP_VERSION(4, 3, 0): 2307 adev->df.funcs = &df_v4_3_funcs; 2308 break; 2309 default: 2310 break; 2311 } 2312 2313 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2314 case IP_VERSION(9, 0, 0): 2315 case IP_VERSION(9, 0, 1): 2316 case IP_VERSION(10, 0, 0): 2317 case IP_VERSION(10, 0, 1): 2318 case IP_VERSION(10, 0, 2): 2319 adev->smuio.funcs = &smuio_v9_0_funcs; 2320 break; 2321 case IP_VERSION(11, 0, 0): 2322 case IP_VERSION(11, 0, 2): 2323 case IP_VERSION(11, 0, 3): 2324 case IP_VERSION(11, 0, 4): 2325 case IP_VERSION(11, 0, 7): 2326 case IP_VERSION(11, 0, 8): 2327 adev->smuio.funcs = &smuio_v11_0_funcs; 2328 break; 2329 case IP_VERSION(11, 0, 6): 2330 case IP_VERSION(11, 0, 10): 2331 case IP_VERSION(11, 0, 11): 2332 case IP_VERSION(11, 5, 0): 2333 case IP_VERSION(13, 0, 1): 2334 case IP_VERSION(13, 0, 9): 2335 case IP_VERSION(13, 0, 10): 2336 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2337 break; 2338 case IP_VERSION(13, 0, 2): 2339 adev->smuio.funcs = &smuio_v13_0_funcs; 2340 break; 2341 case IP_VERSION(13, 0, 6): 2342 case IP_VERSION(13, 0, 8): 2343 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2344 break; 2345 default: 2346 break; 2347 } 2348 2349 switch (adev->ip_versions[LSDMA_HWIP][0]) { 2350 case IP_VERSION(6, 0, 0): 2351 case IP_VERSION(6, 0, 1): 2352 case IP_VERSION(6, 0, 2): 2353 case IP_VERSION(6, 0, 3): 2354 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2355 break; 2356 default: 2357 break; 2358 } 2359 2360 r = amdgpu_discovery_set_common_ip_blocks(adev); 2361 if (r) 2362 return r; 2363 2364 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2365 if (r) 2366 return r; 2367 2368 /* For SR-IOV, PSP needs to be initialized before IH */ 2369 if (amdgpu_sriov_vf(adev)) { 2370 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2371 if (r) 2372 return r; 2373 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2374 if (r) 2375 return r; 2376 } else { 2377 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2378 if (r) 2379 return r; 2380 2381 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2382 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2383 if (r) 2384 return r; 2385 } 2386 } 2387 2388 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2389 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2390 if (r) 2391 return r; 2392 } 2393 2394 r = amdgpu_discovery_set_display_ip_blocks(adev); 2395 if (r) 2396 return r; 2397 2398 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2399 if (r) 2400 return r; 2401 2402 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2403 if (r) 2404 return r; 2405 2406 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2407 !amdgpu_sriov_vf(adev)) || 2408 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2409 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2410 if (r) 2411 return r; 2412 } 2413 2414 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2415 if (r) 2416 return r; 2417 2418 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2419 if (r) 2420 return r; 2421 2422 return 0; 2423 } 2424 2425