1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gmc_v11_0.h" 51 #include "gfxhub_v2_0.h" 52 #include "mmhub_v2_0.h" 53 #include "nbio_v2_3.h" 54 #include "nbio_v4_3.h" 55 #include "nbio_v7_2.h" 56 #include "hdp_v5_0.h" 57 #include "hdp_v6_0.h" 58 #include "nv.h" 59 #include "soc21.h" 60 #include "navi10_ih.h" 61 #include "ih_v6_0.h" 62 #include "gfx_v10_0.h" 63 #include "gfx_v11_0.h" 64 #include "sdma_v5_0.h" 65 #include "sdma_v5_2.h" 66 #include "sdma_v6_0.h" 67 #include "vcn_v2_0.h" 68 #include "jpeg_v2_0.h" 69 #include "vcn_v3_0.h" 70 #include "jpeg_v3_0.h" 71 #include "amdgpu_vkms.h" 72 #include "mes_v10_1.h" 73 #include "mes_v11_0.h" 74 #include "smuio_v11_0.h" 75 #include "smuio_v11_0_6.h" 76 #include "smuio_v13_0.h" 77 #include "smuio_v13_0_6.h" 78 79 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 80 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 81 82 #define mmRCC_CONFIG_MEMSIZE 0xde3 83 #define mmMM_INDEX 0x0 84 #define mmMM_INDEX_HI 0x6 85 #define mmMM_DATA 0x1 86 87 static const char *hw_id_names[HW_ID_MAX] = { 88 [MP1_HWID] = "MP1", 89 [MP2_HWID] = "MP2", 90 [THM_HWID] = "THM", 91 [SMUIO_HWID] = "SMUIO", 92 [FUSE_HWID] = "FUSE", 93 [CLKA_HWID] = "CLKA", 94 [PWR_HWID] = "PWR", 95 [GC_HWID] = "GC", 96 [UVD_HWID] = "UVD", 97 [AUDIO_AZ_HWID] = "AUDIO_AZ", 98 [ACP_HWID] = "ACP", 99 [DCI_HWID] = "DCI", 100 [DMU_HWID] = "DMU", 101 [DCO_HWID] = "DCO", 102 [DIO_HWID] = "DIO", 103 [XDMA_HWID] = "XDMA", 104 [DCEAZ_HWID] = "DCEAZ", 105 [DAZ_HWID] = "DAZ", 106 [SDPMUX_HWID] = "SDPMUX", 107 [NTB_HWID] = "NTB", 108 [IOHC_HWID] = "IOHC", 109 [L2IMU_HWID] = "L2IMU", 110 [VCE_HWID] = "VCE", 111 [MMHUB_HWID] = "MMHUB", 112 [ATHUB_HWID] = "ATHUB", 113 [DBGU_NBIO_HWID] = "DBGU_NBIO", 114 [DFX_HWID] = "DFX", 115 [DBGU0_HWID] = "DBGU0", 116 [DBGU1_HWID] = "DBGU1", 117 [OSSSYS_HWID] = "OSSSYS", 118 [HDP_HWID] = "HDP", 119 [SDMA0_HWID] = "SDMA0", 120 [SDMA1_HWID] = "SDMA1", 121 [SDMA2_HWID] = "SDMA2", 122 [SDMA3_HWID] = "SDMA3", 123 [ISP_HWID] = "ISP", 124 [DBGU_IO_HWID] = "DBGU_IO", 125 [DF_HWID] = "DF", 126 [CLKB_HWID] = "CLKB", 127 [FCH_HWID] = "FCH", 128 [DFX_DAP_HWID] = "DFX_DAP", 129 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 130 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 131 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 132 [L1IMU3_HWID] = "L1IMU3", 133 [L1IMU4_HWID] = "L1IMU4", 134 [L1IMU5_HWID] = "L1IMU5", 135 [L1IMU6_HWID] = "L1IMU6", 136 [L1IMU7_HWID] = "L1IMU7", 137 [L1IMU8_HWID] = "L1IMU8", 138 [L1IMU9_HWID] = "L1IMU9", 139 [L1IMU10_HWID] = "L1IMU10", 140 [L1IMU11_HWID] = "L1IMU11", 141 [L1IMU12_HWID] = "L1IMU12", 142 [L1IMU13_HWID] = "L1IMU13", 143 [L1IMU14_HWID] = "L1IMU14", 144 [L1IMU15_HWID] = "L1IMU15", 145 [WAFLC_HWID] = "WAFLC", 146 [FCH_USB_PD_HWID] = "FCH_USB_PD", 147 [PCIE_HWID] = "PCIE", 148 [PCS_HWID] = "PCS", 149 [DDCL_HWID] = "DDCL", 150 [SST_HWID] = "SST", 151 [IOAGR_HWID] = "IOAGR", 152 [NBIF_HWID] = "NBIF", 153 [IOAPIC_HWID] = "IOAPIC", 154 [SYSTEMHUB_HWID] = "SYSTEMHUB", 155 [NTBCCP_HWID] = "NTBCCP", 156 [UMC_HWID] = "UMC", 157 [SATA_HWID] = "SATA", 158 [USB_HWID] = "USB", 159 [CCXSEC_HWID] = "CCXSEC", 160 [XGMI_HWID] = "XGMI", 161 [XGBE_HWID] = "XGBE", 162 [MP0_HWID] = "MP0", 163 }; 164 165 static int hw_id_map[MAX_HWIP] = { 166 [GC_HWIP] = GC_HWID, 167 [HDP_HWIP] = HDP_HWID, 168 [SDMA0_HWIP] = SDMA0_HWID, 169 [SDMA1_HWIP] = SDMA1_HWID, 170 [SDMA2_HWIP] = SDMA2_HWID, 171 [SDMA3_HWIP] = SDMA3_HWID, 172 [MMHUB_HWIP] = MMHUB_HWID, 173 [ATHUB_HWIP] = ATHUB_HWID, 174 [NBIO_HWIP] = NBIF_HWID, 175 [MP0_HWIP] = MP0_HWID, 176 [MP1_HWIP] = MP1_HWID, 177 [UVD_HWIP] = UVD_HWID, 178 [VCE_HWIP] = VCE_HWID, 179 [DF_HWIP] = DF_HWID, 180 [DCE_HWIP] = DMU_HWID, 181 [OSSSYS_HWIP] = OSSSYS_HWID, 182 [SMUIO_HWIP] = SMUIO_HWID, 183 [PWR_HWIP] = PWR_HWID, 184 [NBIF_HWIP] = NBIF_HWID, 185 [THM_HWIP] = THM_HWID, 186 [CLK_HWIP] = CLKA_HWID, 187 [UMC_HWIP] = UMC_HWID, 188 [XGMI_HWIP] = XGMI_HWID, 189 [DCI_HWIP] = DCI_HWID, 190 }; 191 192 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 193 { 194 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 195 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 196 197 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 198 adev->mman.discovery_tmr_size, false); 199 return 0; 200 } 201 202 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 203 { 204 const struct firmware *fw; 205 const char *fw_name; 206 int r; 207 208 switch (amdgpu_discovery) { 209 case 2: 210 fw_name = FIRMWARE_IP_DISCOVERY; 211 break; 212 default: 213 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 214 return -EINVAL; 215 } 216 217 r = request_firmware(&fw, fw_name, adev->dev); 218 if (r) { 219 dev_err(adev->dev, "can't load firmware \"%s\"\n", 220 fw_name); 221 return r; 222 } 223 224 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 225 release_firmware(fw); 226 227 return 0; 228 } 229 230 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 231 { 232 uint16_t checksum = 0; 233 int i; 234 235 for (i = 0; i < size; i++) 236 checksum += data[i]; 237 238 return checksum; 239 } 240 241 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 242 uint16_t expected) 243 { 244 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 245 } 246 247 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 248 { 249 struct binary_header *bhdr; 250 bhdr = (struct binary_header *)binary; 251 252 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 253 } 254 255 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 256 { 257 /* 258 * So far, apply this quirk only on those Navy Flounder boards which 259 * have a bad harvest table of VCN config. 260 */ 261 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 262 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 263 switch (adev->pdev->revision) { 264 case 0xC1: 265 case 0xC2: 266 case 0xC3: 267 case 0xC5: 268 case 0xC7: 269 case 0xCF: 270 case 0xDF: 271 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 272 break; 273 default: 274 break; 275 } 276 } 277 } 278 279 static int amdgpu_discovery_init(struct amdgpu_device *adev) 280 { 281 struct table_info *info; 282 struct binary_header *bhdr; 283 uint16_t offset; 284 uint16_t size; 285 uint16_t checksum; 286 int r; 287 288 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 289 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 290 if (!adev->mman.discovery_bin) 291 return -ENOMEM; 292 293 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 294 if (r) { 295 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 296 r = -EINVAL; 297 goto out; 298 } 299 300 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 301 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 302 /* retry read ip discovery binary from file */ 303 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 304 if (r) { 305 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 306 r = -EINVAL; 307 goto out; 308 } 309 /* check the ip discovery binary signature */ 310 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 311 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 312 r = -EINVAL; 313 goto out; 314 } 315 } 316 317 bhdr = (struct binary_header *)adev->mman.discovery_bin; 318 319 offset = offsetof(struct binary_header, binary_checksum) + 320 sizeof(bhdr->binary_checksum); 321 size = le16_to_cpu(bhdr->binary_size) - offset; 322 checksum = le16_to_cpu(bhdr->binary_checksum); 323 324 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 325 size, checksum)) { 326 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 327 r = -EINVAL; 328 goto out; 329 } 330 331 info = &bhdr->table_list[IP_DISCOVERY]; 332 offset = le16_to_cpu(info->offset); 333 checksum = le16_to_cpu(info->checksum); 334 335 if (offset) { 336 struct ip_discovery_header *ihdr = 337 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 338 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 339 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 340 r = -EINVAL; 341 goto out; 342 } 343 344 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 345 le16_to_cpu(ihdr->size), checksum)) { 346 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 347 r = -EINVAL; 348 goto out; 349 } 350 } 351 352 info = &bhdr->table_list[GC]; 353 offset = le16_to_cpu(info->offset); 354 checksum = le16_to_cpu(info->checksum); 355 356 if (offset) { 357 struct gpu_info_header *ghdr = 358 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 359 360 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 361 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 362 r = -EINVAL; 363 goto out; 364 } 365 366 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 367 le32_to_cpu(ghdr->size), checksum)) { 368 dev_err(adev->dev, "invalid gc data table checksum\n"); 369 r = -EINVAL; 370 goto out; 371 } 372 } 373 374 info = &bhdr->table_list[HARVEST_INFO]; 375 offset = le16_to_cpu(info->offset); 376 checksum = le16_to_cpu(info->checksum); 377 378 if (offset) { 379 struct harvest_info_header *hhdr = 380 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 381 382 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 383 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 384 r = -EINVAL; 385 goto out; 386 } 387 388 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 389 sizeof(struct harvest_table), checksum)) { 390 dev_err(adev->dev, "invalid harvest data table checksum\n"); 391 r = -EINVAL; 392 goto out; 393 } 394 } 395 396 info = &bhdr->table_list[VCN_INFO]; 397 offset = le16_to_cpu(info->offset); 398 checksum = le16_to_cpu(info->checksum); 399 400 if (offset) { 401 struct vcn_info_header *vhdr = 402 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 403 404 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 405 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 406 r = -EINVAL; 407 goto out; 408 } 409 410 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 411 le32_to_cpu(vhdr->size_bytes), checksum)) { 412 dev_err(adev->dev, "invalid vcn data table checksum\n"); 413 r = -EINVAL; 414 goto out; 415 } 416 } 417 418 info = &bhdr->table_list[MALL_INFO]; 419 offset = le16_to_cpu(info->offset); 420 checksum = le16_to_cpu(info->checksum); 421 422 if (0 && offset) { 423 struct mall_info_header *mhdr = 424 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 425 426 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 427 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 428 r = -EINVAL; 429 goto out; 430 } 431 432 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 433 le32_to_cpu(mhdr->size_bytes), checksum)) { 434 dev_err(adev->dev, "invalid mall data table checksum\n"); 435 r = -EINVAL; 436 goto out; 437 } 438 } 439 440 return 0; 441 442 out: 443 kfree(adev->mman.discovery_bin); 444 adev->mman.discovery_bin = NULL; 445 446 return r; 447 } 448 449 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 450 451 void amdgpu_discovery_fini(struct amdgpu_device *adev) 452 { 453 amdgpu_discovery_sysfs_fini(adev); 454 kfree(adev->mman.discovery_bin); 455 adev->mman.discovery_bin = NULL; 456 } 457 458 static int amdgpu_discovery_validate_ip(const struct ip *ip) 459 { 460 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 461 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 462 ip->number_instance); 463 return -EINVAL; 464 } 465 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 466 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 467 le16_to_cpu(ip->hw_id)); 468 return -EINVAL; 469 } 470 471 return 0; 472 } 473 474 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 475 uint32_t *vcn_harvest_count) 476 { 477 struct binary_header *bhdr; 478 struct ip_discovery_header *ihdr; 479 struct die_header *dhdr; 480 struct ip *ip; 481 uint16_t die_offset, ip_offset, num_dies, num_ips; 482 int i, j; 483 484 bhdr = (struct binary_header *)adev->mman.discovery_bin; 485 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 486 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 487 num_dies = le16_to_cpu(ihdr->num_dies); 488 489 /* scan harvest bit of all IP data structures */ 490 for (i = 0; i < num_dies; i++) { 491 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 492 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 493 num_ips = le16_to_cpu(dhdr->num_ips); 494 ip_offset = die_offset + sizeof(*dhdr); 495 496 for (j = 0; j < num_ips; j++) { 497 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 498 499 if (amdgpu_discovery_validate_ip(ip)) 500 goto next_ip; 501 502 if (le16_to_cpu(ip->harvest) == 1) { 503 switch (le16_to_cpu(ip->hw_id)) { 504 case VCN_HWID: 505 (*vcn_harvest_count)++; 506 if (ip->number_instance == 0) 507 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 508 else 509 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 510 break; 511 case DMU_HWID: 512 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 513 break; 514 default: 515 break; 516 } 517 } 518 next_ip: 519 ip_offset += struct_size(ip, base_address, ip->num_base_address); 520 } 521 } 522 } 523 524 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 525 uint32_t *vcn_harvest_count, 526 uint32_t *umc_harvest_count) 527 { 528 struct binary_header *bhdr; 529 struct harvest_table *harvest_info; 530 u16 offset; 531 int i; 532 533 bhdr = (struct binary_header *)adev->mman.discovery_bin; 534 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 535 536 if (!offset) { 537 dev_err(adev->dev, "invalid harvest table offset\n"); 538 return; 539 } 540 541 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 542 543 for (i = 0; i < 32; i++) { 544 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 545 break; 546 547 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 548 case VCN_HWID: 549 (*vcn_harvest_count)++; 550 if (harvest_info->list[i].number_instance == 0) 551 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 552 else 553 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 554 break; 555 case DMU_HWID: 556 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 557 break; 558 case UMC_HWID: 559 (*umc_harvest_count)++; 560 break; 561 default: 562 break; 563 } 564 } 565 } 566 567 /* ================================================== */ 568 569 struct ip_hw_instance { 570 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 571 572 int hw_id; 573 u8 num_instance; 574 u8 major, minor, revision; 575 u8 harvest; 576 577 int num_base_addresses; 578 u32 base_addr[]; 579 }; 580 581 struct ip_hw_id { 582 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 583 int hw_id; 584 }; 585 586 struct ip_die_entry { 587 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 588 u16 num_ips; 589 }; 590 591 /* -------------------------------------------------- */ 592 593 struct ip_hw_instance_attr { 594 struct attribute attr; 595 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 596 }; 597 598 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 599 { 600 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 601 } 602 603 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 604 { 605 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 606 } 607 608 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 609 { 610 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 611 } 612 613 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 614 { 615 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 616 } 617 618 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 619 { 620 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 621 } 622 623 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 624 { 625 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 626 } 627 628 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 629 { 630 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 631 } 632 633 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 634 { 635 ssize_t res, at; 636 int ii; 637 638 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 639 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 640 */ 641 if (at + 12 > PAGE_SIZE) 642 break; 643 res = sysfs_emit_at(buf, at, "0x%08X\n", 644 ip_hw_instance->base_addr[ii]); 645 if (res <= 0) 646 break; 647 at += res; 648 } 649 650 return res < 0 ? res : at; 651 } 652 653 static struct ip_hw_instance_attr ip_hw_attr[] = { 654 __ATTR_RO(hw_id), 655 __ATTR_RO(num_instance), 656 __ATTR_RO(major), 657 __ATTR_RO(minor), 658 __ATTR_RO(revision), 659 __ATTR_RO(harvest), 660 __ATTR_RO(num_base_addresses), 661 __ATTR_RO(base_addr), 662 }; 663 664 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 665 ATTRIBUTE_GROUPS(ip_hw_instance); 666 667 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 668 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 669 670 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 671 struct attribute *attr, 672 char *buf) 673 { 674 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 675 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 676 677 if (!ip_hw_attr->show) 678 return -EIO; 679 680 return ip_hw_attr->show(ip_hw_instance, buf); 681 } 682 683 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 684 .show = ip_hw_instance_attr_show, 685 }; 686 687 static void ip_hw_instance_release(struct kobject *kobj) 688 { 689 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 690 691 kfree(ip_hw_instance); 692 } 693 694 static struct kobj_type ip_hw_instance_ktype = { 695 .release = ip_hw_instance_release, 696 .sysfs_ops = &ip_hw_instance_sysfs_ops, 697 .default_groups = ip_hw_instance_groups, 698 }; 699 700 /* -------------------------------------------------- */ 701 702 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 703 704 static void ip_hw_id_release(struct kobject *kobj) 705 { 706 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 707 708 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 709 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 710 kfree(ip_hw_id); 711 } 712 713 static struct kobj_type ip_hw_id_ktype = { 714 .release = ip_hw_id_release, 715 .sysfs_ops = &kobj_sysfs_ops, 716 }; 717 718 /* -------------------------------------------------- */ 719 720 static void die_kobj_release(struct kobject *kobj); 721 static void ip_disc_release(struct kobject *kobj); 722 723 struct ip_die_entry_attribute { 724 struct attribute attr; 725 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 726 }; 727 728 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 729 730 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 731 { 732 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 733 } 734 735 /* If there are more ip_die_entry attrs, other than the number of IPs, 736 * we can make this intro an array of attrs, and then initialize 737 * ip_die_entry_attrs in a loop. 738 */ 739 static struct ip_die_entry_attribute num_ips_attr = 740 __ATTR_RO(num_ips); 741 742 static struct attribute *ip_die_entry_attrs[] = { 743 &num_ips_attr.attr, 744 NULL, 745 }; 746 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 747 748 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 749 750 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 751 struct attribute *attr, 752 char *buf) 753 { 754 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 755 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 756 757 if (!ip_die_entry_attr->show) 758 return -EIO; 759 760 return ip_die_entry_attr->show(ip_die_entry, buf); 761 } 762 763 static void ip_die_entry_release(struct kobject *kobj) 764 { 765 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 766 767 if (!list_empty(&ip_die_entry->ip_kset.list)) 768 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 769 kfree(ip_die_entry); 770 } 771 772 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 773 .show = ip_die_entry_attr_show, 774 }; 775 776 static struct kobj_type ip_die_entry_ktype = { 777 .release = ip_die_entry_release, 778 .sysfs_ops = &ip_die_entry_sysfs_ops, 779 .default_groups = ip_die_entry_groups, 780 }; 781 782 static struct kobj_type die_kobj_ktype = { 783 .release = die_kobj_release, 784 .sysfs_ops = &kobj_sysfs_ops, 785 }; 786 787 static struct kobj_type ip_discovery_ktype = { 788 .release = ip_disc_release, 789 .sysfs_ops = &kobj_sysfs_ops, 790 }; 791 792 struct ip_discovery_top { 793 struct kobject kobj; /* ip_discovery/ */ 794 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 795 struct amdgpu_device *adev; 796 }; 797 798 static void die_kobj_release(struct kobject *kobj) 799 { 800 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 801 struct ip_discovery_top, 802 die_kset); 803 if (!list_empty(&ip_top->die_kset.list)) 804 DRM_ERROR("ip_top->die_kset is not empty"); 805 } 806 807 static void ip_disc_release(struct kobject *kobj) 808 { 809 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 810 kobj); 811 struct amdgpu_device *adev = ip_top->adev; 812 813 adev->ip_top = NULL; 814 kfree(ip_top); 815 } 816 817 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 818 struct ip_die_entry *ip_die_entry, 819 const size_t _ip_offset, const int num_ips) 820 { 821 int ii, jj, kk, res; 822 823 DRM_DEBUG("num_ips:%d", num_ips); 824 825 /* Find all IPs of a given HW ID, and add their instance to 826 * #die/#hw_id/#instance/<attributes> 827 */ 828 for (ii = 0; ii < HW_ID_MAX; ii++) { 829 struct ip_hw_id *ip_hw_id = NULL; 830 size_t ip_offset = _ip_offset; 831 832 for (jj = 0; jj < num_ips; jj++) { 833 struct ip *ip; 834 struct ip_hw_instance *ip_hw_instance; 835 836 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 837 if (amdgpu_discovery_validate_ip(ip) || 838 le16_to_cpu(ip->hw_id) != ii) 839 goto next_ip; 840 841 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 842 843 /* We have a hw_id match; register the hw 844 * block if not yet registered. 845 */ 846 if (!ip_hw_id) { 847 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 848 if (!ip_hw_id) 849 return -ENOMEM; 850 ip_hw_id->hw_id = ii; 851 852 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 853 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 854 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 855 res = kset_register(&ip_hw_id->hw_id_kset); 856 if (res) { 857 DRM_ERROR("Couldn't register ip_hw_id kset"); 858 kfree(ip_hw_id); 859 return res; 860 } 861 if (hw_id_names[ii]) { 862 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 863 &ip_hw_id->hw_id_kset.kobj, 864 hw_id_names[ii]); 865 if (res) { 866 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 867 hw_id_names[ii], 868 kobject_name(&ip_die_entry->ip_kset.kobj)); 869 } 870 } 871 } 872 873 /* Now register its instance. 874 */ 875 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 876 base_addr, 877 ip->num_base_address), 878 GFP_KERNEL); 879 if (!ip_hw_instance) { 880 DRM_ERROR("no memory for ip_hw_instance"); 881 return -ENOMEM; 882 } 883 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 884 ip_hw_instance->num_instance = ip->number_instance; 885 ip_hw_instance->major = ip->major; 886 ip_hw_instance->minor = ip->minor; 887 ip_hw_instance->revision = ip->revision; 888 ip_hw_instance->harvest = ip->harvest; 889 ip_hw_instance->num_base_addresses = ip->num_base_address; 890 891 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 892 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 893 894 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 895 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 896 res = kobject_add(&ip_hw_instance->kobj, NULL, 897 "%d", ip_hw_instance->num_instance); 898 next_ip: 899 ip_offset += struct_size(ip, base_address, ip->num_base_address); 900 } 901 } 902 903 return 0; 904 } 905 906 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 907 { 908 struct binary_header *bhdr; 909 struct ip_discovery_header *ihdr; 910 struct die_header *dhdr; 911 struct kset *die_kset = &adev->ip_top->die_kset; 912 u16 num_dies, die_offset, num_ips; 913 size_t ip_offset; 914 int ii, res; 915 916 bhdr = (struct binary_header *)adev->mman.discovery_bin; 917 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 918 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 919 num_dies = le16_to_cpu(ihdr->num_dies); 920 921 DRM_DEBUG("number of dies: %d\n", num_dies); 922 923 for (ii = 0; ii < num_dies; ii++) { 924 struct ip_die_entry *ip_die_entry; 925 926 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 927 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 928 num_ips = le16_to_cpu(dhdr->num_ips); 929 ip_offset = die_offset + sizeof(*dhdr); 930 931 /* Add the die to the kset. 932 * 933 * dhdr->die_id == ii, which was checked in 934 * amdgpu_discovery_reg_base_init(). 935 */ 936 937 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 938 if (!ip_die_entry) 939 return -ENOMEM; 940 941 ip_die_entry->num_ips = num_ips; 942 943 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 944 ip_die_entry->ip_kset.kobj.kset = die_kset; 945 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 946 res = kset_register(&ip_die_entry->ip_kset); 947 if (res) { 948 DRM_ERROR("Couldn't register ip_die_entry kset"); 949 kfree(ip_die_entry); 950 return res; 951 } 952 953 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 954 } 955 956 return 0; 957 } 958 959 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 960 { 961 struct kset *die_kset; 962 int res, ii; 963 964 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 965 if (!adev->ip_top) 966 return -ENOMEM; 967 968 adev->ip_top->adev = adev; 969 970 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 971 &adev->dev->kobj, "ip_discovery"); 972 if (res) { 973 DRM_ERROR("Couldn't init and add ip_discovery/"); 974 goto Err; 975 } 976 977 die_kset = &adev->ip_top->die_kset; 978 kobject_set_name(&die_kset->kobj, "%s", "die"); 979 die_kset->kobj.parent = &adev->ip_top->kobj; 980 die_kset->kobj.ktype = &die_kobj_ktype; 981 res = kset_register(&adev->ip_top->die_kset); 982 if (res) { 983 DRM_ERROR("Couldn't register die_kset"); 984 goto Err; 985 } 986 987 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 988 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 989 ip_hw_instance_attrs[ii] = NULL; 990 991 res = amdgpu_discovery_sysfs_recurse(adev); 992 993 return res; 994 Err: 995 kobject_put(&adev->ip_top->kobj); 996 return res; 997 } 998 999 /* -------------------------------------------------- */ 1000 1001 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1002 1003 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1004 { 1005 struct list_head *el, *tmp; 1006 struct kset *hw_id_kset; 1007 1008 hw_id_kset = &ip_hw_id->hw_id_kset; 1009 spin_lock(&hw_id_kset->list_lock); 1010 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1011 list_del_init(el); 1012 spin_unlock(&hw_id_kset->list_lock); 1013 /* kobject is embedded in ip_hw_instance */ 1014 kobject_put(list_to_kobj(el)); 1015 spin_lock(&hw_id_kset->list_lock); 1016 } 1017 spin_unlock(&hw_id_kset->list_lock); 1018 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1019 } 1020 1021 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1022 { 1023 struct list_head *el, *tmp; 1024 struct kset *ip_kset; 1025 1026 ip_kset = &ip_die_entry->ip_kset; 1027 spin_lock(&ip_kset->list_lock); 1028 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1029 list_del_init(el); 1030 spin_unlock(&ip_kset->list_lock); 1031 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1032 spin_lock(&ip_kset->list_lock); 1033 } 1034 spin_unlock(&ip_kset->list_lock); 1035 kobject_put(&ip_die_entry->ip_kset.kobj); 1036 } 1037 1038 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1039 { 1040 struct list_head *el, *tmp; 1041 struct kset *die_kset; 1042 1043 die_kset = &adev->ip_top->die_kset; 1044 spin_lock(&die_kset->list_lock); 1045 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1046 list_del_init(el); 1047 spin_unlock(&die_kset->list_lock); 1048 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1049 spin_lock(&die_kset->list_lock); 1050 } 1051 spin_unlock(&die_kset->list_lock); 1052 kobject_put(&adev->ip_top->die_kset.kobj); 1053 kobject_put(&adev->ip_top->kobj); 1054 } 1055 1056 /* ================================================== */ 1057 1058 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1059 { 1060 struct binary_header *bhdr; 1061 struct ip_discovery_header *ihdr; 1062 struct die_header *dhdr; 1063 struct ip *ip; 1064 uint16_t die_offset; 1065 uint16_t ip_offset; 1066 uint16_t num_dies; 1067 uint16_t num_ips; 1068 uint8_t num_base_address; 1069 int hw_ip; 1070 int i, j, k; 1071 int r; 1072 1073 r = amdgpu_discovery_init(adev); 1074 if (r) { 1075 DRM_ERROR("amdgpu_discovery_init failed\n"); 1076 return r; 1077 } 1078 1079 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1080 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1081 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1082 num_dies = le16_to_cpu(ihdr->num_dies); 1083 1084 DRM_DEBUG("number of dies: %d\n", num_dies); 1085 1086 for (i = 0; i < num_dies; i++) { 1087 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1088 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1089 num_ips = le16_to_cpu(dhdr->num_ips); 1090 ip_offset = die_offset + sizeof(*dhdr); 1091 1092 if (le16_to_cpu(dhdr->die_id) != i) { 1093 DRM_ERROR("invalid die id %d, expected %d\n", 1094 le16_to_cpu(dhdr->die_id), i); 1095 return -EINVAL; 1096 } 1097 1098 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1099 le16_to_cpu(dhdr->die_id), num_ips); 1100 1101 for (j = 0; j < num_ips; j++) { 1102 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1103 1104 if (amdgpu_discovery_validate_ip(ip)) 1105 goto next_ip; 1106 1107 num_base_address = ip->num_base_address; 1108 1109 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1110 hw_id_names[le16_to_cpu(ip->hw_id)], 1111 le16_to_cpu(ip->hw_id), 1112 ip->number_instance, 1113 ip->major, ip->minor, 1114 ip->revision); 1115 1116 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1117 /* Bit [5:0]: original revision value 1118 * Bit [7:6]: en/decode capability: 1119 * 0b00 : VCN function normally 1120 * 0b10 : encode is disabled 1121 * 0b01 : decode is disabled 1122 */ 1123 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1124 ip->revision & 0xc0; 1125 ip->revision &= ~0xc0; 1126 adev->vcn.num_vcn_inst++; 1127 } 1128 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1129 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1130 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1131 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 1132 adev->sdma.num_instances++; 1133 1134 if (le16_to_cpu(ip->hw_id) == UMC_HWID) 1135 adev->gmc.num_umc++; 1136 1137 for (k = 0; k < num_base_address; k++) { 1138 /* 1139 * convert the endianness of base addresses in place, 1140 * so that we don't need to convert them when accessing adev->reg_offset. 1141 */ 1142 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1143 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1144 } 1145 1146 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1147 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 1148 DRM_DEBUG("set register base offset for %s\n", 1149 hw_id_names[le16_to_cpu(ip->hw_id)]); 1150 adev->reg_offset[hw_ip][ip->number_instance] = 1151 ip->base_address; 1152 /* Instance support is somewhat inconsistent. 1153 * SDMA is a good example. Sienna cichlid has 4 total 1154 * SDMA instances, each enumerated separately (HWIDs 1155 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1156 * but they are enumerated as multiple instances of the 1157 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1158 * example. On most chips there are multiple instances 1159 * with the same HWID. 1160 */ 1161 adev->ip_versions[hw_ip][ip->number_instance] = 1162 IP_VERSION(ip->major, ip->minor, ip->revision); 1163 } 1164 } 1165 1166 next_ip: 1167 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1168 } 1169 } 1170 1171 amdgpu_discovery_sysfs_init(adev); 1172 1173 return 0; 1174 } 1175 1176 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1177 int *major, int *minor, int *revision) 1178 { 1179 struct binary_header *bhdr; 1180 struct ip_discovery_header *ihdr; 1181 struct die_header *dhdr; 1182 struct ip *ip; 1183 uint16_t die_offset; 1184 uint16_t ip_offset; 1185 uint16_t num_dies; 1186 uint16_t num_ips; 1187 int i, j; 1188 1189 if (!adev->mman.discovery_bin) { 1190 DRM_ERROR("ip discovery uninitialized\n"); 1191 return -EINVAL; 1192 } 1193 1194 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1195 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1196 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1197 num_dies = le16_to_cpu(ihdr->num_dies); 1198 1199 for (i = 0; i < num_dies; i++) { 1200 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1201 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1202 num_ips = le16_to_cpu(dhdr->num_ips); 1203 ip_offset = die_offset + sizeof(*dhdr); 1204 1205 for (j = 0; j < num_ips; j++) { 1206 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1207 1208 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1209 if (major) 1210 *major = ip->major; 1211 if (minor) 1212 *minor = ip->minor; 1213 if (revision) 1214 *revision = ip->revision; 1215 return 0; 1216 } 1217 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1218 } 1219 } 1220 1221 return -EINVAL; 1222 } 1223 1224 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1225 { 1226 int vcn_harvest_count = 0; 1227 int umc_harvest_count = 0; 1228 1229 /* 1230 * Harvest table does not fit Navi1x and legacy GPUs, 1231 * so read harvest bit per IP data structure to set 1232 * harvest configuration. 1233 */ 1234 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) { 1235 if ((adev->pdev->device == 0x731E && 1236 (adev->pdev->revision == 0xC6 || 1237 adev->pdev->revision == 0xC7)) || 1238 (adev->pdev->device == 0x7340 && 1239 adev->pdev->revision == 0xC9) || 1240 (adev->pdev->device == 0x7360 && 1241 adev->pdev->revision == 0xC7)) 1242 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1243 &vcn_harvest_count); 1244 } else { 1245 amdgpu_discovery_read_from_harvest_table(adev, 1246 &vcn_harvest_count, 1247 &umc_harvest_count); 1248 } 1249 1250 amdgpu_discovery_harvest_config_quirk(adev); 1251 1252 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1253 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1254 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1255 } 1256 1257 if (umc_harvest_count < adev->gmc.num_umc) { 1258 adev->gmc.num_umc -= umc_harvest_count; 1259 } 1260 } 1261 1262 union gc_info { 1263 struct gc_info_v1_0 v1; 1264 struct gc_info_v1_1 v1_1; 1265 struct gc_info_v1_2 v1_2; 1266 struct gc_info_v2_0 v2; 1267 }; 1268 1269 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1270 { 1271 struct binary_header *bhdr; 1272 union gc_info *gc_info; 1273 u16 offset; 1274 1275 if (!adev->mman.discovery_bin) { 1276 DRM_ERROR("ip discovery uninitialized\n"); 1277 return -EINVAL; 1278 } 1279 1280 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1281 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1282 1283 if (!offset) 1284 return 0; 1285 1286 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1287 1288 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1289 case 1: 1290 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1291 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1292 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1293 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1294 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1295 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1296 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1297 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1298 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1299 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1300 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1301 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1302 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1303 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1304 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1305 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1306 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1307 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1308 if (gc_info->v1.header.version_minor >= 1) { 1309 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1310 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1311 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1312 } 1313 if (gc_info->v1.header.version_minor >= 2) { 1314 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1315 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1316 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1317 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1318 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1319 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1320 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1321 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1322 } 1323 break; 1324 case 2: 1325 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1326 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1327 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1328 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1329 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1330 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1331 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1332 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1333 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1334 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1335 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1336 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1337 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1338 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1339 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1340 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1341 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1342 break; 1343 default: 1344 dev_err(adev->dev, 1345 "Unhandled GC info table %d.%d\n", 1346 le16_to_cpu(gc_info->v1.header.version_major), 1347 le16_to_cpu(gc_info->v1.header.version_minor)); 1348 return -EINVAL; 1349 } 1350 return 0; 1351 } 1352 1353 union mall_info { 1354 struct mall_info_v1_0 v1; 1355 }; 1356 1357 int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1358 { 1359 struct binary_header *bhdr; 1360 union mall_info *mall_info; 1361 u32 u, mall_size_per_umc, m_s_present, half_use; 1362 u64 mall_size; 1363 u16 offset; 1364 1365 if (!adev->mman.discovery_bin) { 1366 DRM_ERROR("ip discovery uninitialized\n"); 1367 return -EINVAL; 1368 } 1369 1370 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1371 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1372 1373 if (!offset) 1374 return 0; 1375 1376 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1377 1378 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1379 case 1: 1380 mall_size = 0; 1381 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1382 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1383 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1384 for (u = 0; u < adev->gmc.num_umc; u++) { 1385 if (m_s_present & (1 << u)) 1386 mall_size += mall_size_per_umc * 2; 1387 else if (half_use & (1 << u)) 1388 mall_size += mall_size_per_umc / 2; 1389 else 1390 mall_size += mall_size_per_umc; 1391 } 1392 adev->gmc.mall_size = mall_size; 1393 break; 1394 default: 1395 dev_err(adev->dev, 1396 "Unhandled MALL info table %d.%d\n", 1397 le16_to_cpu(mall_info->v1.header.version_major), 1398 le16_to_cpu(mall_info->v1.header.version_minor)); 1399 return -EINVAL; 1400 } 1401 return 0; 1402 } 1403 1404 union vcn_info { 1405 struct vcn_info_v1_0 v1; 1406 }; 1407 1408 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1409 { 1410 struct binary_header *bhdr; 1411 union vcn_info *vcn_info; 1412 u16 offset; 1413 int v; 1414 1415 if (!adev->mman.discovery_bin) { 1416 DRM_ERROR("ip discovery uninitialized\n"); 1417 return -EINVAL; 1418 } 1419 1420 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1421 dev_err(adev->dev, "invalid vcn instances\n"); 1422 return -EINVAL; 1423 } 1424 1425 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1426 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1427 1428 if (!offset) 1429 return 0; 1430 1431 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1432 1433 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1434 case 1: 1435 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1436 adev->vcn.vcn_codec_disable_mask[v] = 1437 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1438 } 1439 break; 1440 default: 1441 dev_err(adev->dev, 1442 "Unhandled VCN info table %d.%d\n", 1443 le16_to_cpu(vcn_info->v1.header.version_major), 1444 le16_to_cpu(vcn_info->v1.header.version_minor)); 1445 return -EINVAL; 1446 } 1447 return 0; 1448 } 1449 1450 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1451 { 1452 /* what IP to use for this? */ 1453 switch (adev->ip_versions[GC_HWIP][0]) { 1454 case IP_VERSION(9, 0, 1): 1455 case IP_VERSION(9, 1, 0): 1456 case IP_VERSION(9, 2, 1): 1457 case IP_VERSION(9, 2, 2): 1458 case IP_VERSION(9, 3, 0): 1459 case IP_VERSION(9, 4, 0): 1460 case IP_VERSION(9, 4, 1): 1461 case IP_VERSION(9, 4, 2): 1462 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1463 break; 1464 case IP_VERSION(10, 1, 10): 1465 case IP_VERSION(10, 1, 1): 1466 case IP_VERSION(10, 1, 2): 1467 case IP_VERSION(10, 1, 3): 1468 case IP_VERSION(10, 1, 4): 1469 case IP_VERSION(10, 3, 0): 1470 case IP_VERSION(10, 3, 1): 1471 case IP_VERSION(10, 3, 2): 1472 case IP_VERSION(10, 3, 3): 1473 case IP_VERSION(10, 3, 4): 1474 case IP_VERSION(10, 3, 5): 1475 case IP_VERSION(10, 3, 6): 1476 case IP_VERSION(10, 3, 7): 1477 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1478 break; 1479 case IP_VERSION(11, 0, 0): 1480 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1481 break; 1482 default: 1483 dev_err(adev->dev, 1484 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1485 adev->ip_versions[GC_HWIP][0]); 1486 return -EINVAL; 1487 } 1488 return 0; 1489 } 1490 1491 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1492 { 1493 /* use GC or MMHUB IP version */ 1494 switch (adev->ip_versions[GC_HWIP][0]) { 1495 case IP_VERSION(9, 0, 1): 1496 case IP_VERSION(9, 1, 0): 1497 case IP_VERSION(9, 2, 1): 1498 case IP_VERSION(9, 2, 2): 1499 case IP_VERSION(9, 3, 0): 1500 case IP_VERSION(9, 4, 0): 1501 case IP_VERSION(9, 4, 1): 1502 case IP_VERSION(9, 4, 2): 1503 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1504 break; 1505 case IP_VERSION(10, 1, 10): 1506 case IP_VERSION(10, 1, 1): 1507 case IP_VERSION(10, 1, 2): 1508 case IP_VERSION(10, 1, 3): 1509 case IP_VERSION(10, 1, 4): 1510 case IP_VERSION(10, 3, 0): 1511 case IP_VERSION(10, 3, 1): 1512 case IP_VERSION(10, 3, 2): 1513 case IP_VERSION(10, 3, 3): 1514 case IP_VERSION(10, 3, 4): 1515 case IP_VERSION(10, 3, 5): 1516 case IP_VERSION(10, 3, 6): 1517 case IP_VERSION(10, 3, 7): 1518 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1519 break; 1520 case IP_VERSION(11, 0, 0): 1521 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1522 break; 1523 default: 1524 dev_err(adev->dev, 1525 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1526 adev->ip_versions[GC_HWIP][0]); 1527 return -EINVAL; 1528 } 1529 return 0; 1530 } 1531 1532 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1533 { 1534 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1535 case IP_VERSION(4, 0, 0): 1536 case IP_VERSION(4, 0, 1): 1537 case IP_VERSION(4, 1, 0): 1538 case IP_VERSION(4, 1, 1): 1539 case IP_VERSION(4, 3, 0): 1540 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1541 break; 1542 case IP_VERSION(4, 2, 0): 1543 case IP_VERSION(4, 2, 1): 1544 case IP_VERSION(4, 4, 0): 1545 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1546 break; 1547 case IP_VERSION(5, 0, 0): 1548 case IP_VERSION(5, 0, 1): 1549 case IP_VERSION(5, 0, 2): 1550 case IP_VERSION(5, 0, 3): 1551 case IP_VERSION(5, 2, 0): 1552 case IP_VERSION(5, 2, 1): 1553 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1554 break; 1555 case IP_VERSION(6, 0, 0): 1556 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1557 break; 1558 default: 1559 dev_err(adev->dev, 1560 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1561 adev->ip_versions[OSSSYS_HWIP][0]); 1562 return -EINVAL; 1563 } 1564 return 0; 1565 } 1566 1567 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1568 { 1569 switch (adev->ip_versions[MP0_HWIP][0]) { 1570 case IP_VERSION(9, 0, 0): 1571 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1572 break; 1573 case IP_VERSION(10, 0, 0): 1574 case IP_VERSION(10, 0, 1): 1575 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1576 break; 1577 case IP_VERSION(11, 0, 0): 1578 case IP_VERSION(11, 0, 2): 1579 case IP_VERSION(11, 0, 4): 1580 case IP_VERSION(11, 0, 5): 1581 case IP_VERSION(11, 0, 9): 1582 case IP_VERSION(11, 0, 7): 1583 case IP_VERSION(11, 0, 11): 1584 case IP_VERSION(11, 0, 12): 1585 case IP_VERSION(11, 0, 13): 1586 case IP_VERSION(11, 5, 0): 1587 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1588 break; 1589 case IP_VERSION(11, 0, 8): 1590 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1591 break; 1592 case IP_VERSION(11, 0, 3): 1593 case IP_VERSION(12, 0, 1): 1594 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1595 break; 1596 case IP_VERSION(13, 0, 0): 1597 case IP_VERSION(13, 0, 1): 1598 case IP_VERSION(13, 0, 2): 1599 case IP_VERSION(13, 0, 3): 1600 case IP_VERSION(13, 0, 5): 1601 case IP_VERSION(13, 0, 8): 1602 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1603 break; 1604 default: 1605 dev_err(adev->dev, 1606 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1607 adev->ip_versions[MP0_HWIP][0]); 1608 return -EINVAL; 1609 } 1610 return 0; 1611 } 1612 1613 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1614 { 1615 switch (adev->ip_versions[MP1_HWIP][0]) { 1616 case IP_VERSION(9, 0, 0): 1617 case IP_VERSION(10, 0, 0): 1618 case IP_VERSION(10, 0, 1): 1619 case IP_VERSION(11, 0, 2): 1620 if (adev->asic_type == CHIP_ARCTURUS) 1621 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1622 else 1623 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1624 break; 1625 case IP_VERSION(11, 0, 0): 1626 case IP_VERSION(11, 0, 5): 1627 case IP_VERSION(11, 0, 9): 1628 case IP_VERSION(11, 0, 7): 1629 case IP_VERSION(11, 0, 8): 1630 case IP_VERSION(11, 0, 11): 1631 case IP_VERSION(11, 0, 12): 1632 case IP_VERSION(11, 0, 13): 1633 case IP_VERSION(11, 5, 0): 1634 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1635 break; 1636 case IP_VERSION(12, 0, 0): 1637 case IP_VERSION(12, 0, 1): 1638 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1639 break; 1640 case IP_VERSION(13, 0, 0): 1641 case IP_VERSION(13, 0, 1): 1642 case IP_VERSION(13, 0, 2): 1643 case IP_VERSION(13, 0, 3): 1644 case IP_VERSION(13, 0, 5): 1645 case IP_VERSION(13, 0, 8): 1646 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1647 break; 1648 default: 1649 dev_err(adev->dev, 1650 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1651 adev->ip_versions[MP1_HWIP][0]); 1652 return -EINVAL; 1653 } 1654 return 0; 1655 } 1656 1657 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1658 { 1659 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 1660 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1661 return 0; 1662 } 1663 1664 if (!amdgpu_device_has_dc_support(adev)) 1665 return 0; 1666 1667 #if defined(CONFIG_DRM_AMD_DC) 1668 if (adev->ip_versions[DCE_HWIP][0]) { 1669 switch (adev->ip_versions[DCE_HWIP][0]) { 1670 case IP_VERSION(1, 0, 0): 1671 case IP_VERSION(1, 0, 1): 1672 case IP_VERSION(2, 0, 2): 1673 case IP_VERSION(2, 0, 0): 1674 case IP_VERSION(2, 0, 3): 1675 case IP_VERSION(2, 1, 0): 1676 case IP_VERSION(3, 0, 0): 1677 case IP_VERSION(3, 0, 2): 1678 case IP_VERSION(3, 0, 3): 1679 case IP_VERSION(3, 0, 1): 1680 case IP_VERSION(3, 1, 2): 1681 case IP_VERSION(3, 1, 3): 1682 case IP_VERSION(3, 1, 5): 1683 case IP_VERSION(3, 1, 6): 1684 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1685 break; 1686 default: 1687 dev_err(adev->dev, 1688 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1689 adev->ip_versions[DCE_HWIP][0]); 1690 return -EINVAL; 1691 } 1692 } else if (adev->ip_versions[DCI_HWIP][0]) { 1693 switch (adev->ip_versions[DCI_HWIP][0]) { 1694 case IP_VERSION(12, 0, 0): 1695 case IP_VERSION(12, 0, 1): 1696 case IP_VERSION(12, 1, 0): 1697 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1698 break; 1699 default: 1700 dev_err(adev->dev, 1701 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1702 adev->ip_versions[DCI_HWIP][0]); 1703 return -EINVAL; 1704 } 1705 } 1706 #endif 1707 return 0; 1708 } 1709 1710 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1711 { 1712 switch (adev->ip_versions[GC_HWIP][0]) { 1713 case IP_VERSION(9, 0, 1): 1714 case IP_VERSION(9, 1, 0): 1715 case IP_VERSION(9, 2, 1): 1716 case IP_VERSION(9, 2, 2): 1717 case IP_VERSION(9, 3, 0): 1718 case IP_VERSION(9, 4, 0): 1719 case IP_VERSION(9, 4, 1): 1720 case IP_VERSION(9, 4, 2): 1721 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1722 break; 1723 case IP_VERSION(10, 1, 10): 1724 case IP_VERSION(10, 1, 2): 1725 case IP_VERSION(10, 1, 1): 1726 case IP_VERSION(10, 1, 3): 1727 case IP_VERSION(10, 1, 4): 1728 case IP_VERSION(10, 3, 0): 1729 case IP_VERSION(10, 3, 2): 1730 case IP_VERSION(10, 3, 1): 1731 case IP_VERSION(10, 3, 4): 1732 case IP_VERSION(10, 3, 5): 1733 case IP_VERSION(10, 3, 6): 1734 case IP_VERSION(10, 3, 3): 1735 case IP_VERSION(10, 3, 7): 1736 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1737 break; 1738 case IP_VERSION(11, 0, 0): 1739 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1740 break; 1741 default: 1742 dev_err(adev->dev, 1743 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1744 adev->ip_versions[GC_HWIP][0]); 1745 return -EINVAL; 1746 } 1747 return 0; 1748 } 1749 1750 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1751 { 1752 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1753 case IP_VERSION(4, 0, 0): 1754 case IP_VERSION(4, 0, 1): 1755 case IP_VERSION(4, 1, 0): 1756 case IP_VERSION(4, 1, 1): 1757 case IP_VERSION(4, 1, 2): 1758 case IP_VERSION(4, 2, 0): 1759 case IP_VERSION(4, 2, 2): 1760 case IP_VERSION(4, 4, 0): 1761 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1762 break; 1763 case IP_VERSION(5, 0, 0): 1764 case IP_VERSION(5, 0, 1): 1765 case IP_VERSION(5, 0, 2): 1766 case IP_VERSION(5, 0, 5): 1767 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1768 break; 1769 case IP_VERSION(5, 2, 0): 1770 case IP_VERSION(5, 2, 2): 1771 case IP_VERSION(5, 2, 4): 1772 case IP_VERSION(5, 2, 5): 1773 case IP_VERSION(5, 2, 6): 1774 case IP_VERSION(5, 2, 3): 1775 case IP_VERSION(5, 2, 1): 1776 case IP_VERSION(5, 2, 7): 1777 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1778 break; 1779 case IP_VERSION(6, 0, 0): 1780 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1781 break; 1782 default: 1783 dev_err(adev->dev, 1784 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1785 adev->ip_versions[SDMA0_HWIP][0]); 1786 return -EINVAL; 1787 } 1788 return 0; 1789 } 1790 1791 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1792 { 1793 if (adev->ip_versions[VCE_HWIP][0]) { 1794 switch (adev->ip_versions[UVD_HWIP][0]) { 1795 case IP_VERSION(7, 0, 0): 1796 case IP_VERSION(7, 2, 0): 1797 /* UVD is not supported on vega20 SR-IOV */ 1798 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1799 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1800 break; 1801 default: 1802 dev_err(adev->dev, 1803 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1804 adev->ip_versions[UVD_HWIP][0]); 1805 return -EINVAL; 1806 } 1807 switch (adev->ip_versions[VCE_HWIP][0]) { 1808 case IP_VERSION(4, 0, 0): 1809 case IP_VERSION(4, 1, 0): 1810 /* VCE is not supported on vega20 SR-IOV */ 1811 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1812 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1813 break; 1814 default: 1815 dev_err(adev->dev, 1816 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1817 adev->ip_versions[VCE_HWIP][0]); 1818 return -EINVAL; 1819 } 1820 } else { 1821 switch (adev->ip_versions[UVD_HWIP][0]) { 1822 case IP_VERSION(1, 0, 0): 1823 case IP_VERSION(1, 0, 1): 1824 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1825 break; 1826 case IP_VERSION(2, 0, 0): 1827 case IP_VERSION(2, 0, 2): 1828 case IP_VERSION(2, 2, 0): 1829 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1830 if (!amdgpu_sriov_vf(adev)) 1831 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1832 break; 1833 case IP_VERSION(2, 0, 3): 1834 break; 1835 case IP_VERSION(2, 5, 0): 1836 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1837 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1838 break; 1839 case IP_VERSION(2, 6, 0): 1840 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1841 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1842 break; 1843 case IP_VERSION(3, 0, 0): 1844 case IP_VERSION(3, 0, 16): 1845 case IP_VERSION(3, 1, 1): 1846 case IP_VERSION(3, 1, 2): 1847 case IP_VERSION(3, 0, 2): 1848 case IP_VERSION(3, 0, 192): 1849 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1850 if (!amdgpu_sriov_vf(adev)) 1851 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1852 break; 1853 case IP_VERSION(3, 0, 33): 1854 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1855 break; 1856 default: 1857 dev_err(adev->dev, 1858 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1859 adev->ip_versions[UVD_HWIP][0]); 1860 return -EINVAL; 1861 } 1862 } 1863 return 0; 1864 } 1865 1866 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1867 { 1868 switch (adev->ip_versions[GC_HWIP][0]) { 1869 case IP_VERSION(10, 1, 10): 1870 case IP_VERSION(10, 1, 1): 1871 case IP_VERSION(10, 1, 2): 1872 case IP_VERSION(10, 1, 3): 1873 case IP_VERSION(10, 1, 4): 1874 case IP_VERSION(10, 3, 0): 1875 case IP_VERSION(10, 3, 1): 1876 case IP_VERSION(10, 3, 2): 1877 case IP_VERSION(10, 3, 3): 1878 case IP_VERSION(10, 3, 4): 1879 case IP_VERSION(10, 3, 5): 1880 case IP_VERSION(10, 3, 6): 1881 if (amdgpu_mes) { 1882 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1883 adev->enable_mes = true; 1884 if (amdgpu_mes_kiq) 1885 adev->enable_mes_kiq = true; 1886 } 1887 break; 1888 case IP_VERSION(11, 0, 0): 1889 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 1890 adev->enable_mes = true; 1891 adev->enable_mes_kiq = true; 1892 break; 1893 default: 1894 break; 1895 } 1896 return 0; 1897 } 1898 1899 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1900 { 1901 int r; 1902 1903 switch (adev->asic_type) { 1904 case CHIP_VEGA10: 1905 vega10_reg_base_init(adev); 1906 adev->sdma.num_instances = 2; 1907 adev->gmc.num_umc = 4; 1908 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1909 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1910 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1911 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1912 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1913 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1914 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1915 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1916 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1917 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1918 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1919 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1920 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1921 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1922 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1923 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1924 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1925 break; 1926 case CHIP_VEGA12: 1927 vega10_reg_base_init(adev); 1928 adev->sdma.num_instances = 2; 1929 adev->gmc.num_umc = 4; 1930 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1931 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1932 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1933 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1934 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1935 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1936 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1937 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1938 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1939 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1940 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1941 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1942 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1943 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1944 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1945 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1946 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1947 break; 1948 case CHIP_RAVEN: 1949 vega10_reg_base_init(adev); 1950 adev->sdma.num_instances = 1; 1951 adev->vcn.num_vcn_inst = 1; 1952 adev->gmc.num_umc = 2; 1953 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1954 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1955 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1956 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1957 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1958 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1959 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1960 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1961 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1962 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1963 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1964 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1965 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1966 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1967 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1968 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1969 } else { 1970 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1971 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1972 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1973 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1974 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1975 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1976 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1977 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1978 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1979 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1980 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1981 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1982 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1983 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1984 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1985 } 1986 break; 1987 case CHIP_VEGA20: 1988 vega20_reg_base_init(adev); 1989 adev->sdma.num_instances = 2; 1990 adev->gmc.num_umc = 8; 1991 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1992 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1993 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1994 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1995 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1996 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1997 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1998 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1999 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2000 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2001 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2002 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2003 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2004 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2005 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2006 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2007 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2008 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2009 break; 2010 case CHIP_ARCTURUS: 2011 arct_reg_base_init(adev); 2012 adev->sdma.num_instances = 8; 2013 adev->vcn.num_vcn_inst = 2; 2014 adev->gmc.num_umc = 8; 2015 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2016 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2017 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2018 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2019 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2020 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2021 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2022 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2023 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2024 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2025 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2026 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2027 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2028 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2029 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2030 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2031 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2032 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2033 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2034 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2035 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2036 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2037 break; 2038 case CHIP_ALDEBARAN: 2039 aldebaran_reg_base_init(adev); 2040 adev->sdma.num_instances = 5; 2041 adev->vcn.num_vcn_inst = 2; 2042 adev->gmc.num_umc = 4; 2043 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2044 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2045 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2046 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2047 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2048 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2049 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2050 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2051 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2052 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2053 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2054 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2055 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2056 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2057 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2058 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2059 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2060 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2061 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2062 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2063 break; 2064 default: 2065 r = amdgpu_discovery_reg_base_init(adev); 2066 if (r) 2067 return -EINVAL; 2068 2069 amdgpu_discovery_harvest_ip(adev); 2070 amdgpu_discovery_get_gfx_info(adev); 2071 amdgpu_discovery_get_mall_info(adev); 2072 amdgpu_discovery_get_vcn_info(adev); 2073 break; 2074 } 2075 2076 switch (adev->ip_versions[GC_HWIP][0]) { 2077 case IP_VERSION(9, 0, 1): 2078 case IP_VERSION(9, 2, 1): 2079 case IP_VERSION(9, 4, 0): 2080 case IP_VERSION(9, 4, 1): 2081 case IP_VERSION(9, 4, 2): 2082 adev->family = AMDGPU_FAMILY_AI; 2083 break; 2084 case IP_VERSION(9, 1, 0): 2085 case IP_VERSION(9, 2, 2): 2086 case IP_VERSION(9, 3, 0): 2087 adev->family = AMDGPU_FAMILY_RV; 2088 break; 2089 case IP_VERSION(10, 1, 10): 2090 case IP_VERSION(10, 1, 1): 2091 case IP_VERSION(10, 1, 2): 2092 case IP_VERSION(10, 1, 3): 2093 case IP_VERSION(10, 1, 4): 2094 case IP_VERSION(10, 3, 0): 2095 case IP_VERSION(10, 3, 2): 2096 case IP_VERSION(10, 3, 4): 2097 case IP_VERSION(10, 3, 5): 2098 adev->family = AMDGPU_FAMILY_NV; 2099 break; 2100 case IP_VERSION(10, 3, 1): 2101 adev->family = AMDGPU_FAMILY_VGH; 2102 break; 2103 case IP_VERSION(10, 3, 3): 2104 adev->family = AMDGPU_FAMILY_YC; 2105 break; 2106 case IP_VERSION(10, 3, 6): 2107 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2108 break; 2109 case IP_VERSION(10, 3, 7): 2110 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2111 break; 2112 case IP_VERSION(11, 0, 0): 2113 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2114 break; 2115 default: 2116 return -EINVAL; 2117 } 2118 2119 switch (adev->ip_versions[GC_HWIP][0]) { 2120 case IP_VERSION(9, 1, 0): 2121 case IP_VERSION(9, 2, 2): 2122 case IP_VERSION(9, 3, 0): 2123 case IP_VERSION(10, 1, 3): 2124 case IP_VERSION(10, 1, 4): 2125 case IP_VERSION(10, 3, 1): 2126 case IP_VERSION(10, 3, 3): 2127 case IP_VERSION(10, 3, 6): 2128 case IP_VERSION(10, 3, 7): 2129 adev->flags |= AMD_IS_APU; 2130 break; 2131 default: 2132 break; 2133 } 2134 2135 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2136 adev->gmc.xgmi.supported = true; 2137 2138 /* set NBIO version */ 2139 switch (adev->ip_versions[NBIO_HWIP][0]) { 2140 case IP_VERSION(6, 1, 0): 2141 case IP_VERSION(6, 2, 0): 2142 adev->nbio.funcs = &nbio_v6_1_funcs; 2143 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2144 break; 2145 case IP_VERSION(7, 0, 0): 2146 case IP_VERSION(7, 0, 1): 2147 case IP_VERSION(2, 5, 0): 2148 adev->nbio.funcs = &nbio_v7_0_funcs; 2149 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2150 break; 2151 case IP_VERSION(7, 4, 0): 2152 case IP_VERSION(7, 4, 1): 2153 adev->nbio.funcs = &nbio_v7_4_funcs; 2154 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2155 break; 2156 case IP_VERSION(7, 4, 4): 2157 adev->nbio.funcs = &nbio_v7_4_funcs; 2158 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 2159 break; 2160 case IP_VERSION(7, 2, 0): 2161 case IP_VERSION(7, 2, 1): 2162 case IP_VERSION(7, 3, 0): 2163 case IP_VERSION(7, 5, 0): 2164 case IP_VERSION(7, 5, 1): 2165 adev->nbio.funcs = &nbio_v7_2_funcs; 2166 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2167 break; 2168 case IP_VERSION(2, 1, 1): 2169 case IP_VERSION(2, 3, 0): 2170 case IP_VERSION(2, 3, 1): 2171 case IP_VERSION(2, 3, 2): 2172 adev->nbio.funcs = &nbio_v2_3_funcs; 2173 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2174 break; 2175 case IP_VERSION(3, 3, 0): 2176 case IP_VERSION(3, 3, 1): 2177 case IP_VERSION(3, 3, 2): 2178 case IP_VERSION(3, 3, 3): 2179 adev->nbio.funcs = &nbio_v2_3_funcs; 2180 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 2181 break; 2182 case IP_VERSION(4, 3, 0): 2183 adev->nbio.funcs = &nbio_v4_3_funcs; 2184 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2185 break; 2186 default: 2187 break; 2188 } 2189 2190 switch (adev->ip_versions[HDP_HWIP][0]) { 2191 case IP_VERSION(4, 0, 0): 2192 case IP_VERSION(4, 0, 1): 2193 case IP_VERSION(4, 1, 0): 2194 case IP_VERSION(4, 1, 1): 2195 case IP_VERSION(4, 1, 2): 2196 case IP_VERSION(4, 2, 0): 2197 case IP_VERSION(4, 2, 1): 2198 case IP_VERSION(4, 4, 0): 2199 adev->hdp.funcs = &hdp_v4_0_funcs; 2200 break; 2201 case IP_VERSION(5, 0, 0): 2202 case IP_VERSION(5, 0, 1): 2203 case IP_VERSION(5, 0, 2): 2204 case IP_VERSION(5, 0, 3): 2205 case IP_VERSION(5, 0, 4): 2206 case IP_VERSION(5, 2, 0): 2207 adev->hdp.funcs = &hdp_v5_0_funcs; 2208 break; 2209 case IP_VERSION(6, 0, 0): 2210 adev->hdp.funcs = &hdp_v6_0_funcs; 2211 break; 2212 default: 2213 break; 2214 } 2215 2216 switch (adev->ip_versions[DF_HWIP][0]) { 2217 case IP_VERSION(3, 6, 0): 2218 case IP_VERSION(3, 6, 1): 2219 case IP_VERSION(3, 6, 2): 2220 adev->df.funcs = &df_v3_6_funcs; 2221 break; 2222 case IP_VERSION(2, 1, 0): 2223 case IP_VERSION(2, 1, 1): 2224 case IP_VERSION(2, 5, 0): 2225 case IP_VERSION(3, 5, 1): 2226 case IP_VERSION(3, 5, 2): 2227 adev->df.funcs = &df_v1_7_funcs; 2228 break; 2229 default: 2230 break; 2231 } 2232 2233 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2234 case IP_VERSION(9, 0, 0): 2235 case IP_VERSION(9, 0, 1): 2236 case IP_VERSION(10, 0, 0): 2237 case IP_VERSION(10, 0, 1): 2238 case IP_VERSION(10, 0, 2): 2239 adev->smuio.funcs = &smuio_v9_0_funcs; 2240 break; 2241 case IP_VERSION(11, 0, 0): 2242 case IP_VERSION(11, 0, 2): 2243 case IP_VERSION(11, 0, 3): 2244 case IP_VERSION(11, 0, 4): 2245 case IP_VERSION(11, 0, 7): 2246 case IP_VERSION(11, 0, 8): 2247 adev->smuio.funcs = &smuio_v11_0_funcs; 2248 break; 2249 case IP_VERSION(11, 0, 6): 2250 case IP_VERSION(11, 0, 10): 2251 case IP_VERSION(11, 0, 11): 2252 case IP_VERSION(11, 5, 0): 2253 case IP_VERSION(13, 0, 1): 2254 case IP_VERSION(13, 0, 9): 2255 case IP_VERSION(13, 0, 10): 2256 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2257 break; 2258 case IP_VERSION(13, 0, 2): 2259 adev->smuio.funcs = &smuio_v13_0_funcs; 2260 break; 2261 case IP_VERSION(13, 0, 6): 2262 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2263 break; 2264 default: 2265 break; 2266 } 2267 2268 r = amdgpu_discovery_set_common_ip_blocks(adev); 2269 if (r) 2270 return r; 2271 2272 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2273 if (r) 2274 return r; 2275 2276 /* For SR-IOV, PSP needs to be initialized before IH */ 2277 if (amdgpu_sriov_vf(adev)) { 2278 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2279 if (r) 2280 return r; 2281 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2282 if (r) 2283 return r; 2284 } else { 2285 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2286 if (r) 2287 return r; 2288 2289 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2290 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2291 if (r) 2292 return r; 2293 } 2294 } 2295 2296 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2297 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2298 if (r) 2299 return r; 2300 } 2301 2302 r = amdgpu_discovery_set_display_ip_blocks(adev); 2303 if (r) 2304 return r; 2305 2306 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2307 if (r) 2308 return r; 2309 2310 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2311 if (r) 2312 return r; 2313 2314 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2315 !amdgpu_sriov_vf(adev)) || 2316 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2317 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2318 if (r) 2319 return r; 2320 } 2321 2322 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2323 if (r) 2324 return r; 2325 2326 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2327 if (r) 2328 return r; 2329 2330 return 0; 2331 } 2332 2333