1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __AMDGPU_CTX_H__
24 #define __AMDGPU_CTX_H__
25 
26 #include <linux/ktime.h>
27 #include <linux/types.h>
28 
29 #include "amdgpu_ring.h"
30 
31 struct drm_device;
32 struct drm_file;
33 struct amdgpu_fpriv;
34 struct amdgpu_ctx_mgr;
35 
36 #define AMDGPU_MAX_ENTITY_NUM 4
37 
38 struct amdgpu_ctx_entity {
39 	uint32_t		hw_ip;
40 	uint64_t		sequence;
41 	struct drm_sched_entity	entity;
42 	struct dma_fence	*fences[];
43 };
44 
45 struct amdgpu_ctx {
46 	struct kref			refcount;
47 	struct amdgpu_ctx_mgr		*mgr;
48 	unsigned			reset_counter;
49 	unsigned			reset_counter_query;
50 	uint64_t			generation;
51 	spinlock_t			ring_lock;
52 	struct amdgpu_ctx_entity	*entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
53 	bool				preamble_presented;
54 	int32_t				init_priority;
55 	int32_t				override_priority;
56 	atomic_t			guilty;
57 	unsigned long			ras_counter_ce;
58 	unsigned long			ras_counter_ue;
59 	uint32_t			stable_pstate;
60 	struct amdgpu_ctx_mgr		*ctx_mgr;
61 };
62 
63 struct amdgpu_ctx_mgr {
64 	struct amdgpu_device	*adev;
65 	struct mutex		lock;
66 	/* protected by lock */
67 	struct idr		ctx_handles;
68 	atomic64_t		time_spend[AMDGPU_HW_IP_NUM];
69 };
70 
71 extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
72 
73 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
74 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
75 
76 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
77 			  u32 ring, struct drm_sched_entity **entity);
78 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
79 			      struct drm_sched_entity *entity,
80 			      struct dma_fence *fence);
81 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
82 				       struct drm_sched_entity *entity,
83 				       uint64_t seq);
84 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
85 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);
86 
87 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
88 		     struct drm_file *filp);
89 
90 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
91 			       struct drm_sched_entity *entity);
92 
93 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr,
94 			 struct amdgpu_device *adev);
95 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
96 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
97 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
98 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr,
99 			  ktime_t usage[AMDGPU_HW_IP_NUM]);
100 
101 #endif
102