1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include <drm/drm_drv.h> 27 #include "amdgpu.h" 28 #include "amdgpu_sched.h" 29 #include "amdgpu_ras.h" 30 #include <linux/nospec.h> 31 32 #define to_amdgpu_ctx_entity(e) \ 33 container_of((e), struct amdgpu_ctx_entity, entity) 34 35 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 36 [AMDGPU_HW_IP_GFX] = 1, 37 [AMDGPU_HW_IP_COMPUTE] = 4, 38 [AMDGPU_HW_IP_DMA] = 2, 39 [AMDGPU_HW_IP_UVD] = 1, 40 [AMDGPU_HW_IP_VCE] = 1, 41 [AMDGPU_HW_IP_UVD_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_DEC] = 1, 43 [AMDGPU_HW_IP_VCN_ENC] = 1, 44 [AMDGPU_HW_IP_VCN_JPEG] = 1, 45 }; 46 47 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) 48 { 49 switch (ctx_prio) { 50 case AMDGPU_CTX_PRIORITY_UNSET: 51 case AMDGPU_CTX_PRIORITY_VERY_LOW: 52 case AMDGPU_CTX_PRIORITY_LOW: 53 case AMDGPU_CTX_PRIORITY_NORMAL: 54 case AMDGPU_CTX_PRIORITY_HIGH: 55 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 56 return true; 57 default: 58 return false; 59 } 60 } 61 62 static enum drm_sched_priority 63 amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) 64 { 65 switch (ctx_prio) { 66 case AMDGPU_CTX_PRIORITY_UNSET: 67 return DRM_SCHED_PRIORITY_UNSET; 68 69 case AMDGPU_CTX_PRIORITY_VERY_LOW: 70 return DRM_SCHED_PRIORITY_MIN; 71 72 case AMDGPU_CTX_PRIORITY_LOW: 73 return DRM_SCHED_PRIORITY_MIN; 74 75 case AMDGPU_CTX_PRIORITY_NORMAL: 76 return DRM_SCHED_PRIORITY_NORMAL; 77 78 case AMDGPU_CTX_PRIORITY_HIGH: 79 return DRM_SCHED_PRIORITY_HIGH; 80 81 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 82 return DRM_SCHED_PRIORITY_HIGH; 83 84 /* This should not happen as we sanitized userspace provided priority 85 * already, WARN if this happens. 86 */ 87 default: 88 WARN(1, "Invalid context priority %d\n", ctx_prio); 89 return DRM_SCHED_PRIORITY_NORMAL; 90 } 91 92 } 93 94 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 95 int32_t priority) 96 { 97 if (!amdgpu_ctx_priority_is_valid(priority)) 98 return -EINVAL; 99 100 /* NORMAL and below are accessible by everyone */ 101 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 102 return 0; 103 104 if (capable(CAP_SYS_NICE)) 105 return 0; 106 107 if (drm_is_current_master(filp)) 108 return 0; 109 110 return -EACCES; 111 } 112 113 static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) 114 { 115 switch (prio) { 116 case AMDGPU_CTX_PRIORITY_HIGH: 117 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 118 return AMDGPU_GFX_PIPE_PRIO_HIGH; 119 default: 120 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 121 } 122 } 123 124 static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio) 125 { 126 switch (prio) { 127 case AMDGPU_CTX_PRIORITY_HIGH: 128 return AMDGPU_RING_PRIO_1; 129 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 130 return AMDGPU_RING_PRIO_2; 131 default: 132 return AMDGPU_RING_PRIO_0; 133 } 134 } 135 136 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 137 { 138 struct amdgpu_device *adev = ctx->mgr->adev; 139 unsigned int hw_prio; 140 int32_t ctx_prio; 141 142 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 143 ctx->init_priority : ctx->override_priority; 144 145 switch (hw_ip) { 146 case AMDGPU_HW_IP_GFX: 147 case AMDGPU_HW_IP_COMPUTE: 148 hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); 149 break; 150 case AMDGPU_HW_IP_VCE: 151 case AMDGPU_HW_IP_VCN_ENC: 152 hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio); 153 break; 154 default: 155 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 156 break; 157 } 158 159 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 160 if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0) 161 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 162 163 return hw_prio; 164 } 165 166 /* Calculate the time spend on the hw */ 167 static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 168 { 169 struct drm_sched_fence *s_fence; 170 171 if (!fence) 172 return ns_to_ktime(0); 173 174 /* When the fence is not even scheduled it can't have spend time */ 175 s_fence = to_drm_sched_fence(fence); 176 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 177 return ns_to_ktime(0); 178 179 /* When it is still running account how much already spend */ 180 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 181 return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 182 183 return ktime_sub(s_fence->finished.timestamp, 184 s_fence->scheduled.timestamp); 185 } 186 187 static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 188 struct amdgpu_ctx_entity *centity) 189 { 190 ktime_t res = ns_to_ktime(0); 191 uint32_t i; 192 193 spin_lock(&ctx->ring_lock); 194 for (i = 0; i < amdgpu_sched_jobs; i++) { 195 res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 196 } 197 spin_unlock(&ctx->ring_lock); 198 return res; 199 } 200 201 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 202 const u32 ring) 203 { 204 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 205 struct amdgpu_device *adev = ctx->mgr->adev; 206 struct amdgpu_ctx_entity *entity; 207 enum drm_sched_priority drm_prio; 208 unsigned int hw_prio, num_scheds; 209 int32_t ctx_prio; 210 int r; 211 212 entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs), 213 GFP_KERNEL); 214 if (!entity) 215 return -ENOMEM; 216 217 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 218 ctx->init_priority : ctx->override_priority; 219 entity->hw_ip = hw_ip; 220 entity->sequence = 1; 221 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 222 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 223 224 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 225 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 226 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 227 228 /* disable load balance if the hw engine retains context among dependent jobs */ 229 if (hw_ip == AMDGPU_HW_IP_VCN_ENC || 230 hw_ip == AMDGPU_HW_IP_VCN_DEC || 231 hw_ip == AMDGPU_HW_IP_UVD_ENC || 232 hw_ip == AMDGPU_HW_IP_UVD) { 233 sched = drm_sched_pick_best(scheds, num_scheds); 234 scheds = &sched; 235 num_scheds = 1; 236 } 237 238 r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds, 239 &ctx->guilty); 240 if (r) 241 goto error_free_entity; 242 243 /* It's not an error if we fail to install the new entity */ 244 if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) 245 goto cleanup_entity; 246 247 return 0; 248 249 cleanup_entity: 250 drm_sched_entity_fini(&entity->entity); 251 252 error_free_entity: 253 kfree(entity); 254 255 return r; 256 } 257 258 static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) 259 { 260 ktime_t res = ns_to_ktime(0); 261 int i; 262 263 if (!entity) 264 return res; 265 266 for (i = 0; i < amdgpu_sched_jobs; ++i) { 267 res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 268 dma_fence_put(entity->fences[i]); 269 } 270 271 kfree(entity); 272 return res; 273 } 274 275 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 276 u32 *stable_pstate) 277 { 278 struct amdgpu_device *adev = ctx->mgr->adev; 279 enum amd_dpm_forced_level current_level; 280 281 current_level = amdgpu_dpm_get_performance_level(adev); 282 283 switch (current_level) { 284 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 285 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD; 286 break; 287 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 288 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; 289 break; 290 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 291 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; 292 break; 293 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 294 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK; 295 break; 296 default: 297 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 298 break; 299 } 300 return 0; 301 } 302 303 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 304 struct drm_file *filp, struct amdgpu_ctx *ctx) 305 { 306 u32 current_stable_pstate; 307 int r; 308 309 r = amdgpu_ctx_priority_permit(filp, priority); 310 if (r) 311 return r; 312 313 memset(ctx, 0, sizeof(*ctx)); 314 315 kref_init(&ctx->refcount); 316 ctx->mgr = mgr; 317 spin_lock_init(&ctx->ring_lock); 318 319 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 320 ctx->reset_counter_query = ctx->reset_counter; 321 ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter); 322 ctx->init_priority = priority; 323 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 324 325 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 326 if (r) 327 return r; 328 329 ctx->stable_pstate = current_stable_pstate; 330 331 return 0; 332 } 333 334 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 335 u32 stable_pstate) 336 { 337 struct amdgpu_device *adev = ctx->mgr->adev; 338 enum amd_dpm_forced_level level; 339 u32 current_stable_pstate; 340 int r; 341 342 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 343 if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) { 344 r = -EBUSY; 345 goto done; 346 } 347 348 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 349 if (r || (stable_pstate == current_stable_pstate)) 350 goto done; 351 352 switch (stable_pstate) { 353 case AMDGPU_CTX_STABLE_PSTATE_NONE: 354 level = AMD_DPM_FORCED_LEVEL_AUTO; 355 break; 356 case AMDGPU_CTX_STABLE_PSTATE_STANDARD: 357 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 358 break; 359 case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: 360 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 361 break; 362 case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: 363 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 364 break; 365 case AMDGPU_CTX_STABLE_PSTATE_PEAK: 366 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 367 break; 368 default: 369 r = -EINVAL; 370 goto done; 371 } 372 373 r = amdgpu_dpm_force_performance_level(adev, level); 374 375 if (level == AMD_DPM_FORCED_LEVEL_AUTO) 376 adev->pm.stable_pstate_ctx = NULL; 377 else 378 adev->pm.stable_pstate_ctx = ctx; 379 done: 380 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 381 382 return r; 383 } 384 385 static void amdgpu_ctx_fini(struct kref *ref) 386 { 387 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 388 struct amdgpu_ctx_mgr *mgr = ctx->mgr; 389 struct amdgpu_device *adev = mgr->adev; 390 unsigned i, j, idx; 391 392 if (!adev) 393 return; 394 395 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 396 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 397 ktime_t spend; 398 399 spend = amdgpu_ctx_fini_entity(ctx->entities[i][j]); 400 atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 401 } 402 } 403 404 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 405 amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); 406 drm_dev_exit(idx); 407 } 408 409 kfree(ctx); 410 } 411 412 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 413 u32 ring, struct drm_sched_entity **entity) 414 { 415 int r; 416 417 if (hw_ip >= AMDGPU_HW_IP_NUM) { 418 DRM_ERROR("unknown HW IP type: %d\n", hw_ip); 419 return -EINVAL; 420 } 421 422 /* Right now all IPs have only one instance - multiple rings. */ 423 if (instance != 0) { 424 DRM_DEBUG("invalid ip instance: %d\n", instance); 425 return -EINVAL; 426 } 427 428 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 429 DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring); 430 return -EINVAL; 431 } 432 433 if (ctx->entities[hw_ip][ring] == NULL) { 434 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 435 if (r) 436 return r; 437 } 438 439 *entity = &ctx->entities[hw_ip][ring]->entity; 440 return 0; 441 } 442 443 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 444 struct amdgpu_fpriv *fpriv, 445 struct drm_file *filp, 446 int32_t priority, 447 uint32_t *id) 448 { 449 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 450 struct amdgpu_ctx *ctx; 451 int r; 452 453 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 454 if (!ctx) 455 return -ENOMEM; 456 457 mutex_lock(&mgr->lock); 458 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 459 if (r < 0) { 460 mutex_unlock(&mgr->lock); 461 kfree(ctx); 462 return r; 463 } 464 465 *id = (uint32_t)r; 466 r = amdgpu_ctx_init(mgr, priority, filp, ctx); 467 if (r) { 468 idr_remove(&mgr->ctx_handles, *id); 469 *id = 0; 470 kfree(ctx); 471 } 472 mutex_unlock(&mgr->lock); 473 return r; 474 } 475 476 static void amdgpu_ctx_do_release(struct kref *ref) 477 { 478 struct amdgpu_ctx *ctx; 479 u32 i, j; 480 481 ctx = container_of(ref, struct amdgpu_ctx, refcount); 482 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 483 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 484 if (!ctx->entities[i][j]) 485 continue; 486 487 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 488 } 489 } 490 491 amdgpu_ctx_fini(ref); 492 } 493 494 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 495 { 496 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 497 struct amdgpu_ctx *ctx; 498 499 mutex_lock(&mgr->lock); 500 ctx = idr_remove(&mgr->ctx_handles, id); 501 if (ctx) 502 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 503 mutex_unlock(&mgr->lock); 504 return ctx ? 0 : -EINVAL; 505 } 506 507 static int amdgpu_ctx_query(struct amdgpu_device *adev, 508 struct amdgpu_fpriv *fpriv, uint32_t id, 509 union drm_amdgpu_ctx_out *out) 510 { 511 struct amdgpu_ctx *ctx; 512 struct amdgpu_ctx_mgr *mgr; 513 unsigned reset_counter; 514 515 if (!fpriv) 516 return -EINVAL; 517 518 mgr = &fpriv->ctx_mgr; 519 mutex_lock(&mgr->lock); 520 ctx = idr_find(&mgr->ctx_handles, id); 521 if (!ctx) { 522 mutex_unlock(&mgr->lock); 523 return -EINVAL; 524 } 525 526 /* TODO: these two are always zero */ 527 out->state.flags = 0x0; 528 out->state.hangs = 0x0; 529 530 /* determine if a GPU reset has occured since the last call */ 531 reset_counter = atomic_read(&adev->gpu_reset_counter); 532 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 533 if (ctx->reset_counter_query == reset_counter) 534 out->state.reset_status = AMDGPU_CTX_NO_RESET; 535 else 536 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 537 ctx->reset_counter_query = reset_counter; 538 539 mutex_unlock(&mgr->lock); 540 return 0; 541 } 542 543 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 544 545 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 546 struct amdgpu_fpriv *fpriv, uint32_t id, 547 union drm_amdgpu_ctx_out *out) 548 { 549 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 550 struct amdgpu_ctx *ctx; 551 struct amdgpu_ctx_mgr *mgr; 552 553 if (!fpriv) 554 return -EINVAL; 555 556 mgr = &fpriv->ctx_mgr; 557 mutex_lock(&mgr->lock); 558 ctx = idr_find(&mgr->ctx_handles, id); 559 if (!ctx) { 560 mutex_unlock(&mgr->lock); 561 return -EINVAL; 562 } 563 564 out->state.flags = 0x0; 565 out->state.hangs = 0x0; 566 567 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 568 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 569 570 if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) 571 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 572 573 if (atomic_read(&ctx->guilty)) 574 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 575 576 if (adev->ras_enabled && con) { 577 /* Return the cached values in O(1), 578 * and schedule delayed work to cache 579 * new vaues. 580 */ 581 int ce_count, ue_count; 582 583 ce_count = atomic_read(&con->ras_ce_count); 584 ue_count = atomic_read(&con->ras_ue_count); 585 586 if (ce_count != ctx->ras_counter_ce) { 587 ctx->ras_counter_ce = ce_count; 588 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 589 } 590 591 if (ue_count != ctx->ras_counter_ue) { 592 ctx->ras_counter_ue = ue_count; 593 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 594 } 595 596 schedule_delayed_work(&con->ras_counte_delay_work, 597 msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); 598 } 599 600 mutex_unlock(&mgr->lock); 601 return 0; 602 } 603 604 605 606 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 607 struct amdgpu_fpriv *fpriv, uint32_t id, 608 bool set, u32 *stable_pstate) 609 { 610 struct amdgpu_ctx *ctx; 611 struct amdgpu_ctx_mgr *mgr; 612 int r; 613 614 if (!fpriv) 615 return -EINVAL; 616 617 mgr = &fpriv->ctx_mgr; 618 mutex_lock(&mgr->lock); 619 ctx = idr_find(&mgr->ctx_handles, id); 620 if (!ctx) { 621 mutex_unlock(&mgr->lock); 622 return -EINVAL; 623 } 624 625 if (set) 626 r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate); 627 else 628 r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate); 629 630 mutex_unlock(&mgr->lock); 631 return r; 632 } 633 634 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 635 struct drm_file *filp) 636 { 637 int r; 638 uint32_t id, stable_pstate; 639 int32_t priority; 640 641 union drm_amdgpu_ctx *args = data; 642 struct amdgpu_device *adev = drm_to_adev(dev); 643 struct amdgpu_fpriv *fpriv = filp->driver_priv; 644 645 id = args->in.ctx_id; 646 priority = args->in.priority; 647 648 /* For backwards compatibility reasons, we need to accept 649 * ioctls with garbage in the priority field */ 650 if (!amdgpu_ctx_priority_is_valid(priority)) 651 priority = AMDGPU_CTX_PRIORITY_NORMAL; 652 653 switch (args->in.op) { 654 case AMDGPU_CTX_OP_ALLOC_CTX: 655 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 656 args->out.alloc.ctx_id = id; 657 break; 658 case AMDGPU_CTX_OP_FREE_CTX: 659 r = amdgpu_ctx_free(fpriv, id); 660 break; 661 case AMDGPU_CTX_OP_QUERY_STATE: 662 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 663 break; 664 case AMDGPU_CTX_OP_QUERY_STATE2: 665 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 666 break; 667 case AMDGPU_CTX_OP_GET_STABLE_PSTATE: 668 if (args->in.flags) 669 return -EINVAL; 670 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate); 671 if (!r) 672 args->out.pstate.flags = stable_pstate; 673 break; 674 case AMDGPU_CTX_OP_SET_STABLE_PSTATE: 675 if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK) 676 return -EINVAL; 677 stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK; 678 if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK) 679 return -EINVAL; 680 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); 681 break; 682 default: 683 return -EINVAL; 684 } 685 686 return r; 687 } 688 689 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 690 { 691 struct amdgpu_ctx *ctx; 692 struct amdgpu_ctx_mgr *mgr; 693 694 if (!fpriv) 695 return NULL; 696 697 mgr = &fpriv->ctx_mgr; 698 699 mutex_lock(&mgr->lock); 700 ctx = idr_find(&mgr->ctx_handles, id); 701 if (ctx) 702 kref_get(&ctx->refcount); 703 mutex_unlock(&mgr->lock); 704 return ctx; 705 } 706 707 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 708 { 709 if (ctx == NULL) 710 return -EINVAL; 711 712 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 713 return 0; 714 } 715 716 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 717 struct drm_sched_entity *entity, 718 struct dma_fence *fence) 719 { 720 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 721 uint64_t seq = centity->sequence; 722 struct dma_fence *other = NULL; 723 unsigned idx = 0; 724 725 idx = seq & (amdgpu_sched_jobs - 1); 726 other = centity->fences[idx]; 727 WARN_ON(other && !dma_fence_is_signaled(other)); 728 729 dma_fence_get(fence); 730 731 spin_lock(&ctx->ring_lock); 732 centity->fences[idx] = fence; 733 centity->sequence++; 734 spin_unlock(&ctx->ring_lock); 735 736 atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 737 &ctx->mgr->time_spend[centity->hw_ip]); 738 739 dma_fence_put(other); 740 return seq; 741 } 742 743 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 744 struct drm_sched_entity *entity, 745 uint64_t seq) 746 { 747 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 748 struct dma_fence *fence; 749 750 spin_lock(&ctx->ring_lock); 751 752 if (seq == ~0ull) 753 seq = centity->sequence - 1; 754 755 if (seq >= centity->sequence) { 756 spin_unlock(&ctx->ring_lock); 757 return ERR_PTR(-EINVAL); 758 } 759 760 761 if (seq + amdgpu_sched_jobs < centity->sequence) { 762 spin_unlock(&ctx->ring_lock); 763 return NULL; 764 } 765 766 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 767 spin_unlock(&ctx->ring_lock); 768 769 return fence; 770 } 771 772 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 773 struct amdgpu_ctx_entity *aentity, 774 int hw_ip, 775 int32_t priority) 776 { 777 struct amdgpu_device *adev = ctx->mgr->adev; 778 unsigned int hw_prio; 779 struct drm_gpu_scheduler **scheds = NULL; 780 unsigned num_scheds; 781 782 /* set sw priority */ 783 drm_sched_entity_set_priority(&aentity->entity, 784 amdgpu_ctx_to_drm_sched_prio(priority)); 785 786 /* set hw priority */ 787 if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { 788 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 789 hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); 790 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 791 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 792 drm_sched_entity_modify_sched(&aentity->entity, scheds, 793 num_scheds); 794 } 795 } 796 797 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 798 int32_t priority) 799 { 800 int32_t ctx_prio; 801 unsigned i, j; 802 803 ctx->override_priority = priority; 804 805 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 806 ctx->init_priority : ctx->override_priority; 807 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 808 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 809 if (!ctx->entities[i][j]) 810 continue; 811 812 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 813 i, ctx_prio); 814 } 815 } 816 } 817 818 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 819 struct drm_sched_entity *entity) 820 { 821 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 822 struct dma_fence *other; 823 unsigned idx; 824 long r; 825 826 spin_lock(&ctx->ring_lock); 827 idx = centity->sequence & (amdgpu_sched_jobs - 1); 828 other = dma_fence_get(centity->fences[idx]); 829 spin_unlock(&ctx->ring_lock); 830 831 if (!other) 832 return 0; 833 834 r = dma_fence_wait(other, true); 835 if (r < 0 && r != -ERESTARTSYS) 836 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 837 838 dma_fence_put(other); 839 return r; 840 } 841 842 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 843 struct amdgpu_device *adev) 844 { 845 unsigned int i; 846 847 mgr->adev = adev; 848 mutex_init(&mgr->lock); 849 idr_init_base(&mgr->ctx_handles, 1); 850 851 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 852 atomic64_set(&mgr->time_spend[i], 0); 853 } 854 855 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 856 { 857 struct amdgpu_ctx *ctx; 858 struct idr *idp; 859 uint32_t id, i, j; 860 861 idp = &mgr->ctx_handles; 862 863 mutex_lock(&mgr->lock); 864 idr_for_each_entry(idp, ctx, id) { 865 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 866 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 867 struct drm_sched_entity *entity; 868 869 if (!ctx->entities[i][j]) 870 continue; 871 872 entity = &ctx->entities[i][j]->entity; 873 timeout = drm_sched_entity_flush(entity, timeout); 874 } 875 } 876 } 877 mutex_unlock(&mgr->lock); 878 return timeout; 879 } 880 881 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 882 { 883 struct amdgpu_ctx *ctx; 884 struct idr *idp; 885 uint32_t id, i, j; 886 887 idp = &mgr->ctx_handles; 888 889 idr_for_each_entry(idp, ctx, id) { 890 if (kref_read(&ctx->refcount) != 1) { 891 DRM_ERROR("ctx %p is still alive\n", ctx); 892 continue; 893 } 894 895 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 896 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 897 struct drm_sched_entity *entity; 898 899 if (!ctx->entities[i][j]) 900 continue; 901 902 entity = &ctx->entities[i][j]->entity; 903 drm_sched_entity_fini(entity); 904 } 905 } 906 } 907 } 908 909 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 910 { 911 struct amdgpu_ctx *ctx; 912 struct idr *idp; 913 uint32_t id; 914 915 amdgpu_ctx_mgr_entity_fini(mgr); 916 917 idp = &mgr->ctx_handles; 918 919 idr_for_each_entry(idp, ctx, id) { 920 if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1) 921 DRM_ERROR("ctx %p is still alive\n", ctx); 922 } 923 924 idr_destroy(&mgr->ctx_handles); 925 mutex_destroy(&mgr->lock); 926 } 927 928 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 929 ktime_t usage[AMDGPU_HW_IP_NUM]) 930 { 931 struct amdgpu_ctx *ctx; 932 unsigned int hw_ip, i; 933 uint32_t id; 934 935 /* 936 * This is a little bit racy because it can be that a ctx or a fence are 937 * destroyed just in the moment we try to account them. But that is ok 938 * since exactly that case is explicitely allowed by the interface. 939 */ 940 mutex_lock(&mgr->lock); 941 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 942 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 943 944 usage[hw_ip] = ns_to_ktime(ns); 945 } 946 947 idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 948 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 949 for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 950 struct amdgpu_ctx_entity *centity; 951 ktime_t spend; 952 953 centity = ctx->entities[hw_ip][i]; 954 if (!centity) 955 continue; 956 spend = amdgpu_ctx_entity_time(ctx, centity); 957 usage[hw_ip] = ktime_add(usage[hw_ip], spend); 958 } 959 } 960 } 961 mutex_unlock(&mgr->lock); 962 } 963