1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 28 static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) 29 { 30 unsigned i, j; 31 int r; 32 33 memset(ctx, 0, sizeof(*ctx)); 34 ctx->adev = adev; 35 kref_init(&ctx->refcount); 36 spin_lock_init(&ctx->ring_lock); 37 ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, 38 sizeof(struct fence*), GFP_KERNEL); 39 if (!ctx->fences) 40 return -ENOMEM; 41 42 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 43 ctx->rings[i].sequence = 1; 44 ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; 45 } 46 /* create context entity for each ring */ 47 for (i = 0; i < adev->num_rings; i++) { 48 struct amdgpu_ring *ring = adev->rings[i]; 49 struct amd_sched_rq *rq; 50 51 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 52 r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, 53 rq, amdgpu_sched_jobs); 54 if (r) 55 break; 56 } 57 58 if (i < adev->num_rings) { 59 for (j = 0; j < i; j++) 60 amd_sched_entity_fini(&adev->rings[j]->sched, 61 &ctx->rings[j].entity); 62 kfree(ctx->fences); 63 ctx->fences = NULL; 64 return r; 65 } 66 return 0; 67 } 68 69 static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) 70 { 71 struct amdgpu_device *adev = ctx->adev; 72 unsigned i, j; 73 74 if (!adev) 75 return; 76 77 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) 78 for (j = 0; j < amdgpu_sched_jobs; ++j) 79 fence_put(ctx->rings[i].fences[j]); 80 kfree(ctx->fences); 81 ctx->fences = NULL; 82 83 for (i = 0; i < adev->num_rings; i++) 84 amd_sched_entity_fini(&adev->rings[i]->sched, 85 &ctx->rings[i].entity); 86 } 87 88 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 89 struct amdgpu_fpriv *fpriv, 90 uint32_t *id) 91 { 92 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 93 struct amdgpu_ctx *ctx; 94 int r; 95 96 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 97 if (!ctx) 98 return -ENOMEM; 99 100 mutex_lock(&mgr->lock); 101 r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL); 102 if (r < 0) { 103 mutex_unlock(&mgr->lock); 104 kfree(ctx); 105 return r; 106 } 107 *id = (uint32_t)r; 108 r = amdgpu_ctx_init(adev, ctx); 109 if (r) { 110 idr_remove(&mgr->ctx_handles, *id); 111 *id = 0; 112 kfree(ctx); 113 } 114 mutex_unlock(&mgr->lock); 115 return r; 116 } 117 118 static void amdgpu_ctx_do_release(struct kref *ref) 119 { 120 struct amdgpu_ctx *ctx; 121 122 ctx = container_of(ref, struct amdgpu_ctx, refcount); 123 124 amdgpu_ctx_fini(ctx); 125 126 kfree(ctx); 127 } 128 129 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 130 { 131 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 132 struct amdgpu_ctx *ctx; 133 134 mutex_lock(&mgr->lock); 135 ctx = idr_find(&mgr->ctx_handles, id); 136 if (ctx) { 137 idr_remove(&mgr->ctx_handles, id); 138 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 139 mutex_unlock(&mgr->lock); 140 return 0; 141 } 142 mutex_unlock(&mgr->lock); 143 return -EINVAL; 144 } 145 146 static int amdgpu_ctx_query(struct amdgpu_device *adev, 147 struct amdgpu_fpriv *fpriv, uint32_t id, 148 union drm_amdgpu_ctx_out *out) 149 { 150 struct amdgpu_ctx *ctx; 151 struct amdgpu_ctx_mgr *mgr; 152 unsigned reset_counter; 153 154 if (!fpriv) 155 return -EINVAL; 156 157 mgr = &fpriv->ctx_mgr; 158 mutex_lock(&mgr->lock); 159 ctx = idr_find(&mgr->ctx_handles, id); 160 if (!ctx) { 161 mutex_unlock(&mgr->lock); 162 return -EINVAL; 163 } 164 165 /* TODO: these two are always zero */ 166 out->state.flags = 0x0; 167 out->state.hangs = 0x0; 168 169 /* determine if a GPU reset has occured since the last call */ 170 reset_counter = atomic_read(&adev->gpu_reset_counter); 171 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 172 if (ctx->reset_counter == reset_counter) 173 out->state.reset_status = AMDGPU_CTX_NO_RESET; 174 else 175 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 176 ctx->reset_counter = reset_counter; 177 178 mutex_unlock(&mgr->lock); 179 return 0; 180 } 181 182 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 183 struct drm_file *filp) 184 { 185 int r; 186 uint32_t id; 187 188 union drm_amdgpu_ctx *args = data; 189 struct amdgpu_device *adev = dev->dev_private; 190 struct amdgpu_fpriv *fpriv = filp->driver_priv; 191 192 r = 0; 193 id = args->in.ctx_id; 194 195 switch (args->in.op) { 196 case AMDGPU_CTX_OP_ALLOC_CTX: 197 r = amdgpu_ctx_alloc(adev, fpriv, &id); 198 args->out.alloc.ctx_id = id; 199 break; 200 case AMDGPU_CTX_OP_FREE_CTX: 201 r = amdgpu_ctx_free(fpriv, id); 202 break; 203 case AMDGPU_CTX_OP_QUERY_STATE: 204 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 return r; 211 } 212 213 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 214 { 215 struct amdgpu_ctx *ctx; 216 struct amdgpu_ctx_mgr *mgr; 217 218 if (!fpriv) 219 return NULL; 220 221 mgr = &fpriv->ctx_mgr; 222 223 mutex_lock(&mgr->lock); 224 ctx = idr_find(&mgr->ctx_handles, id); 225 if (ctx) 226 kref_get(&ctx->refcount); 227 mutex_unlock(&mgr->lock); 228 return ctx; 229 } 230 231 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 232 { 233 if (ctx == NULL) 234 return -EINVAL; 235 236 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 237 return 0; 238 } 239 240 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 241 struct fence *fence) 242 { 243 struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 244 uint64_t seq = cring->sequence; 245 unsigned idx = 0; 246 struct fence *other = NULL; 247 248 idx = seq & (amdgpu_sched_jobs - 1); 249 other = cring->fences[idx]; 250 if (other) { 251 signed long r; 252 r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); 253 if (r < 0) 254 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 255 } 256 257 fence_get(fence); 258 259 spin_lock(&ctx->ring_lock); 260 cring->fences[idx] = fence; 261 cring->sequence++; 262 spin_unlock(&ctx->ring_lock); 263 264 fence_put(other); 265 266 return seq; 267 } 268 269 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 270 struct amdgpu_ring *ring, uint64_t seq) 271 { 272 struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 273 struct fence *fence; 274 275 spin_lock(&ctx->ring_lock); 276 277 if (seq >= cring->sequence) { 278 spin_unlock(&ctx->ring_lock); 279 return ERR_PTR(-EINVAL); 280 } 281 282 283 if (seq + amdgpu_sched_jobs < cring->sequence) { 284 spin_unlock(&ctx->ring_lock); 285 return NULL; 286 } 287 288 fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]); 289 spin_unlock(&ctx->ring_lock); 290 291 return fence; 292 } 293 294 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 295 { 296 mutex_init(&mgr->lock); 297 idr_init(&mgr->ctx_handles); 298 } 299 300 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 301 { 302 struct amdgpu_ctx *ctx; 303 struct idr *idp; 304 uint32_t id; 305 306 idp = &mgr->ctx_handles; 307 308 idr_for_each_entry(idp, ctx, id) { 309 if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) 310 DRM_ERROR("ctx %p is still alive\n", ctx); 311 } 312 313 idr_destroy(&mgr->ctx_handles); 314 mutex_destroy(&mgr->lock); 315 } 316