1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: monk liu <monk.liu@amd.com>
23  */
24 
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 
28 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
29 		    struct amdgpu_ctx *ctx)
30 {
31 	unsigned i, j;
32 	int r;
33 
34 	memset(ctx, 0, sizeof(*ctx));
35 	ctx->adev = adev;
36 	kref_init(&ctx->refcount);
37 	spin_lock_init(&ctx->ring_lock);
38 	ctx->fences = kzalloc(sizeof(struct fence *) * amdgpu_sched_jobs *
39 			 AMDGPU_MAX_RINGS, GFP_KERNEL);
40 	if (!ctx->fences)
41 		return -ENOMEM;
42 
43 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
44 		ctx->rings[i].sequence = 1;
45 		ctx->rings[i].fences = (void *)ctx->fences + sizeof(struct fence *) *
46 			amdgpu_sched_jobs * i;
47 	}
48 	if (amdgpu_enable_scheduler) {
49 		/* create context entity for each ring */
50 		for (i = 0; i < adev->num_rings; i++) {
51 			struct amd_sched_rq *rq;
52 			if (pri >= AMD_SCHED_MAX_PRIORITY) {
53 				kfree(ctx->fences);
54 				return -EINVAL;
55 			}
56 			rq = &adev->rings[i]->sched.sched_rq[pri];
57 			r = amd_sched_entity_init(&adev->rings[i]->sched,
58 						  &ctx->rings[i].entity,
59 						  rq, amdgpu_sched_jobs);
60 			if (r)
61 				break;
62 		}
63 
64 		if (i < adev->num_rings) {
65 			for (j = 0; j < i; j++)
66 				amd_sched_entity_fini(&adev->rings[j]->sched,
67 						      &ctx->rings[j].entity);
68 			kfree(ctx->fences);
69 			return r;
70 		}
71 	}
72 	return 0;
73 }
74 
75 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
76 {
77 	struct amdgpu_device *adev = ctx->adev;
78 	unsigned i, j;
79 
80 	if (!adev)
81 		return;
82 
83 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
84 		for (j = 0; j < amdgpu_sched_jobs; ++j)
85 			fence_put(ctx->rings[i].fences[j]);
86 	kfree(ctx->fences);
87 
88 	if (amdgpu_enable_scheduler) {
89 		for (i = 0; i < adev->num_rings; i++)
90 			amd_sched_entity_fini(&adev->rings[i]->sched,
91 					      &ctx->rings[i].entity);
92 	}
93 }
94 
95 static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
96 			    struct amdgpu_fpriv *fpriv,
97 			    uint32_t *id)
98 {
99 	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
100 	struct amdgpu_ctx *ctx;
101 	int r;
102 
103 	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
104 	if (!ctx)
105 		return -ENOMEM;
106 
107 	mutex_lock(&mgr->lock);
108 	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
109 	if (r < 0) {
110 		mutex_unlock(&mgr->lock);
111 		kfree(ctx);
112 		return r;
113 	}
114 	*id = (uint32_t)r;
115 	r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_NORMAL, ctx);
116 	if (r) {
117 		idr_remove(&mgr->ctx_handles, *id);
118 		*id = 0;
119 		kfree(ctx);
120 	}
121 	mutex_unlock(&mgr->lock);
122 	return r;
123 }
124 
125 static void amdgpu_ctx_do_release(struct kref *ref)
126 {
127 	struct amdgpu_ctx *ctx;
128 
129 	ctx = container_of(ref, struct amdgpu_ctx, refcount);
130 
131 	amdgpu_ctx_fini(ctx);
132 
133 	kfree(ctx);
134 }
135 
136 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
137 {
138 	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
139 	struct amdgpu_ctx *ctx;
140 
141 	mutex_lock(&mgr->lock);
142 	ctx = idr_find(&mgr->ctx_handles, id);
143 	if (ctx) {
144 		idr_remove(&mgr->ctx_handles, id);
145 		kref_put(&ctx->refcount, amdgpu_ctx_do_release);
146 		mutex_unlock(&mgr->lock);
147 		return 0;
148 	}
149 	mutex_unlock(&mgr->lock);
150 	return -EINVAL;
151 }
152 
153 static int amdgpu_ctx_query(struct amdgpu_device *adev,
154 			    struct amdgpu_fpriv *fpriv, uint32_t id,
155 			    union drm_amdgpu_ctx_out *out)
156 {
157 	struct amdgpu_ctx *ctx;
158 	struct amdgpu_ctx_mgr *mgr;
159 	unsigned reset_counter;
160 
161 	if (!fpriv)
162 		return -EINVAL;
163 
164 	mgr = &fpriv->ctx_mgr;
165 	mutex_lock(&mgr->lock);
166 	ctx = idr_find(&mgr->ctx_handles, id);
167 	if (!ctx) {
168 		mutex_unlock(&mgr->lock);
169 		return -EINVAL;
170 	}
171 
172 	/* TODO: these two are always zero */
173 	out->state.flags = 0x0;
174 	out->state.hangs = 0x0;
175 
176 	/* determine if a GPU reset has occured since the last call */
177 	reset_counter = atomic_read(&adev->gpu_reset_counter);
178 	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
179 	if (ctx->reset_counter == reset_counter)
180 		out->state.reset_status = AMDGPU_CTX_NO_RESET;
181 	else
182 		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
183 	ctx->reset_counter = reset_counter;
184 
185 	mutex_unlock(&mgr->lock);
186 	return 0;
187 }
188 
189 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
190 		     struct drm_file *filp)
191 {
192 	int r;
193 	uint32_t id;
194 
195 	union drm_amdgpu_ctx *args = data;
196 	struct amdgpu_device *adev = dev->dev_private;
197 	struct amdgpu_fpriv *fpriv = filp->driver_priv;
198 
199 	r = 0;
200 	id = args->in.ctx_id;
201 
202 	switch (args->in.op) {
203 		case AMDGPU_CTX_OP_ALLOC_CTX:
204 			r = amdgpu_ctx_alloc(adev, fpriv, &id);
205 			args->out.alloc.ctx_id = id;
206 			break;
207 		case AMDGPU_CTX_OP_FREE_CTX:
208 			r = amdgpu_ctx_free(fpriv, id);
209 			break;
210 		case AMDGPU_CTX_OP_QUERY_STATE:
211 			r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
212 			break;
213 		default:
214 			return -EINVAL;
215 	}
216 
217 	return r;
218 }
219 
220 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
221 {
222 	struct amdgpu_ctx *ctx;
223 	struct amdgpu_ctx_mgr *mgr;
224 
225 	if (!fpriv)
226 		return NULL;
227 
228 	mgr = &fpriv->ctx_mgr;
229 
230 	mutex_lock(&mgr->lock);
231 	ctx = idr_find(&mgr->ctx_handles, id);
232 	if (ctx)
233 		kref_get(&ctx->refcount);
234 	mutex_unlock(&mgr->lock);
235 	return ctx;
236 }
237 
238 int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
239 {
240 	if (ctx == NULL)
241 		return -EINVAL;
242 
243 	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
244 	return 0;
245 }
246 
247 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
248 			      struct fence *fence)
249 {
250 	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
251 	uint64_t seq = cring->sequence;
252 	unsigned idx = 0;
253 	struct fence *other = NULL;
254 
255 	idx = seq & (amdgpu_sched_jobs - 1);
256 	other = cring->fences[idx];
257 	if (other) {
258 		signed long r;
259 		r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
260 		if (r < 0)
261 			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
262 	}
263 
264 	fence_get(fence);
265 
266 	spin_lock(&ctx->ring_lock);
267 	cring->fences[idx] = fence;
268 	cring->sequence++;
269 	spin_unlock(&ctx->ring_lock);
270 
271 	fence_put(other);
272 
273 	return seq;
274 }
275 
276 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
277 				   struct amdgpu_ring *ring, uint64_t seq)
278 {
279 	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
280 	struct fence *fence;
281 
282 	spin_lock(&ctx->ring_lock);
283 
284 	if (seq >= cring->sequence) {
285 		spin_unlock(&ctx->ring_lock);
286 		return ERR_PTR(-EINVAL);
287 	}
288 
289 
290 	if (seq + amdgpu_sched_jobs < cring->sequence) {
291 		spin_unlock(&ctx->ring_lock);
292 		return NULL;
293 	}
294 
295 	fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
296 	spin_unlock(&ctx->ring_lock);
297 
298 	return fence;
299 }
300 
301 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
302 {
303 	mutex_init(&mgr->lock);
304 	idr_init(&mgr->ctx_handles);
305 }
306 
307 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
308 {
309 	struct amdgpu_ctx *ctx;
310 	struct idr *idp;
311 	uint32_t id;
312 
313 	idp = &mgr->ctx_handles;
314 
315 	idr_for_each_entry(idp, ctx, id) {
316 		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
317 			DRM_ERROR("ctx %p is still alive\n", ctx);
318 	}
319 
320 	idr_destroy(&mgr->ctx_handles);
321 	mutex_destroy(&mgr->lock);
322 }
323