1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2015 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * 4d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 7d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10d38ceaf9SAlex Deucher * 11d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 12d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 13d38ceaf9SAlex Deucher * 14d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21d38ceaf9SAlex Deucher * 22d38ceaf9SAlex Deucher * Authors: monk liu <monk.liu@amd.com> 23d38ceaf9SAlex Deucher */ 24d38ceaf9SAlex Deucher 25d38ceaf9SAlex Deucher #include <drm/drmP.h> 26d38ceaf9SAlex Deucher #include "amdgpu.h" 27d38ceaf9SAlex Deucher 2820874179SChristian König static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) 29d38ceaf9SAlex Deucher { 3047f38501SChristian König unsigned i, j; 3147f38501SChristian König int r; 3247f38501SChristian König 33d38ceaf9SAlex Deucher memset(ctx, 0, sizeof(*ctx)); 349cb7e5a9SChunming Zhou ctx->adev = adev; 35d38ceaf9SAlex Deucher kref_init(&ctx->refcount); 3621c16bf6SChristian König spin_lock_init(&ctx->ring_lock); 37a750b47eSChristian König ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, 38f54d1867SChris Wilson sizeof(struct dma_fence*), GFP_KERNEL); 3937cd0ca2SChunming Zhou if (!ctx->fences) 4037cd0ca2SChunming Zhou return -ENOMEM; 4123ca0e4eSChunming Zhou 4237cd0ca2SChunming Zhou for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 4337cd0ca2SChunming Zhou ctx->rings[i].sequence = 1; 44a750b47eSChristian König ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; 4537cd0ca2SChunming Zhou } 46ce199ad6SNicolai Hähnle 47ce199ad6SNicolai Hähnle ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); 48ce199ad6SNicolai Hähnle 499cb7e5a9SChunming Zhou /* create context entity for each ring */ 509cb7e5a9SChunming Zhou for (i = 0; i < adev->num_rings; i++) { 5120874179SChristian König struct amdgpu_ring *ring = adev->rings[i]; 52432a4ff8SChristian König struct amd_sched_rq *rq; 5320874179SChristian König 5420874179SChristian König rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 5520874179SChristian König r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, 56ddf94d33SChristian König rq, amdgpu_sched_jobs); 579cb7e5a9SChunming Zhou if (r) 589cb7e5a9SChunming Zhou break; 599cb7e5a9SChunming Zhou } 609cb7e5a9SChunming Zhou 619cb7e5a9SChunming Zhou if (i < adev->num_rings) { 629cb7e5a9SChunming Zhou for (j = 0; j < i; j++) 634f839a24SChristian König amd_sched_entity_fini(&adev->rings[j]->sched, 6491404fb2SChristian König &ctx->rings[j].entity); 6537cd0ca2SChunming Zhou kfree(ctx->fences); 6654ddf3a6SGrazvydas Ignotas ctx->fences = NULL; 6747f38501SChristian König return r; 689cb7e5a9SChunming Zhou } 69d38ceaf9SAlex Deucher return 0; 70d38ceaf9SAlex Deucher } 71d38ceaf9SAlex Deucher 7220874179SChristian König static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) 7347f38501SChristian König { 7447f38501SChristian König struct amdgpu_device *adev = ctx->adev; 7547f38501SChristian König unsigned i, j; 7647f38501SChristian König 77fe295b27SDave Airlie if (!adev) 78fe295b27SDave Airlie return; 79fe295b27SDave Airlie 8047f38501SChristian König for (i = 0; i < AMDGPU_MAX_RINGS; ++i) 8137cd0ca2SChunming Zhou for (j = 0; j < amdgpu_sched_jobs; ++j) 82f54d1867SChris Wilson dma_fence_put(ctx->rings[i].fences[j]); 8337cd0ca2SChunming Zhou kfree(ctx->fences); 8454ddf3a6SGrazvydas Ignotas ctx->fences = NULL; 8547f38501SChristian König 8647f38501SChristian König for (i = 0; i < adev->num_rings; i++) 874f839a24SChristian König amd_sched_entity_fini(&adev->rings[i]->sched, 8891404fb2SChristian König &ctx->rings[i].entity); 8947f38501SChristian König } 9047f38501SChristian König 9147f38501SChristian König static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 9247f38501SChristian König struct amdgpu_fpriv *fpriv, 9347f38501SChristian König uint32_t *id) 9447f38501SChristian König { 9547f38501SChristian König struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 9647f38501SChristian König struct amdgpu_ctx *ctx; 9747f38501SChristian König int r; 9847f38501SChristian König 9947f38501SChristian König ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 10047f38501SChristian König if (!ctx) 10147f38501SChristian König return -ENOMEM; 10247f38501SChristian König 10347f38501SChristian König mutex_lock(&mgr->lock); 10447f38501SChristian König r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL); 10547f38501SChristian König if (r < 0) { 10647f38501SChristian König mutex_unlock(&mgr->lock); 10747f38501SChristian König kfree(ctx); 10847f38501SChristian König return r; 10947f38501SChristian König } 11047f38501SChristian König *id = (uint32_t)r; 11120874179SChristian König r = amdgpu_ctx_init(adev, ctx); 112c648ed7cSChunming Zhou if (r) { 113c648ed7cSChunming Zhou idr_remove(&mgr->ctx_handles, *id); 114c648ed7cSChunming Zhou *id = 0; 115c648ed7cSChunming Zhou kfree(ctx); 116c648ed7cSChunming Zhou } 11747f38501SChristian König mutex_unlock(&mgr->lock); 11847f38501SChristian König return r; 11947f38501SChristian König } 12047f38501SChristian König 12147f38501SChristian König static void amdgpu_ctx_do_release(struct kref *ref) 122d38ceaf9SAlex Deucher { 123d38ceaf9SAlex Deucher struct amdgpu_ctx *ctx; 124d38ceaf9SAlex Deucher 12547f38501SChristian König ctx = container_of(ref, struct amdgpu_ctx, refcount); 12647f38501SChristian König 12747f38501SChristian König amdgpu_ctx_fini(ctx); 12847f38501SChristian König 12947f38501SChristian König kfree(ctx); 13047f38501SChristian König } 13147f38501SChristian König 13247f38501SChristian König static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 13347f38501SChristian König { 13423ca0e4eSChunming Zhou struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 13547f38501SChristian König struct amdgpu_ctx *ctx; 13647f38501SChristian König 1370147ee0fSMarek Olšák mutex_lock(&mgr->lock); 138d38ceaf9SAlex Deucher ctx = idr_find(&mgr->ctx_handles, id); 139d38ceaf9SAlex Deucher if (ctx) { 1400b492a4cSAlex Deucher idr_remove(&mgr->ctx_handles, id); 141f11358daSMarek Olšák kref_put(&ctx->refcount, amdgpu_ctx_do_release); 1420147ee0fSMarek Olšák mutex_unlock(&mgr->lock); 143f11358daSMarek Olšák return 0; 144d38ceaf9SAlex Deucher } 1450147ee0fSMarek Olšák mutex_unlock(&mgr->lock); 146d38ceaf9SAlex Deucher return -EINVAL; 147d38ceaf9SAlex Deucher } 148d38ceaf9SAlex Deucher 149d94aed5aSMarek Olšák static int amdgpu_ctx_query(struct amdgpu_device *adev, 150d94aed5aSMarek Olšák struct amdgpu_fpriv *fpriv, uint32_t id, 151d94aed5aSMarek Olšák union drm_amdgpu_ctx_out *out) 152d38ceaf9SAlex Deucher { 153d38ceaf9SAlex Deucher struct amdgpu_ctx *ctx; 15423ca0e4eSChunming Zhou struct amdgpu_ctx_mgr *mgr; 155d94aed5aSMarek Olšák unsigned reset_counter; 156d38ceaf9SAlex Deucher 15723ca0e4eSChunming Zhou if (!fpriv) 15823ca0e4eSChunming Zhou return -EINVAL; 15923ca0e4eSChunming Zhou 16023ca0e4eSChunming Zhou mgr = &fpriv->ctx_mgr; 1610147ee0fSMarek Olšák mutex_lock(&mgr->lock); 162d38ceaf9SAlex Deucher ctx = idr_find(&mgr->ctx_handles, id); 163d94aed5aSMarek Olšák if (!ctx) { 1640147ee0fSMarek Olšák mutex_unlock(&mgr->lock); 165d38ceaf9SAlex Deucher return -EINVAL; 166d38ceaf9SAlex Deucher } 167d38ceaf9SAlex Deucher 168d94aed5aSMarek Olšák /* TODO: these two are always zero */ 1690b492a4cSAlex Deucher out->state.flags = 0x0; 1700b492a4cSAlex Deucher out->state.hangs = 0x0; 171d94aed5aSMarek Olšák 172d94aed5aSMarek Olšák /* determine if a GPU reset has occured since the last call */ 173d94aed5aSMarek Olšák reset_counter = atomic_read(&adev->gpu_reset_counter); 174d94aed5aSMarek Olšák /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 175d94aed5aSMarek Olšák if (ctx->reset_counter == reset_counter) 176d94aed5aSMarek Olšák out->state.reset_status = AMDGPU_CTX_NO_RESET; 177d94aed5aSMarek Olšák else 178d94aed5aSMarek Olšák out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 179d94aed5aSMarek Olšák ctx->reset_counter = reset_counter; 180d94aed5aSMarek Olšák 181d94aed5aSMarek Olšák mutex_unlock(&mgr->lock); 182d94aed5aSMarek Olšák return 0; 183d94aed5aSMarek Olšák } 184d94aed5aSMarek Olšák 185d38ceaf9SAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 186d38ceaf9SAlex Deucher struct drm_file *filp) 187d38ceaf9SAlex Deucher { 188d38ceaf9SAlex Deucher int r; 189d38ceaf9SAlex Deucher uint32_t id; 190d38ceaf9SAlex Deucher 191d38ceaf9SAlex Deucher union drm_amdgpu_ctx *args = data; 192d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 193d38ceaf9SAlex Deucher struct amdgpu_fpriv *fpriv = filp->driver_priv; 194d38ceaf9SAlex Deucher 195d38ceaf9SAlex Deucher r = 0; 196d38ceaf9SAlex Deucher id = args->in.ctx_id; 197d38ceaf9SAlex Deucher 198d38ceaf9SAlex Deucher switch (args->in.op) { 199d38ceaf9SAlex Deucher case AMDGPU_CTX_OP_ALLOC_CTX: 2000b492a4cSAlex Deucher r = amdgpu_ctx_alloc(adev, fpriv, &id); 201d38ceaf9SAlex Deucher args->out.alloc.ctx_id = id; 202d38ceaf9SAlex Deucher break; 203d38ceaf9SAlex Deucher case AMDGPU_CTX_OP_FREE_CTX: 20447f38501SChristian König r = amdgpu_ctx_free(fpriv, id); 205d38ceaf9SAlex Deucher break; 206d38ceaf9SAlex Deucher case AMDGPU_CTX_OP_QUERY_STATE: 207d94aed5aSMarek Olšák r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 208d38ceaf9SAlex Deucher break; 209d38ceaf9SAlex Deucher default: 210d38ceaf9SAlex Deucher return -EINVAL; 211d38ceaf9SAlex Deucher } 212d38ceaf9SAlex Deucher 213d38ceaf9SAlex Deucher return r; 214d38ceaf9SAlex Deucher } 21566b3cf2aSJammy Zhou 21666b3cf2aSJammy Zhou struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 21766b3cf2aSJammy Zhou { 21866b3cf2aSJammy Zhou struct amdgpu_ctx *ctx; 21923ca0e4eSChunming Zhou struct amdgpu_ctx_mgr *mgr; 22023ca0e4eSChunming Zhou 22123ca0e4eSChunming Zhou if (!fpriv) 22223ca0e4eSChunming Zhou return NULL; 22323ca0e4eSChunming Zhou 22423ca0e4eSChunming Zhou mgr = &fpriv->ctx_mgr; 22566b3cf2aSJammy Zhou 22666b3cf2aSJammy Zhou mutex_lock(&mgr->lock); 22766b3cf2aSJammy Zhou ctx = idr_find(&mgr->ctx_handles, id); 22866b3cf2aSJammy Zhou if (ctx) 22966b3cf2aSJammy Zhou kref_get(&ctx->refcount); 23066b3cf2aSJammy Zhou mutex_unlock(&mgr->lock); 23166b3cf2aSJammy Zhou return ctx; 23266b3cf2aSJammy Zhou } 23366b3cf2aSJammy Zhou 23466b3cf2aSJammy Zhou int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 23566b3cf2aSJammy Zhou { 23666b3cf2aSJammy Zhou if (ctx == NULL) 23766b3cf2aSJammy Zhou return -EINVAL; 23866b3cf2aSJammy Zhou 23966b3cf2aSJammy Zhou kref_put(&ctx->refcount, amdgpu_ctx_do_release); 24066b3cf2aSJammy Zhou return 0; 24166b3cf2aSJammy Zhou } 24221c16bf6SChristian König 24321c16bf6SChristian König uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 244f54d1867SChris Wilson struct dma_fence *fence) 24521c16bf6SChristian König { 24621c16bf6SChristian König struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 247ce882e6dSChristian König uint64_t seq = cring->sequence; 248b43a9a7eSChunming Zhou unsigned idx = 0; 249f54d1867SChris Wilson struct dma_fence *other = NULL; 25021c16bf6SChristian König 2515b011235SChunming Zhou idx = seq & (amdgpu_sched_jobs - 1); 252b43a9a7eSChunming Zhou other = cring->fences[idx]; 25321c16bf6SChristian König if (other) { 25421c16bf6SChristian König signed long r; 255f54d1867SChris Wilson r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); 25621c16bf6SChristian König if (r < 0) 25721c16bf6SChristian König DRM_ERROR("Error (%ld) waiting for fence!\n", r); 25821c16bf6SChristian König } 25921c16bf6SChristian König 260f54d1867SChris Wilson dma_fence_get(fence); 26121c16bf6SChristian König 26221c16bf6SChristian König spin_lock(&ctx->ring_lock); 26321c16bf6SChristian König cring->fences[idx] = fence; 26421c16bf6SChristian König cring->sequence++; 26521c16bf6SChristian König spin_unlock(&ctx->ring_lock); 26621c16bf6SChristian König 267f54d1867SChris Wilson dma_fence_put(other); 26821c16bf6SChristian König 26921c16bf6SChristian König return seq; 27021c16bf6SChristian König } 27121c16bf6SChristian König 272f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 27321c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq) 27421c16bf6SChristian König { 27521c16bf6SChristian König struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 276f54d1867SChris Wilson struct dma_fence *fence; 27721c16bf6SChristian König 27821c16bf6SChristian König spin_lock(&ctx->ring_lock); 279b43a9a7eSChunming Zhou 280ce882e6dSChristian König if (seq >= cring->sequence) { 28121c16bf6SChristian König spin_unlock(&ctx->ring_lock); 28221c16bf6SChristian König return ERR_PTR(-EINVAL); 28321c16bf6SChristian König } 28421c16bf6SChristian König 285b43a9a7eSChunming Zhou 28637cd0ca2SChunming Zhou if (seq + amdgpu_sched_jobs < cring->sequence) { 28721c16bf6SChristian König spin_unlock(&ctx->ring_lock); 28821c16bf6SChristian König return NULL; 28921c16bf6SChristian König } 29021c16bf6SChristian König 291f54d1867SChris Wilson fence = dma_fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]); 29221c16bf6SChristian König spin_unlock(&ctx->ring_lock); 29321c16bf6SChristian König 29421c16bf6SChristian König return fence; 29521c16bf6SChristian König } 296efd4ccb5SChristian König 297efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 298efd4ccb5SChristian König { 299efd4ccb5SChristian König mutex_init(&mgr->lock); 300efd4ccb5SChristian König idr_init(&mgr->ctx_handles); 301efd4ccb5SChristian König } 302efd4ccb5SChristian König 303efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 304efd4ccb5SChristian König { 305efd4ccb5SChristian König struct amdgpu_ctx *ctx; 306efd4ccb5SChristian König struct idr *idp; 307efd4ccb5SChristian König uint32_t id; 308efd4ccb5SChristian König 309efd4ccb5SChristian König idp = &mgr->ctx_handles; 310efd4ccb5SChristian König 311efd4ccb5SChristian König idr_for_each_entry(idp, ctx, id) { 312efd4ccb5SChristian König if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) 313efd4ccb5SChristian König DRM_ERROR("ctx %p is still alive\n", ctx); 314efd4ccb5SChristian König } 315efd4ccb5SChristian König 316efd4ccb5SChristian König idr_destroy(&mgr->ctx_handles); 317efd4ccb5SChristian König mutex_destroy(&mgr->lock); 318efd4ccb5SChristian König } 319