1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2015 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * 4d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 7d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10d38ceaf9SAlex Deucher * 11d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 12d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 13d38ceaf9SAlex Deucher * 14d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21d38ceaf9SAlex Deucher * 22d38ceaf9SAlex Deucher * Authors: monk liu <monk.liu@amd.com> 23d38ceaf9SAlex Deucher */ 24d38ceaf9SAlex Deucher 25d38ceaf9SAlex Deucher #include <drm/drmP.h> 26d38ceaf9SAlex Deucher #include "amdgpu.h" 27d38ceaf9SAlex Deucher 2820874179SChristian König static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) 29d38ceaf9SAlex Deucher { 3047f38501SChristian König unsigned i, j; 3147f38501SChristian König int r; 3247f38501SChristian König 33d38ceaf9SAlex Deucher memset(ctx, 0, sizeof(*ctx)); 349cb7e5a9SChunming Zhou ctx->adev = adev; 35d38ceaf9SAlex Deucher kref_init(&ctx->refcount); 3621c16bf6SChristian König spin_lock_init(&ctx->ring_lock); 37a750b47eSChristian König ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, 38f54d1867SChris Wilson sizeof(struct dma_fence*), GFP_KERNEL); 3937cd0ca2SChunming Zhou if (!ctx->fences) 4037cd0ca2SChunming Zhou return -ENOMEM; 4123ca0e4eSChunming Zhou 4237cd0ca2SChunming Zhou for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 4337cd0ca2SChunming Zhou ctx->rings[i].sequence = 1; 44a750b47eSChristian König ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; 4537cd0ca2SChunming Zhou } 46ce199ad6SNicolai Hähnle 47ce199ad6SNicolai Hähnle ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); 48ce199ad6SNicolai Hähnle 499cb7e5a9SChunming Zhou /* create context entity for each ring */ 509cb7e5a9SChunming Zhou for (i = 0; i < adev->num_rings; i++) { 5120874179SChristian König struct amdgpu_ring *ring = adev->rings[i]; 52432a4ff8SChristian König struct amd_sched_rq *rq; 5320874179SChristian König 5420874179SChristian König rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 5575fbed20SMonk Liu 5675fbed20SMonk Liu if (ring == &adev->gfx.kiq.ring) 5775fbed20SMonk Liu continue; 5875fbed20SMonk Liu 5920874179SChristian König r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, 60ddf94d33SChristian König rq, amdgpu_sched_jobs); 619cb7e5a9SChunming Zhou if (r) 628ed8147aSHuang Rui goto failed; 639cb7e5a9SChunming Zhou } 649cb7e5a9SChunming Zhou 65effd924dSAndres Rodriguez r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr); 66effd924dSAndres Rodriguez if (r) 67effd924dSAndres Rodriguez goto failed; 68effd924dSAndres Rodriguez 698ed8147aSHuang Rui return 0; 708ed8147aSHuang Rui 718ed8147aSHuang Rui failed: 729cb7e5a9SChunming Zhou for (j = 0; j < i; j++) 734f839a24SChristian König amd_sched_entity_fini(&adev->rings[j]->sched, 7491404fb2SChristian König &ctx->rings[j].entity); 7537cd0ca2SChunming Zhou kfree(ctx->fences); 7654ddf3a6SGrazvydas Ignotas ctx->fences = NULL; 7747f38501SChristian König return r; 789cb7e5a9SChunming Zhou } 79d38ceaf9SAlex Deucher 8020874179SChristian König static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) 8147f38501SChristian König { 8247f38501SChristian König struct amdgpu_device *adev = ctx->adev; 8347f38501SChristian König unsigned i, j; 8447f38501SChristian König 85fe295b27SDave Airlie if (!adev) 86fe295b27SDave Airlie return; 87fe295b27SDave Airlie 8847f38501SChristian König for (i = 0; i < AMDGPU_MAX_RINGS; ++i) 8937cd0ca2SChunming Zhou for (j = 0; j < amdgpu_sched_jobs; ++j) 90f54d1867SChris Wilson dma_fence_put(ctx->rings[i].fences[j]); 9137cd0ca2SChunming Zhou kfree(ctx->fences); 9254ddf3a6SGrazvydas Ignotas ctx->fences = NULL; 9347f38501SChristian König 9447f38501SChristian König for (i = 0; i < adev->num_rings; i++) 954f839a24SChristian König amd_sched_entity_fini(&adev->rings[i]->sched, 9691404fb2SChristian König &ctx->rings[i].entity); 97effd924dSAndres Rodriguez 98effd924dSAndres Rodriguez amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr); 9947f38501SChristian König } 10047f38501SChristian König 10147f38501SChristian König static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 10247f38501SChristian König struct amdgpu_fpriv *fpriv, 10347f38501SChristian König uint32_t *id) 10447f38501SChristian König { 10547f38501SChristian König struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 10647f38501SChristian König struct amdgpu_ctx *ctx; 10747f38501SChristian König int r; 10847f38501SChristian König 10947f38501SChristian König ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 11047f38501SChristian König if (!ctx) 11147f38501SChristian König return -ENOMEM; 11247f38501SChristian König 11347f38501SChristian König mutex_lock(&mgr->lock); 11447f38501SChristian König r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL); 11547f38501SChristian König if (r < 0) { 11647f38501SChristian König mutex_unlock(&mgr->lock); 11747f38501SChristian König kfree(ctx); 11847f38501SChristian König return r; 11947f38501SChristian König } 12047f38501SChristian König *id = (uint32_t)r; 12120874179SChristian König r = amdgpu_ctx_init(adev, ctx); 122c648ed7cSChunming Zhou if (r) { 123c648ed7cSChunming Zhou idr_remove(&mgr->ctx_handles, *id); 124c648ed7cSChunming Zhou *id = 0; 125c648ed7cSChunming Zhou kfree(ctx); 126c648ed7cSChunming Zhou } 12747f38501SChristian König mutex_unlock(&mgr->lock); 12847f38501SChristian König return r; 12947f38501SChristian König } 13047f38501SChristian König 13147f38501SChristian König static void amdgpu_ctx_do_release(struct kref *ref) 132d38ceaf9SAlex Deucher { 133d38ceaf9SAlex Deucher struct amdgpu_ctx *ctx; 134d38ceaf9SAlex Deucher 13547f38501SChristian König ctx = container_of(ref, struct amdgpu_ctx, refcount); 13647f38501SChristian König 13747f38501SChristian König amdgpu_ctx_fini(ctx); 13847f38501SChristian König 13947f38501SChristian König kfree(ctx); 14047f38501SChristian König } 14147f38501SChristian König 14247f38501SChristian König static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 14347f38501SChristian König { 14423ca0e4eSChunming Zhou struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 14547f38501SChristian König struct amdgpu_ctx *ctx; 14647f38501SChristian König 1470147ee0fSMarek Olšák mutex_lock(&mgr->lock); 148d3e709e6SMatthew Wilcox ctx = idr_remove(&mgr->ctx_handles, id); 149d3e709e6SMatthew Wilcox if (ctx) 150f11358daSMarek Olšák kref_put(&ctx->refcount, amdgpu_ctx_do_release); 1510147ee0fSMarek Olšák mutex_unlock(&mgr->lock); 152d3e709e6SMatthew Wilcox return ctx ? 0 : -EINVAL; 153d38ceaf9SAlex Deucher } 154d38ceaf9SAlex Deucher 155d94aed5aSMarek Olšák static int amdgpu_ctx_query(struct amdgpu_device *adev, 156d94aed5aSMarek Olšák struct amdgpu_fpriv *fpriv, uint32_t id, 157d94aed5aSMarek Olšák union drm_amdgpu_ctx_out *out) 158d38ceaf9SAlex Deucher { 159d38ceaf9SAlex Deucher struct amdgpu_ctx *ctx; 16023ca0e4eSChunming Zhou struct amdgpu_ctx_mgr *mgr; 161d94aed5aSMarek Olšák unsigned reset_counter; 162d38ceaf9SAlex Deucher 16323ca0e4eSChunming Zhou if (!fpriv) 16423ca0e4eSChunming Zhou return -EINVAL; 16523ca0e4eSChunming Zhou 16623ca0e4eSChunming Zhou mgr = &fpriv->ctx_mgr; 1670147ee0fSMarek Olšák mutex_lock(&mgr->lock); 168d38ceaf9SAlex Deucher ctx = idr_find(&mgr->ctx_handles, id); 169d94aed5aSMarek Olšák if (!ctx) { 1700147ee0fSMarek Olšák mutex_unlock(&mgr->lock); 171d38ceaf9SAlex Deucher return -EINVAL; 172d38ceaf9SAlex Deucher } 173d38ceaf9SAlex Deucher 174d94aed5aSMarek Olšák /* TODO: these two are always zero */ 1750b492a4cSAlex Deucher out->state.flags = 0x0; 1760b492a4cSAlex Deucher out->state.hangs = 0x0; 177d94aed5aSMarek Olšák 178d94aed5aSMarek Olšák /* determine if a GPU reset has occured since the last call */ 179d94aed5aSMarek Olšák reset_counter = atomic_read(&adev->gpu_reset_counter); 180d94aed5aSMarek Olšák /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 181d94aed5aSMarek Olšák if (ctx->reset_counter == reset_counter) 182d94aed5aSMarek Olšák out->state.reset_status = AMDGPU_CTX_NO_RESET; 183d94aed5aSMarek Olšák else 184d94aed5aSMarek Olšák out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 185d94aed5aSMarek Olšák ctx->reset_counter = reset_counter; 186d94aed5aSMarek Olšák 187d94aed5aSMarek Olšák mutex_unlock(&mgr->lock); 188d94aed5aSMarek Olšák return 0; 189d94aed5aSMarek Olšák } 190d94aed5aSMarek Olšák 191d38ceaf9SAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 192d38ceaf9SAlex Deucher struct drm_file *filp) 193d38ceaf9SAlex Deucher { 194d38ceaf9SAlex Deucher int r; 195d38ceaf9SAlex Deucher uint32_t id; 196d38ceaf9SAlex Deucher 197d38ceaf9SAlex Deucher union drm_amdgpu_ctx *args = data; 198d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 199d38ceaf9SAlex Deucher struct amdgpu_fpriv *fpriv = filp->driver_priv; 200d38ceaf9SAlex Deucher 201d38ceaf9SAlex Deucher r = 0; 202d38ceaf9SAlex Deucher id = args->in.ctx_id; 203d38ceaf9SAlex Deucher 204d38ceaf9SAlex Deucher switch (args->in.op) { 205d38ceaf9SAlex Deucher case AMDGPU_CTX_OP_ALLOC_CTX: 2060b492a4cSAlex Deucher r = amdgpu_ctx_alloc(adev, fpriv, &id); 207d38ceaf9SAlex Deucher args->out.alloc.ctx_id = id; 208d38ceaf9SAlex Deucher break; 209d38ceaf9SAlex Deucher case AMDGPU_CTX_OP_FREE_CTX: 21047f38501SChristian König r = amdgpu_ctx_free(fpriv, id); 211d38ceaf9SAlex Deucher break; 212d38ceaf9SAlex Deucher case AMDGPU_CTX_OP_QUERY_STATE: 213d94aed5aSMarek Olšák r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 214d38ceaf9SAlex Deucher break; 215d38ceaf9SAlex Deucher default: 216d38ceaf9SAlex Deucher return -EINVAL; 217d38ceaf9SAlex Deucher } 218d38ceaf9SAlex Deucher 219d38ceaf9SAlex Deucher return r; 220d38ceaf9SAlex Deucher } 22166b3cf2aSJammy Zhou 22266b3cf2aSJammy Zhou struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 22366b3cf2aSJammy Zhou { 22466b3cf2aSJammy Zhou struct amdgpu_ctx *ctx; 22523ca0e4eSChunming Zhou struct amdgpu_ctx_mgr *mgr; 22623ca0e4eSChunming Zhou 22723ca0e4eSChunming Zhou if (!fpriv) 22823ca0e4eSChunming Zhou return NULL; 22923ca0e4eSChunming Zhou 23023ca0e4eSChunming Zhou mgr = &fpriv->ctx_mgr; 23166b3cf2aSJammy Zhou 23266b3cf2aSJammy Zhou mutex_lock(&mgr->lock); 23366b3cf2aSJammy Zhou ctx = idr_find(&mgr->ctx_handles, id); 23466b3cf2aSJammy Zhou if (ctx) 23566b3cf2aSJammy Zhou kref_get(&ctx->refcount); 23666b3cf2aSJammy Zhou mutex_unlock(&mgr->lock); 23766b3cf2aSJammy Zhou return ctx; 23866b3cf2aSJammy Zhou } 23966b3cf2aSJammy Zhou 24066b3cf2aSJammy Zhou int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 24166b3cf2aSJammy Zhou { 24266b3cf2aSJammy Zhou if (ctx == NULL) 24366b3cf2aSJammy Zhou return -EINVAL; 24466b3cf2aSJammy Zhou 24566b3cf2aSJammy Zhou kref_put(&ctx->refcount, amdgpu_ctx_do_release); 24666b3cf2aSJammy Zhou return 0; 24766b3cf2aSJammy Zhou } 24821c16bf6SChristian König 249eb01abc7SMonk Liu int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 250eb01abc7SMonk Liu struct dma_fence *fence, uint64_t* handler) 25121c16bf6SChristian König { 25221c16bf6SChristian König struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 253ce882e6dSChristian König uint64_t seq = cring->sequence; 254b43a9a7eSChunming Zhou unsigned idx = 0; 255f54d1867SChris Wilson struct dma_fence *other = NULL; 25621c16bf6SChristian König 2575b011235SChunming Zhou idx = seq & (amdgpu_sched_jobs - 1); 258b43a9a7eSChunming Zhou other = cring->fences[idx]; 25921c16bf6SChristian König if (other) { 26021c16bf6SChristian König signed long r; 261eb01abc7SMonk Liu r = dma_fence_wait_timeout(other, true, MAX_SCHEDULE_TIMEOUT); 26221c16bf6SChristian König if (r < 0) 263eb01abc7SMonk Liu return r; 26421c16bf6SChristian König } 26521c16bf6SChristian König 266f54d1867SChris Wilson dma_fence_get(fence); 26721c16bf6SChristian König 26821c16bf6SChristian König spin_lock(&ctx->ring_lock); 26921c16bf6SChristian König cring->fences[idx] = fence; 27021c16bf6SChristian König cring->sequence++; 27121c16bf6SChristian König spin_unlock(&ctx->ring_lock); 27221c16bf6SChristian König 273f54d1867SChris Wilson dma_fence_put(other); 274eb01abc7SMonk Liu if (handler) 275eb01abc7SMonk Liu *handler = seq; 27621c16bf6SChristian König 277eb01abc7SMonk Liu return 0; 27821c16bf6SChristian König } 27921c16bf6SChristian König 280f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 28121c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq) 28221c16bf6SChristian König { 28321c16bf6SChristian König struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 284f54d1867SChris Wilson struct dma_fence *fence; 28521c16bf6SChristian König 28621c16bf6SChristian König spin_lock(&ctx->ring_lock); 287b43a9a7eSChunming Zhou 288d7b1eeb2SMonk Liu if (seq == ~0ull) 289d7b1eeb2SMonk Liu seq = ctx->rings[ring->idx].sequence - 1; 290d7b1eeb2SMonk Liu 291ce882e6dSChristian König if (seq >= cring->sequence) { 29221c16bf6SChristian König spin_unlock(&ctx->ring_lock); 29321c16bf6SChristian König return ERR_PTR(-EINVAL); 29421c16bf6SChristian König } 29521c16bf6SChristian König 296b43a9a7eSChunming Zhou 29737cd0ca2SChunming Zhou if (seq + amdgpu_sched_jobs < cring->sequence) { 29821c16bf6SChristian König spin_unlock(&ctx->ring_lock); 29921c16bf6SChristian König return NULL; 30021c16bf6SChristian König } 30121c16bf6SChristian König 302f54d1867SChris Wilson fence = dma_fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]); 30321c16bf6SChristian König spin_unlock(&ctx->ring_lock); 30421c16bf6SChristian König 30521c16bf6SChristian König return fence; 30621c16bf6SChristian König } 307efd4ccb5SChristian König 308efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 309efd4ccb5SChristian König { 310efd4ccb5SChristian König mutex_init(&mgr->lock); 311efd4ccb5SChristian König idr_init(&mgr->ctx_handles); 312efd4ccb5SChristian König } 313efd4ccb5SChristian König 314efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 315efd4ccb5SChristian König { 316efd4ccb5SChristian König struct amdgpu_ctx *ctx; 317efd4ccb5SChristian König struct idr *idp; 318efd4ccb5SChristian König uint32_t id; 319efd4ccb5SChristian König 320efd4ccb5SChristian König idp = &mgr->ctx_handles; 321efd4ccb5SChristian König 322efd4ccb5SChristian König idr_for_each_entry(idp, ctx, id) { 323efd4ccb5SChristian König if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) 324efd4ccb5SChristian König DRM_ERROR("ctx %p is still alive\n", ctx); 325efd4ccb5SChristian König } 326efd4ccb5SChristian König 327efd4ccb5SChristian König idr_destroy(&mgr->ctx_handles); 328efd4ccb5SChristian König mutex_destroy(&mgr->lock); 329efd4ccb5SChristian König } 330