1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include <linux/list_sort.h> 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 33 #define AMDGPU_CS_MAX_PRIORITY 32u 34 #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1) 35 36 /* This is based on the bucket sort with O(n) time complexity. 37 * An item with priority "i" is added to bucket[i]. The lists are then 38 * concatenated in descending order. 39 */ 40 struct amdgpu_cs_buckets { 41 struct list_head bucket[AMDGPU_CS_NUM_BUCKETS]; 42 }; 43 44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b) 45 { 46 unsigned i; 47 48 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) 49 INIT_LIST_HEAD(&b->bucket[i]); 50 } 51 52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b, 53 struct list_head *item, unsigned priority) 54 { 55 /* Since buffers which appear sooner in the relocation list are 56 * likely to be used more often than buffers which appear later 57 * in the list, the sort mustn't change the ordering of buffers 58 * with the same priority, i.e. it must be stable. 59 */ 60 list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]); 61 } 62 63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b, 64 struct list_head *out_list) 65 { 66 unsigned i; 67 68 /* Connect the sorted buckets in the output list. */ 69 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) { 70 list_splice(&b->bucket[i], out_list); 71 } 72 } 73 74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 75 u32 ip_instance, u32 ring, 76 struct amdgpu_ring **out_ring) 77 { 78 /* Right now all IPs have only one instance - multiple rings. */ 79 if (ip_instance != 0) { 80 DRM_ERROR("invalid ip instance: %d\n", ip_instance); 81 return -EINVAL; 82 } 83 84 switch (ip_type) { 85 default: 86 DRM_ERROR("unknown ip type: %d\n", ip_type); 87 return -EINVAL; 88 case AMDGPU_HW_IP_GFX: 89 if (ring < adev->gfx.num_gfx_rings) { 90 *out_ring = &adev->gfx.gfx_ring[ring]; 91 } else { 92 DRM_ERROR("only %d gfx rings are supported now\n", 93 adev->gfx.num_gfx_rings); 94 return -EINVAL; 95 } 96 break; 97 case AMDGPU_HW_IP_COMPUTE: 98 if (ring < adev->gfx.num_compute_rings) { 99 *out_ring = &adev->gfx.compute_ring[ring]; 100 } else { 101 DRM_ERROR("only %d compute rings are supported now\n", 102 adev->gfx.num_compute_rings); 103 return -EINVAL; 104 } 105 break; 106 case AMDGPU_HW_IP_DMA: 107 if (ring < 2) { 108 *out_ring = &adev->sdma[ring].ring; 109 } else { 110 DRM_ERROR("only two SDMA rings are supported\n"); 111 return -EINVAL; 112 } 113 break; 114 case AMDGPU_HW_IP_UVD: 115 *out_ring = &adev->uvd.ring; 116 break; 117 case AMDGPU_HW_IP_VCE: 118 if (ring < 2){ 119 *out_ring = &adev->vce.ring[ring]; 120 } else { 121 DRM_ERROR("only two VCE rings are supported\n"); 122 return -EINVAL; 123 } 124 break; 125 } 126 return 0; 127 } 128 129 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 130 struct drm_file *filp, 131 struct amdgpu_ctx *ctx, 132 struct amdgpu_ib *ibs, 133 uint32_t num_ibs) 134 { 135 struct amdgpu_cs_parser *parser; 136 int i; 137 138 parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL); 139 if (!parser) 140 return NULL; 141 142 parser->adev = adev; 143 parser->filp = filp; 144 parser->ctx = ctx; 145 parser->ibs = ibs; 146 parser->num_ibs = num_ibs; 147 for (i = 0; i < num_ibs; i++) 148 ibs[i].ctx = ctx; 149 150 return parser; 151 } 152 153 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 154 { 155 union drm_amdgpu_cs *cs = data; 156 uint64_t *chunk_array_user; 157 uint64_t *chunk_array; 158 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 159 unsigned size, i; 160 int ret; 161 162 if (cs->in.num_chunks == 0) 163 return 0; 164 165 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); 166 if (!chunk_array) 167 return -ENOMEM; 168 169 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); 170 if (!p->ctx) { 171 ret = -EINVAL; 172 goto free_chunk; 173 } 174 175 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); 176 177 /* get chunks */ 178 INIT_LIST_HEAD(&p->validated); 179 chunk_array_user = (uint64_t __user *)(cs->in.chunks); 180 if (copy_from_user(chunk_array, chunk_array_user, 181 sizeof(uint64_t)*cs->in.num_chunks)) { 182 ret = -EFAULT; 183 goto put_bo_list; 184 } 185 186 p->nchunks = cs->in.num_chunks; 187 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), 188 GFP_KERNEL); 189 if (!p->chunks) { 190 ret = -ENOMEM; 191 goto put_bo_list; 192 } 193 194 for (i = 0; i < p->nchunks; i++) { 195 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; 196 struct drm_amdgpu_cs_chunk user_chunk; 197 uint32_t __user *cdata; 198 199 chunk_ptr = (void __user *)chunk_array[i]; 200 if (copy_from_user(&user_chunk, chunk_ptr, 201 sizeof(struct drm_amdgpu_cs_chunk))) { 202 ret = -EFAULT; 203 i--; 204 goto free_partial_kdata; 205 } 206 p->chunks[i].chunk_id = user_chunk.chunk_id; 207 p->chunks[i].length_dw = user_chunk.length_dw; 208 209 size = p->chunks[i].length_dw; 210 cdata = (void __user *)user_chunk.chunk_data; 211 p->chunks[i].user_ptr = cdata; 212 213 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); 214 if (p->chunks[i].kdata == NULL) { 215 ret = -ENOMEM; 216 i--; 217 goto free_partial_kdata; 218 } 219 size *= sizeof(uint32_t); 220 if (copy_from_user(p->chunks[i].kdata, cdata, size)) { 221 ret = -EFAULT; 222 goto free_partial_kdata; 223 } 224 225 switch (p->chunks[i].chunk_id) { 226 case AMDGPU_CHUNK_ID_IB: 227 p->num_ibs++; 228 break; 229 230 case AMDGPU_CHUNK_ID_FENCE: 231 size = sizeof(struct drm_amdgpu_cs_chunk_fence); 232 if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) { 233 uint32_t handle; 234 struct drm_gem_object *gobj; 235 struct drm_amdgpu_cs_chunk_fence *fence_data; 236 237 fence_data = (void *)p->chunks[i].kdata; 238 handle = fence_data->handle; 239 gobj = drm_gem_object_lookup(p->adev->ddev, 240 p->filp, handle); 241 if (gobj == NULL) { 242 ret = -EINVAL; 243 goto free_partial_kdata; 244 } 245 246 p->uf.bo = gem_to_amdgpu_bo(gobj); 247 p->uf.offset = fence_data->offset; 248 } else { 249 ret = -EINVAL; 250 goto free_partial_kdata; 251 } 252 break; 253 254 case AMDGPU_CHUNK_ID_DEPENDENCIES: 255 break; 256 257 default: 258 ret = -EINVAL; 259 goto free_partial_kdata; 260 } 261 } 262 263 264 p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); 265 if (!p->ibs) { 266 ret = -ENOMEM; 267 goto free_all_kdata; 268 } 269 270 kfree(chunk_array); 271 return 0; 272 273 free_all_kdata: 274 i = p->nchunks - 1; 275 free_partial_kdata: 276 for (; i >= 0; i--) 277 drm_free_large(p->chunks[i].kdata); 278 kfree(p->chunks); 279 put_bo_list: 280 if (p->bo_list) 281 amdgpu_bo_list_put(p->bo_list); 282 amdgpu_ctx_put(p->ctx); 283 free_chunk: 284 kfree(chunk_array); 285 286 return ret; 287 } 288 289 /* Returns how many bytes TTM can move per IB. 290 */ 291 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) 292 { 293 u64 real_vram_size = adev->mc.real_vram_size; 294 u64 vram_usage = atomic64_read(&adev->vram_usage); 295 296 /* This function is based on the current VRAM usage. 297 * 298 * - If all of VRAM is free, allow relocating the number of bytes that 299 * is equal to 1/4 of the size of VRAM for this IB. 300 301 * - If more than one half of VRAM is occupied, only allow relocating 302 * 1 MB of data for this IB. 303 * 304 * - From 0 to one half of used VRAM, the threshold decreases 305 * linearly. 306 * __________________ 307 * 1/4 of -|\ | 308 * VRAM | \ | 309 * | \ | 310 * | \ | 311 * | \ | 312 * | \ | 313 * | \ | 314 * | \________|1 MB 315 * |----------------| 316 * VRAM 0 % 100 % 317 * used used 318 * 319 * Note: It's a threshold, not a limit. The threshold must be crossed 320 * for buffer relocations to stop, so any buffer of an arbitrary size 321 * can be moved as long as the threshold isn't crossed before 322 * the relocation takes place. We don't want to disable buffer 323 * relocations completely. 324 * 325 * The idea is that buffers should be placed in VRAM at creation time 326 * and TTM should only do a minimum number of relocations during 327 * command submission. In practice, you need to submit at least 328 * a dozen IBs to move all buffers to VRAM if they are in GTT. 329 * 330 * Also, things can get pretty crazy under memory pressure and actual 331 * VRAM usage can change a lot, so playing safe even at 50% does 332 * consistently increase performance. 333 */ 334 335 u64 half_vram = real_vram_size >> 1; 336 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 337 u64 bytes_moved_threshold = half_free_vram >> 1; 338 return max(bytes_moved_threshold, 1024*1024ull); 339 } 340 341 int amdgpu_cs_list_validate(struct amdgpu_device *adev, 342 struct amdgpu_vm *vm, 343 struct list_head *validated) 344 { 345 struct amdgpu_bo_list_entry *lobj; 346 struct amdgpu_bo *bo; 347 u64 bytes_moved = 0, initial_bytes_moved; 348 u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev); 349 int r; 350 351 list_for_each_entry(lobj, validated, tv.head) { 352 bo = lobj->robj; 353 if (!bo->pin_count) { 354 u32 domain = lobj->prefered_domains; 355 u32 current_domain = 356 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 357 358 /* Check if this buffer will be moved and don't move it 359 * if we have moved too many buffers for this IB already. 360 * 361 * Note that this allows moving at least one buffer of 362 * any size, because it doesn't take the current "bo" 363 * into account. We don't want to disallow buffer moves 364 * completely. 365 */ 366 if ((lobj->allowed_domains & current_domain) != 0 && 367 (domain & current_domain) == 0 && /* will be moved */ 368 bytes_moved > bytes_moved_threshold) { 369 /* don't move it */ 370 domain = current_domain; 371 } 372 373 retry: 374 amdgpu_ttm_placement_from_domain(bo, domain); 375 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); 376 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 377 bytes_moved += atomic64_read(&adev->num_bytes_moved) - 378 initial_bytes_moved; 379 380 if (unlikely(r)) { 381 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) { 382 domain = lobj->allowed_domains; 383 goto retry; 384 } 385 return r; 386 } 387 } 388 lobj->bo_va = amdgpu_vm_bo_find(vm, bo); 389 } 390 return 0; 391 } 392 393 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) 394 { 395 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 396 struct amdgpu_cs_buckets buckets; 397 struct list_head duplicates; 398 bool need_mmap_lock = false; 399 int i, r; 400 401 if (p->bo_list) { 402 need_mmap_lock = p->bo_list->has_userptr; 403 amdgpu_cs_buckets_init(&buckets); 404 for (i = 0; i < p->bo_list->num_entries; i++) 405 amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, 406 p->bo_list->array[i].priority); 407 408 amdgpu_cs_buckets_get_list(&buckets, &p->validated); 409 } 410 411 p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, 412 &p->validated); 413 414 if (need_mmap_lock) 415 down_read(¤t->mm->mmap_sem); 416 417 INIT_LIST_HEAD(&duplicates); 418 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); 419 if (unlikely(r != 0)) 420 goto error_reserve; 421 422 r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated); 423 if (r) 424 goto error_validate; 425 426 r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates); 427 428 error_validate: 429 if (r) 430 ttm_eu_backoff_reservation(&p->ticket, &p->validated); 431 432 error_reserve: 433 if (need_mmap_lock) 434 up_read(¤t->mm->mmap_sem); 435 436 return r; 437 } 438 439 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) 440 { 441 struct amdgpu_bo_list_entry *e; 442 int r; 443 444 list_for_each_entry(e, &p->validated, tv.head) { 445 struct reservation_object *resv = e->robj->tbo.resv; 446 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); 447 448 if (r) 449 return r; 450 } 451 return 0; 452 } 453 454 static int cmp_size_smaller_first(void *priv, struct list_head *a, 455 struct list_head *b) 456 { 457 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); 458 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); 459 460 /* Sort A before B if A is smaller. */ 461 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 462 } 463 464 static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff) 465 { 466 if (!error) { 467 /* Sort the buffer list from the smallest to largest buffer, 468 * which affects the order of buffers in the LRU list. 469 * This assures that the smallest buffers are added first 470 * to the LRU list, so they are likely to be later evicted 471 * first, instead of large buffers whose eviction is more 472 * expensive. 473 * 474 * This slightly lowers the number of bytes moved by TTM 475 * per frame under memory pressure. 476 */ 477 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 478 479 ttm_eu_fence_buffer_objects(&parser->ticket, 480 &parser->validated, 481 &parser->ibs[parser->num_ibs-1].fence->base); 482 } else if (backoff) { 483 ttm_eu_backoff_reservation(&parser->ticket, 484 &parser->validated); 485 } 486 } 487 488 static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser) 489 { 490 unsigned i; 491 if (parser->ctx) 492 amdgpu_ctx_put(parser->ctx); 493 if (parser->bo_list) 494 amdgpu_bo_list_put(parser->bo_list); 495 496 drm_free_large(parser->vm_bos); 497 for (i = 0; i < parser->nchunks; i++) 498 drm_free_large(parser->chunks[i].kdata); 499 kfree(parser->chunks); 500 if (!amdgpu_enable_scheduler) 501 { 502 if (parser->ibs) 503 for (i = 0; i < parser->num_ibs; i++) 504 amdgpu_ib_free(parser->adev, &parser->ibs[i]); 505 kfree(parser->ibs); 506 if (parser->uf.bo) 507 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); 508 } 509 510 kfree(parser); 511 } 512 513 /** 514 * cs_parser_fini() - clean parser states 515 * @parser: parser structure holding parsing context. 516 * @error: error number 517 * 518 * If error is set than unvalidate buffer, otherwise just free memory 519 * used by parsing context. 520 **/ 521 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) 522 { 523 amdgpu_cs_parser_fini_early(parser, error, backoff); 524 amdgpu_cs_parser_fini_late(parser); 525 } 526 527 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, 528 struct amdgpu_vm *vm) 529 { 530 struct amdgpu_device *adev = p->adev; 531 struct amdgpu_bo_va *bo_va; 532 struct amdgpu_bo *bo; 533 int i, r; 534 535 r = amdgpu_vm_update_page_directory(adev, vm); 536 if (r) 537 return r; 538 539 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence); 540 if (r) 541 return r; 542 543 r = amdgpu_vm_clear_freed(adev, vm); 544 if (r) 545 return r; 546 547 if (p->bo_list) { 548 for (i = 0; i < p->bo_list->num_entries; i++) { 549 struct fence *f; 550 551 /* ignore duplicates */ 552 bo = p->bo_list->array[i].robj; 553 if (!bo) 554 continue; 555 556 bo_va = p->bo_list->array[i].bo_va; 557 if (bo_va == NULL) 558 continue; 559 560 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); 561 if (r) 562 return r; 563 564 f = bo_va->last_pt_update; 565 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); 566 if (r) 567 return r; 568 } 569 } 570 571 return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); 572 } 573 574 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 575 struct amdgpu_cs_parser *parser) 576 { 577 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 578 struct amdgpu_vm *vm = &fpriv->vm; 579 struct amdgpu_ring *ring; 580 int i, r; 581 582 if (parser->num_ibs == 0) 583 return 0; 584 585 /* Only for UVD/VCE VM emulation */ 586 for (i = 0; i < parser->num_ibs; i++) { 587 ring = parser->ibs[i].ring; 588 if (ring->funcs->parse_cs) { 589 r = amdgpu_ring_parse_cs(ring, parser, i); 590 if (r) 591 return r; 592 } 593 } 594 595 mutex_lock(&vm->mutex); 596 r = amdgpu_bo_vm_update_pte(parser, vm); 597 if (r) { 598 goto out; 599 } 600 amdgpu_cs_sync_rings(parser); 601 if (!amdgpu_enable_scheduler) 602 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs, 603 parser->filp); 604 605 out: 606 mutex_unlock(&vm->mutex); 607 return r; 608 } 609 610 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) 611 { 612 if (r == -EDEADLK) { 613 r = amdgpu_gpu_reset(adev); 614 if (!r) 615 r = -EAGAIN; 616 } 617 return r; 618 } 619 620 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 621 struct amdgpu_cs_parser *parser) 622 { 623 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 624 struct amdgpu_vm *vm = &fpriv->vm; 625 int i, j; 626 int r; 627 628 for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { 629 struct amdgpu_cs_chunk *chunk; 630 struct amdgpu_ib *ib; 631 struct drm_amdgpu_cs_chunk_ib *chunk_ib; 632 struct amdgpu_ring *ring; 633 634 chunk = &parser->chunks[i]; 635 ib = &parser->ibs[j]; 636 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; 637 638 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) 639 continue; 640 641 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, 642 chunk_ib->ip_instance, chunk_ib->ring, 643 &ring); 644 if (r) 645 return r; 646 647 if (ring->funcs->parse_cs) { 648 struct amdgpu_bo_va_mapping *m; 649 struct amdgpu_bo *aobj = NULL; 650 uint64_t offset; 651 uint8_t *kptr; 652 653 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, 654 &aobj); 655 if (!aobj) { 656 DRM_ERROR("IB va_start is invalid\n"); 657 return -EINVAL; 658 } 659 660 if ((chunk_ib->va_start + chunk_ib->ib_bytes) > 661 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { 662 DRM_ERROR("IB va_start+ib_bytes is invalid\n"); 663 return -EINVAL; 664 } 665 666 /* the IB should be reserved at this point */ 667 r = amdgpu_bo_kmap(aobj, (void **)&kptr); 668 if (r) { 669 return r; 670 } 671 672 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; 673 kptr += chunk_ib->va_start - offset; 674 675 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); 676 if (r) { 677 DRM_ERROR("Failed to get ib !\n"); 678 return r; 679 } 680 681 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); 682 amdgpu_bo_kunmap(aobj); 683 } else { 684 r = amdgpu_ib_get(ring, vm, 0, ib); 685 if (r) { 686 DRM_ERROR("Failed to get ib !\n"); 687 return r; 688 } 689 690 ib->gpu_addr = chunk_ib->va_start; 691 } 692 693 ib->length_dw = chunk_ib->ib_bytes / 4; 694 ib->flags = chunk_ib->flags; 695 ib->ctx = parser->ctx; 696 j++; 697 } 698 699 if (!parser->num_ibs) 700 return 0; 701 702 /* add GDS resources to first IB */ 703 if (parser->bo_list) { 704 struct amdgpu_bo *gds = parser->bo_list->gds_obj; 705 struct amdgpu_bo *gws = parser->bo_list->gws_obj; 706 struct amdgpu_bo *oa = parser->bo_list->oa_obj; 707 struct amdgpu_ib *ib = &parser->ibs[0]; 708 709 if (gds) { 710 ib->gds_base = amdgpu_bo_gpu_offset(gds); 711 ib->gds_size = amdgpu_bo_size(gds); 712 } 713 if (gws) { 714 ib->gws_base = amdgpu_bo_gpu_offset(gws); 715 ib->gws_size = amdgpu_bo_size(gws); 716 } 717 if (oa) { 718 ib->oa_base = amdgpu_bo_gpu_offset(oa); 719 ib->oa_size = amdgpu_bo_size(oa); 720 } 721 } 722 /* wrap the last IB with user fence */ 723 if (parser->uf.bo) { 724 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; 725 726 /* UVD & VCE fw doesn't support user fences */ 727 if (ib->ring->type == AMDGPU_RING_TYPE_UVD || 728 ib->ring->type == AMDGPU_RING_TYPE_VCE) 729 return -EINVAL; 730 731 ib->user = &parser->uf; 732 } 733 734 return 0; 735 } 736 737 static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 738 struct amdgpu_cs_parser *p) 739 { 740 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 741 struct amdgpu_ib *ib; 742 int i, j, r; 743 744 if (!p->num_ibs) 745 return 0; 746 747 /* Add dependencies to first IB */ 748 ib = &p->ibs[0]; 749 for (i = 0; i < p->nchunks; ++i) { 750 struct drm_amdgpu_cs_chunk_dep *deps; 751 struct amdgpu_cs_chunk *chunk; 752 unsigned num_deps; 753 754 chunk = &p->chunks[i]; 755 756 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) 757 continue; 758 759 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; 760 num_deps = chunk->length_dw * 4 / 761 sizeof(struct drm_amdgpu_cs_chunk_dep); 762 763 for (j = 0; j < num_deps; ++j) { 764 struct amdgpu_ring *ring; 765 struct amdgpu_ctx *ctx; 766 struct fence *fence; 767 768 r = amdgpu_cs_get_ring(adev, deps[j].ip_type, 769 deps[j].ip_instance, 770 deps[j].ring, &ring); 771 if (r) 772 return r; 773 774 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); 775 if (ctx == NULL) 776 return -EINVAL; 777 778 fence = amdgpu_ctx_get_fence(ctx, ring, 779 deps[j].handle); 780 if (IS_ERR(fence)) { 781 r = PTR_ERR(fence); 782 amdgpu_ctx_put(ctx); 783 return r; 784 785 } else if (fence) { 786 r = amdgpu_sync_fence(adev, &ib->sync, fence); 787 fence_put(fence); 788 amdgpu_ctx_put(ctx); 789 if (r) 790 return r; 791 } 792 } 793 } 794 795 return 0; 796 } 797 798 static int amdgpu_cs_free_job(struct amdgpu_job *job) 799 { 800 int i; 801 if (job->ibs) 802 for (i = 0; i < job->num_ibs; i++) 803 amdgpu_ib_free(job->adev, &job->ibs[i]); 804 kfree(job->ibs); 805 if (job->uf.bo) 806 drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base); 807 return 0; 808 } 809 810 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 811 { 812 struct amdgpu_device *adev = dev->dev_private; 813 union drm_amdgpu_cs *cs = data; 814 struct amdgpu_cs_parser *parser; 815 bool reserved_buffers = false; 816 int i, r; 817 818 down_read(&adev->exclusive_lock); 819 if (!adev->accel_working) { 820 up_read(&adev->exclusive_lock); 821 return -EBUSY; 822 } 823 824 parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); 825 if (!parser) 826 return -ENOMEM; 827 r = amdgpu_cs_parser_init(parser, data); 828 if (r) { 829 DRM_ERROR("Failed to initialize parser !\n"); 830 kfree(parser); 831 up_read(&adev->exclusive_lock); 832 r = amdgpu_cs_handle_lockup(adev, r); 833 return r; 834 } 835 836 r = amdgpu_cs_parser_relocs(parser); 837 if (r == -ENOMEM) 838 DRM_ERROR("Not enough memory for command submission!\n"); 839 else if (r && r != -ERESTARTSYS) 840 DRM_ERROR("Failed to process the buffer list %d!\n", r); 841 else if (!r) { 842 reserved_buffers = true; 843 r = amdgpu_cs_ib_fill(adev, parser); 844 } 845 846 if (!r) { 847 r = amdgpu_cs_dependencies(adev, parser); 848 if (r) 849 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 850 } 851 852 if (r) 853 goto out; 854 855 for (i = 0; i < parser->num_ibs; i++) 856 trace_amdgpu_cs(parser, i); 857 858 r = amdgpu_cs_ib_vm_chunk(adev, parser); 859 if (r) 860 goto out; 861 862 if (amdgpu_enable_scheduler && parser->num_ibs) { 863 struct amdgpu_job *job; 864 struct amdgpu_ring * ring = parser->ibs->ring; 865 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); 866 if (!job) 867 return -ENOMEM; 868 job->base.sched = &ring->sched; 869 job->base.s_entity = &parser->ctx->rings[ring->idx].entity; 870 job->adev = parser->adev; 871 job->ibs = parser->ibs; 872 job->num_ibs = parser->num_ibs; 873 job->base.owner = parser->filp; 874 mutex_init(&job->job_lock); 875 if (job->ibs[job->num_ibs - 1].user) { 876 memcpy(&job->uf, &parser->uf, 877 sizeof(struct amdgpu_user_fence)); 878 job->ibs[job->num_ibs - 1].user = &job->uf; 879 } 880 881 job->free_job = amdgpu_cs_free_job; 882 mutex_lock(&job->job_lock); 883 r = amd_sched_entity_push_job(&job->base); 884 if (r) { 885 mutex_unlock(&job->job_lock); 886 amdgpu_cs_free_job(job); 887 kfree(job); 888 goto out; 889 } 890 cs->out.handle = 891 amdgpu_ctx_add_fence(parser->ctx, ring, 892 &job->base.s_fence->base); 893 parser->ibs[parser->num_ibs - 1].sequence = cs->out.handle; 894 895 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 896 ttm_eu_fence_buffer_objects(&parser->ticket, 897 &parser->validated, 898 &job->base.s_fence->base); 899 900 mutex_unlock(&job->job_lock); 901 amdgpu_cs_parser_fini_late(parser); 902 up_read(&adev->exclusive_lock); 903 return 0; 904 } 905 906 cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; 907 out: 908 amdgpu_cs_parser_fini(parser, r, reserved_buffers); 909 up_read(&adev->exclusive_lock); 910 r = amdgpu_cs_handle_lockup(adev, r); 911 return r; 912 } 913 914 /** 915 * amdgpu_cs_wait_ioctl - wait for a command submission to finish 916 * 917 * @dev: drm device 918 * @data: data from userspace 919 * @filp: file private 920 * 921 * Wait for the command submission identified by handle to finish. 922 */ 923 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, 924 struct drm_file *filp) 925 { 926 union drm_amdgpu_wait_cs *wait = data; 927 struct amdgpu_device *adev = dev->dev_private; 928 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); 929 struct amdgpu_ring *ring = NULL; 930 struct amdgpu_ctx *ctx; 931 struct fence *fence; 932 long r; 933 934 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, 935 wait->in.ring, &ring); 936 if (r) 937 return r; 938 939 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); 940 if (ctx == NULL) 941 return -EINVAL; 942 943 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); 944 if (IS_ERR(fence)) 945 r = PTR_ERR(fence); 946 else if (fence) { 947 r = fence_wait_timeout(fence, true, timeout); 948 fence_put(fence); 949 } else 950 r = 1; 951 952 amdgpu_ctx_put(ctx); 953 if (r < 0) 954 return r; 955 956 memset(wait, 0, sizeof(*wait)); 957 wait->out.status = (r == 0); 958 959 return 0; 960 } 961 962 /** 963 * amdgpu_cs_find_bo_va - find bo_va for VM address 964 * 965 * @parser: command submission parser context 966 * @addr: VM address 967 * @bo: resulting BO of the mapping found 968 * 969 * Search the buffer objects in the command submission context for a certain 970 * virtual memory address. Returns allocation structure when found, NULL 971 * otherwise. 972 */ 973 struct amdgpu_bo_va_mapping * 974 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 975 uint64_t addr, struct amdgpu_bo **bo) 976 { 977 struct amdgpu_bo_list_entry *reloc; 978 struct amdgpu_bo_va_mapping *mapping; 979 980 addr /= AMDGPU_GPU_PAGE_SIZE; 981 982 list_for_each_entry(reloc, &parser->validated, tv.head) { 983 if (!reloc->bo_va) 984 continue; 985 986 list_for_each_entry(mapping, &reloc->bo_va->valids, list) { 987 if (mapping->it.start > addr || 988 addr > mapping->it.last) 989 continue; 990 991 *bo = reloc->bo_va->bo; 992 return mapping; 993 } 994 995 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) { 996 if (mapping->it.start > addr || 997 addr > mapping->it.last) 998 continue; 999 1000 *bo = reloc->bo_va->bo; 1001 return mapping; 1002 } 1003 } 1004 1005 return NULL; 1006 } 1007