1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73 int saved_dpms = connector->dpms; 74 /* Only turn off the display if it's physically disconnected */ 75 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't try to start link training before we 79 * have the dpcd */ 80 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 return; 82 83 /* set it to OFF so that drm_helper_connector_dpms() 84 * won't return immediately since the current state 85 * is ON at this point. 86 */ 87 connector->dpms = DRM_MODE_DPMS_OFF; 88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89 } 90 connector->dpms = saved_dpms; 91 } 92 } 93 } 94 95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 96 { 97 struct drm_crtc *crtc = encoder->crtc; 98 99 if (crtc && crtc->enabled) { 100 drm_crtc_helper_set_mode(crtc, &crtc->mode, 101 crtc->x, crtc->y, crtc->primary->fb); 102 } 103 } 104 105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 106 { 107 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 108 struct amdgpu_connector_atom_dig *dig_connector; 109 int bpc = 8; 110 unsigned mode_clock, max_tmds_clock; 111 112 switch (connector->connector_type) { 113 case DRM_MODE_CONNECTOR_DVII: 114 case DRM_MODE_CONNECTOR_HDMIB: 115 if (amdgpu_connector->use_digital) { 116 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 117 if (connector->display_info.bpc) 118 bpc = connector->display_info.bpc; 119 } 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DVID: 123 case DRM_MODE_CONNECTOR_HDMIA: 124 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 125 if (connector->display_info.bpc) 126 bpc = connector->display_info.bpc; 127 } 128 break; 129 case DRM_MODE_CONNECTOR_DisplayPort: 130 dig_connector = amdgpu_connector->con_priv; 131 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 132 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 133 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 134 if (connector->display_info.bpc) 135 bpc = connector->display_info.bpc; 136 } 137 break; 138 case DRM_MODE_CONNECTOR_eDP: 139 case DRM_MODE_CONNECTOR_LVDS: 140 if (connector->display_info.bpc) 141 bpc = connector->display_info.bpc; 142 else { 143 const struct drm_connector_helper_funcs *connector_funcs = 144 connector->helper_private; 145 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 146 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 147 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 148 149 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 150 bpc = 6; 151 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 152 bpc = 8; 153 } 154 break; 155 } 156 157 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 158 /* 159 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 160 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 161 * 12 bpc is always supported on hdmi deep color sinks, as this is 162 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 163 */ 164 if (bpc > 12) { 165 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 166 connector->name, bpc); 167 bpc = 12; 168 } 169 170 /* Any defined maximum tmds clock limit we must not exceed? */ 171 if (connector->display_info.max_tmds_clock > 0) { 172 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 173 mode_clock = amdgpu_connector->pixelclock_for_modeset; 174 175 /* Maximum allowable input clock in kHz */ 176 max_tmds_clock = connector->display_info.max_tmds_clock; 177 178 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 179 connector->name, mode_clock, max_tmds_clock); 180 181 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 182 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 183 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 184 (mode_clock * 5/4 <= max_tmds_clock)) 185 bpc = 10; 186 else 187 bpc = 8; 188 189 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 190 connector->name, bpc); 191 } 192 193 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 194 bpc = 8; 195 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 196 connector->name, bpc); 197 } 198 } else if (bpc > 8) { 199 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 200 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 201 connector->name); 202 bpc = 8; 203 } 204 } 205 206 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 207 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 208 connector->name); 209 bpc = 8; 210 } 211 212 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 213 connector->name, connector->display_info.bpc, bpc); 214 215 return bpc; 216 } 217 218 static void 219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 220 enum drm_connector_status status) 221 { 222 struct drm_encoder *best_encoder = NULL; 223 struct drm_encoder *encoder = NULL; 224 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 225 bool connected; 226 int i; 227 228 best_encoder = connector_funcs->best_encoder(connector); 229 230 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 231 if (connector->encoder_ids[i] == 0) 232 break; 233 234 encoder = drm_encoder_find(connector->dev, 235 connector->encoder_ids[i]); 236 if (!encoder) 237 continue; 238 239 if ((encoder == best_encoder) && (status == connector_status_connected)) 240 connected = true; 241 else 242 connected = false; 243 244 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 245 246 } 247 } 248 249 static struct drm_encoder * 250 amdgpu_connector_find_encoder(struct drm_connector *connector, 251 int encoder_type) 252 { 253 struct drm_encoder *encoder; 254 int i; 255 256 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 257 if (connector->encoder_ids[i] == 0) 258 break; 259 encoder = drm_encoder_find(connector->dev, 260 connector->encoder_ids[i]); 261 if (!encoder) 262 continue; 263 264 if (encoder->encoder_type == encoder_type) 265 return encoder; 266 } 267 return NULL; 268 } 269 270 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 271 { 272 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 273 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 274 275 if (amdgpu_connector->edid) { 276 return amdgpu_connector->edid; 277 } else if (edid_blob) { 278 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 279 if (edid) 280 amdgpu_connector->edid = edid; 281 } 282 return amdgpu_connector->edid; 283 } 284 285 static struct edid * 286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 287 { 288 struct edid *edid; 289 290 if (adev->mode_info.bios_hardcoded_edid) { 291 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 292 if (edid) { 293 memcpy((unsigned char *)edid, 294 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 295 adev->mode_info.bios_hardcoded_edid_size); 296 return edid; 297 } 298 } 299 return NULL; 300 } 301 302 static void amdgpu_connector_get_edid(struct drm_connector *connector) 303 { 304 struct drm_device *dev = connector->dev; 305 struct amdgpu_device *adev = dev->dev_private; 306 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307 308 if (amdgpu_connector->edid) 309 return; 310 311 /* on hw with routers, select right port */ 312 if (amdgpu_connector->router.ddc_valid) 313 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 314 315 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 316 ENCODER_OBJECT_ID_NONE) && 317 amdgpu_connector->ddc_bus->has_aux) { 318 amdgpu_connector->edid = drm_get_edid(connector, 319 &amdgpu_connector->ddc_bus->aux.ddc); 320 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 321 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 322 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 323 324 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 325 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 326 amdgpu_connector->ddc_bus->has_aux) 327 amdgpu_connector->edid = drm_get_edid(connector, 328 &amdgpu_connector->ddc_bus->aux.ddc); 329 else if (amdgpu_connector->ddc_bus) 330 amdgpu_connector->edid = drm_get_edid(connector, 331 &amdgpu_connector->ddc_bus->adapter); 332 } else if (amdgpu_connector->ddc_bus) { 333 amdgpu_connector->edid = drm_get_edid(connector, 334 &amdgpu_connector->ddc_bus->adapter); 335 } 336 337 if (!amdgpu_connector->edid) { 338 /* some laptops provide a hardcoded edid in rom for LCDs */ 339 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 340 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 341 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 342 } 343 } 344 345 static void amdgpu_connector_free_edid(struct drm_connector *connector) 346 { 347 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 348 349 if (amdgpu_connector->edid) { 350 kfree(amdgpu_connector->edid); 351 amdgpu_connector->edid = NULL; 352 } 353 } 354 355 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 356 { 357 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 358 int ret; 359 360 if (amdgpu_connector->edid) { 361 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 362 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 363 drm_edid_to_eld(connector, amdgpu_connector->edid); 364 return ret; 365 } 366 drm_mode_connector_update_edid_property(connector, NULL); 367 return 0; 368 } 369 370 static struct drm_encoder * 371 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 372 { 373 int enc_id = connector->encoder_ids[0]; 374 375 /* pick the encoder ids */ 376 if (enc_id) 377 return drm_encoder_find(connector->dev, enc_id); 378 return NULL; 379 } 380 381 static void amdgpu_get_native_mode(struct drm_connector *connector) 382 { 383 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 384 struct amdgpu_encoder *amdgpu_encoder; 385 386 if (encoder == NULL) 387 return; 388 389 amdgpu_encoder = to_amdgpu_encoder(encoder); 390 391 if (!list_empty(&connector->probed_modes)) { 392 struct drm_display_mode *preferred_mode = 393 list_first_entry(&connector->probed_modes, 394 struct drm_display_mode, head); 395 396 amdgpu_encoder->native_mode = *preferred_mode; 397 } else { 398 amdgpu_encoder->native_mode.clock = 0; 399 } 400 } 401 402 static struct drm_display_mode * 403 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 404 { 405 struct drm_device *dev = encoder->dev; 406 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 407 struct drm_display_mode *mode = NULL; 408 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 409 410 if (native_mode->hdisplay != 0 && 411 native_mode->vdisplay != 0 && 412 native_mode->clock != 0) { 413 mode = drm_mode_duplicate(dev, native_mode); 414 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 415 drm_mode_set_name(mode); 416 417 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 418 } else if (native_mode->hdisplay != 0 && 419 native_mode->vdisplay != 0) { 420 /* mac laptops without an edid */ 421 /* Note that this is not necessarily the exact panel mode, 422 * but an approximation based on the cvt formula. For these 423 * systems we should ideally read the mode info out of the 424 * registers or add a mode table, but this works and is much 425 * simpler. 426 */ 427 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 428 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 429 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 430 } 431 return mode; 432 } 433 434 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 435 struct drm_connector *connector) 436 { 437 struct drm_device *dev = encoder->dev; 438 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 439 struct drm_display_mode *mode = NULL; 440 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 441 int i; 442 static const struct mode_size { 443 int w; 444 int h; 445 } common_modes[17] = { 446 { 640, 480}, 447 { 720, 480}, 448 { 800, 600}, 449 { 848, 480}, 450 {1024, 768}, 451 {1152, 768}, 452 {1280, 720}, 453 {1280, 800}, 454 {1280, 854}, 455 {1280, 960}, 456 {1280, 1024}, 457 {1440, 900}, 458 {1400, 1050}, 459 {1680, 1050}, 460 {1600, 1200}, 461 {1920, 1080}, 462 {1920, 1200} 463 }; 464 465 for (i = 0; i < 17; i++) { 466 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 467 if (common_modes[i].w > 1024 || 468 common_modes[i].h > 768) 469 continue; 470 } 471 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 472 if (common_modes[i].w > native_mode->hdisplay || 473 common_modes[i].h > native_mode->vdisplay || 474 (common_modes[i].w == native_mode->hdisplay && 475 common_modes[i].h == native_mode->vdisplay)) 476 continue; 477 } 478 if (common_modes[i].w < 320 || common_modes[i].h < 200) 479 continue; 480 481 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 482 drm_mode_probed_add(connector, mode); 483 } 484 } 485 486 static int amdgpu_connector_set_property(struct drm_connector *connector, 487 struct drm_property *property, 488 uint64_t val) 489 { 490 struct drm_device *dev = connector->dev; 491 struct amdgpu_device *adev = dev->dev_private; 492 struct drm_encoder *encoder; 493 struct amdgpu_encoder *amdgpu_encoder; 494 495 if (property == adev->mode_info.coherent_mode_property) { 496 struct amdgpu_encoder_atom_dig *dig; 497 bool new_coherent_mode; 498 499 /* need to find digital encoder on connector */ 500 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 501 if (!encoder) 502 return 0; 503 504 amdgpu_encoder = to_amdgpu_encoder(encoder); 505 506 if (!amdgpu_encoder->enc_priv) 507 return 0; 508 509 dig = amdgpu_encoder->enc_priv; 510 new_coherent_mode = val ? true : false; 511 if (dig->coherent_mode != new_coherent_mode) { 512 dig->coherent_mode = new_coherent_mode; 513 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 514 } 515 } 516 517 if (property == adev->mode_info.audio_property) { 518 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 519 /* need to find digital encoder on connector */ 520 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 521 if (!encoder) 522 return 0; 523 524 amdgpu_encoder = to_amdgpu_encoder(encoder); 525 526 if (amdgpu_connector->audio != val) { 527 amdgpu_connector->audio = val; 528 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 529 } 530 } 531 532 if (property == adev->mode_info.dither_property) { 533 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 534 /* need to find digital encoder on connector */ 535 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 536 if (!encoder) 537 return 0; 538 539 amdgpu_encoder = to_amdgpu_encoder(encoder); 540 541 if (amdgpu_connector->dither != val) { 542 amdgpu_connector->dither = val; 543 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 544 } 545 } 546 547 if (property == adev->mode_info.underscan_property) { 548 /* need to find digital encoder on connector */ 549 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 550 if (!encoder) 551 return 0; 552 553 amdgpu_encoder = to_amdgpu_encoder(encoder); 554 555 if (amdgpu_encoder->underscan_type != val) { 556 amdgpu_encoder->underscan_type = val; 557 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 558 } 559 } 560 561 if (property == adev->mode_info.underscan_hborder_property) { 562 /* need to find digital encoder on connector */ 563 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 564 if (!encoder) 565 return 0; 566 567 amdgpu_encoder = to_amdgpu_encoder(encoder); 568 569 if (amdgpu_encoder->underscan_hborder != val) { 570 amdgpu_encoder->underscan_hborder = val; 571 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 572 } 573 } 574 575 if (property == adev->mode_info.underscan_vborder_property) { 576 /* need to find digital encoder on connector */ 577 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 578 if (!encoder) 579 return 0; 580 581 amdgpu_encoder = to_amdgpu_encoder(encoder); 582 583 if (amdgpu_encoder->underscan_vborder != val) { 584 amdgpu_encoder->underscan_vborder = val; 585 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 586 } 587 } 588 589 if (property == adev->mode_info.load_detect_property) { 590 struct amdgpu_connector *amdgpu_connector = 591 to_amdgpu_connector(connector); 592 593 if (val == 0) 594 amdgpu_connector->dac_load_detect = false; 595 else 596 amdgpu_connector->dac_load_detect = true; 597 } 598 599 if (property == dev->mode_config.scaling_mode_property) { 600 enum amdgpu_rmx_type rmx_type; 601 602 if (connector->encoder) { 603 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 604 } else { 605 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 606 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 607 } 608 609 switch (val) { 610 default: 611 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 612 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 613 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 614 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 615 } 616 if (amdgpu_encoder->rmx_type == rmx_type) 617 return 0; 618 619 if ((rmx_type != DRM_MODE_SCALE_NONE) && 620 (amdgpu_encoder->native_mode.clock == 0)) 621 return 0; 622 623 amdgpu_encoder->rmx_type = rmx_type; 624 625 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 626 } 627 628 return 0; 629 } 630 631 static void 632 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 633 struct drm_connector *connector) 634 { 635 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 636 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 637 struct drm_display_mode *t, *mode; 638 639 /* If the EDID preferred mode doesn't match the native mode, use it */ 640 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 641 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 642 if (mode->hdisplay != native_mode->hdisplay || 643 mode->vdisplay != native_mode->vdisplay) 644 memcpy(native_mode, mode, sizeof(*mode)); 645 } 646 } 647 648 /* Try to get native mode details from EDID if necessary */ 649 if (!native_mode->clock) { 650 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 651 if (mode->hdisplay == native_mode->hdisplay && 652 mode->vdisplay == native_mode->vdisplay) { 653 *native_mode = *mode; 654 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 655 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 656 break; 657 } 658 } 659 } 660 661 if (!native_mode->clock) { 662 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 663 amdgpu_encoder->rmx_type = RMX_OFF; 664 } 665 } 666 667 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 668 { 669 struct drm_encoder *encoder; 670 int ret = 0; 671 struct drm_display_mode *mode; 672 673 amdgpu_connector_get_edid(connector); 674 ret = amdgpu_connector_ddc_get_modes(connector); 675 if (ret > 0) { 676 encoder = amdgpu_connector_best_single_encoder(connector); 677 if (encoder) { 678 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 679 /* add scaled modes */ 680 amdgpu_connector_add_common_modes(encoder, connector); 681 } 682 return ret; 683 } 684 685 encoder = amdgpu_connector_best_single_encoder(connector); 686 if (!encoder) 687 return 0; 688 689 /* we have no EDID modes */ 690 mode = amdgpu_connector_lcd_native_mode(encoder); 691 if (mode) { 692 ret = 1; 693 drm_mode_probed_add(connector, mode); 694 /* add the width/height from vbios tables if available */ 695 connector->display_info.width_mm = mode->width_mm; 696 connector->display_info.height_mm = mode->height_mm; 697 /* add scaled modes */ 698 amdgpu_connector_add_common_modes(encoder, connector); 699 } 700 701 return ret; 702 } 703 704 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 705 struct drm_display_mode *mode) 706 { 707 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708 709 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 710 return MODE_PANEL; 711 712 if (encoder) { 713 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 714 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 715 716 /* AVIVO hardware supports downscaling modes larger than the panel 717 * to the panel size, but I'm not sure this is desirable. 718 */ 719 if ((mode->hdisplay > native_mode->hdisplay) || 720 (mode->vdisplay > native_mode->vdisplay)) 721 return MODE_PANEL; 722 723 /* if scaling is disabled, block non-native modes */ 724 if (amdgpu_encoder->rmx_type == RMX_OFF) { 725 if ((mode->hdisplay != native_mode->hdisplay) || 726 (mode->vdisplay != native_mode->vdisplay)) 727 return MODE_PANEL; 728 } 729 } 730 731 return MODE_OK; 732 } 733 734 static enum drm_connector_status 735 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 736 { 737 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 738 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 739 enum drm_connector_status ret = connector_status_disconnected; 740 int r; 741 742 r = pm_runtime_get_sync(connector->dev->dev); 743 if (r < 0) 744 return connector_status_disconnected; 745 746 if (encoder) { 747 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 748 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 749 750 /* check if panel is valid */ 751 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 752 ret = connector_status_connected; 753 754 } 755 756 /* check for edid as well */ 757 amdgpu_connector_get_edid(connector); 758 if (amdgpu_connector->edid) 759 ret = connector_status_connected; 760 /* check acpi lid status ??? */ 761 762 amdgpu_connector_update_scratch_regs(connector, ret); 763 pm_runtime_mark_last_busy(connector->dev->dev); 764 pm_runtime_put_autosuspend(connector->dev->dev); 765 return ret; 766 } 767 768 static void amdgpu_connector_destroy(struct drm_connector *connector) 769 { 770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 771 772 if (amdgpu_connector->ddc_bus->has_aux) { 773 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 774 amdgpu_connector->ddc_bus->has_aux = false; 775 } 776 amdgpu_connector_free_edid(connector); 777 kfree(amdgpu_connector->con_priv); 778 drm_connector_unregister(connector); 779 drm_connector_cleanup(connector); 780 kfree(connector); 781 } 782 783 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 784 struct drm_property *property, 785 uint64_t value) 786 { 787 struct drm_device *dev = connector->dev; 788 struct amdgpu_encoder *amdgpu_encoder; 789 enum amdgpu_rmx_type rmx_type; 790 791 DRM_DEBUG_KMS("\n"); 792 if (property != dev->mode_config.scaling_mode_property) 793 return 0; 794 795 if (connector->encoder) 796 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 797 else { 798 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 799 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 800 } 801 802 switch (value) { 803 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 804 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 805 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 806 default: 807 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 808 } 809 if (amdgpu_encoder->rmx_type == rmx_type) 810 return 0; 811 812 amdgpu_encoder->rmx_type = rmx_type; 813 814 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 815 return 0; 816 } 817 818 819 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 820 .get_modes = amdgpu_connector_lvds_get_modes, 821 .mode_valid = amdgpu_connector_lvds_mode_valid, 822 .best_encoder = amdgpu_connector_best_single_encoder, 823 }; 824 825 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 826 .dpms = drm_helper_connector_dpms, 827 .detect = amdgpu_connector_lvds_detect, 828 .fill_modes = drm_helper_probe_single_connector_modes, 829 .destroy = amdgpu_connector_destroy, 830 .set_property = amdgpu_connector_set_lcd_property, 831 }; 832 833 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 834 { 835 int ret; 836 837 amdgpu_connector_get_edid(connector); 838 ret = amdgpu_connector_ddc_get_modes(connector); 839 840 return ret; 841 } 842 843 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 844 struct drm_display_mode *mode) 845 { 846 struct drm_device *dev = connector->dev; 847 struct amdgpu_device *adev = dev->dev_private; 848 849 /* XXX check mode bandwidth */ 850 851 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 852 return MODE_CLOCK_HIGH; 853 854 return MODE_OK; 855 } 856 857 static enum drm_connector_status 858 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 859 { 860 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 861 struct drm_encoder *encoder; 862 const struct drm_encoder_helper_funcs *encoder_funcs; 863 bool dret = false; 864 enum drm_connector_status ret = connector_status_disconnected; 865 int r; 866 867 r = pm_runtime_get_sync(connector->dev->dev); 868 if (r < 0) 869 return connector_status_disconnected; 870 871 encoder = amdgpu_connector_best_single_encoder(connector); 872 if (!encoder) 873 ret = connector_status_disconnected; 874 875 if (amdgpu_connector->ddc_bus) 876 dret = amdgpu_ddc_probe(amdgpu_connector, false); 877 if (dret) { 878 amdgpu_connector->detected_by_load = false; 879 amdgpu_connector_free_edid(connector); 880 amdgpu_connector_get_edid(connector); 881 882 if (!amdgpu_connector->edid) { 883 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 884 connector->name); 885 ret = connector_status_connected; 886 } else { 887 amdgpu_connector->use_digital = 888 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 889 890 /* some oems have boards with separate digital and analog connectors 891 * with a shared ddc line (often vga + hdmi) 892 */ 893 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 894 amdgpu_connector_free_edid(connector); 895 ret = connector_status_disconnected; 896 } else { 897 ret = connector_status_connected; 898 } 899 } 900 } else { 901 902 /* if we aren't forcing don't do destructive polling */ 903 if (!force) { 904 /* only return the previous status if we last 905 * detected a monitor via load. 906 */ 907 if (amdgpu_connector->detected_by_load) 908 ret = connector->status; 909 goto out; 910 } 911 912 if (amdgpu_connector->dac_load_detect && encoder) { 913 encoder_funcs = encoder->helper_private; 914 ret = encoder_funcs->detect(encoder, connector); 915 if (ret != connector_status_disconnected) 916 amdgpu_connector->detected_by_load = true; 917 } 918 } 919 920 amdgpu_connector_update_scratch_regs(connector, ret); 921 922 out: 923 pm_runtime_mark_last_busy(connector->dev->dev); 924 pm_runtime_put_autosuspend(connector->dev->dev); 925 926 return ret; 927 } 928 929 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 930 .get_modes = amdgpu_connector_vga_get_modes, 931 .mode_valid = amdgpu_connector_vga_mode_valid, 932 .best_encoder = amdgpu_connector_best_single_encoder, 933 }; 934 935 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 936 .dpms = drm_helper_connector_dpms, 937 .detect = amdgpu_connector_vga_detect, 938 .fill_modes = drm_helper_probe_single_connector_modes, 939 .destroy = amdgpu_connector_destroy, 940 .set_property = amdgpu_connector_set_property, 941 }; 942 943 static bool 944 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 945 { 946 struct drm_device *dev = connector->dev; 947 struct amdgpu_device *adev = dev->dev_private; 948 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 949 enum drm_connector_status status; 950 951 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 952 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 953 status = connector_status_connected; 954 else 955 status = connector_status_disconnected; 956 if (connector->status == status) 957 return true; 958 } 959 960 return false; 961 } 962 963 /* 964 * DVI is complicated 965 * Do a DDC probe, if DDC probe passes, get the full EDID so 966 * we can do analog/digital monitor detection at this point. 967 * If the monitor is an analog monitor or we got no DDC, 968 * we need to find the DAC encoder object for this connector. 969 * If we got no DDC, we do load detection on the DAC encoder object. 970 * If we got analog DDC or load detection passes on the DAC encoder 971 * we have to check if this analog encoder is shared with anyone else (TV) 972 * if its shared we have to set the other connector to disconnected. 973 */ 974 static enum drm_connector_status 975 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 976 { 977 struct drm_device *dev = connector->dev; 978 struct amdgpu_device *adev = dev->dev_private; 979 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 980 struct drm_encoder *encoder = NULL; 981 const struct drm_encoder_helper_funcs *encoder_funcs; 982 int i, r; 983 enum drm_connector_status ret = connector_status_disconnected; 984 bool dret = false, broken_edid = false; 985 986 r = pm_runtime_get_sync(connector->dev->dev); 987 if (r < 0) 988 return connector_status_disconnected; 989 990 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 991 ret = connector->status; 992 goto exit; 993 } 994 995 if (amdgpu_connector->ddc_bus) 996 dret = amdgpu_ddc_probe(amdgpu_connector, false); 997 if (dret) { 998 amdgpu_connector->detected_by_load = false; 999 amdgpu_connector_free_edid(connector); 1000 amdgpu_connector_get_edid(connector); 1001 1002 if (!amdgpu_connector->edid) { 1003 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1004 connector->name); 1005 ret = connector_status_connected; 1006 broken_edid = true; /* defer use_digital to later */ 1007 } else { 1008 amdgpu_connector->use_digital = 1009 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1010 1011 /* some oems have boards with separate digital and analog connectors 1012 * with a shared ddc line (often vga + hdmi) 1013 */ 1014 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1015 amdgpu_connector_free_edid(connector); 1016 ret = connector_status_disconnected; 1017 } else { 1018 ret = connector_status_connected; 1019 } 1020 1021 /* This gets complicated. We have boards with VGA + HDMI with a 1022 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1023 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1024 * you don't really know what's connected to which port as both are digital. 1025 */ 1026 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1027 struct drm_connector *list_connector; 1028 struct amdgpu_connector *list_amdgpu_connector; 1029 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1030 if (connector == list_connector) 1031 continue; 1032 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1033 if (list_amdgpu_connector->shared_ddc && 1034 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1035 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1036 /* cases where both connectors are digital */ 1037 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1038 /* hpd is our only option in this case */ 1039 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1040 amdgpu_connector_free_edid(connector); 1041 ret = connector_status_disconnected; 1042 } 1043 } 1044 } 1045 } 1046 } 1047 } 1048 } 1049 1050 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1051 goto out; 1052 1053 /* DVI-D and HDMI-A are digital only */ 1054 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1055 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1056 goto out; 1057 1058 /* if we aren't forcing don't do destructive polling */ 1059 if (!force) { 1060 /* only return the previous status if we last 1061 * detected a monitor via load. 1062 */ 1063 if (amdgpu_connector->detected_by_load) 1064 ret = connector->status; 1065 goto out; 1066 } 1067 1068 /* find analog encoder */ 1069 if (amdgpu_connector->dac_load_detect) { 1070 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1071 if (connector->encoder_ids[i] == 0) 1072 break; 1073 1074 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1075 if (!encoder) 1076 continue; 1077 1078 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1079 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1080 continue; 1081 1082 encoder_funcs = encoder->helper_private; 1083 if (encoder_funcs->detect) { 1084 if (!broken_edid) { 1085 if (ret != connector_status_connected) { 1086 /* deal with analog monitors without DDC */ 1087 ret = encoder_funcs->detect(encoder, connector); 1088 if (ret == connector_status_connected) { 1089 amdgpu_connector->use_digital = false; 1090 } 1091 if (ret != connector_status_disconnected) 1092 amdgpu_connector->detected_by_load = true; 1093 } 1094 } else { 1095 enum drm_connector_status lret; 1096 /* assume digital unless load detected otherwise */ 1097 amdgpu_connector->use_digital = true; 1098 lret = encoder_funcs->detect(encoder, connector); 1099 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1100 if (lret == connector_status_connected) 1101 amdgpu_connector->use_digital = false; 1102 } 1103 break; 1104 } 1105 } 1106 } 1107 1108 out: 1109 /* updated in get modes as well since we need to know if it's analog or digital */ 1110 amdgpu_connector_update_scratch_regs(connector, ret); 1111 1112 exit: 1113 pm_runtime_mark_last_busy(connector->dev->dev); 1114 pm_runtime_put_autosuspend(connector->dev->dev); 1115 1116 return ret; 1117 } 1118 1119 /* okay need to be smart in here about which encoder to pick */ 1120 static struct drm_encoder * 1121 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1122 { 1123 int enc_id = connector->encoder_ids[0]; 1124 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1125 struct drm_encoder *encoder; 1126 int i; 1127 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1128 if (connector->encoder_ids[i] == 0) 1129 break; 1130 1131 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1132 if (!encoder) 1133 continue; 1134 1135 if (amdgpu_connector->use_digital == true) { 1136 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1137 return encoder; 1138 } else { 1139 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1140 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1141 return encoder; 1142 } 1143 } 1144 1145 /* see if we have a default encoder TODO */ 1146 1147 /* then check use digitial */ 1148 /* pick the first one */ 1149 if (enc_id) 1150 return drm_encoder_find(connector->dev, enc_id); 1151 return NULL; 1152 } 1153 1154 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1155 { 1156 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1157 if (connector->force == DRM_FORCE_ON) 1158 amdgpu_connector->use_digital = false; 1159 if (connector->force == DRM_FORCE_ON_DIGITAL) 1160 amdgpu_connector->use_digital = true; 1161 } 1162 1163 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1164 struct drm_display_mode *mode) 1165 { 1166 struct drm_device *dev = connector->dev; 1167 struct amdgpu_device *adev = dev->dev_private; 1168 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1169 1170 /* XXX check mode bandwidth */ 1171 1172 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1173 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1174 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1175 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1176 return MODE_OK; 1177 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1178 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1179 if (mode->clock > 340000) 1180 return MODE_CLOCK_HIGH; 1181 else 1182 return MODE_OK; 1183 } else { 1184 return MODE_CLOCK_HIGH; 1185 } 1186 } 1187 1188 /* check against the max pixel clock */ 1189 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1190 return MODE_CLOCK_HIGH; 1191 1192 return MODE_OK; 1193 } 1194 1195 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1196 .get_modes = amdgpu_connector_vga_get_modes, 1197 .mode_valid = amdgpu_connector_dvi_mode_valid, 1198 .best_encoder = amdgpu_connector_dvi_encoder, 1199 }; 1200 1201 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1202 .dpms = drm_helper_connector_dpms, 1203 .detect = amdgpu_connector_dvi_detect, 1204 .fill_modes = drm_helper_probe_single_connector_modes, 1205 .set_property = amdgpu_connector_set_property, 1206 .destroy = amdgpu_connector_destroy, 1207 .force = amdgpu_connector_dvi_force, 1208 }; 1209 1210 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1211 { 1212 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1213 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1214 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1215 int ret; 1216 1217 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1218 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1219 struct drm_display_mode *mode; 1220 1221 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1222 if (!amdgpu_dig_connector->edp_on) 1223 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1224 ATOM_TRANSMITTER_ACTION_POWER_ON); 1225 amdgpu_connector_get_edid(connector); 1226 ret = amdgpu_connector_ddc_get_modes(connector); 1227 if (!amdgpu_dig_connector->edp_on) 1228 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1229 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1230 } else { 1231 /* need to setup ddc on the bridge */ 1232 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1233 ENCODER_OBJECT_ID_NONE) { 1234 if (encoder) 1235 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1236 } 1237 amdgpu_connector_get_edid(connector); 1238 ret = amdgpu_connector_ddc_get_modes(connector); 1239 } 1240 1241 if (ret > 0) { 1242 if (encoder) { 1243 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1244 /* add scaled modes */ 1245 amdgpu_connector_add_common_modes(encoder, connector); 1246 } 1247 return ret; 1248 } 1249 1250 if (!encoder) 1251 return 0; 1252 1253 /* we have no EDID modes */ 1254 mode = amdgpu_connector_lcd_native_mode(encoder); 1255 if (mode) { 1256 ret = 1; 1257 drm_mode_probed_add(connector, mode); 1258 /* add the width/height from vbios tables if available */ 1259 connector->display_info.width_mm = mode->width_mm; 1260 connector->display_info.height_mm = mode->height_mm; 1261 /* add scaled modes */ 1262 amdgpu_connector_add_common_modes(encoder, connector); 1263 } 1264 } else { 1265 /* need to setup ddc on the bridge */ 1266 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1267 ENCODER_OBJECT_ID_NONE) { 1268 if (encoder) 1269 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1270 } 1271 amdgpu_connector_get_edid(connector); 1272 ret = amdgpu_connector_ddc_get_modes(connector); 1273 1274 amdgpu_get_native_mode(connector); 1275 } 1276 1277 return ret; 1278 } 1279 1280 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1281 { 1282 struct drm_encoder *encoder; 1283 struct amdgpu_encoder *amdgpu_encoder; 1284 int i; 1285 1286 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1287 if (connector->encoder_ids[i] == 0) 1288 break; 1289 1290 encoder = drm_encoder_find(connector->dev, 1291 connector->encoder_ids[i]); 1292 if (!encoder) 1293 continue; 1294 1295 amdgpu_encoder = to_amdgpu_encoder(encoder); 1296 1297 switch (amdgpu_encoder->encoder_id) { 1298 case ENCODER_OBJECT_ID_TRAVIS: 1299 case ENCODER_OBJECT_ID_NUTMEG: 1300 return amdgpu_encoder->encoder_id; 1301 default: 1302 break; 1303 } 1304 } 1305 1306 return ENCODER_OBJECT_ID_NONE; 1307 } 1308 1309 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1310 { 1311 struct drm_encoder *encoder; 1312 struct amdgpu_encoder *amdgpu_encoder; 1313 int i; 1314 bool found = false; 1315 1316 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1317 if (connector->encoder_ids[i] == 0) 1318 break; 1319 encoder = drm_encoder_find(connector->dev, 1320 connector->encoder_ids[i]); 1321 if (!encoder) 1322 continue; 1323 1324 amdgpu_encoder = to_amdgpu_encoder(encoder); 1325 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1326 found = true; 1327 } 1328 1329 return found; 1330 } 1331 1332 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1333 { 1334 struct drm_device *dev = connector->dev; 1335 struct amdgpu_device *adev = dev->dev_private; 1336 1337 if ((adev->clock.default_dispclk >= 53900) && 1338 amdgpu_connector_encoder_is_hbr2(connector)) { 1339 return true; 1340 } 1341 1342 return false; 1343 } 1344 1345 static enum drm_connector_status 1346 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1347 { 1348 struct drm_device *dev = connector->dev; 1349 struct amdgpu_device *adev = dev->dev_private; 1350 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1351 enum drm_connector_status ret = connector_status_disconnected; 1352 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1353 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1354 int r; 1355 1356 r = pm_runtime_get_sync(connector->dev->dev); 1357 if (r < 0) 1358 return connector_status_disconnected; 1359 1360 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1361 ret = connector->status; 1362 goto out; 1363 } 1364 1365 amdgpu_connector_free_edid(connector); 1366 1367 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1368 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1369 if (encoder) { 1370 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1371 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1372 1373 /* check if panel is valid */ 1374 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1375 ret = connector_status_connected; 1376 } 1377 /* eDP is always DP */ 1378 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1379 if (!amdgpu_dig_connector->edp_on) 1380 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1381 ATOM_TRANSMITTER_ACTION_POWER_ON); 1382 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1383 ret = connector_status_connected; 1384 if (!amdgpu_dig_connector->edp_on) 1385 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1386 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1387 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1388 ENCODER_OBJECT_ID_NONE) { 1389 /* DP bridges are always DP */ 1390 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1391 /* get the DPCD from the bridge */ 1392 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1393 1394 if (encoder) { 1395 /* setup ddc on the bridge */ 1396 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1397 /* bridge chips are always aux */ 1398 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1399 ret = connector_status_connected; 1400 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1401 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1402 ret = encoder_funcs->detect(encoder, connector); 1403 } 1404 } 1405 } else { 1406 amdgpu_dig_connector->dp_sink_type = 1407 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1408 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1409 ret = connector_status_connected; 1410 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1411 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1412 } else { 1413 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1414 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1415 ret = connector_status_connected; 1416 } else { 1417 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1418 if (amdgpu_ddc_probe(amdgpu_connector, false)) 1419 ret = connector_status_connected; 1420 } 1421 } 1422 } 1423 1424 amdgpu_connector_update_scratch_regs(connector, ret); 1425 out: 1426 pm_runtime_mark_last_busy(connector->dev->dev); 1427 pm_runtime_put_autosuspend(connector->dev->dev); 1428 1429 return ret; 1430 } 1431 1432 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1433 struct drm_display_mode *mode) 1434 { 1435 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1436 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1437 1438 /* XXX check mode bandwidth */ 1439 1440 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1441 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1442 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1443 1444 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1445 return MODE_PANEL; 1446 1447 if (encoder) { 1448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1449 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1450 1451 /* AVIVO hardware supports downscaling modes larger than the panel 1452 * to the panel size, but I'm not sure this is desirable. 1453 */ 1454 if ((mode->hdisplay > native_mode->hdisplay) || 1455 (mode->vdisplay > native_mode->vdisplay)) 1456 return MODE_PANEL; 1457 1458 /* if scaling is disabled, block non-native modes */ 1459 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1460 if ((mode->hdisplay != native_mode->hdisplay) || 1461 (mode->vdisplay != native_mode->vdisplay)) 1462 return MODE_PANEL; 1463 } 1464 } 1465 return MODE_OK; 1466 } else { 1467 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1468 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1469 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1470 } else { 1471 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1472 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1473 if (mode->clock > 340000) 1474 return MODE_CLOCK_HIGH; 1475 } else { 1476 if (mode->clock > 165000) 1477 return MODE_CLOCK_HIGH; 1478 } 1479 } 1480 } 1481 1482 return MODE_OK; 1483 } 1484 1485 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1486 .get_modes = amdgpu_connector_dp_get_modes, 1487 .mode_valid = amdgpu_connector_dp_mode_valid, 1488 .best_encoder = amdgpu_connector_dvi_encoder, 1489 }; 1490 1491 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1492 .dpms = drm_helper_connector_dpms, 1493 .detect = amdgpu_connector_dp_detect, 1494 .fill_modes = drm_helper_probe_single_connector_modes, 1495 .set_property = amdgpu_connector_set_property, 1496 .destroy = amdgpu_connector_destroy, 1497 .force = amdgpu_connector_dvi_force, 1498 }; 1499 1500 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1501 .dpms = drm_helper_connector_dpms, 1502 .detect = amdgpu_connector_dp_detect, 1503 .fill_modes = drm_helper_probe_single_connector_modes, 1504 .set_property = amdgpu_connector_set_lcd_property, 1505 .destroy = amdgpu_connector_destroy, 1506 .force = amdgpu_connector_dvi_force, 1507 }; 1508 1509 static struct drm_encoder * 1510 amdgpu_connector_virtual_encoder(struct drm_connector *connector) 1511 { 1512 int enc_id = connector->encoder_ids[0]; 1513 struct drm_encoder *encoder; 1514 int i; 1515 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1516 if (connector->encoder_ids[i] == 0) 1517 break; 1518 1519 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1520 if (!encoder) 1521 continue; 1522 1523 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) 1524 return encoder; 1525 } 1526 1527 /* pick the first one */ 1528 if (enc_id) 1529 return drm_encoder_find(connector->dev, enc_id); 1530 return NULL; 1531 } 1532 1533 static int amdgpu_connector_virtual_get_modes(struct drm_connector *connector) 1534 { 1535 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1536 1537 if (encoder) { 1538 amdgpu_connector_add_common_modes(encoder, connector); 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int amdgpu_connector_virtual_mode_valid(struct drm_connector *connector, 1545 struct drm_display_mode *mode) 1546 { 1547 return MODE_OK; 1548 } 1549 1550 static int 1551 amdgpu_connector_virtual_dpms(struct drm_connector *connector, int mode) 1552 { 1553 return 0; 1554 } 1555 1556 static enum drm_connector_status 1557 1558 amdgpu_connector_virtual_detect(struct drm_connector *connector, bool force) 1559 { 1560 return connector_status_connected; 1561 } 1562 1563 static int 1564 amdgpu_connector_virtual_set_property(struct drm_connector *connector, 1565 struct drm_property *property, 1566 uint64_t val) 1567 { 1568 return 0; 1569 } 1570 1571 static void amdgpu_connector_virtual_force(struct drm_connector *connector) 1572 { 1573 return; 1574 } 1575 1576 static const struct drm_connector_helper_funcs amdgpu_connector_virtual_helper_funcs = { 1577 .get_modes = amdgpu_connector_virtual_get_modes, 1578 .mode_valid = amdgpu_connector_virtual_mode_valid, 1579 .best_encoder = amdgpu_connector_virtual_encoder, 1580 }; 1581 1582 static const struct drm_connector_funcs amdgpu_connector_virtual_funcs = { 1583 .dpms = amdgpu_connector_virtual_dpms, 1584 .detect = amdgpu_connector_virtual_detect, 1585 .fill_modes = drm_helper_probe_single_connector_modes, 1586 .set_property = amdgpu_connector_virtual_set_property, 1587 .destroy = amdgpu_connector_destroy, 1588 .force = amdgpu_connector_virtual_force, 1589 }; 1590 1591 void 1592 amdgpu_connector_add(struct amdgpu_device *adev, 1593 uint32_t connector_id, 1594 uint32_t supported_device, 1595 int connector_type, 1596 struct amdgpu_i2c_bus_rec *i2c_bus, 1597 uint16_t connector_object_id, 1598 struct amdgpu_hpd *hpd, 1599 struct amdgpu_router *router) 1600 { 1601 struct drm_device *dev = adev->ddev; 1602 struct drm_connector *connector; 1603 struct amdgpu_connector *amdgpu_connector; 1604 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1605 struct drm_encoder *encoder; 1606 struct amdgpu_encoder *amdgpu_encoder; 1607 uint32_t subpixel_order = SubPixelNone; 1608 bool shared_ddc = false; 1609 bool is_dp_bridge = false; 1610 bool has_aux = false; 1611 1612 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1613 return; 1614 1615 /* see if we already added it */ 1616 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1617 amdgpu_connector = to_amdgpu_connector(connector); 1618 if (amdgpu_connector->connector_id == connector_id) { 1619 amdgpu_connector->devices |= supported_device; 1620 return; 1621 } 1622 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1623 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1624 amdgpu_connector->shared_ddc = true; 1625 shared_ddc = true; 1626 } 1627 if (amdgpu_connector->router_bus && router->ddc_valid && 1628 (amdgpu_connector->router.router_id == router->router_id)) { 1629 amdgpu_connector->shared_ddc = false; 1630 shared_ddc = false; 1631 } 1632 } 1633 } 1634 1635 /* check if it's a dp bridge */ 1636 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1637 amdgpu_encoder = to_amdgpu_encoder(encoder); 1638 if (amdgpu_encoder->devices & supported_device) { 1639 switch (amdgpu_encoder->encoder_id) { 1640 case ENCODER_OBJECT_ID_TRAVIS: 1641 case ENCODER_OBJECT_ID_NUTMEG: 1642 is_dp_bridge = true; 1643 break; 1644 default: 1645 break; 1646 } 1647 } 1648 } 1649 1650 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1651 if (!amdgpu_connector) 1652 return; 1653 1654 connector = &amdgpu_connector->base; 1655 1656 amdgpu_connector->connector_id = connector_id; 1657 amdgpu_connector->devices = supported_device; 1658 amdgpu_connector->shared_ddc = shared_ddc; 1659 amdgpu_connector->connector_object_id = connector_object_id; 1660 amdgpu_connector->hpd = *hpd; 1661 1662 amdgpu_connector->router = *router; 1663 if (router->ddc_valid || router->cd_valid) { 1664 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1665 if (!amdgpu_connector->router_bus) 1666 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1667 } 1668 1669 if (is_dp_bridge) { 1670 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1671 if (!amdgpu_dig_connector) 1672 goto failed; 1673 amdgpu_connector->con_priv = amdgpu_dig_connector; 1674 if (i2c_bus->valid) { 1675 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1676 if (amdgpu_connector->ddc_bus) 1677 has_aux = true; 1678 else 1679 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1680 } 1681 switch (connector_type) { 1682 case DRM_MODE_CONNECTOR_VGA: 1683 case DRM_MODE_CONNECTOR_DVIA: 1684 default: 1685 drm_connector_init(dev, &amdgpu_connector->base, 1686 &amdgpu_connector_dp_funcs, connector_type); 1687 drm_connector_helper_add(&amdgpu_connector->base, 1688 &amdgpu_connector_dp_helper_funcs); 1689 connector->interlace_allowed = true; 1690 connector->doublescan_allowed = true; 1691 amdgpu_connector->dac_load_detect = true; 1692 drm_object_attach_property(&amdgpu_connector->base.base, 1693 adev->mode_info.load_detect_property, 1694 1); 1695 drm_object_attach_property(&amdgpu_connector->base.base, 1696 dev->mode_config.scaling_mode_property, 1697 DRM_MODE_SCALE_NONE); 1698 break; 1699 case DRM_MODE_CONNECTOR_DVII: 1700 case DRM_MODE_CONNECTOR_DVID: 1701 case DRM_MODE_CONNECTOR_HDMIA: 1702 case DRM_MODE_CONNECTOR_HDMIB: 1703 case DRM_MODE_CONNECTOR_DisplayPort: 1704 drm_connector_init(dev, &amdgpu_connector->base, 1705 &amdgpu_connector_dp_funcs, connector_type); 1706 drm_connector_helper_add(&amdgpu_connector->base, 1707 &amdgpu_connector_dp_helper_funcs); 1708 drm_object_attach_property(&amdgpu_connector->base.base, 1709 adev->mode_info.underscan_property, 1710 UNDERSCAN_OFF); 1711 drm_object_attach_property(&amdgpu_connector->base.base, 1712 adev->mode_info.underscan_hborder_property, 1713 0); 1714 drm_object_attach_property(&amdgpu_connector->base.base, 1715 adev->mode_info.underscan_vborder_property, 1716 0); 1717 1718 drm_object_attach_property(&amdgpu_connector->base.base, 1719 dev->mode_config.scaling_mode_property, 1720 DRM_MODE_SCALE_NONE); 1721 1722 drm_object_attach_property(&amdgpu_connector->base.base, 1723 adev->mode_info.dither_property, 1724 AMDGPU_FMT_DITHER_DISABLE); 1725 1726 if (amdgpu_audio != 0) 1727 drm_object_attach_property(&amdgpu_connector->base.base, 1728 adev->mode_info.audio_property, 1729 AMDGPU_AUDIO_AUTO); 1730 1731 subpixel_order = SubPixelHorizontalRGB; 1732 connector->interlace_allowed = true; 1733 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1734 connector->doublescan_allowed = true; 1735 else 1736 connector->doublescan_allowed = false; 1737 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1738 amdgpu_connector->dac_load_detect = true; 1739 drm_object_attach_property(&amdgpu_connector->base.base, 1740 adev->mode_info.load_detect_property, 1741 1); 1742 } 1743 break; 1744 case DRM_MODE_CONNECTOR_LVDS: 1745 case DRM_MODE_CONNECTOR_eDP: 1746 drm_connector_init(dev, &amdgpu_connector->base, 1747 &amdgpu_connector_edp_funcs, connector_type); 1748 drm_connector_helper_add(&amdgpu_connector->base, 1749 &amdgpu_connector_dp_helper_funcs); 1750 drm_object_attach_property(&amdgpu_connector->base.base, 1751 dev->mode_config.scaling_mode_property, 1752 DRM_MODE_SCALE_FULLSCREEN); 1753 subpixel_order = SubPixelHorizontalRGB; 1754 connector->interlace_allowed = false; 1755 connector->doublescan_allowed = false; 1756 break; 1757 } 1758 } else { 1759 switch (connector_type) { 1760 case DRM_MODE_CONNECTOR_VGA: 1761 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1762 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1763 if (i2c_bus->valid) { 1764 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1765 if (!amdgpu_connector->ddc_bus) 1766 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1767 } 1768 amdgpu_connector->dac_load_detect = true; 1769 drm_object_attach_property(&amdgpu_connector->base.base, 1770 adev->mode_info.load_detect_property, 1771 1); 1772 drm_object_attach_property(&amdgpu_connector->base.base, 1773 dev->mode_config.scaling_mode_property, 1774 DRM_MODE_SCALE_NONE); 1775 /* no HPD on analog connectors */ 1776 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1777 connector->interlace_allowed = true; 1778 connector->doublescan_allowed = true; 1779 break; 1780 case DRM_MODE_CONNECTOR_DVIA: 1781 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1782 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1783 if (i2c_bus->valid) { 1784 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1785 if (!amdgpu_connector->ddc_bus) 1786 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1787 } 1788 amdgpu_connector->dac_load_detect = true; 1789 drm_object_attach_property(&amdgpu_connector->base.base, 1790 adev->mode_info.load_detect_property, 1791 1); 1792 drm_object_attach_property(&amdgpu_connector->base.base, 1793 dev->mode_config.scaling_mode_property, 1794 DRM_MODE_SCALE_NONE); 1795 /* no HPD on analog connectors */ 1796 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1797 connector->interlace_allowed = true; 1798 connector->doublescan_allowed = true; 1799 break; 1800 case DRM_MODE_CONNECTOR_DVII: 1801 case DRM_MODE_CONNECTOR_DVID: 1802 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1803 if (!amdgpu_dig_connector) 1804 goto failed; 1805 amdgpu_connector->con_priv = amdgpu_dig_connector; 1806 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1807 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1808 if (i2c_bus->valid) { 1809 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1810 if (!amdgpu_connector->ddc_bus) 1811 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1812 } 1813 subpixel_order = SubPixelHorizontalRGB; 1814 drm_object_attach_property(&amdgpu_connector->base.base, 1815 adev->mode_info.coherent_mode_property, 1816 1); 1817 drm_object_attach_property(&amdgpu_connector->base.base, 1818 adev->mode_info.underscan_property, 1819 UNDERSCAN_OFF); 1820 drm_object_attach_property(&amdgpu_connector->base.base, 1821 adev->mode_info.underscan_hborder_property, 1822 0); 1823 drm_object_attach_property(&amdgpu_connector->base.base, 1824 adev->mode_info.underscan_vborder_property, 1825 0); 1826 drm_object_attach_property(&amdgpu_connector->base.base, 1827 dev->mode_config.scaling_mode_property, 1828 DRM_MODE_SCALE_NONE); 1829 1830 if (amdgpu_audio != 0) { 1831 drm_object_attach_property(&amdgpu_connector->base.base, 1832 adev->mode_info.audio_property, 1833 AMDGPU_AUDIO_AUTO); 1834 } 1835 drm_object_attach_property(&amdgpu_connector->base.base, 1836 adev->mode_info.dither_property, 1837 AMDGPU_FMT_DITHER_DISABLE); 1838 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1839 amdgpu_connector->dac_load_detect = true; 1840 drm_object_attach_property(&amdgpu_connector->base.base, 1841 adev->mode_info.load_detect_property, 1842 1); 1843 } 1844 connector->interlace_allowed = true; 1845 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1846 connector->doublescan_allowed = true; 1847 else 1848 connector->doublescan_allowed = false; 1849 break; 1850 case DRM_MODE_CONNECTOR_HDMIA: 1851 case DRM_MODE_CONNECTOR_HDMIB: 1852 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1853 if (!amdgpu_dig_connector) 1854 goto failed; 1855 amdgpu_connector->con_priv = amdgpu_dig_connector; 1856 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1857 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1858 if (i2c_bus->valid) { 1859 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1860 if (!amdgpu_connector->ddc_bus) 1861 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1862 } 1863 drm_object_attach_property(&amdgpu_connector->base.base, 1864 adev->mode_info.coherent_mode_property, 1865 1); 1866 drm_object_attach_property(&amdgpu_connector->base.base, 1867 adev->mode_info.underscan_property, 1868 UNDERSCAN_OFF); 1869 drm_object_attach_property(&amdgpu_connector->base.base, 1870 adev->mode_info.underscan_hborder_property, 1871 0); 1872 drm_object_attach_property(&amdgpu_connector->base.base, 1873 adev->mode_info.underscan_vborder_property, 1874 0); 1875 drm_object_attach_property(&amdgpu_connector->base.base, 1876 dev->mode_config.scaling_mode_property, 1877 DRM_MODE_SCALE_NONE); 1878 if (amdgpu_audio != 0) { 1879 drm_object_attach_property(&amdgpu_connector->base.base, 1880 adev->mode_info.audio_property, 1881 AMDGPU_AUDIO_AUTO); 1882 } 1883 drm_object_attach_property(&amdgpu_connector->base.base, 1884 adev->mode_info.dither_property, 1885 AMDGPU_FMT_DITHER_DISABLE); 1886 subpixel_order = SubPixelHorizontalRGB; 1887 connector->interlace_allowed = true; 1888 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1889 connector->doublescan_allowed = true; 1890 else 1891 connector->doublescan_allowed = false; 1892 break; 1893 case DRM_MODE_CONNECTOR_DisplayPort: 1894 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1895 if (!amdgpu_dig_connector) 1896 goto failed; 1897 amdgpu_connector->con_priv = amdgpu_dig_connector; 1898 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1899 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1900 if (i2c_bus->valid) { 1901 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1902 if (amdgpu_connector->ddc_bus) 1903 has_aux = true; 1904 else 1905 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1906 } 1907 subpixel_order = SubPixelHorizontalRGB; 1908 drm_object_attach_property(&amdgpu_connector->base.base, 1909 adev->mode_info.coherent_mode_property, 1910 1); 1911 drm_object_attach_property(&amdgpu_connector->base.base, 1912 adev->mode_info.underscan_property, 1913 UNDERSCAN_OFF); 1914 drm_object_attach_property(&amdgpu_connector->base.base, 1915 adev->mode_info.underscan_hborder_property, 1916 0); 1917 drm_object_attach_property(&amdgpu_connector->base.base, 1918 adev->mode_info.underscan_vborder_property, 1919 0); 1920 drm_object_attach_property(&amdgpu_connector->base.base, 1921 dev->mode_config.scaling_mode_property, 1922 DRM_MODE_SCALE_NONE); 1923 if (amdgpu_audio != 0) { 1924 drm_object_attach_property(&amdgpu_connector->base.base, 1925 adev->mode_info.audio_property, 1926 AMDGPU_AUDIO_AUTO); 1927 } 1928 drm_object_attach_property(&amdgpu_connector->base.base, 1929 adev->mode_info.dither_property, 1930 AMDGPU_FMT_DITHER_DISABLE); 1931 connector->interlace_allowed = true; 1932 /* in theory with a DP to VGA converter... */ 1933 connector->doublescan_allowed = false; 1934 break; 1935 case DRM_MODE_CONNECTOR_eDP: 1936 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1937 if (!amdgpu_dig_connector) 1938 goto failed; 1939 amdgpu_connector->con_priv = amdgpu_dig_connector; 1940 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1941 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1942 if (i2c_bus->valid) { 1943 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1944 if (amdgpu_connector->ddc_bus) 1945 has_aux = true; 1946 else 1947 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1948 } 1949 drm_object_attach_property(&amdgpu_connector->base.base, 1950 dev->mode_config.scaling_mode_property, 1951 DRM_MODE_SCALE_FULLSCREEN); 1952 subpixel_order = SubPixelHorizontalRGB; 1953 connector->interlace_allowed = false; 1954 connector->doublescan_allowed = false; 1955 break; 1956 case DRM_MODE_CONNECTOR_LVDS: 1957 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1958 if (!amdgpu_dig_connector) 1959 goto failed; 1960 amdgpu_connector->con_priv = amdgpu_dig_connector; 1961 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1962 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1963 if (i2c_bus->valid) { 1964 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1965 if (!amdgpu_connector->ddc_bus) 1966 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1967 } 1968 drm_object_attach_property(&amdgpu_connector->base.base, 1969 dev->mode_config.scaling_mode_property, 1970 DRM_MODE_SCALE_FULLSCREEN); 1971 subpixel_order = SubPixelHorizontalRGB; 1972 connector->interlace_allowed = false; 1973 connector->doublescan_allowed = false; 1974 break; 1975 case DRM_MODE_CONNECTOR_VIRTUAL: 1976 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1977 if (!amdgpu_dig_connector) 1978 goto failed; 1979 amdgpu_connector->con_priv = amdgpu_dig_connector; 1980 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_virtual_funcs, connector_type); 1981 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_virtual_helper_funcs); 1982 subpixel_order = SubPixelHorizontalRGB; 1983 connector->interlace_allowed = false; 1984 connector->doublescan_allowed = false; 1985 break; 1986 } 1987 } 1988 1989 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1990 if (i2c_bus->valid) { 1991 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1992 DRM_CONNECTOR_POLL_DISCONNECT; 1993 } 1994 } else 1995 connector->polled = DRM_CONNECTOR_POLL_HPD; 1996 1997 connector->display_info.subpixel_order = subpixel_order; 1998 drm_connector_register(connector); 1999 2000 if (has_aux) 2001 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2002 2003 return; 2004 2005 failed: 2006 drm_connector_cleanup(connector); 2007 kfree(connector); 2008 } 2009