1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73 int saved_dpms = connector->dpms; 74 /* Only turn off the display if it's physically disconnected */ 75 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't try to start link training before we 79 * have the dpcd */ 80 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 return; 82 83 /* set it to OFF so that drm_helper_connector_dpms() 84 * won't return immediately since the current state 85 * is ON at this point. 86 */ 87 connector->dpms = DRM_MODE_DPMS_OFF; 88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89 } 90 connector->dpms = saved_dpms; 91 } 92 } 93 } 94 95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 96 { 97 struct drm_crtc *crtc = encoder->crtc; 98 99 if (crtc && crtc->enabled) { 100 drm_crtc_helper_set_mode(crtc, &crtc->mode, 101 crtc->x, crtc->y, crtc->primary->fb); 102 } 103 } 104 105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 106 { 107 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 108 struct amdgpu_connector_atom_dig *dig_connector; 109 int bpc = 8; 110 unsigned mode_clock, max_tmds_clock; 111 112 switch (connector->connector_type) { 113 case DRM_MODE_CONNECTOR_DVII: 114 case DRM_MODE_CONNECTOR_HDMIB: 115 if (amdgpu_connector->use_digital) { 116 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 117 if (connector->display_info.bpc) 118 bpc = connector->display_info.bpc; 119 } 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DVID: 123 case DRM_MODE_CONNECTOR_HDMIA: 124 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 125 if (connector->display_info.bpc) 126 bpc = connector->display_info.bpc; 127 } 128 break; 129 case DRM_MODE_CONNECTOR_DisplayPort: 130 dig_connector = amdgpu_connector->con_priv; 131 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 132 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 133 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 134 if (connector->display_info.bpc) 135 bpc = connector->display_info.bpc; 136 } 137 break; 138 case DRM_MODE_CONNECTOR_eDP: 139 case DRM_MODE_CONNECTOR_LVDS: 140 if (connector->display_info.bpc) 141 bpc = connector->display_info.bpc; 142 else { 143 const struct drm_connector_helper_funcs *connector_funcs = 144 connector->helper_private; 145 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 146 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 147 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 148 149 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 150 bpc = 6; 151 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 152 bpc = 8; 153 } 154 break; 155 } 156 157 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 158 /* 159 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 160 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 161 * 12 bpc is always supported on hdmi deep color sinks, as this is 162 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 163 */ 164 if (bpc > 12) { 165 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 166 connector->name, bpc); 167 bpc = 12; 168 } 169 170 /* Any defined maximum tmds clock limit we must not exceed? */ 171 if (connector->max_tmds_clock > 0) { 172 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 173 mode_clock = amdgpu_connector->pixelclock_for_modeset; 174 175 /* Maximum allowable input clock in kHz */ 176 max_tmds_clock = connector->max_tmds_clock * 1000; 177 178 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 179 connector->name, mode_clock, max_tmds_clock); 180 181 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 182 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 183 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 184 (mode_clock * 5/4 <= max_tmds_clock)) 185 bpc = 10; 186 else 187 bpc = 8; 188 189 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 190 connector->name, bpc); 191 } 192 193 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 194 bpc = 8; 195 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 196 connector->name, bpc); 197 } else if (bpc > 8) { 198 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 199 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 200 connector->name); 201 bpc = 8; 202 } 203 } 204 } 205 206 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 207 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 208 connector->name); 209 bpc = 8; 210 } 211 212 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 213 connector->name, connector->display_info.bpc, bpc); 214 215 return bpc; 216 } 217 218 static void 219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 220 enum drm_connector_status status) 221 { 222 struct drm_encoder *best_encoder = NULL; 223 struct drm_encoder *encoder = NULL; 224 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 225 bool connected; 226 int i; 227 228 best_encoder = connector_funcs->best_encoder(connector); 229 230 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 231 if (connector->encoder_ids[i] == 0) 232 break; 233 234 encoder = drm_encoder_find(connector->dev, 235 connector->encoder_ids[i]); 236 if (!encoder) 237 continue; 238 239 if ((encoder == best_encoder) && (status == connector_status_connected)) 240 connected = true; 241 else 242 connected = false; 243 244 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 245 246 } 247 } 248 249 static struct drm_encoder * 250 amdgpu_connector_find_encoder(struct drm_connector *connector, 251 int encoder_type) 252 { 253 struct drm_encoder *encoder; 254 int i; 255 256 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 257 if (connector->encoder_ids[i] == 0) 258 break; 259 encoder = drm_encoder_find(connector->dev, 260 connector->encoder_ids[i]); 261 if (!encoder) 262 continue; 263 264 if (encoder->encoder_type == encoder_type) 265 return encoder; 266 } 267 return NULL; 268 } 269 270 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 271 { 272 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 273 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 274 275 if (amdgpu_connector->edid) { 276 return amdgpu_connector->edid; 277 } else if (edid_blob) { 278 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 279 if (edid) 280 amdgpu_connector->edid = edid; 281 } 282 return amdgpu_connector->edid; 283 } 284 285 static struct edid * 286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 287 { 288 struct edid *edid; 289 290 if (adev->mode_info.bios_hardcoded_edid) { 291 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 292 if (edid) { 293 memcpy((unsigned char *)edid, 294 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 295 adev->mode_info.bios_hardcoded_edid_size); 296 return edid; 297 } 298 } 299 return NULL; 300 } 301 302 static void amdgpu_connector_get_edid(struct drm_connector *connector) 303 { 304 struct drm_device *dev = connector->dev; 305 struct amdgpu_device *adev = dev->dev_private; 306 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307 308 if (amdgpu_connector->edid) 309 return; 310 311 /* on hw with routers, select right port */ 312 if (amdgpu_connector->router.ddc_valid) 313 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 314 315 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 316 ENCODER_OBJECT_ID_NONE) && 317 amdgpu_connector->ddc_bus->has_aux) { 318 amdgpu_connector->edid = drm_get_edid(connector, 319 &amdgpu_connector->ddc_bus->aux.ddc); 320 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 321 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 322 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 323 324 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 325 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 326 amdgpu_connector->ddc_bus->has_aux) 327 amdgpu_connector->edid = drm_get_edid(connector, 328 &amdgpu_connector->ddc_bus->aux.ddc); 329 else if (amdgpu_connector->ddc_bus) 330 amdgpu_connector->edid = drm_get_edid(connector, 331 &amdgpu_connector->ddc_bus->adapter); 332 } else if (amdgpu_connector->ddc_bus) { 333 amdgpu_connector->edid = drm_get_edid(connector, 334 &amdgpu_connector->ddc_bus->adapter); 335 } 336 337 if (!amdgpu_connector->edid) { 338 /* some laptops provide a hardcoded edid in rom for LCDs */ 339 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 340 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 341 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 342 } 343 } 344 345 static void amdgpu_connector_free_edid(struct drm_connector *connector) 346 { 347 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 348 349 if (amdgpu_connector->edid) { 350 kfree(amdgpu_connector->edid); 351 amdgpu_connector->edid = NULL; 352 } 353 } 354 355 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 356 { 357 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 358 int ret; 359 360 if (amdgpu_connector->edid) { 361 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 362 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 363 drm_edid_to_eld(connector, amdgpu_connector->edid); 364 return ret; 365 } 366 drm_mode_connector_update_edid_property(connector, NULL); 367 return 0; 368 } 369 370 static struct drm_encoder * 371 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 372 { 373 int enc_id = connector->encoder_ids[0]; 374 375 /* pick the encoder ids */ 376 if (enc_id) 377 return drm_encoder_find(connector->dev, enc_id); 378 return NULL; 379 } 380 381 static void amdgpu_get_native_mode(struct drm_connector *connector) 382 { 383 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 384 struct amdgpu_encoder *amdgpu_encoder; 385 386 if (encoder == NULL) 387 return; 388 389 amdgpu_encoder = to_amdgpu_encoder(encoder); 390 391 if (!list_empty(&connector->probed_modes)) { 392 struct drm_display_mode *preferred_mode = 393 list_first_entry(&connector->probed_modes, 394 struct drm_display_mode, head); 395 396 amdgpu_encoder->native_mode = *preferred_mode; 397 } else { 398 amdgpu_encoder->native_mode.clock = 0; 399 } 400 } 401 402 static struct drm_display_mode * 403 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 404 { 405 struct drm_device *dev = encoder->dev; 406 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 407 struct drm_display_mode *mode = NULL; 408 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 409 410 if (native_mode->hdisplay != 0 && 411 native_mode->vdisplay != 0 && 412 native_mode->clock != 0) { 413 mode = drm_mode_duplicate(dev, native_mode); 414 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 415 drm_mode_set_name(mode); 416 417 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 418 } else if (native_mode->hdisplay != 0 && 419 native_mode->vdisplay != 0) { 420 /* mac laptops without an edid */ 421 /* Note that this is not necessarily the exact panel mode, 422 * but an approximation based on the cvt formula. For these 423 * systems we should ideally read the mode info out of the 424 * registers or add a mode table, but this works and is much 425 * simpler. 426 */ 427 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 428 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 429 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 430 } 431 return mode; 432 } 433 434 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 435 struct drm_connector *connector) 436 { 437 struct drm_device *dev = encoder->dev; 438 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 439 struct drm_display_mode *mode = NULL; 440 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 441 int i; 442 struct mode_size { 443 int w; 444 int h; 445 } common_modes[17] = { 446 { 640, 480}, 447 { 720, 480}, 448 { 800, 600}, 449 { 848, 480}, 450 {1024, 768}, 451 {1152, 768}, 452 {1280, 720}, 453 {1280, 800}, 454 {1280, 854}, 455 {1280, 960}, 456 {1280, 1024}, 457 {1440, 900}, 458 {1400, 1050}, 459 {1680, 1050}, 460 {1600, 1200}, 461 {1920, 1080}, 462 {1920, 1200} 463 }; 464 465 for (i = 0; i < 17; i++) { 466 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 467 if (common_modes[i].w > 1024 || 468 common_modes[i].h > 768) 469 continue; 470 } 471 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 472 if (common_modes[i].w > native_mode->hdisplay || 473 common_modes[i].h > native_mode->vdisplay || 474 (common_modes[i].w == native_mode->hdisplay && 475 common_modes[i].h == native_mode->vdisplay)) 476 continue; 477 } 478 if (common_modes[i].w < 320 || common_modes[i].h < 200) 479 continue; 480 481 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 482 drm_mode_probed_add(connector, mode); 483 } 484 } 485 486 static int amdgpu_connector_set_property(struct drm_connector *connector, 487 struct drm_property *property, 488 uint64_t val) 489 { 490 struct drm_device *dev = connector->dev; 491 struct amdgpu_device *adev = dev->dev_private; 492 struct drm_encoder *encoder; 493 struct amdgpu_encoder *amdgpu_encoder; 494 495 if (property == adev->mode_info.coherent_mode_property) { 496 struct amdgpu_encoder_atom_dig *dig; 497 bool new_coherent_mode; 498 499 /* need to find digital encoder on connector */ 500 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 501 if (!encoder) 502 return 0; 503 504 amdgpu_encoder = to_amdgpu_encoder(encoder); 505 506 if (!amdgpu_encoder->enc_priv) 507 return 0; 508 509 dig = amdgpu_encoder->enc_priv; 510 new_coherent_mode = val ? true : false; 511 if (dig->coherent_mode != new_coherent_mode) { 512 dig->coherent_mode = new_coherent_mode; 513 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 514 } 515 } 516 517 if (property == adev->mode_info.audio_property) { 518 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 519 /* need to find digital encoder on connector */ 520 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 521 if (!encoder) 522 return 0; 523 524 amdgpu_encoder = to_amdgpu_encoder(encoder); 525 526 if (amdgpu_connector->audio != val) { 527 amdgpu_connector->audio = val; 528 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 529 } 530 } 531 532 if (property == adev->mode_info.dither_property) { 533 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 534 /* need to find digital encoder on connector */ 535 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 536 if (!encoder) 537 return 0; 538 539 amdgpu_encoder = to_amdgpu_encoder(encoder); 540 541 if (amdgpu_connector->dither != val) { 542 amdgpu_connector->dither = val; 543 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 544 } 545 } 546 547 if (property == adev->mode_info.underscan_property) { 548 /* need to find digital encoder on connector */ 549 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 550 if (!encoder) 551 return 0; 552 553 amdgpu_encoder = to_amdgpu_encoder(encoder); 554 555 if (amdgpu_encoder->underscan_type != val) { 556 amdgpu_encoder->underscan_type = val; 557 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 558 } 559 } 560 561 if (property == adev->mode_info.underscan_hborder_property) { 562 /* need to find digital encoder on connector */ 563 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 564 if (!encoder) 565 return 0; 566 567 amdgpu_encoder = to_amdgpu_encoder(encoder); 568 569 if (amdgpu_encoder->underscan_hborder != val) { 570 amdgpu_encoder->underscan_hborder = val; 571 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 572 } 573 } 574 575 if (property == adev->mode_info.underscan_vborder_property) { 576 /* need to find digital encoder on connector */ 577 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 578 if (!encoder) 579 return 0; 580 581 amdgpu_encoder = to_amdgpu_encoder(encoder); 582 583 if (amdgpu_encoder->underscan_vborder != val) { 584 amdgpu_encoder->underscan_vborder = val; 585 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 586 } 587 } 588 589 if (property == adev->mode_info.load_detect_property) { 590 struct amdgpu_connector *amdgpu_connector = 591 to_amdgpu_connector(connector); 592 593 if (val == 0) 594 amdgpu_connector->dac_load_detect = false; 595 else 596 amdgpu_connector->dac_load_detect = true; 597 } 598 599 if (property == dev->mode_config.scaling_mode_property) { 600 enum amdgpu_rmx_type rmx_type; 601 602 if (connector->encoder) { 603 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 604 } else { 605 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 606 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 607 } 608 609 switch (val) { 610 default: 611 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 612 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 613 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 614 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 615 } 616 if (amdgpu_encoder->rmx_type == rmx_type) 617 return 0; 618 619 if ((rmx_type != DRM_MODE_SCALE_NONE) && 620 (amdgpu_encoder->native_mode.clock == 0)) 621 return 0; 622 623 amdgpu_encoder->rmx_type = rmx_type; 624 625 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 626 } 627 628 return 0; 629 } 630 631 static void 632 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 633 struct drm_connector *connector) 634 { 635 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 636 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 637 struct drm_display_mode *t, *mode; 638 639 /* If the EDID preferred mode doesn't match the native mode, use it */ 640 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 641 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 642 if (mode->hdisplay != native_mode->hdisplay || 643 mode->vdisplay != native_mode->vdisplay) 644 memcpy(native_mode, mode, sizeof(*mode)); 645 } 646 } 647 648 /* Try to get native mode details from EDID if necessary */ 649 if (!native_mode->clock) { 650 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 651 if (mode->hdisplay == native_mode->hdisplay && 652 mode->vdisplay == native_mode->vdisplay) { 653 *native_mode = *mode; 654 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 655 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 656 break; 657 } 658 } 659 } 660 661 if (!native_mode->clock) { 662 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 663 amdgpu_encoder->rmx_type = RMX_OFF; 664 } 665 } 666 667 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 668 { 669 struct drm_encoder *encoder; 670 int ret = 0; 671 struct drm_display_mode *mode; 672 673 amdgpu_connector_get_edid(connector); 674 ret = amdgpu_connector_ddc_get_modes(connector); 675 if (ret > 0) { 676 encoder = amdgpu_connector_best_single_encoder(connector); 677 if (encoder) { 678 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 679 /* add scaled modes */ 680 amdgpu_connector_add_common_modes(encoder, connector); 681 } 682 return ret; 683 } 684 685 encoder = amdgpu_connector_best_single_encoder(connector); 686 if (!encoder) 687 return 0; 688 689 /* we have no EDID modes */ 690 mode = amdgpu_connector_lcd_native_mode(encoder); 691 if (mode) { 692 ret = 1; 693 drm_mode_probed_add(connector, mode); 694 /* add the width/height from vbios tables if available */ 695 connector->display_info.width_mm = mode->width_mm; 696 connector->display_info.height_mm = mode->height_mm; 697 /* add scaled modes */ 698 amdgpu_connector_add_common_modes(encoder, connector); 699 } 700 701 return ret; 702 } 703 704 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 705 struct drm_display_mode *mode) 706 { 707 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708 709 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 710 return MODE_PANEL; 711 712 if (encoder) { 713 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 714 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 715 716 /* AVIVO hardware supports downscaling modes larger than the panel 717 * to the panel size, but I'm not sure this is desirable. 718 */ 719 if ((mode->hdisplay > native_mode->hdisplay) || 720 (mode->vdisplay > native_mode->vdisplay)) 721 return MODE_PANEL; 722 723 /* if scaling is disabled, block non-native modes */ 724 if (amdgpu_encoder->rmx_type == RMX_OFF) { 725 if ((mode->hdisplay != native_mode->hdisplay) || 726 (mode->vdisplay != native_mode->vdisplay)) 727 return MODE_PANEL; 728 } 729 } 730 731 return MODE_OK; 732 } 733 734 static enum drm_connector_status 735 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 736 { 737 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 738 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 739 enum drm_connector_status ret = connector_status_disconnected; 740 int r; 741 742 r = pm_runtime_get_sync(connector->dev->dev); 743 if (r < 0) 744 return connector_status_disconnected; 745 746 if (encoder) { 747 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 748 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 749 750 /* check if panel is valid */ 751 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 752 ret = connector_status_connected; 753 754 } 755 756 /* check for edid as well */ 757 amdgpu_connector_get_edid(connector); 758 if (amdgpu_connector->edid) 759 ret = connector_status_connected; 760 /* check acpi lid status ??? */ 761 762 amdgpu_connector_update_scratch_regs(connector, ret); 763 pm_runtime_mark_last_busy(connector->dev->dev); 764 pm_runtime_put_autosuspend(connector->dev->dev); 765 return ret; 766 } 767 768 static void amdgpu_connector_destroy(struct drm_connector *connector) 769 { 770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 771 772 if (amdgpu_connector->ddc_bus->has_aux) 773 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 774 amdgpu_connector_free_edid(connector); 775 kfree(amdgpu_connector->con_priv); 776 drm_connector_unregister(connector); 777 drm_connector_cleanup(connector); 778 kfree(connector); 779 } 780 781 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 782 struct drm_property *property, 783 uint64_t value) 784 { 785 struct drm_device *dev = connector->dev; 786 struct amdgpu_encoder *amdgpu_encoder; 787 enum amdgpu_rmx_type rmx_type; 788 789 DRM_DEBUG_KMS("\n"); 790 if (property != dev->mode_config.scaling_mode_property) 791 return 0; 792 793 if (connector->encoder) 794 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 795 else { 796 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 797 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 798 } 799 800 switch (value) { 801 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 802 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 803 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 804 default: 805 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 806 } 807 if (amdgpu_encoder->rmx_type == rmx_type) 808 return 0; 809 810 amdgpu_encoder->rmx_type = rmx_type; 811 812 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 813 return 0; 814 } 815 816 817 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 818 .get_modes = amdgpu_connector_lvds_get_modes, 819 .mode_valid = amdgpu_connector_lvds_mode_valid, 820 .best_encoder = amdgpu_connector_best_single_encoder, 821 }; 822 823 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 824 .dpms = drm_helper_connector_dpms, 825 .detect = amdgpu_connector_lvds_detect, 826 .fill_modes = drm_helper_probe_single_connector_modes, 827 .destroy = amdgpu_connector_destroy, 828 .set_property = amdgpu_connector_set_lcd_property, 829 }; 830 831 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 832 { 833 int ret; 834 835 amdgpu_connector_get_edid(connector); 836 ret = amdgpu_connector_ddc_get_modes(connector); 837 838 return ret; 839 } 840 841 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 842 struct drm_display_mode *mode) 843 { 844 struct drm_device *dev = connector->dev; 845 struct amdgpu_device *adev = dev->dev_private; 846 847 /* XXX check mode bandwidth */ 848 849 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 850 return MODE_CLOCK_HIGH; 851 852 return MODE_OK; 853 } 854 855 static enum drm_connector_status 856 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 857 { 858 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 859 struct drm_encoder *encoder; 860 const struct drm_encoder_helper_funcs *encoder_funcs; 861 bool dret = false; 862 enum drm_connector_status ret = connector_status_disconnected; 863 int r; 864 865 r = pm_runtime_get_sync(connector->dev->dev); 866 if (r < 0) 867 return connector_status_disconnected; 868 869 encoder = amdgpu_connector_best_single_encoder(connector); 870 if (!encoder) 871 ret = connector_status_disconnected; 872 873 if (amdgpu_connector->ddc_bus) 874 dret = amdgpu_ddc_probe(amdgpu_connector, false); 875 if (dret) { 876 amdgpu_connector->detected_by_load = false; 877 amdgpu_connector_free_edid(connector); 878 amdgpu_connector_get_edid(connector); 879 880 if (!amdgpu_connector->edid) { 881 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 882 connector->name); 883 ret = connector_status_connected; 884 } else { 885 amdgpu_connector->use_digital = 886 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 887 888 /* some oems have boards with separate digital and analog connectors 889 * with a shared ddc line (often vga + hdmi) 890 */ 891 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 892 amdgpu_connector_free_edid(connector); 893 ret = connector_status_disconnected; 894 } else { 895 ret = connector_status_connected; 896 } 897 } 898 } else { 899 900 /* if we aren't forcing don't do destructive polling */ 901 if (!force) { 902 /* only return the previous status if we last 903 * detected a monitor via load. 904 */ 905 if (amdgpu_connector->detected_by_load) 906 ret = connector->status; 907 goto out; 908 } 909 910 if (amdgpu_connector->dac_load_detect && encoder) { 911 encoder_funcs = encoder->helper_private; 912 ret = encoder_funcs->detect(encoder, connector); 913 if (ret != connector_status_disconnected) 914 amdgpu_connector->detected_by_load = true; 915 } 916 } 917 918 amdgpu_connector_update_scratch_regs(connector, ret); 919 920 out: 921 pm_runtime_mark_last_busy(connector->dev->dev); 922 pm_runtime_put_autosuspend(connector->dev->dev); 923 924 return ret; 925 } 926 927 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 928 .get_modes = amdgpu_connector_vga_get_modes, 929 .mode_valid = amdgpu_connector_vga_mode_valid, 930 .best_encoder = amdgpu_connector_best_single_encoder, 931 }; 932 933 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 934 .dpms = drm_helper_connector_dpms, 935 .detect = amdgpu_connector_vga_detect, 936 .fill_modes = drm_helper_probe_single_connector_modes, 937 .destroy = amdgpu_connector_destroy, 938 .set_property = amdgpu_connector_set_property, 939 }; 940 941 static bool 942 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 943 { 944 struct drm_device *dev = connector->dev; 945 struct amdgpu_device *adev = dev->dev_private; 946 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 947 enum drm_connector_status status; 948 949 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 950 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 951 status = connector_status_connected; 952 else 953 status = connector_status_disconnected; 954 if (connector->status == status) 955 return true; 956 } 957 958 return false; 959 } 960 961 /* 962 * DVI is complicated 963 * Do a DDC probe, if DDC probe passes, get the full EDID so 964 * we can do analog/digital monitor detection at this point. 965 * If the monitor is an analog monitor or we got no DDC, 966 * we need to find the DAC encoder object for this connector. 967 * If we got no DDC, we do load detection on the DAC encoder object. 968 * If we got analog DDC or load detection passes on the DAC encoder 969 * we have to check if this analog encoder is shared with anyone else (TV) 970 * if its shared we have to set the other connector to disconnected. 971 */ 972 static enum drm_connector_status 973 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 974 { 975 struct drm_device *dev = connector->dev; 976 struct amdgpu_device *adev = dev->dev_private; 977 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 978 struct drm_encoder *encoder = NULL; 979 const struct drm_encoder_helper_funcs *encoder_funcs; 980 int i, r; 981 enum drm_connector_status ret = connector_status_disconnected; 982 bool dret = false, broken_edid = false; 983 984 r = pm_runtime_get_sync(connector->dev->dev); 985 if (r < 0) 986 return connector_status_disconnected; 987 988 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 989 ret = connector->status; 990 goto exit; 991 } 992 993 if (amdgpu_connector->ddc_bus) 994 dret = amdgpu_ddc_probe(amdgpu_connector, false); 995 if (dret) { 996 amdgpu_connector->detected_by_load = false; 997 amdgpu_connector_free_edid(connector); 998 amdgpu_connector_get_edid(connector); 999 1000 if (!amdgpu_connector->edid) { 1001 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1002 connector->name); 1003 ret = connector_status_connected; 1004 broken_edid = true; /* defer use_digital to later */ 1005 } else { 1006 amdgpu_connector->use_digital = 1007 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1008 1009 /* some oems have boards with separate digital and analog connectors 1010 * with a shared ddc line (often vga + hdmi) 1011 */ 1012 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1013 amdgpu_connector_free_edid(connector); 1014 ret = connector_status_disconnected; 1015 } else { 1016 ret = connector_status_connected; 1017 } 1018 1019 /* This gets complicated. We have boards with VGA + HDMI with a 1020 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1021 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1022 * you don't really know what's connected to which port as both are digital. 1023 */ 1024 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1025 struct drm_connector *list_connector; 1026 struct amdgpu_connector *list_amdgpu_connector; 1027 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1028 if (connector == list_connector) 1029 continue; 1030 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1031 if (list_amdgpu_connector->shared_ddc && 1032 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1033 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1034 /* cases where both connectors are digital */ 1035 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1036 /* hpd is our only option in this case */ 1037 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1038 amdgpu_connector_free_edid(connector); 1039 ret = connector_status_disconnected; 1040 } 1041 } 1042 } 1043 } 1044 } 1045 } 1046 } 1047 1048 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1049 goto out; 1050 1051 /* DVI-D and HDMI-A are digital only */ 1052 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1053 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1054 goto out; 1055 1056 /* if we aren't forcing don't do destructive polling */ 1057 if (!force) { 1058 /* only return the previous status if we last 1059 * detected a monitor via load. 1060 */ 1061 if (amdgpu_connector->detected_by_load) 1062 ret = connector->status; 1063 goto out; 1064 } 1065 1066 /* find analog encoder */ 1067 if (amdgpu_connector->dac_load_detect) { 1068 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1069 if (connector->encoder_ids[i] == 0) 1070 break; 1071 1072 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1073 if (!encoder) 1074 continue; 1075 1076 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1077 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1078 continue; 1079 1080 encoder_funcs = encoder->helper_private; 1081 if (encoder_funcs->detect) { 1082 if (!broken_edid) { 1083 if (ret != connector_status_connected) { 1084 /* deal with analog monitors without DDC */ 1085 ret = encoder_funcs->detect(encoder, connector); 1086 if (ret == connector_status_connected) { 1087 amdgpu_connector->use_digital = false; 1088 } 1089 if (ret != connector_status_disconnected) 1090 amdgpu_connector->detected_by_load = true; 1091 } 1092 } else { 1093 enum drm_connector_status lret; 1094 /* assume digital unless load detected otherwise */ 1095 amdgpu_connector->use_digital = true; 1096 lret = encoder_funcs->detect(encoder, connector); 1097 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1098 if (lret == connector_status_connected) 1099 amdgpu_connector->use_digital = false; 1100 } 1101 break; 1102 } 1103 } 1104 } 1105 1106 out: 1107 /* updated in get modes as well since we need to know if it's analog or digital */ 1108 amdgpu_connector_update_scratch_regs(connector, ret); 1109 1110 exit: 1111 pm_runtime_mark_last_busy(connector->dev->dev); 1112 pm_runtime_put_autosuspend(connector->dev->dev); 1113 1114 return ret; 1115 } 1116 1117 /* okay need to be smart in here about which encoder to pick */ 1118 static struct drm_encoder * 1119 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1120 { 1121 int enc_id = connector->encoder_ids[0]; 1122 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1123 struct drm_encoder *encoder; 1124 int i; 1125 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1126 if (connector->encoder_ids[i] == 0) 1127 break; 1128 1129 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1130 if (!encoder) 1131 continue; 1132 1133 if (amdgpu_connector->use_digital == true) { 1134 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1135 return encoder; 1136 } else { 1137 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1138 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1139 return encoder; 1140 } 1141 } 1142 1143 /* see if we have a default encoder TODO */ 1144 1145 /* then check use digitial */ 1146 /* pick the first one */ 1147 if (enc_id) 1148 return drm_encoder_find(connector->dev, enc_id); 1149 return NULL; 1150 } 1151 1152 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1153 { 1154 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1155 if (connector->force == DRM_FORCE_ON) 1156 amdgpu_connector->use_digital = false; 1157 if (connector->force == DRM_FORCE_ON_DIGITAL) 1158 amdgpu_connector->use_digital = true; 1159 } 1160 1161 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1162 struct drm_display_mode *mode) 1163 { 1164 struct drm_device *dev = connector->dev; 1165 struct amdgpu_device *adev = dev->dev_private; 1166 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1167 1168 /* XXX check mode bandwidth */ 1169 1170 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1171 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1172 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1173 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1174 return MODE_OK; 1175 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1176 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1177 if (mode->clock > 340000) 1178 return MODE_CLOCK_HIGH; 1179 else 1180 return MODE_OK; 1181 } else { 1182 return MODE_CLOCK_HIGH; 1183 } 1184 } 1185 1186 /* check against the max pixel clock */ 1187 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1188 return MODE_CLOCK_HIGH; 1189 1190 return MODE_OK; 1191 } 1192 1193 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1194 .get_modes = amdgpu_connector_vga_get_modes, 1195 .mode_valid = amdgpu_connector_dvi_mode_valid, 1196 .best_encoder = amdgpu_connector_dvi_encoder, 1197 }; 1198 1199 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1200 .dpms = drm_helper_connector_dpms, 1201 .detect = amdgpu_connector_dvi_detect, 1202 .fill_modes = drm_helper_probe_single_connector_modes, 1203 .set_property = amdgpu_connector_set_property, 1204 .destroy = amdgpu_connector_destroy, 1205 .force = amdgpu_connector_dvi_force, 1206 }; 1207 1208 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1209 { 1210 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1211 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1212 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1213 int ret; 1214 1215 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1216 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1217 struct drm_display_mode *mode; 1218 1219 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1220 if (!amdgpu_dig_connector->edp_on) 1221 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1222 ATOM_TRANSMITTER_ACTION_POWER_ON); 1223 amdgpu_connector_get_edid(connector); 1224 ret = amdgpu_connector_ddc_get_modes(connector); 1225 if (!amdgpu_dig_connector->edp_on) 1226 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1227 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1228 } else { 1229 /* need to setup ddc on the bridge */ 1230 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1231 ENCODER_OBJECT_ID_NONE) { 1232 if (encoder) 1233 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1234 } 1235 amdgpu_connector_get_edid(connector); 1236 ret = amdgpu_connector_ddc_get_modes(connector); 1237 } 1238 1239 if (ret > 0) { 1240 if (encoder) { 1241 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1242 /* add scaled modes */ 1243 amdgpu_connector_add_common_modes(encoder, connector); 1244 } 1245 return ret; 1246 } 1247 1248 if (!encoder) 1249 return 0; 1250 1251 /* we have no EDID modes */ 1252 mode = amdgpu_connector_lcd_native_mode(encoder); 1253 if (mode) { 1254 ret = 1; 1255 drm_mode_probed_add(connector, mode); 1256 /* add the width/height from vbios tables if available */ 1257 connector->display_info.width_mm = mode->width_mm; 1258 connector->display_info.height_mm = mode->height_mm; 1259 /* add scaled modes */ 1260 amdgpu_connector_add_common_modes(encoder, connector); 1261 } 1262 } else { 1263 /* need to setup ddc on the bridge */ 1264 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1265 ENCODER_OBJECT_ID_NONE) { 1266 if (encoder) 1267 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1268 } 1269 amdgpu_connector_get_edid(connector); 1270 ret = amdgpu_connector_ddc_get_modes(connector); 1271 1272 amdgpu_get_native_mode(connector); 1273 } 1274 1275 return ret; 1276 } 1277 1278 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1279 { 1280 struct drm_encoder *encoder; 1281 struct amdgpu_encoder *amdgpu_encoder; 1282 int i; 1283 1284 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1285 if (connector->encoder_ids[i] == 0) 1286 break; 1287 1288 encoder = drm_encoder_find(connector->dev, 1289 connector->encoder_ids[i]); 1290 if (!encoder) 1291 continue; 1292 1293 amdgpu_encoder = to_amdgpu_encoder(encoder); 1294 1295 switch (amdgpu_encoder->encoder_id) { 1296 case ENCODER_OBJECT_ID_TRAVIS: 1297 case ENCODER_OBJECT_ID_NUTMEG: 1298 return amdgpu_encoder->encoder_id; 1299 default: 1300 break; 1301 } 1302 } 1303 1304 return ENCODER_OBJECT_ID_NONE; 1305 } 1306 1307 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1308 { 1309 struct drm_encoder *encoder; 1310 struct amdgpu_encoder *amdgpu_encoder; 1311 int i; 1312 bool found = false; 1313 1314 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1315 if (connector->encoder_ids[i] == 0) 1316 break; 1317 encoder = drm_encoder_find(connector->dev, 1318 connector->encoder_ids[i]); 1319 if (!encoder) 1320 continue; 1321 1322 amdgpu_encoder = to_amdgpu_encoder(encoder); 1323 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1324 found = true; 1325 } 1326 1327 return found; 1328 } 1329 1330 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1331 { 1332 struct drm_device *dev = connector->dev; 1333 struct amdgpu_device *adev = dev->dev_private; 1334 1335 if ((adev->clock.default_dispclk >= 53900) && 1336 amdgpu_connector_encoder_is_hbr2(connector)) { 1337 return true; 1338 } 1339 1340 return false; 1341 } 1342 1343 static enum drm_connector_status 1344 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1345 { 1346 struct drm_device *dev = connector->dev; 1347 struct amdgpu_device *adev = dev->dev_private; 1348 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1349 enum drm_connector_status ret = connector_status_disconnected; 1350 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1351 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1352 int r; 1353 1354 r = pm_runtime_get_sync(connector->dev->dev); 1355 if (r < 0) 1356 return connector_status_disconnected; 1357 1358 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1359 ret = connector->status; 1360 goto out; 1361 } 1362 1363 amdgpu_connector_free_edid(connector); 1364 1365 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1366 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1367 if (encoder) { 1368 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1369 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1370 1371 /* check if panel is valid */ 1372 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1373 ret = connector_status_connected; 1374 } 1375 /* eDP is always DP */ 1376 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1377 if (!amdgpu_dig_connector->edp_on) 1378 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1379 ATOM_TRANSMITTER_ACTION_POWER_ON); 1380 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1381 ret = connector_status_connected; 1382 if (!amdgpu_dig_connector->edp_on) 1383 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1384 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1385 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1386 ENCODER_OBJECT_ID_NONE) { 1387 /* DP bridges are always DP */ 1388 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1389 /* get the DPCD from the bridge */ 1390 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1391 1392 if (encoder) { 1393 /* setup ddc on the bridge */ 1394 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1395 /* bridge chips are always aux */ 1396 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1397 ret = connector_status_connected; 1398 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1399 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1400 ret = encoder_funcs->detect(encoder, connector); 1401 } 1402 } 1403 } else { 1404 amdgpu_dig_connector->dp_sink_type = 1405 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1406 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1407 ret = connector_status_connected; 1408 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1409 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1410 } else { 1411 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1412 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1413 ret = connector_status_connected; 1414 } else { 1415 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1416 if (amdgpu_ddc_probe(amdgpu_connector, false)) 1417 ret = connector_status_connected; 1418 } 1419 } 1420 } 1421 1422 amdgpu_connector_update_scratch_regs(connector, ret); 1423 out: 1424 pm_runtime_mark_last_busy(connector->dev->dev); 1425 pm_runtime_put_autosuspend(connector->dev->dev); 1426 1427 return ret; 1428 } 1429 1430 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1431 struct drm_display_mode *mode) 1432 { 1433 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1434 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1435 1436 /* XXX check mode bandwidth */ 1437 1438 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1439 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1440 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1441 1442 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1443 return MODE_PANEL; 1444 1445 if (encoder) { 1446 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1447 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1448 1449 /* AVIVO hardware supports downscaling modes larger than the panel 1450 * to the panel size, but I'm not sure this is desirable. 1451 */ 1452 if ((mode->hdisplay > native_mode->hdisplay) || 1453 (mode->vdisplay > native_mode->vdisplay)) 1454 return MODE_PANEL; 1455 1456 /* if scaling is disabled, block non-native modes */ 1457 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1458 if ((mode->hdisplay != native_mode->hdisplay) || 1459 (mode->vdisplay != native_mode->vdisplay)) 1460 return MODE_PANEL; 1461 } 1462 } 1463 return MODE_OK; 1464 } else { 1465 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1466 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1467 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1468 } else { 1469 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1470 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1471 if (mode->clock > 340000) 1472 return MODE_CLOCK_HIGH; 1473 } else { 1474 if (mode->clock > 165000) 1475 return MODE_CLOCK_HIGH; 1476 } 1477 } 1478 } 1479 1480 return MODE_OK; 1481 } 1482 1483 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1484 .get_modes = amdgpu_connector_dp_get_modes, 1485 .mode_valid = amdgpu_connector_dp_mode_valid, 1486 .best_encoder = amdgpu_connector_dvi_encoder, 1487 }; 1488 1489 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1490 .dpms = drm_helper_connector_dpms, 1491 .detect = amdgpu_connector_dp_detect, 1492 .fill_modes = drm_helper_probe_single_connector_modes, 1493 .set_property = amdgpu_connector_set_property, 1494 .destroy = amdgpu_connector_destroy, 1495 .force = amdgpu_connector_dvi_force, 1496 }; 1497 1498 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1499 .dpms = drm_helper_connector_dpms, 1500 .detect = amdgpu_connector_dp_detect, 1501 .fill_modes = drm_helper_probe_single_connector_modes, 1502 .set_property = amdgpu_connector_set_lcd_property, 1503 .destroy = amdgpu_connector_destroy, 1504 .force = amdgpu_connector_dvi_force, 1505 }; 1506 1507 void 1508 amdgpu_connector_add(struct amdgpu_device *adev, 1509 uint32_t connector_id, 1510 uint32_t supported_device, 1511 int connector_type, 1512 struct amdgpu_i2c_bus_rec *i2c_bus, 1513 uint16_t connector_object_id, 1514 struct amdgpu_hpd *hpd, 1515 struct amdgpu_router *router) 1516 { 1517 struct drm_device *dev = adev->ddev; 1518 struct drm_connector *connector; 1519 struct amdgpu_connector *amdgpu_connector; 1520 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1521 struct drm_encoder *encoder; 1522 struct amdgpu_encoder *amdgpu_encoder; 1523 uint32_t subpixel_order = SubPixelNone; 1524 bool shared_ddc = false; 1525 bool is_dp_bridge = false; 1526 bool has_aux = false; 1527 1528 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1529 return; 1530 1531 /* see if we already added it */ 1532 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1533 amdgpu_connector = to_amdgpu_connector(connector); 1534 if (amdgpu_connector->connector_id == connector_id) { 1535 amdgpu_connector->devices |= supported_device; 1536 return; 1537 } 1538 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1539 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1540 amdgpu_connector->shared_ddc = true; 1541 shared_ddc = true; 1542 } 1543 if (amdgpu_connector->router_bus && router->ddc_valid && 1544 (amdgpu_connector->router.router_id == router->router_id)) { 1545 amdgpu_connector->shared_ddc = false; 1546 shared_ddc = false; 1547 } 1548 } 1549 } 1550 1551 /* check if it's a dp bridge */ 1552 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1553 amdgpu_encoder = to_amdgpu_encoder(encoder); 1554 if (amdgpu_encoder->devices & supported_device) { 1555 switch (amdgpu_encoder->encoder_id) { 1556 case ENCODER_OBJECT_ID_TRAVIS: 1557 case ENCODER_OBJECT_ID_NUTMEG: 1558 is_dp_bridge = true; 1559 break; 1560 default: 1561 break; 1562 } 1563 } 1564 } 1565 1566 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1567 if (!amdgpu_connector) 1568 return; 1569 1570 connector = &amdgpu_connector->base; 1571 1572 amdgpu_connector->connector_id = connector_id; 1573 amdgpu_connector->devices = supported_device; 1574 amdgpu_connector->shared_ddc = shared_ddc; 1575 amdgpu_connector->connector_object_id = connector_object_id; 1576 amdgpu_connector->hpd = *hpd; 1577 1578 amdgpu_connector->router = *router; 1579 if (router->ddc_valid || router->cd_valid) { 1580 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1581 if (!amdgpu_connector->router_bus) 1582 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1583 } 1584 1585 if (is_dp_bridge) { 1586 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1587 if (!amdgpu_dig_connector) 1588 goto failed; 1589 amdgpu_connector->con_priv = amdgpu_dig_connector; 1590 if (i2c_bus->valid) { 1591 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1592 if (amdgpu_connector->ddc_bus) 1593 has_aux = true; 1594 else 1595 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1596 } 1597 switch (connector_type) { 1598 case DRM_MODE_CONNECTOR_VGA: 1599 case DRM_MODE_CONNECTOR_DVIA: 1600 default: 1601 drm_connector_init(dev, &amdgpu_connector->base, 1602 &amdgpu_connector_dp_funcs, connector_type); 1603 drm_connector_helper_add(&amdgpu_connector->base, 1604 &amdgpu_connector_dp_helper_funcs); 1605 connector->interlace_allowed = true; 1606 connector->doublescan_allowed = true; 1607 amdgpu_connector->dac_load_detect = true; 1608 drm_object_attach_property(&amdgpu_connector->base.base, 1609 adev->mode_info.load_detect_property, 1610 1); 1611 drm_object_attach_property(&amdgpu_connector->base.base, 1612 dev->mode_config.scaling_mode_property, 1613 DRM_MODE_SCALE_NONE); 1614 break; 1615 case DRM_MODE_CONNECTOR_DVII: 1616 case DRM_MODE_CONNECTOR_DVID: 1617 case DRM_MODE_CONNECTOR_HDMIA: 1618 case DRM_MODE_CONNECTOR_HDMIB: 1619 case DRM_MODE_CONNECTOR_DisplayPort: 1620 drm_connector_init(dev, &amdgpu_connector->base, 1621 &amdgpu_connector_dp_funcs, connector_type); 1622 drm_connector_helper_add(&amdgpu_connector->base, 1623 &amdgpu_connector_dp_helper_funcs); 1624 drm_object_attach_property(&amdgpu_connector->base.base, 1625 adev->mode_info.underscan_property, 1626 UNDERSCAN_OFF); 1627 drm_object_attach_property(&amdgpu_connector->base.base, 1628 adev->mode_info.underscan_hborder_property, 1629 0); 1630 drm_object_attach_property(&amdgpu_connector->base.base, 1631 adev->mode_info.underscan_vborder_property, 1632 0); 1633 1634 drm_object_attach_property(&amdgpu_connector->base.base, 1635 dev->mode_config.scaling_mode_property, 1636 DRM_MODE_SCALE_NONE); 1637 1638 drm_object_attach_property(&amdgpu_connector->base.base, 1639 adev->mode_info.dither_property, 1640 AMDGPU_FMT_DITHER_DISABLE); 1641 1642 if (amdgpu_audio != 0) 1643 drm_object_attach_property(&amdgpu_connector->base.base, 1644 adev->mode_info.audio_property, 1645 AMDGPU_AUDIO_AUTO); 1646 1647 subpixel_order = SubPixelHorizontalRGB; 1648 connector->interlace_allowed = true; 1649 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1650 connector->doublescan_allowed = true; 1651 else 1652 connector->doublescan_allowed = false; 1653 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1654 amdgpu_connector->dac_load_detect = true; 1655 drm_object_attach_property(&amdgpu_connector->base.base, 1656 adev->mode_info.load_detect_property, 1657 1); 1658 } 1659 break; 1660 case DRM_MODE_CONNECTOR_LVDS: 1661 case DRM_MODE_CONNECTOR_eDP: 1662 drm_connector_init(dev, &amdgpu_connector->base, 1663 &amdgpu_connector_edp_funcs, connector_type); 1664 drm_connector_helper_add(&amdgpu_connector->base, 1665 &amdgpu_connector_dp_helper_funcs); 1666 drm_object_attach_property(&amdgpu_connector->base.base, 1667 dev->mode_config.scaling_mode_property, 1668 DRM_MODE_SCALE_FULLSCREEN); 1669 subpixel_order = SubPixelHorizontalRGB; 1670 connector->interlace_allowed = false; 1671 connector->doublescan_allowed = false; 1672 break; 1673 } 1674 } else { 1675 switch (connector_type) { 1676 case DRM_MODE_CONNECTOR_VGA: 1677 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1678 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1679 if (i2c_bus->valid) { 1680 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1681 if (!amdgpu_connector->ddc_bus) 1682 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1683 } 1684 amdgpu_connector->dac_load_detect = true; 1685 drm_object_attach_property(&amdgpu_connector->base.base, 1686 adev->mode_info.load_detect_property, 1687 1); 1688 drm_object_attach_property(&amdgpu_connector->base.base, 1689 dev->mode_config.scaling_mode_property, 1690 DRM_MODE_SCALE_NONE); 1691 /* no HPD on analog connectors */ 1692 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1693 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1694 connector->interlace_allowed = true; 1695 connector->doublescan_allowed = true; 1696 break; 1697 case DRM_MODE_CONNECTOR_DVIA: 1698 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1699 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1700 if (i2c_bus->valid) { 1701 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1702 if (!amdgpu_connector->ddc_bus) 1703 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1704 } 1705 amdgpu_connector->dac_load_detect = true; 1706 drm_object_attach_property(&amdgpu_connector->base.base, 1707 adev->mode_info.load_detect_property, 1708 1); 1709 drm_object_attach_property(&amdgpu_connector->base.base, 1710 dev->mode_config.scaling_mode_property, 1711 DRM_MODE_SCALE_NONE); 1712 /* no HPD on analog connectors */ 1713 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1714 connector->interlace_allowed = true; 1715 connector->doublescan_allowed = true; 1716 break; 1717 case DRM_MODE_CONNECTOR_DVII: 1718 case DRM_MODE_CONNECTOR_DVID: 1719 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1720 if (!amdgpu_dig_connector) 1721 goto failed; 1722 amdgpu_connector->con_priv = amdgpu_dig_connector; 1723 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1724 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1725 if (i2c_bus->valid) { 1726 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1727 if (!amdgpu_connector->ddc_bus) 1728 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1729 } 1730 subpixel_order = SubPixelHorizontalRGB; 1731 drm_object_attach_property(&amdgpu_connector->base.base, 1732 adev->mode_info.coherent_mode_property, 1733 1); 1734 drm_object_attach_property(&amdgpu_connector->base.base, 1735 adev->mode_info.underscan_property, 1736 UNDERSCAN_OFF); 1737 drm_object_attach_property(&amdgpu_connector->base.base, 1738 adev->mode_info.underscan_hborder_property, 1739 0); 1740 drm_object_attach_property(&amdgpu_connector->base.base, 1741 adev->mode_info.underscan_vborder_property, 1742 0); 1743 drm_object_attach_property(&amdgpu_connector->base.base, 1744 dev->mode_config.scaling_mode_property, 1745 DRM_MODE_SCALE_NONE); 1746 1747 if (amdgpu_audio != 0) { 1748 drm_object_attach_property(&amdgpu_connector->base.base, 1749 adev->mode_info.audio_property, 1750 AMDGPU_AUDIO_AUTO); 1751 } 1752 drm_object_attach_property(&amdgpu_connector->base.base, 1753 adev->mode_info.dither_property, 1754 AMDGPU_FMT_DITHER_DISABLE); 1755 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1756 amdgpu_connector->dac_load_detect = true; 1757 drm_object_attach_property(&amdgpu_connector->base.base, 1758 adev->mode_info.load_detect_property, 1759 1); 1760 } 1761 connector->interlace_allowed = true; 1762 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1763 connector->doublescan_allowed = true; 1764 else 1765 connector->doublescan_allowed = false; 1766 break; 1767 case DRM_MODE_CONNECTOR_HDMIA: 1768 case DRM_MODE_CONNECTOR_HDMIB: 1769 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1770 if (!amdgpu_dig_connector) 1771 goto failed; 1772 amdgpu_connector->con_priv = amdgpu_dig_connector; 1773 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1774 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1775 if (i2c_bus->valid) { 1776 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1777 if (!amdgpu_connector->ddc_bus) 1778 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1779 } 1780 drm_object_attach_property(&amdgpu_connector->base.base, 1781 adev->mode_info.coherent_mode_property, 1782 1); 1783 drm_object_attach_property(&amdgpu_connector->base.base, 1784 adev->mode_info.underscan_property, 1785 UNDERSCAN_OFF); 1786 drm_object_attach_property(&amdgpu_connector->base.base, 1787 adev->mode_info.underscan_hborder_property, 1788 0); 1789 drm_object_attach_property(&amdgpu_connector->base.base, 1790 adev->mode_info.underscan_vborder_property, 1791 0); 1792 drm_object_attach_property(&amdgpu_connector->base.base, 1793 dev->mode_config.scaling_mode_property, 1794 DRM_MODE_SCALE_NONE); 1795 if (amdgpu_audio != 0) { 1796 drm_object_attach_property(&amdgpu_connector->base.base, 1797 adev->mode_info.audio_property, 1798 AMDGPU_AUDIO_AUTO); 1799 } 1800 drm_object_attach_property(&amdgpu_connector->base.base, 1801 adev->mode_info.dither_property, 1802 AMDGPU_FMT_DITHER_DISABLE); 1803 subpixel_order = SubPixelHorizontalRGB; 1804 connector->interlace_allowed = true; 1805 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1806 connector->doublescan_allowed = true; 1807 else 1808 connector->doublescan_allowed = false; 1809 break; 1810 case DRM_MODE_CONNECTOR_DisplayPort: 1811 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1812 if (!amdgpu_dig_connector) 1813 goto failed; 1814 amdgpu_connector->con_priv = amdgpu_dig_connector; 1815 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1816 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1817 if (i2c_bus->valid) { 1818 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1819 if (amdgpu_connector->ddc_bus) 1820 has_aux = true; 1821 else 1822 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1823 } 1824 subpixel_order = SubPixelHorizontalRGB; 1825 drm_object_attach_property(&amdgpu_connector->base.base, 1826 adev->mode_info.coherent_mode_property, 1827 1); 1828 drm_object_attach_property(&amdgpu_connector->base.base, 1829 adev->mode_info.underscan_property, 1830 UNDERSCAN_OFF); 1831 drm_object_attach_property(&amdgpu_connector->base.base, 1832 adev->mode_info.underscan_hborder_property, 1833 0); 1834 drm_object_attach_property(&amdgpu_connector->base.base, 1835 adev->mode_info.underscan_vborder_property, 1836 0); 1837 drm_object_attach_property(&amdgpu_connector->base.base, 1838 dev->mode_config.scaling_mode_property, 1839 DRM_MODE_SCALE_NONE); 1840 if (amdgpu_audio != 0) { 1841 drm_object_attach_property(&amdgpu_connector->base.base, 1842 adev->mode_info.audio_property, 1843 AMDGPU_AUDIO_AUTO); 1844 } 1845 drm_object_attach_property(&amdgpu_connector->base.base, 1846 adev->mode_info.dither_property, 1847 AMDGPU_FMT_DITHER_DISABLE); 1848 connector->interlace_allowed = true; 1849 /* in theory with a DP to VGA converter... */ 1850 connector->doublescan_allowed = false; 1851 break; 1852 case DRM_MODE_CONNECTOR_eDP: 1853 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1854 if (!amdgpu_dig_connector) 1855 goto failed; 1856 amdgpu_connector->con_priv = amdgpu_dig_connector; 1857 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1858 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1859 if (i2c_bus->valid) { 1860 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1861 if (amdgpu_connector->ddc_bus) 1862 has_aux = true; 1863 else 1864 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1865 } 1866 drm_object_attach_property(&amdgpu_connector->base.base, 1867 dev->mode_config.scaling_mode_property, 1868 DRM_MODE_SCALE_FULLSCREEN); 1869 subpixel_order = SubPixelHorizontalRGB; 1870 connector->interlace_allowed = false; 1871 connector->doublescan_allowed = false; 1872 break; 1873 case DRM_MODE_CONNECTOR_LVDS: 1874 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1875 if (!amdgpu_dig_connector) 1876 goto failed; 1877 amdgpu_connector->con_priv = amdgpu_dig_connector; 1878 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1879 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1880 if (i2c_bus->valid) { 1881 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1882 if (!amdgpu_connector->ddc_bus) 1883 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1884 } 1885 drm_object_attach_property(&amdgpu_connector->base.base, 1886 dev->mode_config.scaling_mode_property, 1887 DRM_MODE_SCALE_FULLSCREEN); 1888 subpixel_order = SubPixelHorizontalRGB; 1889 connector->interlace_allowed = false; 1890 connector->doublescan_allowed = false; 1891 break; 1892 } 1893 } 1894 1895 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1896 if (i2c_bus->valid) 1897 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1898 } else 1899 connector->polled = DRM_CONNECTOR_POLL_HPD; 1900 1901 connector->display_info.subpixel_order = subpixel_order; 1902 drm_connector_register(connector); 1903 1904 if (has_aux) 1905 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1906 1907 return; 1908 1909 failed: 1910 drm_connector_cleanup(connector); 1911 kfree(connector); 1912 } 1913