1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 250 { 251 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 252 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 253 254 if (amdgpu_connector->edid) { 255 return amdgpu_connector->edid; 256 } else if (edid_blob) { 257 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 258 if (edid) 259 amdgpu_connector->edid = edid; 260 } 261 return amdgpu_connector->edid; 262 } 263 264 static struct edid * 265 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 266 { 267 struct edid *edid; 268 269 if (adev->mode_info.bios_hardcoded_edid) { 270 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 271 if (edid) { 272 memcpy((unsigned char *)edid, 273 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 274 adev->mode_info.bios_hardcoded_edid_size); 275 return edid; 276 } 277 } 278 return NULL; 279 } 280 281 static void amdgpu_connector_get_edid(struct drm_connector *connector) 282 { 283 struct drm_device *dev = connector->dev; 284 struct amdgpu_device *adev = drm_to_adev(dev); 285 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 286 287 if (amdgpu_connector->edid) 288 return; 289 290 /* on hw with routers, select right port */ 291 if (amdgpu_connector->router.ddc_valid) 292 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 293 294 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 295 ENCODER_OBJECT_ID_NONE) && 296 amdgpu_connector->ddc_bus->has_aux) { 297 amdgpu_connector->edid = drm_get_edid(connector, 298 &amdgpu_connector->ddc_bus->aux.ddc); 299 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 300 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 301 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 302 303 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 304 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 305 amdgpu_connector->ddc_bus->has_aux) 306 amdgpu_connector->edid = drm_get_edid(connector, 307 &amdgpu_connector->ddc_bus->aux.ddc); 308 else if (amdgpu_connector->ddc_bus) 309 amdgpu_connector->edid = drm_get_edid(connector, 310 &amdgpu_connector->ddc_bus->adapter); 311 } else if (amdgpu_connector->ddc_bus) { 312 amdgpu_connector->edid = drm_get_edid(connector, 313 &amdgpu_connector->ddc_bus->adapter); 314 } 315 316 if (!amdgpu_connector->edid) { 317 /* some laptops provide a hardcoded edid in rom for LCDs */ 318 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 319 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 320 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 321 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 322 } 323 } 324 } 325 326 static void amdgpu_connector_free_edid(struct drm_connector *connector) 327 { 328 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 329 330 kfree(amdgpu_connector->edid); 331 amdgpu_connector->edid = NULL; 332 } 333 334 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 335 { 336 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 337 int ret; 338 339 if (amdgpu_connector->edid) { 340 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 341 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 342 return ret; 343 } 344 drm_connector_update_edid_property(connector, NULL); 345 return 0; 346 } 347 348 static struct drm_encoder * 349 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 350 { 351 struct drm_encoder *encoder; 352 353 /* pick the first one */ 354 drm_connector_for_each_possible_encoder(connector, encoder) 355 return encoder; 356 357 return NULL; 358 } 359 360 static void amdgpu_get_native_mode(struct drm_connector *connector) 361 { 362 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 363 struct amdgpu_encoder *amdgpu_encoder; 364 365 if (encoder == NULL) 366 return; 367 368 amdgpu_encoder = to_amdgpu_encoder(encoder); 369 370 if (!list_empty(&connector->probed_modes)) { 371 struct drm_display_mode *preferred_mode = 372 list_first_entry(&connector->probed_modes, 373 struct drm_display_mode, head); 374 375 amdgpu_encoder->native_mode = *preferred_mode; 376 } else { 377 amdgpu_encoder->native_mode.clock = 0; 378 } 379 } 380 381 static struct drm_display_mode * 382 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 383 { 384 struct drm_device *dev = encoder->dev; 385 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 386 struct drm_display_mode *mode = NULL; 387 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 388 389 if (native_mode->hdisplay != 0 && 390 native_mode->vdisplay != 0 && 391 native_mode->clock != 0) { 392 mode = drm_mode_duplicate(dev, native_mode); 393 if (!mode) 394 return NULL; 395 396 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 397 drm_mode_set_name(mode); 398 399 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 400 } else if (native_mode->hdisplay != 0 && 401 native_mode->vdisplay != 0) { 402 /* mac laptops without an edid */ 403 /* Note that this is not necessarily the exact panel mode, 404 * but an approximation based on the cvt formula. For these 405 * systems we should ideally read the mode info out of the 406 * registers or add a mode table, but this works and is much 407 * simpler. 408 */ 409 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 410 if (!mode) 411 return NULL; 412 413 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 414 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 415 } 416 return mode; 417 } 418 419 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 420 struct drm_connector *connector) 421 { 422 struct drm_device *dev = encoder->dev; 423 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 424 struct drm_display_mode *mode = NULL; 425 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 426 int i; 427 static const struct mode_size { 428 int w; 429 int h; 430 } common_modes[17] = { 431 { 640, 480}, 432 { 720, 480}, 433 { 800, 600}, 434 { 848, 480}, 435 {1024, 768}, 436 {1152, 768}, 437 {1280, 720}, 438 {1280, 800}, 439 {1280, 854}, 440 {1280, 960}, 441 {1280, 1024}, 442 {1440, 900}, 443 {1400, 1050}, 444 {1680, 1050}, 445 {1600, 1200}, 446 {1920, 1080}, 447 {1920, 1200} 448 }; 449 450 for (i = 0; i < 17; i++) { 451 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 452 if (common_modes[i].w > 1024 || 453 common_modes[i].h > 768) 454 continue; 455 } 456 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 457 if (common_modes[i].w > native_mode->hdisplay || 458 common_modes[i].h > native_mode->vdisplay || 459 (common_modes[i].w == native_mode->hdisplay && 460 common_modes[i].h == native_mode->vdisplay)) 461 continue; 462 } 463 if (common_modes[i].w < 320 || common_modes[i].h < 200) 464 continue; 465 466 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 467 drm_mode_probed_add(connector, mode); 468 } 469 } 470 471 static int amdgpu_connector_set_property(struct drm_connector *connector, 472 struct drm_property *property, 473 uint64_t val) 474 { 475 struct drm_device *dev = connector->dev; 476 struct amdgpu_device *adev = drm_to_adev(dev); 477 struct drm_encoder *encoder; 478 struct amdgpu_encoder *amdgpu_encoder; 479 480 if (property == adev->mode_info.coherent_mode_property) { 481 struct amdgpu_encoder_atom_dig *dig; 482 bool new_coherent_mode; 483 484 /* need to find digital encoder on connector */ 485 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 486 if (!encoder) 487 return 0; 488 489 amdgpu_encoder = to_amdgpu_encoder(encoder); 490 491 if (!amdgpu_encoder->enc_priv) 492 return 0; 493 494 dig = amdgpu_encoder->enc_priv; 495 new_coherent_mode = val ? true : false; 496 if (dig->coherent_mode != new_coherent_mode) { 497 dig->coherent_mode = new_coherent_mode; 498 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 499 } 500 } 501 502 if (property == adev->mode_info.audio_property) { 503 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 504 /* need to find digital encoder on connector */ 505 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 506 if (!encoder) 507 return 0; 508 509 amdgpu_encoder = to_amdgpu_encoder(encoder); 510 511 if (amdgpu_connector->audio != val) { 512 amdgpu_connector->audio = val; 513 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 514 } 515 } 516 517 if (property == adev->mode_info.dither_property) { 518 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 519 /* need to find digital encoder on connector */ 520 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 521 if (!encoder) 522 return 0; 523 524 amdgpu_encoder = to_amdgpu_encoder(encoder); 525 526 if (amdgpu_connector->dither != val) { 527 amdgpu_connector->dither = val; 528 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 529 } 530 } 531 532 if (property == adev->mode_info.underscan_property) { 533 /* need to find digital encoder on connector */ 534 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 535 if (!encoder) 536 return 0; 537 538 amdgpu_encoder = to_amdgpu_encoder(encoder); 539 540 if (amdgpu_encoder->underscan_type != val) { 541 amdgpu_encoder->underscan_type = val; 542 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 543 } 544 } 545 546 if (property == adev->mode_info.underscan_hborder_property) { 547 /* need to find digital encoder on connector */ 548 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 549 if (!encoder) 550 return 0; 551 552 amdgpu_encoder = to_amdgpu_encoder(encoder); 553 554 if (amdgpu_encoder->underscan_hborder != val) { 555 amdgpu_encoder->underscan_hborder = val; 556 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 557 } 558 } 559 560 if (property == adev->mode_info.underscan_vborder_property) { 561 /* need to find digital encoder on connector */ 562 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 563 if (!encoder) 564 return 0; 565 566 amdgpu_encoder = to_amdgpu_encoder(encoder); 567 568 if (amdgpu_encoder->underscan_vborder != val) { 569 amdgpu_encoder->underscan_vborder = val; 570 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 571 } 572 } 573 574 if (property == adev->mode_info.load_detect_property) { 575 struct amdgpu_connector *amdgpu_connector = 576 to_amdgpu_connector(connector); 577 578 if (val == 0) 579 amdgpu_connector->dac_load_detect = false; 580 else 581 amdgpu_connector->dac_load_detect = true; 582 } 583 584 if (property == dev->mode_config.scaling_mode_property) { 585 enum amdgpu_rmx_type rmx_type; 586 587 if (connector->encoder) { 588 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 589 } else { 590 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 591 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 592 } 593 594 switch (val) { 595 default: 596 case DRM_MODE_SCALE_NONE: 597 rmx_type = RMX_OFF; 598 break; 599 case DRM_MODE_SCALE_CENTER: 600 rmx_type = RMX_CENTER; 601 break; 602 case DRM_MODE_SCALE_ASPECT: 603 rmx_type = RMX_ASPECT; 604 break; 605 case DRM_MODE_SCALE_FULLSCREEN: 606 rmx_type = RMX_FULL; 607 break; 608 } 609 610 if (amdgpu_encoder->rmx_type == rmx_type) 611 return 0; 612 613 if ((rmx_type != DRM_MODE_SCALE_NONE) && 614 (amdgpu_encoder->native_mode.clock == 0)) 615 return 0; 616 617 amdgpu_encoder->rmx_type = rmx_type; 618 619 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 620 } 621 622 return 0; 623 } 624 625 static void 626 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 627 struct drm_connector *connector) 628 { 629 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 630 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 631 struct drm_display_mode *t, *mode; 632 633 /* If the EDID preferred mode doesn't match the native mode, use it */ 634 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 635 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 636 if (mode->hdisplay != native_mode->hdisplay || 637 mode->vdisplay != native_mode->vdisplay) 638 drm_mode_copy(native_mode, mode); 639 } 640 } 641 642 /* Try to get native mode details from EDID if necessary */ 643 if (!native_mode->clock) { 644 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 645 if (mode->hdisplay == native_mode->hdisplay && 646 mode->vdisplay == native_mode->vdisplay) { 647 drm_mode_copy(native_mode, mode); 648 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 649 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 650 break; 651 } 652 } 653 } 654 655 if (!native_mode->clock) { 656 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 657 amdgpu_encoder->rmx_type = RMX_OFF; 658 } 659 } 660 661 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 662 { 663 struct drm_encoder *encoder; 664 int ret = 0; 665 struct drm_display_mode *mode; 666 667 amdgpu_connector_get_edid(connector); 668 ret = amdgpu_connector_ddc_get_modes(connector); 669 if (ret > 0) { 670 encoder = amdgpu_connector_best_single_encoder(connector); 671 if (encoder) { 672 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 673 /* add scaled modes */ 674 amdgpu_connector_add_common_modes(encoder, connector); 675 } 676 return ret; 677 } 678 679 encoder = amdgpu_connector_best_single_encoder(connector); 680 if (!encoder) 681 return 0; 682 683 /* we have no EDID modes */ 684 mode = amdgpu_connector_lcd_native_mode(encoder); 685 if (mode) { 686 ret = 1; 687 drm_mode_probed_add(connector, mode); 688 /* add the width/height from vbios tables if available */ 689 connector->display_info.width_mm = mode->width_mm; 690 connector->display_info.height_mm = mode->height_mm; 691 /* add scaled modes */ 692 amdgpu_connector_add_common_modes(encoder, connector); 693 } 694 695 return ret; 696 } 697 698 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 699 struct drm_display_mode *mode) 700 { 701 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 702 703 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 704 return MODE_PANEL; 705 706 if (encoder) { 707 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 708 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 709 710 /* AVIVO hardware supports downscaling modes larger than the panel 711 * to the panel size, but I'm not sure this is desirable. 712 */ 713 if ((mode->hdisplay > native_mode->hdisplay) || 714 (mode->vdisplay > native_mode->vdisplay)) 715 return MODE_PANEL; 716 717 /* if scaling is disabled, block non-native modes */ 718 if (amdgpu_encoder->rmx_type == RMX_OFF) { 719 if ((mode->hdisplay != native_mode->hdisplay) || 720 (mode->vdisplay != native_mode->vdisplay)) 721 return MODE_PANEL; 722 } 723 } 724 725 return MODE_OK; 726 } 727 728 static enum drm_connector_status 729 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 730 { 731 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 732 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 733 enum drm_connector_status ret = connector_status_disconnected; 734 int r; 735 736 if (!drm_kms_helper_is_poll_worker()) { 737 r = pm_runtime_get_sync(connector->dev->dev); 738 if (r < 0) { 739 pm_runtime_put_autosuspend(connector->dev->dev); 740 return connector_status_disconnected; 741 } 742 } 743 744 if (encoder) { 745 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 746 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 747 748 /* check if panel is valid */ 749 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 750 ret = connector_status_connected; 751 752 } 753 754 /* check for edid as well */ 755 amdgpu_connector_get_edid(connector); 756 if (amdgpu_connector->edid) 757 ret = connector_status_connected; 758 /* check acpi lid status ??? */ 759 760 amdgpu_connector_update_scratch_regs(connector, ret); 761 762 if (!drm_kms_helper_is_poll_worker()) { 763 pm_runtime_mark_last_busy(connector->dev->dev); 764 pm_runtime_put_autosuspend(connector->dev->dev); 765 } 766 767 return ret; 768 } 769 770 static void amdgpu_connector_unregister(struct drm_connector *connector) 771 { 772 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 773 774 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 775 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 776 amdgpu_connector->ddc_bus->has_aux = false; 777 } 778 } 779 780 static void amdgpu_connector_destroy(struct drm_connector *connector) 781 { 782 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 783 784 amdgpu_connector_free_edid(connector); 785 kfree(amdgpu_connector->con_priv); 786 drm_connector_unregister(connector); 787 drm_connector_cleanup(connector); 788 kfree(connector); 789 } 790 791 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 792 struct drm_property *property, 793 uint64_t value) 794 { 795 struct drm_device *dev = connector->dev; 796 struct amdgpu_encoder *amdgpu_encoder; 797 enum amdgpu_rmx_type rmx_type; 798 799 DRM_DEBUG_KMS("\n"); 800 if (property != dev->mode_config.scaling_mode_property) 801 return 0; 802 803 if (connector->encoder) 804 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 805 else { 806 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 807 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 808 } 809 810 switch (value) { 811 case DRM_MODE_SCALE_NONE: 812 rmx_type = RMX_OFF; 813 break; 814 case DRM_MODE_SCALE_CENTER: 815 rmx_type = RMX_CENTER; 816 break; 817 case DRM_MODE_SCALE_ASPECT: 818 rmx_type = RMX_ASPECT; 819 break; 820 default: 821 case DRM_MODE_SCALE_FULLSCREEN: 822 rmx_type = RMX_FULL; 823 break; 824 } 825 826 if (amdgpu_encoder->rmx_type == rmx_type) 827 return 0; 828 829 amdgpu_encoder->rmx_type = rmx_type; 830 831 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 832 return 0; 833 } 834 835 836 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 837 .get_modes = amdgpu_connector_lvds_get_modes, 838 .mode_valid = amdgpu_connector_lvds_mode_valid, 839 .best_encoder = amdgpu_connector_best_single_encoder, 840 }; 841 842 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 843 .dpms = drm_helper_connector_dpms, 844 .detect = amdgpu_connector_lvds_detect, 845 .fill_modes = drm_helper_probe_single_connector_modes, 846 .early_unregister = amdgpu_connector_unregister, 847 .destroy = amdgpu_connector_destroy, 848 .set_property = amdgpu_connector_set_lcd_property, 849 }; 850 851 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 852 { 853 int ret; 854 855 amdgpu_connector_get_edid(connector); 856 ret = amdgpu_connector_ddc_get_modes(connector); 857 amdgpu_get_native_mode(connector); 858 859 return ret; 860 } 861 862 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 863 struct drm_display_mode *mode) 864 { 865 struct drm_device *dev = connector->dev; 866 struct amdgpu_device *adev = drm_to_adev(dev); 867 868 /* XXX check mode bandwidth */ 869 870 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 871 return MODE_CLOCK_HIGH; 872 873 return MODE_OK; 874 } 875 876 static enum drm_connector_status 877 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 878 { 879 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 880 struct drm_encoder *encoder; 881 const struct drm_encoder_helper_funcs *encoder_funcs; 882 bool dret = false; 883 enum drm_connector_status ret = connector_status_disconnected; 884 int r; 885 886 if (!drm_kms_helper_is_poll_worker()) { 887 r = pm_runtime_get_sync(connector->dev->dev); 888 if (r < 0) { 889 pm_runtime_put_autosuspend(connector->dev->dev); 890 return connector_status_disconnected; 891 } 892 } 893 894 encoder = amdgpu_connector_best_single_encoder(connector); 895 if (!encoder) 896 ret = connector_status_disconnected; 897 898 if (amdgpu_connector->ddc_bus) 899 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 900 if (dret) { 901 amdgpu_connector->detected_by_load = false; 902 amdgpu_connector_free_edid(connector); 903 amdgpu_connector_get_edid(connector); 904 905 if (!amdgpu_connector->edid) { 906 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 907 connector->name); 908 ret = connector_status_connected; 909 } else { 910 amdgpu_connector->use_digital = 911 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 912 913 /* some oems have boards with separate digital and analog connectors 914 * with a shared ddc line (often vga + hdmi) 915 */ 916 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 917 amdgpu_connector_free_edid(connector); 918 ret = connector_status_disconnected; 919 } else { 920 ret = connector_status_connected; 921 } 922 } 923 } else { 924 925 /* if we aren't forcing don't do destructive polling */ 926 if (!force) { 927 /* only return the previous status if we last 928 * detected a monitor via load. 929 */ 930 if (amdgpu_connector->detected_by_load) 931 ret = connector->status; 932 goto out; 933 } 934 935 if (amdgpu_connector->dac_load_detect && encoder) { 936 encoder_funcs = encoder->helper_private; 937 ret = encoder_funcs->detect(encoder, connector); 938 if (ret != connector_status_disconnected) 939 amdgpu_connector->detected_by_load = true; 940 } 941 } 942 943 amdgpu_connector_update_scratch_regs(connector, ret); 944 945 out: 946 if (!drm_kms_helper_is_poll_worker()) { 947 pm_runtime_mark_last_busy(connector->dev->dev); 948 pm_runtime_put_autosuspend(connector->dev->dev); 949 } 950 951 return ret; 952 } 953 954 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 955 .get_modes = amdgpu_connector_vga_get_modes, 956 .mode_valid = amdgpu_connector_vga_mode_valid, 957 .best_encoder = amdgpu_connector_best_single_encoder, 958 }; 959 960 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 961 .dpms = drm_helper_connector_dpms, 962 .detect = amdgpu_connector_vga_detect, 963 .fill_modes = drm_helper_probe_single_connector_modes, 964 .early_unregister = amdgpu_connector_unregister, 965 .destroy = amdgpu_connector_destroy, 966 .set_property = amdgpu_connector_set_property, 967 }; 968 969 static bool 970 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 971 { 972 struct drm_device *dev = connector->dev; 973 struct amdgpu_device *adev = drm_to_adev(dev); 974 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 975 enum drm_connector_status status; 976 977 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 978 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 979 status = connector_status_connected; 980 else 981 status = connector_status_disconnected; 982 if (connector->status == status) 983 return true; 984 } 985 986 return false; 987 } 988 989 /* 990 * DVI is complicated 991 * Do a DDC probe, if DDC probe passes, get the full EDID so 992 * we can do analog/digital monitor detection at this point. 993 * If the monitor is an analog monitor or we got no DDC, 994 * we need to find the DAC encoder object for this connector. 995 * If we got no DDC, we do load detection on the DAC encoder object. 996 * If we got analog DDC or load detection passes on the DAC encoder 997 * we have to check if this analog encoder is shared with anyone else (TV) 998 * if its shared we have to set the other connector to disconnected. 999 */ 1000 static enum drm_connector_status 1001 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1002 { 1003 struct drm_device *dev = connector->dev; 1004 struct amdgpu_device *adev = drm_to_adev(dev); 1005 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1006 const struct drm_encoder_helper_funcs *encoder_funcs; 1007 int r; 1008 enum drm_connector_status ret = connector_status_disconnected; 1009 bool dret = false, broken_edid = false; 1010 1011 if (!drm_kms_helper_is_poll_worker()) { 1012 r = pm_runtime_get_sync(connector->dev->dev); 1013 if (r < 0) { 1014 pm_runtime_put_autosuspend(connector->dev->dev); 1015 return connector_status_disconnected; 1016 } 1017 } 1018 1019 if (amdgpu_connector->detected_hpd_without_ddc) { 1020 force = true; 1021 amdgpu_connector->detected_hpd_without_ddc = false; 1022 } 1023 1024 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1025 ret = connector->status; 1026 goto exit; 1027 } 1028 1029 if (amdgpu_connector->ddc_bus) { 1030 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1031 1032 /* Sometimes the pins required for the DDC probe on DVI 1033 * connectors don't make contact at the same time that the ones 1034 * for HPD do. If the DDC probe fails even though we had an HPD 1035 * signal, try again later 1036 */ 1037 if (!dret && !force && 1038 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1039 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1040 amdgpu_connector->detected_hpd_without_ddc = true; 1041 schedule_delayed_work(&adev->hotplug_work, 1042 msecs_to_jiffies(1000)); 1043 goto exit; 1044 } 1045 } 1046 if (dret) { 1047 amdgpu_connector->detected_by_load = false; 1048 amdgpu_connector_free_edid(connector); 1049 amdgpu_connector_get_edid(connector); 1050 1051 if (!amdgpu_connector->edid) { 1052 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1053 connector->name); 1054 ret = connector_status_connected; 1055 broken_edid = true; /* defer use_digital to later */ 1056 } else { 1057 amdgpu_connector->use_digital = 1058 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1059 1060 /* some oems have boards with separate digital and analog connectors 1061 * with a shared ddc line (often vga + hdmi) 1062 */ 1063 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1064 amdgpu_connector_free_edid(connector); 1065 ret = connector_status_disconnected; 1066 } else { 1067 ret = connector_status_connected; 1068 } 1069 1070 /* This gets complicated. We have boards with VGA + HDMI with a 1071 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1072 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1073 * you don't really know what's connected to which port as both are digital. 1074 */ 1075 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1076 struct drm_connector *list_connector; 1077 struct drm_connector_list_iter iter; 1078 struct amdgpu_connector *list_amdgpu_connector; 1079 1080 drm_connector_list_iter_begin(dev, &iter); 1081 drm_for_each_connector_iter(list_connector, 1082 &iter) { 1083 if (connector == list_connector) 1084 continue; 1085 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1086 if (list_amdgpu_connector->shared_ddc && 1087 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1088 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1089 /* cases where both connectors are digital */ 1090 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1091 /* hpd is our only option in this case */ 1092 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1093 amdgpu_connector_free_edid(connector); 1094 ret = connector_status_disconnected; 1095 } 1096 } 1097 } 1098 } 1099 drm_connector_list_iter_end(&iter); 1100 } 1101 } 1102 } 1103 1104 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1105 goto out; 1106 1107 /* DVI-D and HDMI-A are digital only */ 1108 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1109 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1110 goto out; 1111 1112 /* if we aren't forcing don't do destructive polling */ 1113 if (!force) { 1114 /* only return the previous status if we last 1115 * detected a monitor via load. 1116 */ 1117 if (amdgpu_connector->detected_by_load) 1118 ret = connector->status; 1119 goto out; 1120 } 1121 1122 /* find analog encoder */ 1123 if (amdgpu_connector->dac_load_detect) { 1124 struct drm_encoder *encoder; 1125 1126 drm_connector_for_each_possible_encoder(connector, encoder) { 1127 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1128 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1129 continue; 1130 1131 encoder_funcs = encoder->helper_private; 1132 if (encoder_funcs->detect) { 1133 if (!broken_edid) { 1134 if (ret != connector_status_connected) { 1135 /* deal with analog monitors without DDC */ 1136 ret = encoder_funcs->detect(encoder, connector); 1137 if (ret == connector_status_connected) { 1138 amdgpu_connector->use_digital = false; 1139 } 1140 if (ret != connector_status_disconnected) 1141 amdgpu_connector->detected_by_load = true; 1142 } 1143 } else { 1144 enum drm_connector_status lret; 1145 /* assume digital unless load detected otherwise */ 1146 amdgpu_connector->use_digital = true; 1147 lret = encoder_funcs->detect(encoder, connector); 1148 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1149 encoder->encoder_type, lret); 1150 if (lret == connector_status_connected) 1151 amdgpu_connector->use_digital = false; 1152 } 1153 break; 1154 } 1155 } 1156 } 1157 1158 out: 1159 /* updated in get modes as well since we need to know if it's analog or digital */ 1160 amdgpu_connector_update_scratch_regs(connector, ret); 1161 1162 exit: 1163 if (!drm_kms_helper_is_poll_worker()) { 1164 pm_runtime_mark_last_busy(connector->dev->dev); 1165 pm_runtime_put_autosuspend(connector->dev->dev); 1166 } 1167 1168 return ret; 1169 } 1170 1171 /* okay need to be smart in here about which encoder to pick */ 1172 static struct drm_encoder * 1173 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1174 { 1175 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1176 struct drm_encoder *encoder; 1177 1178 drm_connector_for_each_possible_encoder(connector, encoder) { 1179 if (amdgpu_connector->use_digital == true) { 1180 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1181 return encoder; 1182 } else { 1183 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1184 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1185 return encoder; 1186 } 1187 } 1188 1189 /* see if we have a default encoder TODO */ 1190 1191 /* then check use digitial */ 1192 /* pick the first one */ 1193 drm_connector_for_each_possible_encoder(connector, encoder) 1194 return encoder; 1195 1196 return NULL; 1197 } 1198 1199 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1200 { 1201 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1202 if (connector->force == DRM_FORCE_ON) 1203 amdgpu_connector->use_digital = false; 1204 if (connector->force == DRM_FORCE_ON_DIGITAL) 1205 amdgpu_connector->use_digital = true; 1206 } 1207 1208 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1209 struct drm_display_mode *mode) 1210 { 1211 struct drm_device *dev = connector->dev; 1212 struct amdgpu_device *adev = drm_to_adev(dev); 1213 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1214 1215 /* XXX check mode bandwidth */ 1216 1217 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1218 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1219 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1220 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1221 return MODE_OK; 1222 } else if (connector->display_info.is_hdmi) { 1223 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1224 if (mode->clock > 340000) 1225 return MODE_CLOCK_HIGH; 1226 else 1227 return MODE_OK; 1228 } else { 1229 return MODE_CLOCK_HIGH; 1230 } 1231 } 1232 1233 /* check against the max pixel clock */ 1234 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1235 return MODE_CLOCK_HIGH; 1236 1237 return MODE_OK; 1238 } 1239 1240 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1241 .get_modes = amdgpu_connector_vga_get_modes, 1242 .mode_valid = amdgpu_connector_dvi_mode_valid, 1243 .best_encoder = amdgpu_connector_dvi_encoder, 1244 }; 1245 1246 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1247 .dpms = drm_helper_connector_dpms, 1248 .detect = amdgpu_connector_dvi_detect, 1249 .fill_modes = drm_helper_probe_single_connector_modes, 1250 .set_property = amdgpu_connector_set_property, 1251 .early_unregister = amdgpu_connector_unregister, 1252 .destroy = amdgpu_connector_destroy, 1253 .force = amdgpu_connector_dvi_force, 1254 }; 1255 1256 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1257 { 1258 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1259 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1260 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1261 int ret; 1262 1263 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1264 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1265 struct drm_display_mode *mode; 1266 1267 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1268 if (!amdgpu_dig_connector->edp_on) 1269 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1270 ATOM_TRANSMITTER_ACTION_POWER_ON); 1271 amdgpu_connector_get_edid(connector); 1272 ret = amdgpu_connector_ddc_get_modes(connector); 1273 if (!amdgpu_dig_connector->edp_on) 1274 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1275 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1276 } else { 1277 /* need to setup ddc on the bridge */ 1278 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1279 ENCODER_OBJECT_ID_NONE) { 1280 if (encoder) 1281 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1282 } 1283 amdgpu_connector_get_edid(connector); 1284 ret = amdgpu_connector_ddc_get_modes(connector); 1285 } 1286 1287 if (ret > 0) { 1288 if (encoder) { 1289 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1290 /* add scaled modes */ 1291 amdgpu_connector_add_common_modes(encoder, connector); 1292 } 1293 return ret; 1294 } 1295 1296 if (!encoder) 1297 return 0; 1298 1299 /* we have no EDID modes */ 1300 mode = amdgpu_connector_lcd_native_mode(encoder); 1301 if (mode) { 1302 ret = 1; 1303 drm_mode_probed_add(connector, mode); 1304 /* add the width/height from vbios tables if available */ 1305 connector->display_info.width_mm = mode->width_mm; 1306 connector->display_info.height_mm = mode->height_mm; 1307 /* add scaled modes */ 1308 amdgpu_connector_add_common_modes(encoder, connector); 1309 } 1310 } else { 1311 /* need to setup ddc on the bridge */ 1312 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1313 ENCODER_OBJECT_ID_NONE) { 1314 if (encoder) 1315 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1316 } 1317 amdgpu_connector_get_edid(connector); 1318 ret = amdgpu_connector_ddc_get_modes(connector); 1319 1320 amdgpu_get_native_mode(connector); 1321 } 1322 1323 return ret; 1324 } 1325 1326 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1327 { 1328 struct drm_encoder *encoder; 1329 struct amdgpu_encoder *amdgpu_encoder; 1330 1331 drm_connector_for_each_possible_encoder(connector, encoder) { 1332 amdgpu_encoder = to_amdgpu_encoder(encoder); 1333 1334 switch (amdgpu_encoder->encoder_id) { 1335 case ENCODER_OBJECT_ID_TRAVIS: 1336 case ENCODER_OBJECT_ID_NUTMEG: 1337 return amdgpu_encoder->encoder_id; 1338 default: 1339 break; 1340 } 1341 } 1342 1343 return ENCODER_OBJECT_ID_NONE; 1344 } 1345 1346 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1347 { 1348 struct drm_encoder *encoder; 1349 struct amdgpu_encoder *amdgpu_encoder; 1350 bool found = false; 1351 1352 drm_connector_for_each_possible_encoder(connector, encoder) { 1353 amdgpu_encoder = to_amdgpu_encoder(encoder); 1354 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1355 found = true; 1356 } 1357 1358 return found; 1359 } 1360 1361 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1362 { 1363 struct drm_device *dev = connector->dev; 1364 struct amdgpu_device *adev = drm_to_adev(dev); 1365 1366 if ((adev->clock.default_dispclk >= 53900) && 1367 amdgpu_connector_encoder_is_hbr2(connector)) { 1368 return true; 1369 } 1370 1371 return false; 1372 } 1373 1374 static enum drm_connector_status 1375 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1376 { 1377 struct drm_device *dev = connector->dev; 1378 struct amdgpu_device *adev = drm_to_adev(dev); 1379 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1380 enum drm_connector_status ret = connector_status_disconnected; 1381 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1382 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1383 int r; 1384 1385 if (!drm_kms_helper_is_poll_worker()) { 1386 r = pm_runtime_get_sync(connector->dev->dev); 1387 if (r < 0) { 1388 pm_runtime_put_autosuspend(connector->dev->dev); 1389 return connector_status_disconnected; 1390 } 1391 } 1392 1393 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1394 ret = connector->status; 1395 goto out; 1396 } 1397 1398 amdgpu_connector_free_edid(connector); 1399 1400 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1401 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1402 if (encoder) { 1403 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1404 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1405 1406 /* check if panel is valid */ 1407 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1408 ret = connector_status_connected; 1409 } 1410 /* eDP is always DP */ 1411 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1412 if (!amdgpu_dig_connector->edp_on) 1413 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1414 ATOM_TRANSMITTER_ACTION_POWER_ON); 1415 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1416 ret = connector_status_connected; 1417 if (!amdgpu_dig_connector->edp_on) 1418 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1419 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1420 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1421 ENCODER_OBJECT_ID_NONE) { 1422 /* DP bridges are always DP */ 1423 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1424 /* get the DPCD from the bridge */ 1425 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1426 1427 if (encoder) { 1428 /* setup ddc on the bridge */ 1429 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1430 /* bridge chips are always aux */ 1431 /* try DDC */ 1432 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1433 ret = connector_status_connected; 1434 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1435 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1436 ret = encoder_funcs->detect(encoder, connector); 1437 } 1438 } 1439 } else { 1440 amdgpu_dig_connector->dp_sink_type = 1441 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1442 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1443 ret = connector_status_connected; 1444 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1445 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1446 } else { 1447 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1448 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1449 ret = connector_status_connected; 1450 } else { 1451 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1452 if (amdgpu_display_ddc_probe(amdgpu_connector, 1453 false)) 1454 ret = connector_status_connected; 1455 } 1456 } 1457 } 1458 1459 amdgpu_connector_update_scratch_regs(connector, ret); 1460 out: 1461 if (!drm_kms_helper_is_poll_worker()) { 1462 pm_runtime_mark_last_busy(connector->dev->dev); 1463 pm_runtime_put_autosuspend(connector->dev->dev); 1464 } 1465 1466 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1467 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1468 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1469 ret, 1470 amdgpu_dig_connector->dpcd, 1471 amdgpu_dig_connector->downstream_ports); 1472 return ret; 1473 } 1474 1475 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1476 struct drm_display_mode *mode) 1477 { 1478 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1479 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1480 1481 /* XXX check mode bandwidth */ 1482 1483 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1484 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1485 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1486 1487 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1488 return MODE_PANEL; 1489 1490 if (encoder) { 1491 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1492 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1493 1494 /* AVIVO hardware supports downscaling modes larger than the panel 1495 * to the panel size, but I'm not sure this is desirable. 1496 */ 1497 if ((mode->hdisplay > native_mode->hdisplay) || 1498 (mode->vdisplay > native_mode->vdisplay)) 1499 return MODE_PANEL; 1500 1501 /* if scaling is disabled, block non-native modes */ 1502 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1503 if ((mode->hdisplay != native_mode->hdisplay) || 1504 (mode->vdisplay != native_mode->vdisplay)) 1505 return MODE_PANEL; 1506 } 1507 } 1508 return MODE_OK; 1509 } else { 1510 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1511 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1512 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1513 } else { 1514 if (connector->display_info.is_hdmi) { 1515 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1516 if (mode->clock > 340000) 1517 return MODE_CLOCK_HIGH; 1518 } else { 1519 if (mode->clock > 165000) 1520 return MODE_CLOCK_HIGH; 1521 } 1522 } 1523 } 1524 1525 return MODE_OK; 1526 } 1527 1528 static int 1529 amdgpu_connector_late_register(struct drm_connector *connector) 1530 { 1531 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1532 int r = 0; 1533 1534 if (amdgpu_connector->ddc_bus->has_aux) { 1535 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1536 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1537 } 1538 1539 return r; 1540 } 1541 1542 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1543 .get_modes = amdgpu_connector_dp_get_modes, 1544 .mode_valid = amdgpu_connector_dp_mode_valid, 1545 .best_encoder = amdgpu_connector_dvi_encoder, 1546 }; 1547 1548 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1549 .dpms = drm_helper_connector_dpms, 1550 .detect = amdgpu_connector_dp_detect, 1551 .fill_modes = drm_helper_probe_single_connector_modes, 1552 .set_property = amdgpu_connector_set_property, 1553 .early_unregister = amdgpu_connector_unregister, 1554 .destroy = amdgpu_connector_destroy, 1555 .force = amdgpu_connector_dvi_force, 1556 .late_register = amdgpu_connector_late_register, 1557 }; 1558 1559 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1560 .dpms = drm_helper_connector_dpms, 1561 .detect = amdgpu_connector_dp_detect, 1562 .fill_modes = drm_helper_probe_single_connector_modes, 1563 .set_property = amdgpu_connector_set_lcd_property, 1564 .early_unregister = amdgpu_connector_unregister, 1565 .destroy = amdgpu_connector_destroy, 1566 .force = amdgpu_connector_dvi_force, 1567 .late_register = amdgpu_connector_late_register, 1568 }; 1569 1570 void 1571 amdgpu_connector_add(struct amdgpu_device *adev, 1572 uint32_t connector_id, 1573 uint32_t supported_device, 1574 int connector_type, 1575 struct amdgpu_i2c_bus_rec *i2c_bus, 1576 uint16_t connector_object_id, 1577 struct amdgpu_hpd *hpd, 1578 struct amdgpu_router *router) 1579 { 1580 struct drm_device *dev = adev_to_drm(adev); 1581 struct drm_connector *connector; 1582 struct drm_connector_list_iter iter; 1583 struct amdgpu_connector *amdgpu_connector; 1584 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1585 struct drm_encoder *encoder; 1586 struct amdgpu_encoder *amdgpu_encoder; 1587 struct i2c_adapter *ddc = NULL; 1588 uint32_t subpixel_order = SubPixelNone; 1589 bool shared_ddc = false; 1590 bool is_dp_bridge = false; 1591 bool has_aux = false; 1592 1593 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1594 return; 1595 1596 /* see if we already added it */ 1597 drm_connector_list_iter_begin(dev, &iter); 1598 drm_for_each_connector_iter(connector, &iter) { 1599 amdgpu_connector = to_amdgpu_connector(connector); 1600 if (amdgpu_connector->connector_id == connector_id) { 1601 amdgpu_connector->devices |= supported_device; 1602 drm_connector_list_iter_end(&iter); 1603 return; 1604 } 1605 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1606 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1607 amdgpu_connector->shared_ddc = true; 1608 shared_ddc = true; 1609 } 1610 if (amdgpu_connector->router_bus && router->ddc_valid && 1611 (amdgpu_connector->router.router_id == router->router_id)) { 1612 amdgpu_connector->shared_ddc = false; 1613 shared_ddc = false; 1614 } 1615 } 1616 } 1617 drm_connector_list_iter_end(&iter); 1618 1619 /* check if it's a dp bridge */ 1620 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1621 amdgpu_encoder = to_amdgpu_encoder(encoder); 1622 if (amdgpu_encoder->devices & supported_device) { 1623 switch (amdgpu_encoder->encoder_id) { 1624 case ENCODER_OBJECT_ID_TRAVIS: 1625 case ENCODER_OBJECT_ID_NUTMEG: 1626 is_dp_bridge = true; 1627 break; 1628 default: 1629 break; 1630 } 1631 } 1632 } 1633 1634 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1635 if (!amdgpu_connector) 1636 return; 1637 1638 connector = &amdgpu_connector->base; 1639 1640 amdgpu_connector->connector_id = connector_id; 1641 amdgpu_connector->devices = supported_device; 1642 amdgpu_connector->shared_ddc = shared_ddc; 1643 amdgpu_connector->connector_object_id = connector_object_id; 1644 amdgpu_connector->hpd = *hpd; 1645 1646 amdgpu_connector->router = *router; 1647 if (router->ddc_valid || router->cd_valid) { 1648 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1649 if (!amdgpu_connector->router_bus) 1650 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1651 } 1652 1653 if (is_dp_bridge) { 1654 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1655 if (!amdgpu_dig_connector) 1656 goto failed; 1657 amdgpu_connector->con_priv = amdgpu_dig_connector; 1658 if (i2c_bus->valid) { 1659 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1660 if (amdgpu_connector->ddc_bus) { 1661 has_aux = true; 1662 ddc = &amdgpu_connector->ddc_bus->adapter; 1663 } else { 1664 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1665 } 1666 } 1667 switch (connector_type) { 1668 case DRM_MODE_CONNECTOR_VGA: 1669 case DRM_MODE_CONNECTOR_DVIA: 1670 default: 1671 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1672 &amdgpu_connector_dp_funcs, 1673 connector_type, 1674 ddc); 1675 drm_connector_helper_add(&amdgpu_connector->base, 1676 &amdgpu_connector_dp_helper_funcs); 1677 connector->interlace_allowed = true; 1678 connector->doublescan_allowed = true; 1679 amdgpu_connector->dac_load_detect = true; 1680 drm_object_attach_property(&amdgpu_connector->base.base, 1681 adev->mode_info.load_detect_property, 1682 1); 1683 drm_object_attach_property(&amdgpu_connector->base.base, 1684 dev->mode_config.scaling_mode_property, 1685 DRM_MODE_SCALE_NONE); 1686 break; 1687 case DRM_MODE_CONNECTOR_DVII: 1688 case DRM_MODE_CONNECTOR_DVID: 1689 case DRM_MODE_CONNECTOR_HDMIA: 1690 case DRM_MODE_CONNECTOR_HDMIB: 1691 case DRM_MODE_CONNECTOR_DisplayPort: 1692 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1693 &amdgpu_connector_dp_funcs, 1694 connector_type, 1695 ddc); 1696 drm_connector_helper_add(&amdgpu_connector->base, 1697 &amdgpu_connector_dp_helper_funcs); 1698 drm_object_attach_property(&amdgpu_connector->base.base, 1699 adev->mode_info.underscan_property, 1700 UNDERSCAN_OFF); 1701 drm_object_attach_property(&amdgpu_connector->base.base, 1702 adev->mode_info.underscan_hborder_property, 1703 0); 1704 drm_object_attach_property(&amdgpu_connector->base.base, 1705 adev->mode_info.underscan_vborder_property, 1706 0); 1707 1708 drm_object_attach_property(&amdgpu_connector->base.base, 1709 dev->mode_config.scaling_mode_property, 1710 DRM_MODE_SCALE_NONE); 1711 1712 drm_object_attach_property(&amdgpu_connector->base.base, 1713 adev->mode_info.dither_property, 1714 AMDGPU_FMT_DITHER_DISABLE); 1715 1716 if (amdgpu_audio != 0) { 1717 drm_object_attach_property(&amdgpu_connector->base.base, 1718 adev->mode_info.audio_property, 1719 AMDGPU_AUDIO_AUTO); 1720 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1721 } 1722 1723 subpixel_order = SubPixelHorizontalRGB; 1724 connector->interlace_allowed = true; 1725 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1726 connector->doublescan_allowed = true; 1727 else 1728 connector->doublescan_allowed = false; 1729 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1730 amdgpu_connector->dac_load_detect = true; 1731 drm_object_attach_property(&amdgpu_connector->base.base, 1732 adev->mode_info.load_detect_property, 1733 1); 1734 } 1735 break; 1736 case DRM_MODE_CONNECTOR_LVDS: 1737 case DRM_MODE_CONNECTOR_eDP: 1738 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1739 &amdgpu_connector_edp_funcs, 1740 connector_type, 1741 ddc); 1742 drm_connector_helper_add(&amdgpu_connector->base, 1743 &amdgpu_connector_dp_helper_funcs); 1744 drm_object_attach_property(&amdgpu_connector->base.base, 1745 dev->mode_config.scaling_mode_property, 1746 DRM_MODE_SCALE_FULLSCREEN); 1747 subpixel_order = SubPixelHorizontalRGB; 1748 connector->interlace_allowed = false; 1749 connector->doublescan_allowed = false; 1750 break; 1751 } 1752 } else { 1753 switch (connector_type) { 1754 case DRM_MODE_CONNECTOR_VGA: 1755 if (i2c_bus->valid) { 1756 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1757 if (!amdgpu_connector->ddc_bus) 1758 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1759 else 1760 ddc = &amdgpu_connector->ddc_bus->adapter; 1761 } 1762 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1763 &amdgpu_connector_vga_funcs, 1764 connector_type, 1765 ddc); 1766 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1767 amdgpu_connector->dac_load_detect = true; 1768 drm_object_attach_property(&amdgpu_connector->base.base, 1769 adev->mode_info.load_detect_property, 1770 1); 1771 drm_object_attach_property(&amdgpu_connector->base.base, 1772 dev->mode_config.scaling_mode_property, 1773 DRM_MODE_SCALE_NONE); 1774 /* no HPD on analog connectors */ 1775 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1776 connector->interlace_allowed = true; 1777 connector->doublescan_allowed = true; 1778 break; 1779 case DRM_MODE_CONNECTOR_DVIA: 1780 if (i2c_bus->valid) { 1781 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1782 if (!amdgpu_connector->ddc_bus) 1783 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1784 else 1785 ddc = &amdgpu_connector->ddc_bus->adapter; 1786 } 1787 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1788 &amdgpu_connector_vga_funcs, 1789 connector_type, 1790 ddc); 1791 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1792 amdgpu_connector->dac_load_detect = true; 1793 drm_object_attach_property(&amdgpu_connector->base.base, 1794 adev->mode_info.load_detect_property, 1795 1); 1796 drm_object_attach_property(&amdgpu_connector->base.base, 1797 dev->mode_config.scaling_mode_property, 1798 DRM_MODE_SCALE_NONE); 1799 /* no HPD on analog connectors */ 1800 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1801 connector->interlace_allowed = true; 1802 connector->doublescan_allowed = true; 1803 break; 1804 case DRM_MODE_CONNECTOR_DVII: 1805 case DRM_MODE_CONNECTOR_DVID: 1806 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1807 if (!amdgpu_dig_connector) 1808 goto failed; 1809 amdgpu_connector->con_priv = amdgpu_dig_connector; 1810 if (i2c_bus->valid) { 1811 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1812 if (!amdgpu_connector->ddc_bus) 1813 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1814 else 1815 ddc = &amdgpu_connector->ddc_bus->adapter; 1816 } 1817 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1818 &amdgpu_connector_dvi_funcs, 1819 connector_type, 1820 ddc); 1821 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1822 subpixel_order = SubPixelHorizontalRGB; 1823 drm_object_attach_property(&amdgpu_connector->base.base, 1824 adev->mode_info.coherent_mode_property, 1825 1); 1826 drm_object_attach_property(&amdgpu_connector->base.base, 1827 adev->mode_info.underscan_property, 1828 UNDERSCAN_OFF); 1829 drm_object_attach_property(&amdgpu_connector->base.base, 1830 adev->mode_info.underscan_hborder_property, 1831 0); 1832 drm_object_attach_property(&amdgpu_connector->base.base, 1833 adev->mode_info.underscan_vborder_property, 1834 0); 1835 drm_object_attach_property(&amdgpu_connector->base.base, 1836 dev->mode_config.scaling_mode_property, 1837 DRM_MODE_SCALE_NONE); 1838 1839 if (amdgpu_audio != 0) { 1840 drm_object_attach_property(&amdgpu_connector->base.base, 1841 adev->mode_info.audio_property, 1842 AMDGPU_AUDIO_AUTO); 1843 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1844 } 1845 drm_object_attach_property(&amdgpu_connector->base.base, 1846 adev->mode_info.dither_property, 1847 AMDGPU_FMT_DITHER_DISABLE); 1848 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1849 amdgpu_connector->dac_load_detect = true; 1850 drm_object_attach_property(&amdgpu_connector->base.base, 1851 adev->mode_info.load_detect_property, 1852 1); 1853 } 1854 connector->interlace_allowed = true; 1855 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1856 connector->doublescan_allowed = true; 1857 else 1858 connector->doublescan_allowed = false; 1859 break; 1860 case DRM_MODE_CONNECTOR_HDMIA: 1861 case DRM_MODE_CONNECTOR_HDMIB: 1862 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1863 if (!amdgpu_dig_connector) 1864 goto failed; 1865 amdgpu_connector->con_priv = amdgpu_dig_connector; 1866 if (i2c_bus->valid) { 1867 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1868 if (!amdgpu_connector->ddc_bus) 1869 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1870 else 1871 ddc = &amdgpu_connector->ddc_bus->adapter; 1872 } 1873 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1874 &amdgpu_connector_dvi_funcs, 1875 connector_type, 1876 ddc); 1877 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1878 drm_object_attach_property(&amdgpu_connector->base.base, 1879 adev->mode_info.coherent_mode_property, 1880 1); 1881 drm_object_attach_property(&amdgpu_connector->base.base, 1882 adev->mode_info.underscan_property, 1883 UNDERSCAN_OFF); 1884 drm_object_attach_property(&amdgpu_connector->base.base, 1885 adev->mode_info.underscan_hborder_property, 1886 0); 1887 drm_object_attach_property(&amdgpu_connector->base.base, 1888 adev->mode_info.underscan_vborder_property, 1889 0); 1890 drm_object_attach_property(&amdgpu_connector->base.base, 1891 dev->mode_config.scaling_mode_property, 1892 DRM_MODE_SCALE_NONE); 1893 if (amdgpu_audio != 0) { 1894 drm_object_attach_property(&amdgpu_connector->base.base, 1895 adev->mode_info.audio_property, 1896 AMDGPU_AUDIO_AUTO); 1897 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1898 } 1899 drm_object_attach_property(&amdgpu_connector->base.base, 1900 adev->mode_info.dither_property, 1901 AMDGPU_FMT_DITHER_DISABLE); 1902 subpixel_order = SubPixelHorizontalRGB; 1903 connector->interlace_allowed = true; 1904 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1905 connector->doublescan_allowed = true; 1906 else 1907 connector->doublescan_allowed = false; 1908 break; 1909 case DRM_MODE_CONNECTOR_DisplayPort: 1910 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1911 if (!amdgpu_dig_connector) 1912 goto failed; 1913 amdgpu_connector->con_priv = amdgpu_dig_connector; 1914 if (i2c_bus->valid) { 1915 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1916 if (amdgpu_connector->ddc_bus) { 1917 has_aux = true; 1918 ddc = &amdgpu_connector->ddc_bus->adapter; 1919 } else { 1920 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1921 } 1922 } 1923 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1924 &amdgpu_connector_dp_funcs, 1925 connector_type, 1926 ddc); 1927 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1928 subpixel_order = SubPixelHorizontalRGB; 1929 drm_object_attach_property(&amdgpu_connector->base.base, 1930 adev->mode_info.coherent_mode_property, 1931 1); 1932 drm_object_attach_property(&amdgpu_connector->base.base, 1933 adev->mode_info.underscan_property, 1934 UNDERSCAN_OFF); 1935 drm_object_attach_property(&amdgpu_connector->base.base, 1936 adev->mode_info.underscan_hborder_property, 1937 0); 1938 drm_object_attach_property(&amdgpu_connector->base.base, 1939 adev->mode_info.underscan_vborder_property, 1940 0); 1941 drm_object_attach_property(&amdgpu_connector->base.base, 1942 dev->mode_config.scaling_mode_property, 1943 DRM_MODE_SCALE_NONE); 1944 if (amdgpu_audio != 0) { 1945 drm_object_attach_property(&amdgpu_connector->base.base, 1946 adev->mode_info.audio_property, 1947 AMDGPU_AUDIO_AUTO); 1948 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1949 } 1950 drm_object_attach_property(&amdgpu_connector->base.base, 1951 adev->mode_info.dither_property, 1952 AMDGPU_FMT_DITHER_DISABLE); 1953 connector->interlace_allowed = true; 1954 /* in theory with a DP to VGA converter... */ 1955 connector->doublescan_allowed = false; 1956 break; 1957 case DRM_MODE_CONNECTOR_eDP: 1958 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1959 if (!amdgpu_dig_connector) 1960 goto failed; 1961 amdgpu_connector->con_priv = amdgpu_dig_connector; 1962 if (i2c_bus->valid) { 1963 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1964 if (amdgpu_connector->ddc_bus) { 1965 has_aux = true; 1966 ddc = &amdgpu_connector->ddc_bus->adapter; 1967 } else { 1968 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1969 } 1970 } 1971 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1972 &amdgpu_connector_edp_funcs, 1973 connector_type, 1974 ddc); 1975 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1976 drm_object_attach_property(&amdgpu_connector->base.base, 1977 dev->mode_config.scaling_mode_property, 1978 DRM_MODE_SCALE_FULLSCREEN); 1979 subpixel_order = SubPixelHorizontalRGB; 1980 connector->interlace_allowed = false; 1981 connector->doublescan_allowed = false; 1982 break; 1983 case DRM_MODE_CONNECTOR_LVDS: 1984 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1985 if (!amdgpu_dig_connector) 1986 goto failed; 1987 amdgpu_connector->con_priv = amdgpu_dig_connector; 1988 if (i2c_bus->valid) { 1989 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1990 if (!amdgpu_connector->ddc_bus) 1991 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1992 else 1993 ddc = &amdgpu_connector->ddc_bus->adapter; 1994 } 1995 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1996 &amdgpu_connector_lvds_funcs, 1997 connector_type, 1998 ddc); 1999 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2000 drm_object_attach_property(&amdgpu_connector->base.base, 2001 dev->mode_config.scaling_mode_property, 2002 DRM_MODE_SCALE_FULLSCREEN); 2003 subpixel_order = SubPixelHorizontalRGB; 2004 connector->interlace_allowed = false; 2005 connector->doublescan_allowed = false; 2006 break; 2007 } 2008 } 2009 2010 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2011 if (i2c_bus->valid) { 2012 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2013 DRM_CONNECTOR_POLL_DISCONNECT; 2014 } 2015 } else 2016 connector->polled = DRM_CONNECTOR_POLL_HPD; 2017 2018 connector->display_info.subpixel_order = subpixel_order; 2019 2020 if (has_aux) 2021 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2022 2023 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2024 connector_type == DRM_MODE_CONNECTOR_eDP) { 2025 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2026 } 2027 2028 return; 2029 2030 failed: 2031 drm_connector_cleanup(connector); 2032 kfree(connector); 2033 } 2034