1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_fb_helper.h> 29 #include <drm/drm_dp_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "atom.h" 34 #include "atombios_encoders.h" 35 #include "atombios_dp.h" 36 #include "amdgpu_connectors.h" 37 #include "amdgpu_i2c.h" 38 #include "amdgpu_display.h" 39 40 #include <linux/pm_runtime.h> 41 42 void amdgpu_connector_hotplug(struct drm_connector *connector) 43 { 44 struct drm_device *dev = connector->dev; 45 struct amdgpu_device *adev = drm_to_adev(dev); 46 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 47 48 /* bail if the connector does not have hpd pin, e.g., 49 * VGA, TV, etc. 50 */ 51 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 52 return; 53 54 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 55 56 /* if the connector is already off, don't turn it back on */ 57 if (connector->dpms != DRM_MODE_DPMS_ON) 58 return; 59 60 /* just deal with DP (not eDP) here. */ 61 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 62 struct amdgpu_connector_atom_dig *dig_connector = 63 amdgpu_connector->con_priv; 64 65 /* if existing sink type was not DP no need to retrain */ 66 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 67 return; 68 69 /* first get sink type as it may be reset after (un)plug */ 70 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 71 /* don't do anything if sink is not display port, i.e., 72 * passive dp->(dvi|hdmi) adaptor 73 */ 74 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 75 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 76 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 77 /* Don't start link training before we have the DPCD */ 78 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 79 return; 80 81 /* Turn the connector off and back on immediately, which 82 * will trigger link training 83 */ 84 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 86 } 87 } 88 } 89 90 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 91 { 92 struct drm_crtc *crtc = encoder->crtc; 93 94 if (crtc && crtc->enabled) { 95 drm_crtc_helper_set_mode(crtc, &crtc->mode, 96 crtc->x, crtc->y, crtc->primary->fb); 97 } 98 } 99 100 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 101 { 102 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 103 struct amdgpu_connector_atom_dig *dig_connector; 104 int bpc = 8; 105 unsigned mode_clock, max_tmds_clock; 106 107 switch (connector->connector_type) { 108 case DRM_MODE_CONNECTOR_DVII: 109 case DRM_MODE_CONNECTOR_HDMIB: 110 if (amdgpu_connector->use_digital) { 111 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 112 if (connector->display_info.bpc) 113 bpc = connector->display_info.bpc; 114 } 115 } 116 break; 117 case DRM_MODE_CONNECTOR_DVID: 118 case DRM_MODE_CONNECTOR_HDMIA: 119 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 120 if (connector->display_info.bpc) 121 bpc = connector->display_info.bpc; 122 } 123 break; 124 case DRM_MODE_CONNECTOR_DisplayPort: 125 dig_connector = amdgpu_connector->con_priv; 126 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 127 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 128 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 129 if (connector->display_info.bpc) 130 bpc = connector->display_info.bpc; 131 } 132 break; 133 case DRM_MODE_CONNECTOR_eDP: 134 case DRM_MODE_CONNECTOR_LVDS: 135 if (connector->display_info.bpc) 136 bpc = connector->display_info.bpc; 137 else { 138 const struct drm_connector_helper_funcs *connector_funcs = 139 connector->helper_private; 140 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 141 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 142 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 143 144 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 145 bpc = 6; 146 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 147 bpc = 8; 148 } 149 break; 150 } 151 152 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 153 /* 154 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 155 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 156 * 12 bpc is always supported on hdmi deep color sinks, as this is 157 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 158 */ 159 if (bpc > 12) { 160 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 161 connector->name, bpc); 162 bpc = 12; 163 } 164 165 /* Any defined maximum tmds clock limit we must not exceed? */ 166 if (connector->display_info.max_tmds_clock > 0) { 167 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 168 mode_clock = amdgpu_connector->pixelclock_for_modeset; 169 170 /* Maximum allowable input clock in kHz */ 171 max_tmds_clock = connector->display_info.max_tmds_clock; 172 173 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 174 connector->name, mode_clock, max_tmds_clock); 175 176 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 177 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 178 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 179 (mode_clock * 5/4 <= max_tmds_clock)) 180 bpc = 10; 181 else 182 bpc = 8; 183 184 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 185 connector->name, bpc); 186 } 187 188 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 189 bpc = 8; 190 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 191 connector->name, bpc); 192 } 193 } else if (bpc > 8) { 194 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 195 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 196 connector->name); 197 bpc = 8; 198 } 199 } 200 201 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 202 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 203 connector->name); 204 bpc = 8; 205 } 206 207 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 208 connector->name, connector->display_info.bpc, bpc); 209 210 return bpc; 211 } 212 213 static void 214 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 215 enum drm_connector_status status) 216 { 217 struct drm_encoder *best_encoder; 218 struct drm_encoder *encoder; 219 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 220 bool connected; 221 222 best_encoder = connector_funcs->best_encoder(connector); 223 224 drm_connector_for_each_possible_encoder(connector, encoder) { 225 if ((encoder == best_encoder) && (status == connector_status_connected)) 226 connected = true; 227 else 228 connected = false; 229 230 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 231 } 232 } 233 234 static struct drm_encoder * 235 amdgpu_connector_find_encoder(struct drm_connector *connector, 236 int encoder_type) 237 { 238 struct drm_encoder *encoder; 239 240 drm_connector_for_each_possible_encoder(connector, encoder) { 241 if (encoder->encoder_type == encoder_type) 242 return encoder; 243 } 244 245 return NULL; 246 } 247 248 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 249 { 250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 251 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 252 253 if (amdgpu_connector->edid) { 254 return amdgpu_connector->edid; 255 } else if (edid_blob) { 256 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 257 if (edid) 258 amdgpu_connector->edid = edid; 259 } 260 return amdgpu_connector->edid; 261 } 262 263 static struct edid * 264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 265 { 266 struct edid *edid; 267 268 if (adev->mode_info.bios_hardcoded_edid) { 269 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 270 if (edid) { 271 memcpy((unsigned char *)edid, 272 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 273 adev->mode_info.bios_hardcoded_edid_size); 274 return edid; 275 } 276 } 277 return NULL; 278 } 279 280 static void amdgpu_connector_get_edid(struct drm_connector *connector) 281 { 282 struct drm_device *dev = connector->dev; 283 struct amdgpu_device *adev = drm_to_adev(dev); 284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 285 286 if (amdgpu_connector->edid) 287 return; 288 289 /* on hw with routers, select right port */ 290 if (amdgpu_connector->router.ddc_valid) 291 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 292 293 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 294 ENCODER_OBJECT_ID_NONE) && 295 amdgpu_connector->ddc_bus->has_aux) { 296 amdgpu_connector->edid = drm_get_edid(connector, 297 &amdgpu_connector->ddc_bus->aux.ddc); 298 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 300 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 301 302 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 303 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 304 amdgpu_connector->ddc_bus->has_aux) 305 amdgpu_connector->edid = drm_get_edid(connector, 306 &amdgpu_connector->ddc_bus->aux.ddc); 307 else if (amdgpu_connector->ddc_bus) 308 amdgpu_connector->edid = drm_get_edid(connector, 309 &amdgpu_connector->ddc_bus->adapter); 310 } else if (amdgpu_connector->ddc_bus) { 311 amdgpu_connector->edid = drm_get_edid(connector, 312 &amdgpu_connector->ddc_bus->adapter); 313 } 314 315 if (!amdgpu_connector->edid) { 316 /* some laptops provide a hardcoded edid in rom for LCDs */ 317 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 318 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 319 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 320 } 321 } 322 323 static void amdgpu_connector_free_edid(struct drm_connector *connector) 324 { 325 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 326 327 kfree(amdgpu_connector->edid); 328 amdgpu_connector->edid = NULL; 329 } 330 331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 332 { 333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 334 int ret; 335 336 if (amdgpu_connector->edid) { 337 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 338 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 339 return ret; 340 } 341 drm_connector_update_edid_property(connector, NULL); 342 return 0; 343 } 344 345 static struct drm_encoder * 346 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 347 { 348 struct drm_encoder *encoder; 349 350 /* pick the first one */ 351 drm_connector_for_each_possible_encoder(connector, encoder) 352 return encoder; 353 354 return NULL; 355 } 356 357 static void amdgpu_get_native_mode(struct drm_connector *connector) 358 { 359 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 360 struct amdgpu_encoder *amdgpu_encoder; 361 362 if (encoder == NULL) 363 return; 364 365 amdgpu_encoder = to_amdgpu_encoder(encoder); 366 367 if (!list_empty(&connector->probed_modes)) { 368 struct drm_display_mode *preferred_mode = 369 list_first_entry(&connector->probed_modes, 370 struct drm_display_mode, head); 371 372 amdgpu_encoder->native_mode = *preferred_mode; 373 } else { 374 amdgpu_encoder->native_mode.clock = 0; 375 } 376 } 377 378 static struct drm_display_mode * 379 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 380 { 381 struct drm_device *dev = encoder->dev; 382 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 383 struct drm_display_mode *mode = NULL; 384 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 385 386 if (native_mode->hdisplay != 0 && 387 native_mode->vdisplay != 0 && 388 native_mode->clock != 0) { 389 mode = drm_mode_duplicate(dev, native_mode); 390 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 391 drm_mode_set_name(mode); 392 393 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 394 } else if (native_mode->hdisplay != 0 && 395 native_mode->vdisplay != 0) { 396 /* mac laptops without an edid */ 397 /* Note that this is not necessarily the exact panel mode, 398 * but an approximation based on the cvt formula. For these 399 * systems we should ideally read the mode info out of the 400 * registers or add a mode table, but this works and is much 401 * simpler. 402 */ 403 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 404 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 405 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 406 } 407 return mode; 408 } 409 410 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 411 struct drm_connector *connector) 412 { 413 struct drm_device *dev = encoder->dev; 414 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 415 struct drm_display_mode *mode = NULL; 416 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 417 int i; 418 static const struct mode_size { 419 int w; 420 int h; 421 } common_modes[17] = { 422 { 640, 480}, 423 { 720, 480}, 424 { 800, 600}, 425 { 848, 480}, 426 {1024, 768}, 427 {1152, 768}, 428 {1280, 720}, 429 {1280, 800}, 430 {1280, 854}, 431 {1280, 960}, 432 {1280, 1024}, 433 {1440, 900}, 434 {1400, 1050}, 435 {1680, 1050}, 436 {1600, 1200}, 437 {1920, 1080}, 438 {1920, 1200} 439 }; 440 441 for (i = 0; i < 17; i++) { 442 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 443 if (common_modes[i].w > 1024 || 444 common_modes[i].h > 768) 445 continue; 446 } 447 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 448 if (common_modes[i].w > native_mode->hdisplay || 449 common_modes[i].h > native_mode->vdisplay || 450 (common_modes[i].w == native_mode->hdisplay && 451 common_modes[i].h == native_mode->vdisplay)) 452 continue; 453 } 454 if (common_modes[i].w < 320 || common_modes[i].h < 200) 455 continue; 456 457 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 458 drm_mode_probed_add(connector, mode); 459 } 460 } 461 462 static int amdgpu_connector_set_property(struct drm_connector *connector, 463 struct drm_property *property, 464 uint64_t val) 465 { 466 struct drm_device *dev = connector->dev; 467 struct amdgpu_device *adev = drm_to_adev(dev); 468 struct drm_encoder *encoder; 469 struct amdgpu_encoder *amdgpu_encoder; 470 471 if (property == adev->mode_info.coherent_mode_property) { 472 struct amdgpu_encoder_atom_dig *dig; 473 bool new_coherent_mode; 474 475 /* need to find digital encoder on connector */ 476 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 477 if (!encoder) 478 return 0; 479 480 amdgpu_encoder = to_amdgpu_encoder(encoder); 481 482 if (!amdgpu_encoder->enc_priv) 483 return 0; 484 485 dig = amdgpu_encoder->enc_priv; 486 new_coherent_mode = val ? true : false; 487 if (dig->coherent_mode != new_coherent_mode) { 488 dig->coherent_mode = new_coherent_mode; 489 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 490 } 491 } 492 493 if (property == adev->mode_info.audio_property) { 494 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 495 /* need to find digital encoder on connector */ 496 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 497 if (!encoder) 498 return 0; 499 500 amdgpu_encoder = to_amdgpu_encoder(encoder); 501 502 if (amdgpu_connector->audio != val) { 503 amdgpu_connector->audio = val; 504 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 505 } 506 } 507 508 if (property == adev->mode_info.dither_property) { 509 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 510 /* need to find digital encoder on connector */ 511 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 512 if (!encoder) 513 return 0; 514 515 amdgpu_encoder = to_amdgpu_encoder(encoder); 516 517 if (amdgpu_connector->dither != val) { 518 amdgpu_connector->dither = val; 519 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 520 } 521 } 522 523 if (property == adev->mode_info.underscan_property) { 524 /* need to find digital encoder on connector */ 525 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 526 if (!encoder) 527 return 0; 528 529 amdgpu_encoder = to_amdgpu_encoder(encoder); 530 531 if (amdgpu_encoder->underscan_type != val) { 532 amdgpu_encoder->underscan_type = val; 533 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 534 } 535 } 536 537 if (property == adev->mode_info.underscan_hborder_property) { 538 /* need to find digital encoder on connector */ 539 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 540 if (!encoder) 541 return 0; 542 543 amdgpu_encoder = to_amdgpu_encoder(encoder); 544 545 if (amdgpu_encoder->underscan_hborder != val) { 546 amdgpu_encoder->underscan_hborder = val; 547 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 548 } 549 } 550 551 if (property == adev->mode_info.underscan_vborder_property) { 552 /* need to find digital encoder on connector */ 553 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 554 if (!encoder) 555 return 0; 556 557 amdgpu_encoder = to_amdgpu_encoder(encoder); 558 559 if (amdgpu_encoder->underscan_vborder != val) { 560 amdgpu_encoder->underscan_vborder = val; 561 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 562 } 563 } 564 565 if (property == adev->mode_info.load_detect_property) { 566 struct amdgpu_connector *amdgpu_connector = 567 to_amdgpu_connector(connector); 568 569 if (val == 0) 570 amdgpu_connector->dac_load_detect = false; 571 else 572 amdgpu_connector->dac_load_detect = true; 573 } 574 575 if (property == dev->mode_config.scaling_mode_property) { 576 enum amdgpu_rmx_type rmx_type; 577 578 if (connector->encoder) { 579 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 580 } else { 581 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 582 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 583 } 584 585 switch (val) { 586 default: 587 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 588 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 589 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 590 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 591 } 592 if (amdgpu_encoder->rmx_type == rmx_type) 593 return 0; 594 595 if ((rmx_type != DRM_MODE_SCALE_NONE) && 596 (amdgpu_encoder->native_mode.clock == 0)) 597 return 0; 598 599 amdgpu_encoder->rmx_type = rmx_type; 600 601 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 602 } 603 604 return 0; 605 } 606 607 static void 608 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 609 struct drm_connector *connector) 610 { 611 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 612 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 613 struct drm_display_mode *t, *mode; 614 615 /* If the EDID preferred mode doesn't match the native mode, use it */ 616 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 617 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 618 if (mode->hdisplay != native_mode->hdisplay || 619 mode->vdisplay != native_mode->vdisplay) 620 memcpy(native_mode, mode, sizeof(*mode)); 621 } 622 } 623 624 /* Try to get native mode details from EDID if necessary */ 625 if (!native_mode->clock) { 626 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 627 if (mode->hdisplay == native_mode->hdisplay && 628 mode->vdisplay == native_mode->vdisplay) { 629 *native_mode = *mode; 630 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 631 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 632 break; 633 } 634 } 635 } 636 637 if (!native_mode->clock) { 638 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 639 amdgpu_encoder->rmx_type = RMX_OFF; 640 } 641 } 642 643 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 644 { 645 struct drm_encoder *encoder; 646 int ret = 0; 647 struct drm_display_mode *mode; 648 649 amdgpu_connector_get_edid(connector); 650 ret = amdgpu_connector_ddc_get_modes(connector); 651 if (ret > 0) { 652 encoder = amdgpu_connector_best_single_encoder(connector); 653 if (encoder) { 654 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 655 /* add scaled modes */ 656 amdgpu_connector_add_common_modes(encoder, connector); 657 } 658 return ret; 659 } 660 661 encoder = amdgpu_connector_best_single_encoder(connector); 662 if (!encoder) 663 return 0; 664 665 /* we have no EDID modes */ 666 mode = amdgpu_connector_lcd_native_mode(encoder); 667 if (mode) { 668 ret = 1; 669 drm_mode_probed_add(connector, mode); 670 /* add the width/height from vbios tables if available */ 671 connector->display_info.width_mm = mode->width_mm; 672 connector->display_info.height_mm = mode->height_mm; 673 /* add scaled modes */ 674 amdgpu_connector_add_common_modes(encoder, connector); 675 } 676 677 return ret; 678 } 679 680 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 681 struct drm_display_mode *mode) 682 { 683 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 684 685 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 686 return MODE_PANEL; 687 688 if (encoder) { 689 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 690 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 691 692 /* AVIVO hardware supports downscaling modes larger than the panel 693 * to the panel size, but I'm not sure this is desirable. 694 */ 695 if ((mode->hdisplay > native_mode->hdisplay) || 696 (mode->vdisplay > native_mode->vdisplay)) 697 return MODE_PANEL; 698 699 /* if scaling is disabled, block non-native modes */ 700 if (amdgpu_encoder->rmx_type == RMX_OFF) { 701 if ((mode->hdisplay != native_mode->hdisplay) || 702 (mode->vdisplay != native_mode->vdisplay)) 703 return MODE_PANEL; 704 } 705 } 706 707 return MODE_OK; 708 } 709 710 static enum drm_connector_status 711 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 712 { 713 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 714 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 715 enum drm_connector_status ret = connector_status_disconnected; 716 int r; 717 718 if (!drm_kms_helper_is_poll_worker()) { 719 r = pm_runtime_get_sync(connector->dev->dev); 720 if (r < 0) { 721 pm_runtime_put_autosuspend(connector->dev->dev); 722 return connector_status_disconnected; 723 } 724 } 725 726 if (encoder) { 727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 728 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 729 730 /* check if panel is valid */ 731 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 732 ret = connector_status_connected; 733 734 } 735 736 /* check for edid as well */ 737 amdgpu_connector_get_edid(connector); 738 if (amdgpu_connector->edid) 739 ret = connector_status_connected; 740 /* check acpi lid status ??? */ 741 742 amdgpu_connector_update_scratch_regs(connector, ret); 743 744 if (!drm_kms_helper_is_poll_worker()) { 745 pm_runtime_mark_last_busy(connector->dev->dev); 746 pm_runtime_put_autosuspend(connector->dev->dev); 747 } 748 749 return ret; 750 } 751 752 static void amdgpu_connector_unregister(struct drm_connector *connector) 753 { 754 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 755 756 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 757 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 758 amdgpu_connector->ddc_bus->has_aux = false; 759 } 760 } 761 762 static void amdgpu_connector_destroy(struct drm_connector *connector) 763 { 764 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 765 766 amdgpu_connector_free_edid(connector); 767 kfree(amdgpu_connector->con_priv); 768 drm_connector_unregister(connector); 769 drm_connector_cleanup(connector); 770 kfree(connector); 771 } 772 773 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 774 struct drm_property *property, 775 uint64_t value) 776 { 777 struct drm_device *dev = connector->dev; 778 struct amdgpu_encoder *amdgpu_encoder; 779 enum amdgpu_rmx_type rmx_type; 780 781 DRM_DEBUG_KMS("\n"); 782 if (property != dev->mode_config.scaling_mode_property) 783 return 0; 784 785 if (connector->encoder) 786 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 787 else { 788 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 789 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 790 } 791 792 switch (value) { 793 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 794 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 795 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 796 default: 797 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 798 } 799 if (amdgpu_encoder->rmx_type == rmx_type) 800 return 0; 801 802 amdgpu_encoder->rmx_type = rmx_type; 803 804 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 805 return 0; 806 } 807 808 809 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 810 .get_modes = amdgpu_connector_lvds_get_modes, 811 .mode_valid = amdgpu_connector_lvds_mode_valid, 812 .best_encoder = amdgpu_connector_best_single_encoder, 813 }; 814 815 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 816 .dpms = drm_helper_connector_dpms, 817 .detect = amdgpu_connector_lvds_detect, 818 .fill_modes = drm_helper_probe_single_connector_modes, 819 .early_unregister = amdgpu_connector_unregister, 820 .destroy = amdgpu_connector_destroy, 821 .set_property = amdgpu_connector_set_lcd_property, 822 }; 823 824 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 825 { 826 int ret; 827 828 amdgpu_connector_get_edid(connector); 829 ret = amdgpu_connector_ddc_get_modes(connector); 830 amdgpu_get_native_mode(connector); 831 832 return ret; 833 } 834 835 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 836 struct drm_display_mode *mode) 837 { 838 struct drm_device *dev = connector->dev; 839 struct amdgpu_device *adev = drm_to_adev(dev); 840 841 /* XXX check mode bandwidth */ 842 843 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 844 return MODE_CLOCK_HIGH; 845 846 return MODE_OK; 847 } 848 849 static enum drm_connector_status 850 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 851 { 852 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 853 struct drm_encoder *encoder; 854 const struct drm_encoder_helper_funcs *encoder_funcs; 855 bool dret = false; 856 enum drm_connector_status ret = connector_status_disconnected; 857 int r; 858 859 if (!drm_kms_helper_is_poll_worker()) { 860 r = pm_runtime_get_sync(connector->dev->dev); 861 if (r < 0) { 862 pm_runtime_put_autosuspend(connector->dev->dev); 863 return connector_status_disconnected; 864 } 865 } 866 867 encoder = amdgpu_connector_best_single_encoder(connector); 868 if (!encoder) 869 ret = connector_status_disconnected; 870 871 if (amdgpu_connector->ddc_bus) 872 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 873 if (dret) { 874 amdgpu_connector->detected_by_load = false; 875 amdgpu_connector_free_edid(connector); 876 amdgpu_connector_get_edid(connector); 877 878 if (!amdgpu_connector->edid) { 879 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 880 connector->name); 881 ret = connector_status_connected; 882 } else { 883 amdgpu_connector->use_digital = 884 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 885 886 /* some oems have boards with separate digital and analog connectors 887 * with a shared ddc line (often vga + hdmi) 888 */ 889 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 890 amdgpu_connector_free_edid(connector); 891 ret = connector_status_disconnected; 892 } else { 893 ret = connector_status_connected; 894 } 895 } 896 } else { 897 898 /* if we aren't forcing don't do destructive polling */ 899 if (!force) { 900 /* only return the previous status if we last 901 * detected a monitor via load. 902 */ 903 if (amdgpu_connector->detected_by_load) 904 ret = connector->status; 905 goto out; 906 } 907 908 if (amdgpu_connector->dac_load_detect && encoder) { 909 encoder_funcs = encoder->helper_private; 910 ret = encoder_funcs->detect(encoder, connector); 911 if (ret != connector_status_disconnected) 912 amdgpu_connector->detected_by_load = true; 913 } 914 } 915 916 amdgpu_connector_update_scratch_regs(connector, ret); 917 918 out: 919 if (!drm_kms_helper_is_poll_worker()) { 920 pm_runtime_mark_last_busy(connector->dev->dev); 921 pm_runtime_put_autosuspend(connector->dev->dev); 922 } 923 924 return ret; 925 } 926 927 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 928 .get_modes = amdgpu_connector_vga_get_modes, 929 .mode_valid = amdgpu_connector_vga_mode_valid, 930 .best_encoder = amdgpu_connector_best_single_encoder, 931 }; 932 933 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 934 .dpms = drm_helper_connector_dpms, 935 .detect = amdgpu_connector_vga_detect, 936 .fill_modes = drm_helper_probe_single_connector_modes, 937 .early_unregister = amdgpu_connector_unregister, 938 .destroy = amdgpu_connector_destroy, 939 .set_property = amdgpu_connector_set_property, 940 }; 941 942 static bool 943 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 944 { 945 struct drm_device *dev = connector->dev; 946 struct amdgpu_device *adev = drm_to_adev(dev); 947 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 948 enum drm_connector_status status; 949 950 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 951 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 952 status = connector_status_connected; 953 else 954 status = connector_status_disconnected; 955 if (connector->status == status) 956 return true; 957 } 958 959 return false; 960 } 961 962 /* 963 * DVI is complicated 964 * Do a DDC probe, if DDC probe passes, get the full EDID so 965 * we can do analog/digital monitor detection at this point. 966 * If the monitor is an analog monitor or we got no DDC, 967 * we need to find the DAC encoder object for this connector. 968 * If we got no DDC, we do load detection on the DAC encoder object. 969 * If we got analog DDC or load detection passes on the DAC encoder 970 * we have to check if this analog encoder is shared with anyone else (TV) 971 * if its shared we have to set the other connector to disconnected. 972 */ 973 static enum drm_connector_status 974 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 975 { 976 struct drm_device *dev = connector->dev; 977 struct amdgpu_device *adev = drm_to_adev(dev); 978 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 979 const struct drm_encoder_helper_funcs *encoder_funcs; 980 int r; 981 enum drm_connector_status ret = connector_status_disconnected; 982 bool dret = false, broken_edid = false; 983 984 if (!drm_kms_helper_is_poll_worker()) { 985 r = pm_runtime_get_sync(connector->dev->dev); 986 if (r < 0) { 987 pm_runtime_put_autosuspend(connector->dev->dev); 988 return connector_status_disconnected; 989 } 990 } 991 992 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 993 ret = connector->status; 994 goto exit; 995 } 996 997 if (amdgpu_connector->ddc_bus) 998 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 999 if (dret) { 1000 amdgpu_connector->detected_by_load = false; 1001 amdgpu_connector_free_edid(connector); 1002 amdgpu_connector_get_edid(connector); 1003 1004 if (!amdgpu_connector->edid) { 1005 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1006 connector->name); 1007 ret = connector_status_connected; 1008 broken_edid = true; /* defer use_digital to later */ 1009 } else { 1010 amdgpu_connector->use_digital = 1011 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1012 1013 /* some oems have boards with separate digital and analog connectors 1014 * with a shared ddc line (often vga + hdmi) 1015 */ 1016 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1017 amdgpu_connector_free_edid(connector); 1018 ret = connector_status_disconnected; 1019 } else { 1020 ret = connector_status_connected; 1021 } 1022 1023 /* This gets complicated. We have boards with VGA + HDMI with a 1024 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1025 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1026 * you don't really know what's connected to which port as both are digital. 1027 */ 1028 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1029 struct drm_connector *list_connector; 1030 struct drm_connector_list_iter iter; 1031 struct amdgpu_connector *list_amdgpu_connector; 1032 1033 drm_connector_list_iter_begin(dev, &iter); 1034 drm_for_each_connector_iter(list_connector, 1035 &iter) { 1036 if (connector == list_connector) 1037 continue; 1038 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1039 if (list_amdgpu_connector->shared_ddc && 1040 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1041 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1042 /* cases where both connectors are digital */ 1043 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1044 /* hpd is our only option in this case */ 1045 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1046 amdgpu_connector_free_edid(connector); 1047 ret = connector_status_disconnected; 1048 } 1049 } 1050 } 1051 } 1052 drm_connector_list_iter_end(&iter); 1053 } 1054 } 1055 } 1056 1057 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1058 goto out; 1059 1060 /* DVI-D and HDMI-A are digital only */ 1061 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1062 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1063 goto out; 1064 1065 /* if we aren't forcing don't do destructive polling */ 1066 if (!force) { 1067 /* only return the previous status if we last 1068 * detected a monitor via load. 1069 */ 1070 if (amdgpu_connector->detected_by_load) 1071 ret = connector->status; 1072 goto out; 1073 } 1074 1075 /* find analog encoder */ 1076 if (amdgpu_connector->dac_load_detect) { 1077 struct drm_encoder *encoder; 1078 1079 drm_connector_for_each_possible_encoder(connector, encoder) { 1080 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1081 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1082 continue; 1083 1084 encoder_funcs = encoder->helper_private; 1085 if (encoder_funcs->detect) { 1086 if (!broken_edid) { 1087 if (ret != connector_status_connected) { 1088 /* deal with analog monitors without DDC */ 1089 ret = encoder_funcs->detect(encoder, connector); 1090 if (ret == connector_status_connected) { 1091 amdgpu_connector->use_digital = false; 1092 } 1093 if (ret != connector_status_disconnected) 1094 amdgpu_connector->detected_by_load = true; 1095 } 1096 } else { 1097 enum drm_connector_status lret; 1098 /* assume digital unless load detected otherwise */ 1099 amdgpu_connector->use_digital = true; 1100 lret = encoder_funcs->detect(encoder, connector); 1101 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1102 if (lret == connector_status_connected) 1103 amdgpu_connector->use_digital = false; 1104 } 1105 break; 1106 } 1107 } 1108 } 1109 1110 out: 1111 /* updated in get modes as well since we need to know if it's analog or digital */ 1112 amdgpu_connector_update_scratch_regs(connector, ret); 1113 1114 exit: 1115 if (!drm_kms_helper_is_poll_worker()) { 1116 pm_runtime_mark_last_busy(connector->dev->dev); 1117 pm_runtime_put_autosuspend(connector->dev->dev); 1118 } 1119 1120 return ret; 1121 } 1122 1123 /* okay need to be smart in here about which encoder to pick */ 1124 static struct drm_encoder * 1125 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1126 { 1127 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1128 struct drm_encoder *encoder; 1129 1130 drm_connector_for_each_possible_encoder(connector, encoder) { 1131 if (amdgpu_connector->use_digital == true) { 1132 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1133 return encoder; 1134 } else { 1135 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1136 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1137 return encoder; 1138 } 1139 } 1140 1141 /* see if we have a default encoder TODO */ 1142 1143 /* then check use digitial */ 1144 /* pick the first one */ 1145 drm_connector_for_each_possible_encoder(connector, encoder) 1146 return encoder; 1147 1148 return NULL; 1149 } 1150 1151 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1152 { 1153 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1154 if (connector->force == DRM_FORCE_ON) 1155 amdgpu_connector->use_digital = false; 1156 if (connector->force == DRM_FORCE_ON_DIGITAL) 1157 amdgpu_connector->use_digital = true; 1158 } 1159 1160 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1161 struct drm_display_mode *mode) 1162 { 1163 struct drm_device *dev = connector->dev; 1164 struct amdgpu_device *adev = drm_to_adev(dev); 1165 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1166 1167 /* XXX check mode bandwidth */ 1168 1169 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1170 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1171 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1172 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1173 return MODE_OK; 1174 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1175 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1176 if (mode->clock > 340000) 1177 return MODE_CLOCK_HIGH; 1178 else 1179 return MODE_OK; 1180 } else { 1181 return MODE_CLOCK_HIGH; 1182 } 1183 } 1184 1185 /* check against the max pixel clock */ 1186 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1187 return MODE_CLOCK_HIGH; 1188 1189 return MODE_OK; 1190 } 1191 1192 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1193 .get_modes = amdgpu_connector_vga_get_modes, 1194 .mode_valid = amdgpu_connector_dvi_mode_valid, 1195 .best_encoder = amdgpu_connector_dvi_encoder, 1196 }; 1197 1198 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1199 .dpms = drm_helper_connector_dpms, 1200 .detect = amdgpu_connector_dvi_detect, 1201 .fill_modes = drm_helper_probe_single_connector_modes, 1202 .set_property = amdgpu_connector_set_property, 1203 .early_unregister = amdgpu_connector_unregister, 1204 .destroy = amdgpu_connector_destroy, 1205 .force = amdgpu_connector_dvi_force, 1206 }; 1207 1208 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1209 { 1210 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1211 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1212 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1213 int ret; 1214 1215 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1216 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1217 struct drm_display_mode *mode; 1218 1219 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1220 if (!amdgpu_dig_connector->edp_on) 1221 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1222 ATOM_TRANSMITTER_ACTION_POWER_ON); 1223 amdgpu_connector_get_edid(connector); 1224 ret = amdgpu_connector_ddc_get_modes(connector); 1225 if (!amdgpu_dig_connector->edp_on) 1226 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1227 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1228 } else { 1229 /* need to setup ddc on the bridge */ 1230 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1231 ENCODER_OBJECT_ID_NONE) { 1232 if (encoder) 1233 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1234 } 1235 amdgpu_connector_get_edid(connector); 1236 ret = amdgpu_connector_ddc_get_modes(connector); 1237 } 1238 1239 if (ret > 0) { 1240 if (encoder) { 1241 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1242 /* add scaled modes */ 1243 amdgpu_connector_add_common_modes(encoder, connector); 1244 } 1245 return ret; 1246 } 1247 1248 if (!encoder) 1249 return 0; 1250 1251 /* we have no EDID modes */ 1252 mode = amdgpu_connector_lcd_native_mode(encoder); 1253 if (mode) { 1254 ret = 1; 1255 drm_mode_probed_add(connector, mode); 1256 /* add the width/height from vbios tables if available */ 1257 connector->display_info.width_mm = mode->width_mm; 1258 connector->display_info.height_mm = mode->height_mm; 1259 /* add scaled modes */ 1260 amdgpu_connector_add_common_modes(encoder, connector); 1261 } 1262 } else { 1263 /* need to setup ddc on the bridge */ 1264 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1265 ENCODER_OBJECT_ID_NONE) { 1266 if (encoder) 1267 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1268 } 1269 amdgpu_connector_get_edid(connector); 1270 ret = amdgpu_connector_ddc_get_modes(connector); 1271 1272 amdgpu_get_native_mode(connector); 1273 } 1274 1275 return ret; 1276 } 1277 1278 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1279 { 1280 struct drm_encoder *encoder; 1281 struct amdgpu_encoder *amdgpu_encoder; 1282 1283 drm_connector_for_each_possible_encoder(connector, encoder) { 1284 amdgpu_encoder = to_amdgpu_encoder(encoder); 1285 1286 switch (amdgpu_encoder->encoder_id) { 1287 case ENCODER_OBJECT_ID_TRAVIS: 1288 case ENCODER_OBJECT_ID_NUTMEG: 1289 return amdgpu_encoder->encoder_id; 1290 default: 1291 break; 1292 } 1293 } 1294 1295 return ENCODER_OBJECT_ID_NONE; 1296 } 1297 1298 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1299 { 1300 struct drm_encoder *encoder; 1301 struct amdgpu_encoder *amdgpu_encoder; 1302 bool found = false; 1303 1304 drm_connector_for_each_possible_encoder(connector, encoder) { 1305 amdgpu_encoder = to_amdgpu_encoder(encoder); 1306 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1307 found = true; 1308 } 1309 1310 return found; 1311 } 1312 1313 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1314 { 1315 struct drm_device *dev = connector->dev; 1316 struct amdgpu_device *adev = drm_to_adev(dev); 1317 1318 if ((adev->clock.default_dispclk >= 53900) && 1319 amdgpu_connector_encoder_is_hbr2(connector)) { 1320 return true; 1321 } 1322 1323 return false; 1324 } 1325 1326 static enum drm_connector_status 1327 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1328 { 1329 struct drm_device *dev = connector->dev; 1330 struct amdgpu_device *adev = drm_to_adev(dev); 1331 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1332 enum drm_connector_status ret = connector_status_disconnected; 1333 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1334 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1335 int r; 1336 1337 if (!drm_kms_helper_is_poll_worker()) { 1338 r = pm_runtime_get_sync(connector->dev->dev); 1339 if (r < 0) { 1340 pm_runtime_put_autosuspend(connector->dev->dev); 1341 return connector_status_disconnected; 1342 } 1343 } 1344 1345 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1346 ret = connector->status; 1347 goto out; 1348 } 1349 1350 amdgpu_connector_free_edid(connector); 1351 1352 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1353 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1354 if (encoder) { 1355 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1356 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1357 1358 /* check if panel is valid */ 1359 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1360 ret = connector_status_connected; 1361 } 1362 /* eDP is always DP */ 1363 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1364 if (!amdgpu_dig_connector->edp_on) 1365 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1366 ATOM_TRANSMITTER_ACTION_POWER_ON); 1367 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1368 ret = connector_status_connected; 1369 if (!amdgpu_dig_connector->edp_on) 1370 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1371 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1372 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1373 ENCODER_OBJECT_ID_NONE) { 1374 /* DP bridges are always DP */ 1375 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1376 /* get the DPCD from the bridge */ 1377 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1378 1379 if (encoder) { 1380 /* setup ddc on the bridge */ 1381 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1382 /* bridge chips are always aux */ 1383 /* try DDC */ 1384 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1385 ret = connector_status_connected; 1386 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1387 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1388 ret = encoder_funcs->detect(encoder, connector); 1389 } 1390 } 1391 } else { 1392 amdgpu_dig_connector->dp_sink_type = 1393 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1394 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1395 ret = connector_status_connected; 1396 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1397 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1398 } else { 1399 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1400 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1401 ret = connector_status_connected; 1402 } else { 1403 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1404 if (amdgpu_display_ddc_probe(amdgpu_connector, 1405 false)) 1406 ret = connector_status_connected; 1407 } 1408 } 1409 } 1410 1411 amdgpu_connector_update_scratch_regs(connector, ret); 1412 out: 1413 if (!drm_kms_helper_is_poll_worker()) { 1414 pm_runtime_mark_last_busy(connector->dev->dev); 1415 pm_runtime_put_autosuspend(connector->dev->dev); 1416 } 1417 1418 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1419 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1420 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1421 ret, 1422 amdgpu_dig_connector->dpcd, 1423 amdgpu_dig_connector->downstream_ports); 1424 return ret; 1425 } 1426 1427 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1428 struct drm_display_mode *mode) 1429 { 1430 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1431 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1432 1433 /* XXX check mode bandwidth */ 1434 1435 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1436 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1437 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1438 1439 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1440 return MODE_PANEL; 1441 1442 if (encoder) { 1443 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1444 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1445 1446 /* AVIVO hardware supports downscaling modes larger than the panel 1447 * to the panel size, but I'm not sure this is desirable. 1448 */ 1449 if ((mode->hdisplay > native_mode->hdisplay) || 1450 (mode->vdisplay > native_mode->vdisplay)) 1451 return MODE_PANEL; 1452 1453 /* if scaling is disabled, block non-native modes */ 1454 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1455 if ((mode->hdisplay != native_mode->hdisplay) || 1456 (mode->vdisplay != native_mode->vdisplay)) 1457 return MODE_PANEL; 1458 } 1459 } 1460 return MODE_OK; 1461 } else { 1462 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1463 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1464 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1465 } else { 1466 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1467 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1468 if (mode->clock > 340000) 1469 return MODE_CLOCK_HIGH; 1470 } else { 1471 if (mode->clock > 165000) 1472 return MODE_CLOCK_HIGH; 1473 } 1474 } 1475 } 1476 1477 return MODE_OK; 1478 } 1479 1480 static int 1481 amdgpu_connector_late_register(struct drm_connector *connector) 1482 { 1483 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1484 int r = 0; 1485 1486 if (amdgpu_connector->ddc_bus->has_aux) { 1487 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1488 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1489 } 1490 1491 return r; 1492 } 1493 1494 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1495 .get_modes = amdgpu_connector_dp_get_modes, 1496 .mode_valid = amdgpu_connector_dp_mode_valid, 1497 .best_encoder = amdgpu_connector_dvi_encoder, 1498 }; 1499 1500 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1501 .dpms = drm_helper_connector_dpms, 1502 .detect = amdgpu_connector_dp_detect, 1503 .fill_modes = drm_helper_probe_single_connector_modes, 1504 .set_property = amdgpu_connector_set_property, 1505 .early_unregister = amdgpu_connector_unregister, 1506 .destroy = amdgpu_connector_destroy, 1507 .force = amdgpu_connector_dvi_force, 1508 .late_register = amdgpu_connector_late_register, 1509 }; 1510 1511 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1512 .dpms = drm_helper_connector_dpms, 1513 .detect = amdgpu_connector_dp_detect, 1514 .fill_modes = drm_helper_probe_single_connector_modes, 1515 .set_property = amdgpu_connector_set_lcd_property, 1516 .early_unregister = amdgpu_connector_unregister, 1517 .destroy = amdgpu_connector_destroy, 1518 .force = amdgpu_connector_dvi_force, 1519 .late_register = amdgpu_connector_late_register, 1520 }; 1521 1522 void 1523 amdgpu_connector_add(struct amdgpu_device *adev, 1524 uint32_t connector_id, 1525 uint32_t supported_device, 1526 int connector_type, 1527 struct amdgpu_i2c_bus_rec *i2c_bus, 1528 uint16_t connector_object_id, 1529 struct amdgpu_hpd *hpd, 1530 struct amdgpu_router *router) 1531 { 1532 struct drm_device *dev = adev_to_drm(adev); 1533 struct drm_connector *connector; 1534 struct drm_connector_list_iter iter; 1535 struct amdgpu_connector *amdgpu_connector; 1536 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1537 struct drm_encoder *encoder; 1538 struct amdgpu_encoder *amdgpu_encoder; 1539 struct i2c_adapter *ddc = NULL; 1540 uint32_t subpixel_order = SubPixelNone; 1541 bool shared_ddc = false; 1542 bool is_dp_bridge = false; 1543 bool has_aux = false; 1544 1545 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1546 return; 1547 1548 /* see if we already added it */ 1549 drm_connector_list_iter_begin(dev, &iter); 1550 drm_for_each_connector_iter(connector, &iter) { 1551 amdgpu_connector = to_amdgpu_connector(connector); 1552 if (amdgpu_connector->connector_id == connector_id) { 1553 amdgpu_connector->devices |= supported_device; 1554 drm_connector_list_iter_end(&iter); 1555 return; 1556 } 1557 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1558 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1559 amdgpu_connector->shared_ddc = true; 1560 shared_ddc = true; 1561 } 1562 if (amdgpu_connector->router_bus && router->ddc_valid && 1563 (amdgpu_connector->router.router_id == router->router_id)) { 1564 amdgpu_connector->shared_ddc = false; 1565 shared_ddc = false; 1566 } 1567 } 1568 } 1569 drm_connector_list_iter_end(&iter); 1570 1571 /* check if it's a dp bridge */ 1572 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1573 amdgpu_encoder = to_amdgpu_encoder(encoder); 1574 if (amdgpu_encoder->devices & supported_device) { 1575 switch (amdgpu_encoder->encoder_id) { 1576 case ENCODER_OBJECT_ID_TRAVIS: 1577 case ENCODER_OBJECT_ID_NUTMEG: 1578 is_dp_bridge = true; 1579 break; 1580 default: 1581 break; 1582 } 1583 } 1584 } 1585 1586 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1587 if (!amdgpu_connector) 1588 return; 1589 1590 connector = &amdgpu_connector->base; 1591 1592 amdgpu_connector->connector_id = connector_id; 1593 amdgpu_connector->devices = supported_device; 1594 amdgpu_connector->shared_ddc = shared_ddc; 1595 amdgpu_connector->connector_object_id = connector_object_id; 1596 amdgpu_connector->hpd = *hpd; 1597 1598 amdgpu_connector->router = *router; 1599 if (router->ddc_valid || router->cd_valid) { 1600 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1601 if (!amdgpu_connector->router_bus) 1602 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1603 } 1604 1605 if (is_dp_bridge) { 1606 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1607 if (!amdgpu_dig_connector) 1608 goto failed; 1609 amdgpu_connector->con_priv = amdgpu_dig_connector; 1610 if (i2c_bus->valid) { 1611 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1612 if (amdgpu_connector->ddc_bus) { 1613 has_aux = true; 1614 ddc = &amdgpu_connector->ddc_bus->adapter; 1615 } else { 1616 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1617 } 1618 } 1619 switch (connector_type) { 1620 case DRM_MODE_CONNECTOR_VGA: 1621 case DRM_MODE_CONNECTOR_DVIA: 1622 default: 1623 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1624 &amdgpu_connector_dp_funcs, 1625 connector_type, 1626 ddc); 1627 drm_connector_helper_add(&amdgpu_connector->base, 1628 &amdgpu_connector_dp_helper_funcs); 1629 connector->interlace_allowed = true; 1630 connector->doublescan_allowed = true; 1631 amdgpu_connector->dac_load_detect = true; 1632 drm_object_attach_property(&amdgpu_connector->base.base, 1633 adev->mode_info.load_detect_property, 1634 1); 1635 drm_object_attach_property(&amdgpu_connector->base.base, 1636 dev->mode_config.scaling_mode_property, 1637 DRM_MODE_SCALE_NONE); 1638 break; 1639 case DRM_MODE_CONNECTOR_DVII: 1640 case DRM_MODE_CONNECTOR_DVID: 1641 case DRM_MODE_CONNECTOR_HDMIA: 1642 case DRM_MODE_CONNECTOR_HDMIB: 1643 case DRM_MODE_CONNECTOR_DisplayPort: 1644 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1645 &amdgpu_connector_dp_funcs, 1646 connector_type, 1647 ddc); 1648 drm_connector_helper_add(&amdgpu_connector->base, 1649 &amdgpu_connector_dp_helper_funcs); 1650 drm_object_attach_property(&amdgpu_connector->base.base, 1651 adev->mode_info.underscan_property, 1652 UNDERSCAN_OFF); 1653 drm_object_attach_property(&amdgpu_connector->base.base, 1654 adev->mode_info.underscan_hborder_property, 1655 0); 1656 drm_object_attach_property(&amdgpu_connector->base.base, 1657 adev->mode_info.underscan_vborder_property, 1658 0); 1659 1660 drm_object_attach_property(&amdgpu_connector->base.base, 1661 dev->mode_config.scaling_mode_property, 1662 DRM_MODE_SCALE_NONE); 1663 1664 drm_object_attach_property(&amdgpu_connector->base.base, 1665 adev->mode_info.dither_property, 1666 AMDGPU_FMT_DITHER_DISABLE); 1667 1668 if (amdgpu_audio != 0) 1669 drm_object_attach_property(&amdgpu_connector->base.base, 1670 adev->mode_info.audio_property, 1671 AMDGPU_AUDIO_AUTO); 1672 1673 subpixel_order = SubPixelHorizontalRGB; 1674 connector->interlace_allowed = true; 1675 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1676 connector->doublescan_allowed = true; 1677 else 1678 connector->doublescan_allowed = false; 1679 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1680 amdgpu_connector->dac_load_detect = true; 1681 drm_object_attach_property(&amdgpu_connector->base.base, 1682 adev->mode_info.load_detect_property, 1683 1); 1684 } 1685 break; 1686 case DRM_MODE_CONNECTOR_LVDS: 1687 case DRM_MODE_CONNECTOR_eDP: 1688 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1689 &amdgpu_connector_edp_funcs, 1690 connector_type, 1691 ddc); 1692 drm_connector_helper_add(&amdgpu_connector->base, 1693 &amdgpu_connector_dp_helper_funcs); 1694 drm_object_attach_property(&amdgpu_connector->base.base, 1695 dev->mode_config.scaling_mode_property, 1696 DRM_MODE_SCALE_FULLSCREEN); 1697 subpixel_order = SubPixelHorizontalRGB; 1698 connector->interlace_allowed = false; 1699 connector->doublescan_allowed = false; 1700 break; 1701 } 1702 } else { 1703 switch (connector_type) { 1704 case DRM_MODE_CONNECTOR_VGA: 1705 if (i2c_bus->valid) { 1706 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1707 if (!amdgpu_connector->ddc_bus) 1708 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1709 else 1710 ddc = &amdgpu_connector->ddc_bus->adapter; 1711 } 1712 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1713 &amdgpu_connector_vga_funcs, 1714 connector_type, 1715 ddc); 1716 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1717 amdgpu_connector->dac_load_detect = true; 1718 drm_object_attach_property(&amdgpu_connector->base.base, 1719 adev->mode_info.load_detect_property, 1720 1); 1721 drm_object_attach_property(&amdgpu_connector->base.base, 1722 dev->mode_config.scaling_mode_property, 1723 DRM_MODE_SCALE_NONE); 1724 /* no HPD on analog connectors */ 1725 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1726 connector->interlace_allowed = true; 1727 connector->doublescan_allowed = true; 1728 break; 1729 case DRM_MODE_CONNECTOR_DVIA: 1730 if (i2c_bus->valid) { 1731 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1732 if (!amdgpu_connector->ddc_bus) 1733 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1734 else 1735 ddc = &amdgpu_connector->ddc_bus->adapter; 1736 } 1737 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1738 &amdgpu_connector_vga_funcs, 1739 connector_type, 1740 ddc); 1741 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1742 amdgpu_connector->dac_load_detect = true; 1743 drm_object_attach_property(&amdgpu_connector->base.base, 1744 adev->mode_info.load_detect_property, 1745 1); 1746 drm_object_attach_property(&amdgpu_connector->base.base, 1747 dev->mode_config.scaling_mode_property, 1748 DRM_MODE_SCALE_NONE); 1749 /* no HPD on analog connectors */ 1750 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1751 connector->interlace_allowed = true; 1752 connector->doublescan_allowed = true; 1753 break; 1754 case DRM_MODE_CONNECTOR_DVII: 1755 case DRM_MODE_CONNECTOR_DVID: 1756 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1757 if (!amdgpu_dig_connector) 1758 goto failed; 1759 amdgpu_connector->con_priv = amdgpu_dig_connector; 1760 if (i2c_bus->valid) { 1761 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1762 if (!amdgpu_connector->ddc_bus) 1763 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1764 else 1765 ddc = &amdgpu_connector->ddc_bus->adapter; 1766 } 1767 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1768 &amdgpu_connector_dvi_funcs, 1769 connector_type, 1770 ddc); 1771 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1772 subpixel_order = SubPixelHorizontalRGB; 1773 drm_object_attach_property(&amdgpu_connector->base.base, 1774 adev->mode_info.coherent_mode_property, 1775 1); 1776 drm_object_attach_property(&amdgpu_connector->base.base, 1777 adev->mode_info.underscan_property, 1778 UNDERSCAN_OFF); 1779 drm_object_attach_property(&amdgpu_connector->base.base, 1780 adev->mode_info.underscan_hborder_property, 1781 0); 1782 drm_object_attach_property(&amdgpu_connector->base.base, 1783 adev->mode_info.underscan_vborder_property, 1784 0); 1785 drm_object_attach_property(&amdgpu_connector->base.base, 1786 dev->mode_config.scaling_mode_property, 1787 DRM_MODE_SCALE_NONE); 1788 1789 if (amdgpu_audio != 0) { 1790 drm_object_attach_property(&amdgpu_connector->base.base, 1791 adev->mode_info.audio_property, 1792 AMDGPU_AUDIO_AUTO); 1793 } 1794 drm_object_attach_property(&amdgpu_connector->base.base, 1795 adev->mode_info.dither_property, 1796 AMDGPU_FMT_DITHER_DISABLE); 1797 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1798 amdgpu_connector->dac_load_detect = true; 1799 drm_object_attach_property(&amdgpu_connector->base.base, 1800 adev->mode_info.load_detect_property, 1801 1); 1802 } 1803 connector->interlace_allowed = true; 1804 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1805 connector->doublescan_allowed = true; 1806 else 1807 connector->doublescan_allowed = false; 1808 break; 1809 case DRM_MODE_CONNECTOR_HDMIA: 1810 case DRM_MODE_CONNECTOR_HDMIB: 1811 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1812 if (!amdgpu_dig_connector) 1813 goto failed; 1814 amdgpu_connector->con_priv = amdgpu_dig_connector; 1815 if (i2c_bus->valid) { 1816 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1817 if (!amdgpu_connector->ddc_bus) 1818 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1819 else 1820 ddc = &amdgpu_connector->ddc_bus->adapter; 1821 } 1822 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1823 &amdgpu_connector_dvi_funcs, 1824 connector_type, 1825 ddc); 1826 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1827 drm_object_attach_property(&amdgpu_connector->base.base, 1828 adev->mode_info.coherent_mode_property, 1829 1); 1830 drm_object_attach_property(&amdgpu_connector->base.base, 1831 adev->mode_info.underscan_property, 1832 UNDERSCAN_OFF); 1833 drm_object_attach_property(&amdgpu_connector->base.base, 1834 adev->mode_info.underscan_hborder_property, 1835 0); 1836 drm_object_attach_property(&amdgpu_connector->base.base, 1837 adev->mode_info.underscan_vborder_property, 1838 0); 1839 drm_object_attach_property(&amdgpu_connector->base.base, 1840 dev->mode_config.scaling_mode_property, 1841 DRM_MODE_SCALE_NONE); 1842 if (amdgpu_audio != 0) { 1843 drm_object_attach_property(&amdgpu_connector->base.base, 1844 adev->mode_info.audio_property, 1845 AMDGPU_AUDIO_AUTO); 1846 } 1847 drm_object_attach_property(&amdgpu_connector->base.base, 1848 adev->mode_info.dither_property, 1849 AMDGPU_FMT_DITHER_DISABLE); 1850 subpixel_order = SubPixelHorizontalRGB; 1851 connector->interlace_allowed = true; 1852 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1853 connector->doublescan_allowed = true; 1854 else 1855 connector->doublescan_allowed = false; 1856 break; 1857 case DRM_MODE_CONNECTOR_DisplayPort: 1858 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1859 if (!amdgpu_dig_connector) 1860 goto failed; 1861 amdgpu_connector->con_priv = amdgpu_dig_connector; 1862 if (i2c_bus->valid) { 1863 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1864 if (amdgpu_connector->ddc_bus) { 1865 has_aux = true; 1866 ddc = &amdgpu_connector->ddc_bus->adapter; 1867 } else { 1868 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1869 } 1870 } 1871 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1872 &amdgpu_connector_dp_funcs, 1873 connector_type, 1874 ddc); 1875 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1876 subpixel_order = SubPixelHorizontalRGB; 1877 drm_object_attach_property(&amdgpu_connector->base.base, 1878 adev->mode_info.coherent_mode_property, 1879 1); 1880 drm_object_attach_property(&amdgpu_connector->base.base, 1881 adev->mode_info.underscan_property, 1882 UNDERSCAN_OFF); 1883 drm_object_attach_property(&amdgpu_connector->base.base, 1884 adev->mode_info.underscan_hborder_property, 1885 0); 1886 drm_object_attach_property(&amdgpu_connector->base.base, 1887 adev->mode_info.underscan_vborder_property, 1888 0); 1889 drm_object_attach_property(&amdgpu_connector->base.base, 1890 dev->mode_config.scaling_mode_property, 1891 DRM_MODE_SCALE_NONE); 1892 if (amdgpu_audio != 0) { 1893 drm_object_attach_property(&amdgpu_connector->base.base, 1894 adev->mode_info.audio_property, 1895 AMDGPU_AUDIO_AUTO); 1896 } 1897 drm_object_attach_property(&amdgpu_connector->base.base, 1898 adev->mode_info.dither_property, 1899 AMDGPU_FMT_DITHER_DISABLE); 1900 connector->interlace_allowed = true; 1901 /* in theory with a DP to VGA converter... */ 1902 connector->doublescan_allowed = false; 1903 break; 1904 case DRM_MODE_CONNECTOR_eDP: 1905 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1906 if (!amdgpu_dig_connector) 1907 goto failed; 1908 amdgpu_connector->con_priv = amdgpu_dig_connector; 1909 if (i2c_bus->valid) { 1910 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1911 if (amdgpu_connector->ddc_bus) { 1912 has_aux = true; 1913 ddc = &amdgpu_connector->ddc_bus->adapter; 1914 } else { 1915 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1916 } 1917 } 1918 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1919 &amdgpu_connector_edp_funcs, 1920 connector_type, 1921 ddc); 1922 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1923 drm_object_attach_property(&amdgpu_connector->base.base, 1924 dev->mode_config.scaling_mode_property, 1925 DRM_MODE_SCALE_FULLSCREEN); 1926 subpixel_order = SubPixelHorizontalRGB; 1927 connector->interlace_allowed = false; 1928 connector->doublescan_allowed = false; 1929 break; 1930 case DRM_MODE_CONNECTOR_LVDS: 1931 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1932 if (!amdgpu_dig_connector) 1933 goto failed; 1934 amdgpu_connector->con_priv = amdgpu_dig_connector; 1935 if (i2c_bus->valid) { 1936 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1937 if (!amdgpu_connector->ddc_bus) 1938 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1939 else 1940 ddc = &amdgpu_connector->ddc_bus->adapter; 1941 } 1942 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1943 &amdgpu_connector_lvds_funcs, 1944 connector_type, 1945 ddc); 1946 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1947 drm_object_attach_property(&amdgpu_connector->base.base, 1948 dev->mode_config.scaling_mode_property, 1949 DRM_MODE_SCALE_FULLSCREEN); 1950 subpixel_order = SubPixelHorizontalRGB; 1951 connector->interlace_allowed = false; 1952 connector->doublescan_allowed = false; 1953 break; 1954 } 1955 } 1956 1957 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1958 if (i2c_bus->valid) { 1959 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1960 DRM_CONNECTOR_POLL_DISCONNECT; 1961 } 1962 } else 1963 connector->polled = DRM_CONNECTOR_POLL_HPD; 1964 1965 connector->display_info.subpixel_order = subpixel_order; 1966 1967 if (has_aux) 1968 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1969 1970 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1971 connector_type == DRM_MODE_CONNECTOR_eDP) { 1972 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 1973 } 1974 1975 return; 1976 1977 failed: 1978 drm_connector_cleanup(connector); 1979 kfree(connector); 1980 } 1981