1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73 int saved_dpms = connector->dpms; 74 /* Only turn off the display if it's physically disconnected */ 75 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't try to start link training before we 79 * have the dpcd */ 80 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 return; 82 83 /* set it to OFF so that drm_helper_connector_dpms() 84 * won't return immediately since the current state 85 * is ON at this point. 86 */ 87 connector->dpms = DRM_MODE_DPMS_OFF; 88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89 } 90 connector->dpms = saved_dpms; 91 } 92 } 93 } 94 95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 96 { 97 struct drm_crtc *crtc = encoder->crtc; 98 99 if (crtc && crtc->enabled) { 100 drm_crtc_helper_set_mode(crtc, &crtc->mode, 101 crtc->x, crtc->y, crtc->primary->fb); 102 } 103 } 104 105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 106 { 107 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 108 struct amdgpu_connector_atom_dig *dig_connector; 109 int bpc = 8; 110 unsigned mode_clock, max_tmds_clock; 111 112 switch (connector->connector_type) { 113 case DRM_MODE_CONNECTOR_DVII: 114 case DRM_MODE_CONNECTOR_HDMIB: 115 if (amdgpu_connector->use_digital) { 116 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 117 if (connector->display_info.bpc) 118 bpc = connector->display_info.bpc; 119 } 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DVID: 123 case DRM_MODE_CONNECTOR_HDMIA: 124 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 125 if (connector->display_info.bpc) 126 bpc = connector->display_info.bpc; 127 } 128 break; 129 case DRM_MODE_CONNECTOR_DisplayPort: 130 dig_connector = amdgpu_connector->con_priv; 131 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 132 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 133 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 134 if (connector->display_info.bpc) 135 bpc = connector->display_info.bpc; 136 } 137 break; 138 case DRM_MODE_CONNECTOR_eDP: 139 case DRM_MODE_CONNECTOR_LVDS: 140 if (connector->display_info.bpc) 141 bpc = connector->display_info.bpc; 142 else { 143 const struct drm_connector_helper_funcs *connector_funcs = 144 connector->helper_private; 145 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 146 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 147 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 148 149 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 150 bpc = 6; 151 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 152 bpc = 8; 153 } 154 break; 155 } 156 157 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 158 /* 159 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 160 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 161 * 12 bpc is always supported on hdmi deep color sinks, as this is 162 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 163 */ 164 if (bpc > 12) { 165 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 166 connector->name, bpc); 167 bpc = 12; 168 } 169 170 /* Any defined maximum tmds clock limit we must not exceed? */ 171 if (connector->display_info.max_tmds_clock > 0) { 172 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 173 mode_clock = amdgpu_connector->pixelclock_for_modeset; 174 175 /* Maximum allowable input clock in kHz */ 176 max_tmds_clock = connector->display_info.max_tmds_clock; 177 178 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 179 connector->name, mode_clock, max_tmds_clock); 180 181 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 182 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 183 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 184 (mode_clock * 5/4 <= max_tmds_clock)) 185 bpc = 10; 186 else 187 bpc = 8; 188 189 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 190 connector->name, bpc); 191 } 192 193 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 194 bpc = 8; 195 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 196 connector->name, bpc); 197 } 198 } else if (bpc > 8) { 199 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 200 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 201 connector->name); 202 bpc = 8; 203 } 204 } 205 206 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 207 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 208 connector->name); 209 bpc = 8; 210 } 211 212 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 213 connector->name, connector->display_info.bpc, bpc); 214 215 return bpc; 216 } 217 218 static void 219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 220 enum drm_connector_status status) 221 { 222 struct drm_encoder *best_encoder = NULL; 223 struct drm_encoder *encoder = NULL; 224 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 225 bool connected; 226 int i; 227 228 best_encoder = connector_funcs->best_encoder(connector); 229 230 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 231 if (connector->encoder_ids[i] == 0) 232 break; 233 234 encoder = drm_encoder_find(connector->dev, NULL, 235 connector->encoder_ids[i]); 236 if (!encoder) 237 continue; 238 239 if ((encoder == best_encoder) && (status == connector_status_connected)) 240 connected = true; 241 else 242 connected = false; 243 244 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 245 246 } 247 } 248 249 static struct drm_encoder * 250 amdgpu_connector_find_encoder(struct drm_connector *connector, 251 int encoder_type) 252 { 253 struct drm_encoder *encoder; 254 int i; 255 256 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 257 if (connector->encoder_ids[i] == 0) 258 break; 259 encoder = drm_encoder_find(connector->dev, NULL, 260 connector->encoder_ids[i]); 261 if (!encoder) 262 continue; 263 264 if (encoder->encoder_type == encoder_type) 265 return encoder; 266 } 267 return NULL; 268 } 269 270 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 271 { 272 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 273 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 274 275 if (amdgpu_connector->edid) { 276 return amdgpu_connector->edid; 277 } else if (edid_blob) { 278 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 279 if (edid) 280 amdgpu_connector->edid = edid; 281 } 282 return amdgpu_connector->edid; 283 } 284 285 static struct edid * 286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 287 { 288 struct edid *edid; 289 290 if (adev->mode_info.bios_hardcoded_edid) { 291 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 292 if (edid) { 293 memcpy((unsigned char *)edid, 294 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 295 adev->mode_info.bios_hardcoded_edid_size); 296 return edid; 297 } 298 } 299 return NULL; 300 } 301 302 static void amdgpu_connector_get_edid(struct drm_connector *connector) 303 { 304 struct drm_device *dev = connector->dev; 305 struct amdgpu_device *adev = dev->dev_private; 306 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307 308 if (amdgpu_connector->edid) 309 return; 310 311 /* on hw with routers, select right port */ 312 if (amdgpu_connector->router.ddc_valid) 313 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 314 315 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 316 ENCODER_OBJECT_ID_NONE) && 317 amdgpu_connector->ddc_bus->has_aux) { 318 amdgpu_connector->edid = drm_get_edid(connector, 319 &amdgpu_connector->ddc_bus->aux.ddc); 320 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 321 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 322 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 323 324 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 325 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 326 amdgpu_connector->ddc_bus->has_aux) 327 amdgpu_connector->edid = drm_get_edid(connector, 328 &amdgpu_connector->ddc_bus->aux.ddc); 329 else if (amdgpu_connector->ddc_bus) 330 amdgpu_connector->edid = drm_get_edid(connector, 331 &amdgpu_connector->ddc_bus->adapter); 332 } else if (amdgpu_connector->ddc_bus) { 333 amdgpu_connector->edid = drm_get_edid(connector, 334 &amdgpu_connector->ddc_bus->adapter); 335 } 336 337 if (!amdgpu_connector->edid) { 338 /* some laptops provide a hardcoded edid in rom for LCDs */ 339 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 340 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 341 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 342 } 343 } 344 345 static void amdgpu_connector_free_edid(struct drm_connector *connector) 346 { 347 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 348 349 kfree(amdgpu_connector->edid); 350 amdgpu_connector->edid = NULL; 351 } 352 353 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 354 { 355 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 356 int ret; 357 358 if (amdgpu_connector->edid) { 359 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 360 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 361 drm_edid_to_eld(connector, amdgpu_connector->edid); 362 return ret; 363 } 364 drm_mode_connector_update_edid_property(connector, NULL); 365 return 0; 366 } 367 368 static struct drm_encoder * 369 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 370 { 371 int enc_id = connector->encoder_ids[0]; 372 373 /* pick the encoder ids */ 374 if (enc_id) 375 return drm_encoder_find(connector->dev, NULL, enc_id); 376 return NULL; 377 } 378 379 static void amdgpu_get_native_mode(struct drm_connector *connector) 380 { 381 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 382 struct amdgpu_encoder *amdgpu_encoder; 383 384 if (encoder == NULL) 385 return; 386 387 amdgpu_encoder = to_amdgpu_encoder(encoder); 388 389 if (!list_empty(&connector->probed_modes)) { 390 struct drm_display_mode *preferred_mode = 391 list_first_entry(&connector->probed_modes, 392 struct drm_display_mode, head); 393 394 amdgpu_encoder->native_mode = *preferred_mode; 395 } else { 396 amdgpu_encoder->native_mode.clock = 0; 397 } 398 } 399 400 static struct drm_display_mode * 401 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 402 { 403 struct drm_device *dev = encoder->dev; 404 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 405 struct drm_display_mode *mode = NULL; 406 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 407 408 if (native_mode->hdisplay != 0 && 409 native_mode->vdisplay != 0 && 410 native_mode->clock != 0) { 411 mode = drm_mode_duplicate(dev, native_mode); 412 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 413 drm_mode_set_name(mode); 414 415 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 416 } else if (native_mode->hdisplay != 0 && 417 native_mode->vdisplay != 0) { 418 /* mac laptops without an edid */ 419 /* Note that this is not necessarily the exact panel mode, 420 * but an approximation based on the cvt formula. For these 421 * systems we should ideally read the mode info out of the 422 * registers or add a mode table, but this works and is much 423 * simpler. 424 */ 425 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 426 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 427 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 428 } 429 return mode; 430 } 431 432 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 433 struct drm_connector *connector) 434 { 435 struct drm_device *dev = encoder->dev; 436 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 437 struct drm_display_mode *mode = NULL; 438 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 439 int i; 440 static const struct mode_size { 441 int w; 442 int h; 443 } common_modes[17] = { 444 { 640, 480}, 445 { 720, 480}, 446 { 800, 600}, 447 { 848, 480}, 448 {1024, 768}, 449 {1152, 768}, 450 {1280, 720}, 451 {1280, 800}, 452 {1280, 854}, 453 {1280, 960}, 454 {1280, 1024}, 455 {1440, 900}, 456 {1400, 1050}, 457 {1680, 1050}, 458 {1600, 1200}, 459 {1920, 1080}, 460 {1920, 1200} 461 }; 462 463 for (i = 0; i < 17; i++) { 464 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 465 if (common_modes[i].w > 1024 || 466 common_modes[i].h > 768) 467 continue; 468 } 469 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 470 if (common_modes[i].w > native_mode->hdisplay || 471 common_modes[i].h > native_mode->vdisplay || 472 (common_modes[i].w == native_mode->hdisplay && 473 common_modes[i].h == native_mode->vdisplay)) 474 continue; 475 } 476 if (common_modes[i].w < 320 || common_modes[i].h < 200) 477 continue; 478 479 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 480 drm_mode_probed_add(connector, mode); 481 } 482 } 483 484 static int amdgpu_connector_set_property(struct drm_connector *connector, 485 struct drm_property *property, 486 uint64_t val) 487 { 488 struct drm_device *dev = connector->dev; 489 struct amdgpu_device *adev = dev->dev_private; 490 struct drm_encoder *encoder; 491 struct amdgpu_encoder *amdgpu_encoder; 492 493 if (property == adev->mode_info.coherent_mode_property) { 494 struct amdgpu_encoder_atom_dig *dig; 495 bool new_coherent_mode; 496 497 /* need to find digital encoder on connector */ 498 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 499 if (!encoder) 500 return 0; 501 502 amdgpu_encoder = to_amdgpu_encoder(encoder); 503 504 if (!amdgpu_encoder->enc_priv) 505 return 0; 506 507 dig = amdgpu_encoder->enc_priv; 508 new_coherent_mode = val ? true : false; 509 if (dig->coherent_mode != new_coherent_mode) { 510 dig->coherent_mode = new_coherent_mode; 511 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 512 } 513 } 514 515 if (property == adev->mode_info.audio_property) { 516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 517 /* need to find digital encoder on connector */ 518 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 519 if (!encoder) 520 return 0; 521 522 amdgpu_encoder = to_amdgpu_encoder(encoder); 523 524 if (amdgpu_connector->audio != val) { 525 amdgpu_connector->audio = val; 526 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 527 } 528 } 529 530 if (property == adev->mode_info.dither_property) { 531 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 532 /* need to find digital encoder on connector */ 533 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 534 if (!encoder) 535 return 0; 536 537 amdgpu_encoder = to_amdgpu_encoder(encoder); 538 539 if (amdgpu_connector->dither != val) { 540 amdgpu_connector->dither = val; 541 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 542 } 543 } 544 545 if (property == adev->mode_info.underscan_property) { 546 /* need to find digital encoder on connector */ 547 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 548 if (!encoder) 549 return 0; 550 551 amdgpu_encoder = to_amdgpu_encoder(encoder); 552 553 if (amdgpu_encoder->underscan_type != val) { 554 amdgpu_encoder->underscan_type = val; 555 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 556 } 557 } 558 559 if (property == adev->mode_info.underscan_hborder_property) { 560 /* need to find digital encoder on connector */ 561 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 562 if (!encoder) 563 return 0; 564 565 amdgpu_encoder = to_amdgpu_encoder(encoder); 566 567 if (amdgpu_encoder->underscan_hborder != val) { 568 amdgpu_encoder->underscan_hborder = val; 569 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 570 } 571 } 572 573 if (property == adev->mode_info.underscan_vborder_property) { 574 /* need to find digital encoder on connector */ 575 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 576 if (!encoder) 577 return 0; 578 579 amdgpu_encoder = to_amdgpu_encoder(encoder); 580 581 if (amdgpu_encoder->underscan_vborder != val) { 582 amdgpu_encoder->underscan_vborder = val; 583 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 584 } 585 } 586 587 if (property == adev->mode_info.load_detect_property) { 588 struct amdgpu_connector *amdgpu_connector = 589 to_amdgpu_connector(connector); 590 591 if (val == 0) 592 amdgpu_connector->dac_load_detect = false; 593 else 594 amdgpu_connector->dac_load_detect = true; 595 } 596 597 if (property == dev->mode_config.scaling_mode_property) { 598 enum amdgpu_rmx_type rmx_type; 599 600 if (connector->encoder) { 601 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 602 } else { 603 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 604 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 605 } 606 607 switch (val) { 608 default: 609 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 610 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 611 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 612 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 613 } 614 if (amdgpu_encoder->rmx_type == rmx_type) 615 return 0; 616 617 if ((rmx_type != DRM_MODE_SCALE_NONE) && 618 (amdgpu_encoder->native_mode.clock == 0)) 619 return 0; 620 621 amdgpu_encoder->rmx_type = rmx_type; 622 623 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 624 } 625 626 return 0; 627 } 628 629 static void 630 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 631 struct drm_connector *connector) 632 { 633 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 634 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 635 struct drm_display_mode *t, *mode; 636 637 /* If the EDID preferred mode doesn't match the native mode, use it */ 638 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 639 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 640 if (mode->hdisplay != native_mode->hdisplay || 641 mode->vdisplay != native_mode->vdisplay) 642 memcpy(native_mode, mode, sizeof(*mode)); 643 } 644 } 645 646 /* Try to get native mode details from EDID if necessary */ 647 if (!native_mode->clock) { 648 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 649 if (mode->hdisplay == native_mode->hdisplay && 650 mode->vdisplay == native_mode->vdisplay) { 651 *native_mode = *mode; 652 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 653 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 654 break; 655 } 656 } 657 } 658 659 if (!native_mode->clock) { 660 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 661 amdgpu_encoder->rmx_type = RMX_OFF; 662 } 663 } 664 665 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 666 { 667 struct drm_encoder *encoder; 668 int ret = 0; 669 struct drm_display_mode *mode; 670 671 amdgpu_connector_get_edid(connector); 672 ret = amdgpu_connector_ddc_get_modes(connector); 673 if (ret > 0) { 674 encoder = amdgpu_connector_best_single_encoder(connector); 675 if (encoder) { 676 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 677 /* add scaled modes */ 678 amdgpu_connector_add_common_modes(encoder, connector); 679 } 680 return ret; 681 } 682 683 encoder = amdgpu_connector_best_single_encoder(connector); 684 if (!encoder) 685 return 0; 686 687 /* we have no EDID modes */ 688 mode = amdgpu_connector_lcd_native_mode(encoder); 689 if (mode) { 690 ret = 1; 691 drm_mode_probed_add(connector, mode); 692 /* add the width/height from vbios tables if available */ 693 connector->display_info.width_mm = mode->width_mm; 694 connector->display_info.height_mm = mode->height_mm; 695 /* add scaled modes */ 696 amdgpu_connector_add_common_modes(encoder, connector); 697 } 698 699 return ret; 700 } 701 702 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 703 struct drm_display_mode *mode) 704 { 705 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 706 707 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 708 return MODE_PANEL; 709 710 if (encoder) { 711 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 712 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 713 714 /* AVIVO hardware supports downscaling modes larger than the panel 715 * to the panel size, but I'm not sure this is desirable. 716 */ 717 if ((mode->hdisplay > native_mode->hdisplay) || 718 (mode->vdisplay > native_mode->vdisplay)) 719 return MODE_PANEL; 720 721 /* if scaling is disabled, block non-native modes */ 722 if (amdgpu_encoder->rmx_type == RMX_OFF) { 723 if ((mode->hdisplay != native_mode->hdisplay) || 724 (mode->vdisplay != native_mode->vdisplay)) 725 return MODE_PANEL; 726 } 727 } 728 729 return MODE_OK; 730 } 731 732 static enum drm_connector_status 733 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 734 { 735 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 736 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 737 enum drm_connector_status ret = connector_status_disconnected; 738 int r; 739 740 r = pm_runtime_get_sync(connector->dev->dev); 741 if (r < 0) 742 return connector_status_disconnected; 743 744 if (encoder) { 745 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 746 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 747 748 /* check if panel is valid */ 749 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 750 ret = connector_status_connected; 751 752 } 753 754 /* check for edid as well */ 755 amdgpu_connector_get_edid(connector); 756 if (amdgpu_connector->edid) 757 ret = connector_status_connected; 758 /* check acpi lid status ??? */ 759 760 amdgpu_connector_update_scratch_regs(connector, ret); 761 pm_runtime_mark_last_busy(connector->dev->dev); 762 pm_runtime_put_autosuspend(connector->dev->dev); 763 return ret; 764 } 765 766 static void amdgpu_connector_unregister(struct drm_connector *connector) 767 { 768 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 769 770 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 771 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 772 amdgpu_connector->ddc_bus->has_aux = false; 773 } 774 } 775 776 static void amdgpu_connector_destroy(struct drm_connector *connector) 777 { 778 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 779 780 amdgpu_connector_free_edid(connector); 781 kfree(amdgpu_connector->con_priv); 782 drm_connector_unregister(connector); 783 drm_connector_cleanup(connector); 784 kfree(connector); 785 } 786 787 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 788 struct drm_property *property, 789 uint64_t value) 790 { 791 struct drm_device *dev = connector->dev; 792 struct amdgpu_encoder *amdgpu_encoder; 793 enum amdgpu_rmx_type rmx_type; 794 795 DRM_DEBUG_KMS("\n"); 796 if (property != dev->mode_config.scaling_mode_property) 797 return 0; 798 799 if (connector->encoder) 800 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 801 else { 802 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 803 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 804 } 805 806 switch (value) { 807 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 808 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 809 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 810 default: 811 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 812 } 813 if (amdgpu_encoder->rmx_type == rmx_type) 814 return 0; 815 816 amdgpu_encoder->rmx_type = rmx_type; 817 818 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 819 return 0; 820 } 821 822 823 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 824 .get_modes = amdgpu_connector_lvds_get_modes, 825 .mode_valid = amdgpu_connector_lvds_mode_valid, 826 .best_encoder = amdgpu_connector_best_single_encoder, 827 }; 828 829 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 830 .dpms = drm_helper_connector_dpms, 831 .detect = amdgpu_connector_lvds_detect, 832 .fill_modes = drm_helper_probe_single_connector_modes, 833 .early_unregister = amdgpu_connector_unregister, 834 .destroy = amdgpu_connector_destroy, 835 .set_property = amdgpu_connector_set_lcd_property, 836 }; 837 838 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 839 { 840 int ret; 841 842 amdgpu_connector_get_edid(connector); 843 ret = amdgpu_connector_ddc_get_modes(connector); 844 845 return ret; 846 } 847 848 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 849 struct drm_display_mode *mode) 850 { 851 struct drm_device *dev = connector->dev; 852 struct amdgpu_device *adev = dev->dev_private; 853 854 /* XXX check mode bandwidth */ 855 856 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 857 return MODE_CLOCK_HIGH; 858 859 return MODE_OK; 860 } 861 862 static enum drm_connector_status 863 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 864 { 865 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 866 struct drm_encoder *encoder; 867 const struct drm_encoder_helper_funcs *encoder_funcs; 868 bool dret = false; 869 enum drm_connector_status ret = connector_status_disconnected; 870 int r; 871 872 r = pm_runtime_get_sync(connector->dev->dev); 873 if (r < 0) 874 return connector_status_disconnected; 875 876 encoder = amdgpu_connector_best_single_encoder(connector); 877 if (!encoder) 878 ret = connector_status_disconnected; 879 880 if (amdgpu_connector->ddc_bus) 881 dret = amdgpu_ddc_probe(amdgpu_connector, false); 882 if (dret) { 883 amdgpu_connector->detected_by_load = false; 884 amdgpu_connector_free_edid(connector); 885 amdgpu_connector_get_edid(connector); 886 887 if (!amdgpu_connector->edid) { 888 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 889 connector->name); 890 ret = connector_status_connected; 891 } else { 892 amdgpu_connector->use_digital = 893 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 894 895 /* some oems have boards with separate digital and analog connectors 896 * with a shared ddc line (often vga + hdmi) 897 */ 898 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 899 amdgpu_connector_free_edid(connector); 900 ret = connector_status_disconnected; 901 } else { 902 ret = connector_status_connected; 903 } 904 } 905 } else { 906 907 /* if we aren't forcing don't do destructive polling */ 908 if (!force) { 909 /* only return the previous status if we last 910 * detected a monitor via load. 911 */ 912 if (amdgpu_connector->detected_by_load) 913 ret = connector->status; 914 goto out; 915 } 916 917 if (amdgpu_connector->dac_load_detect && encoder) { 918 encoder_funcs = encoder->helper_private; 919 ret = encoder_funcs->detect(encoder, connector); 920 if (ret != connector_status_disconnected) 921 amdgpu_connector->detected_by_load = true; 922 } 923 } 924 925 amdgpu_connector_update_scratch_regs(connector, ret); 926 927 out: 928 pm_runtime_mark_last_busy(connector->dev->dev); 929 pm_runtime_put_autosuspend(connector->dev->dev); 930 931 return ret; 932 } 933 934 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 935 .get_modes = amdgpu_connector_vga_get_modes, 936 .mode_valid = amdgpu_connector_vga_mode_valid, 937 .best_encoder = amdgpu_connector_best_single_encoder, 938 }; 939 940 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 941 .dpms = drm_helper_connector_dpms, 942 .detect = amdgpu_connector_vga_detect, 943 .fill_modes = drm_helper_probe_single_connector_modes, 944 .early_unregister = amdgpu_connector_unregister, 945 .destroy = amdgpu_connector_destroy, 946 .set_property = amdgpu_connector_set_property, 947 }; 948 949 static bool 950 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 951 { 952 struct drm_device *dev = connector->dev; 953 struct amdgpu_device *adev = dev->dev_private; 954 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 955 enum drm_connector_status status; 956 957 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 958 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 959 status = connector_status_connected; 960 else 961 status = connector_status_disconnected; 962 if (connector->status == status) 963 return true; 964 } 965 966 return false; 967 } 968 969 /* 970 * DVI is complicated 971 * Do a DDC probe, if DDC probe passes, get the full EDID so 972 * we can do analog/digital monitor detection at this point. 973 * If the monitor is an analog monitor or we got no DDC, 974 * we need to find the DAC encoder object for this connector. 975 * If we got no DDC, we do load detection on the DAC encoder object. 976 * If we got analog DDC or load detection passes on the DAC encoder 977 * we have to check if this analog encoder is shared with anyone else (TV) 978 * if its shared we have to set the other connector to disconnected. 979 */ 980 static enum drm_connector_status 981 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 982 { 983 struct drm_device *dev = connector->dev; 984 struct amdgpu_device *adev = dev->dev_private; 985 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 986 struct drm_encoder *encoder = NULL; 987 const struct drm_encoder_helper_funcs *encoder_funcs; 988 int i, r; 989 enum drm_connector_status ret = connector_status_disconnected; 990 bool dret = false, broken_edid = false; 991 992 r = pm_runtime_get_sync(connector->dev->dev); 993 if (r < 0) 994 return connector_status_disconnected; 995 996 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 997 ret = connector->status; 998 goto exit; 999 } 1000 1001 if (amdgpu_connector->ddc_bus) 1002 dret = amdgpu_ddc_probe(amdgpu_connector, false); 1003 if (dret) { 1004 amdgpu_connector->detected_by_load = false; 1005 amdgpu_connector_free_edid(connector); 1006 amdgpu_connector_get_edid(connector); 1007 1008 if (!amdgpu_connector->edid) { 1009 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1010 connector->name); 1011 ret = connector_status_connected; 1012 broken_edid = true; /* defer use_digital to later */ 1013 } else { 1014 amdgpu_connector->use_digital = 1015 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1016 1017 /* some oems have boards with separate digital and analog connectors 1018 * with a shared ddc line (often vga + hdmi) 1019 */ 1020 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1021 amdgpu_connector_free_edid(connector); 1022 ret = connector_status_disconnected; 1023 } else { 1024 ret = connector_status_connected; 1025 } 1026 1027 /* This gets complicated. We have boards with VGA + HDMI with a 1028 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1029 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1030 * you don't really know what's connected to which port as both are digital. 1031 */ 1032 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1033 struct drm_connector *list_connector; 1034 struct amdgpu_connector *list_amdgpu_connector; 1035 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1036 if (connector == list_connector) 1037 continue; 1038 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1039 if (list_amdgpu_connector->shared_ddc && 1040 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1041 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1042 /* cases where both connectors are digital */ 1043 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1044 /* hpd is our only option in this case */ 1045 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1046 amdgpu_connector_free_edid(connector); 1047 ret = connector_status_disconnected; 1048 } 1049 } 1050 } 1051 } 1052 } 1053 } 1054 } 1055 1056 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1057 goto out; 1058 1059 /* DVI-D and HDMI-A are digital only */ 1060 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1061 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1062 goto out; 1063 1064 /* if we aren't forcing don't do destructive polling */ 1065 if (!force) { 1066 /* only return the previous status if we last 1067 * detected a monitor via load. 1068 */ 1069 if (amdgpu_connector->detected_by_load) 1070 ret = connector->status; 1071 goto out; 1072 } 1073 1074 /* find analog encoder */ 1075 if (amdgpu_connector->dac_load_detect) { 1076 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1077 if (connector->encoder_ids[i] == 0) 1078 break; 1079 1080 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]); 1081 if (!encoder) 1082 continue; 1083 1084 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1085 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1086 continue; 1087 1088 encoder_funcs = encoder->helper_private; 1089 if (encoder_funcs->detect) { 1090 if (!broken_edid) { 1091 if (ret != connector_status_connected) { 1092 /* deal with analog monitors without DDC */ 1093 ret = encoder_funcs->detect(encoder, connector); 1094 if (ret == connector_status_connected) { 1095 amdgpu_connector->use_digital = false; 1096 } 1097 if (ret != connector_status_disconnected) 1098 amdgpu_connector->detected_by_load = true; 1099 } 1100 } else { 1101 enum drm_connector_status lret; 1102 /* assume digital unless load detected otherwise */ 1103 amdgpu_connector->use_digital = true; 1104 lret = encoder_funcs->detect(encoder, connector); 1105 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1106 if (lret == connector_status_connected) 1107 amdgpu_connector->use_digital = false; 1108 } 1109 break; 1110 } 1111 } 1112 } 1113 1114 out: 1115 /* updated in get modes as well since we need to know if it's analog or digital */ 1116 amdgpu_connector_update_scratch_regs(connector, ret); 1117 1118 exit: 1119 pm_runtime_mark_last_busy(connector->dev->dev); 1120 pm_runtime_put_autosuspend(connector->dev->dev); 1121 1122 return ret; 1123 } 1124 1125 /* okay need to be smart in here about which encoder to pick */ 1126 static struct drm_encoder * 1127 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1128 { 1129 int enc_id = connector->encoder_ids[0]; 1130 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1131 struct drm_encoder *encoder; 1132 int i; 1133 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1134 if (connector->encoder_ids[i] == 0) 1135 break; 1136 1137 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]); 1138 if (!encoder) 1139 continue; 1140 1141 if (amdgpu_connector->use_digital == true) { 1142 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1143 return encoder; 1144 } else { 1145 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1146 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1147 return encoder; 1148 } 1149 } 1150 1151 /* see if we have a default encoder TODO */ 1152 1153 /* then check use digitial */ 1154 /* pick the first one */ 1155 if (enc_id) 1156 return drm_encoder_find(connector->dev, NULL, enc_id); 1157 return NULL; 1158 } 1159 1160 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1161 { 1162 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1163 if (connector->force == DRM_FORCE_ON) 1164 amdgpu_connector->use_digital = false; 1165 if (connector->force == DRM_FORCE_ON_DIGITAL) 1166 amdgpu_connector->use_digital = true; 1167 } 1168 1169 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1170 struct drm_display_mode *mode) 1171 { 1172 struct drm_device *dev = connector->dev; 1173 struct amdgpu_device *adev = dev->dev_private; 1174 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1175 1176 /* XXX check mode bandwidth */ 1177 1178 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1179 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1180 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1181 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1182 return MODE_OK; 1183 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1184 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1185 if (mode->clock > 340000) 1186 return MODE_CLOCK_HIGH; 1187 else 1188 return MODE_OK; 1189 } else { 1190 return MODE_CLOCK_HIGH; 1191 } 1192 } 1193 1194 /* check against the max pixel clock */ 1195 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1196 return MODE_CLOCK_HIGH; 1197 1198 return MODE_OK; 1199 } 1200 1201 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1202 .get_modes = amdgpu_connector_vga_get_modes, 1203 .mode_valid = amdgpu_connector_dvi_mode_valid, 1204 .best_encoder = amdgpu_connector_dvi_encoder, 1205 }; 1206 1207 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1208 .dpms = drm_helper_connector_dpms, 1209 .detect = amdgpu_connector_dvi_detect, 1210 .fill_modes = drm_helper_probe_single_connector_modes, 1211 .set_property = amdgpu_connector_set_property, 1212 .early_unregister = amdgpu_connector_unregister, 1213 .destroy = amdgpu_connector_destroy, 1214 .force = amdgpu_connector_dvi_force, 1215 }; 1216 1217 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1218 { 1219 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1220 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1221 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1222 int ret; 1223 1224 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1225 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1226 struct drm_display_mode *mode; 1227 1228 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1229 if (!amdgpu_dig_connector->edp_on) 1230 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1231 ATOM_TRANSMITTER_ACTION_POWER_ON); 1232 amdgpu_connector_get_edid(connector); 1233 ret = amdgpu_connector_ddc_get_modes(connector); 1234 if (!amdgpu_dig_connector->edp_on) 1235 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1236 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1237 } else { 1238 /* need to setup ddc on the bridge */ 1239 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1240 ENCODER_OBJECT_ID_NONE) { 1241 if (encoder) 1242 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1243 } 1244 amdgpu_connector_get_edid(connector); 1245 ret = amdgpu_connector_ddc_get_modes(connector); 1246 } 1247 1248 if (ret > 0) { 1249 if (encoder) { 1250 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1251 /* add scaled modes */ 1252 amdgpu_connector_add_common_modes(encoder, connector); 1253 } 1254 return ret; 1255 } 1256 1257 if (!encoder) 1258 return 0; 1259 1260 /* we have no EDID modes */ 1261 mode = amdgpu_connector_lcd_native_mode(encoder); 1262 if (mode) { 1263 ret = 1; 1264 drm_mode_probed_add(connector, mode); 1265 /* add the width/height from vbios tables if available */ 1266 connector->display_info.width_mm = mode->width_mm; 1267 connector->display_info.height_mm = mode->height_mm; 1268 /* add scaled modes */ 1269 amdgpu_connector_add_common_modes(encoder, connector); 1270 } 1271 } else { 1272 /* need to setup ddc on the bridge */ 1273 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1274 ENCODER_OBJECT_ID_NONE) { 1275 if (encoder) 1276 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1277 } 1278 amdgpu_connector_get_edid(connector); 1279 ret = amdgpu_connector_ddc_get_modes(connector); 1280 1281 amdgpu_get_native_mode(connector); 1282 } 1283 1284 return ret; 1285 } 1286 1287 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1288 { 1289 struct drm_encoder *encoder; 1290 struct amdgpu_encoder *amdgpu_encoder; 1291 int i; 1292 1293 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1294 if (connector->encoder_ids[i] == 0) 1295 break; 1296 1297 encoder = drm_encoder_find(connector->dev, NULL, 1298 connector->encoder_ids[i]); 1299 if (!encoder) 1300 continue; 1301 1302 amdgpu_encoder = to_amdgpu_encoder(encoder); 1303 1304 switch (amdgpu_encoder->encoder_id) { 1305 case ENCODER_OBJECT_ID_TRAVIS: 1306 case ENCODER_OBJECT_ID_NUTMEG: 1307 return amdgpu_encoder->encoder_id; 1308 default: 1309 break; 1310 } 1311 } 1312 1313 return ENCODER_OBJECT_ID_NONE; 1314 } 1315 1316 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1317 { 1318 struct drm_encoder *encoder; 1319 struct amdgpu_encoder *amdgpu_encoder; 1320 int i; 1321 bool found = false; 1322 1323 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1324 if (connector->encoder_ids[i] == 0) 1325 break; 1326 encoder = drm_encoder_find(connector->dev, NULL, 1327 connector->encoder_ids[i]); 1328 if (!encoder) 1329 continue; 1330 1331 amdgpu_encoder = to_amdgpu_encoder(encoder); 1332 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1333 found = true; 1334 } 1335 1336 return found; 1337 } 1338 1339 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1340 { 1341 struct drm_device *dev = connector->dev; 1342 struct amdgpu_device *adev = dev->dev_private; 1343 1344 if ((adev->clock.default_dispclk >= 53900) && 1345 amdgpu_connector_encoder_is_hbr2(connector)) { 1346 return true; 1347 } 1348 1349 return false; 1350 } 1351 1352 static enum drm_connector_status 1353 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1354 { 1355 struct drm_device *dev = connector->dev; 1356 struct amdgpu_device *adev = dev->dev_private; 1357 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1358 enum drm_connector_status ret = connector_status_disconnected; 1359 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1360 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1361 int r; 1362 1363 r = pm_runtime_get_sync(connector->dev->dev); 1364 if (r < 0) 1365 return connector_status_disconnected; 1366 1367 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1368 ret = connector->status; 1369 goto out; 1370 } 1371 1372 amdgpu_connector_free_edid(connector); 1373 1374 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1375 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1376 if (encoder) { 1377 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1378 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1379 1380 /* check if panel is valid */ 1381 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1382 ret = connector_status_connected; 1383 } 1384 /* eDP is always DP */ 1385 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1386 if (!amdgpu_dig_connector->edp_on) 1387 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1388 ATOM_TRANSMITTER_ACTION_POWER_ON); 1389 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1390 ret = connector_status_connected; 1391 if (!amdgpu_dig_connector->edp_on) 1392 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1393 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1394 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1395 ENCODER_OBJECT_ID_NONE) { 1396 /* DP bridges are always DP */ 1397 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1398 /* get the DPCD from the bridge */ 1399 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1400 1401 if (encoder) { 1402 /* setup ddc on the bridge */ 1403 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1404 /* bridge chips are always aux */ 1405 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1406 ret = connector_status_connected; 1407 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1408 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1409 ret = encoder_funcs->detect(encoder, connector); 1410 } 1411 } 1412 } else { 1413 amdgpu_dig_connector->dp_sink_type = 1414 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1415 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1416 ret = connector_status_connected; 1417 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1418 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1419 } else { 1420 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1421 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1422 ret = connector_status_connected; 1423 } else { 1424 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1425 if (amdgpu_ddc_probe(amdgpu_connector, false)) 1426 ret = connector_status_connected; 1427 } 1428 } 1429 } 1430 1431 amdgpu_connector_update_scratch_regs(connector, ret); 1432 out: 1433 pm_runtime_mark_last_busy(connector->dev->dev); 1434 pm_runtime_put_autosuspend(connector->dev->dev); 1435 1436 return ret; 1437 } 1438 1439 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1440 struct drm_display_mode *mode) 1441 { 1442 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1443 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1444 1445 /* XXX check mode bandwidth */ 1446 1447 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1448 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1449 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1450 1451 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1452 return MODE_PANEL; 1453 1454 if (encoder) { 1455 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1456 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1457 1458 /* AVIVO hardware supports downscaling modes larger than the panel 1459 * to the panel size, but I'm not sure this is desirable. 1460 */ 1461 if ((mode->hdisplay > native_mode->hdisplay) || 1462 (mode->vdisplay > native_mode->vdisplay)) 1463 return MODE_PANEL; 1464 1465 /* if scaling is disabled, block non-native modes */ 1466 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1467 if ((mode->hdisplay != native_mode->hdisplay) || 1468 (mode->vdisplay != native_mode->vdisplay)) 1469 return MODE_PANEL; 1470 } 1471 } 1472 return MODE_OK; 1473 } else { 1474 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1475 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1476 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1477 } else { 1478 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1479 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1480 if (mode->clock > 340000) 1481 return MODE_CLOCK_HIGH; 1482 } else { 1483 if (mode->clock > 165000) 1484 return MODE_CLOCK_HIGH; 1485 } 1486 } 1487 } 1488 1489 return MODE_OK; 1490 } 1491 1492 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1493 .get_modes = amdgpu_connector_dp_get_modes, 1494 .mode_valid = amdgpu_connector_dp_mode_valid, 1495 .best_encoder = amdgpu_connector_dvi_encoder, 1496 }; 1497 1498 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1499 .dpms = drm_helper_connector_dpms, 1500 .detect = amdgpu_connector_dp_detect, 1501 .fill_modes = drm_helper_probe_single_connector_modes, 1502 .set_property = amdgpu_connector_set_property, 1503 .early_unregister = amdgpu_connector_unregister, 1504 .destroy = amdgpu_connector_destroy, 1505 .force = amdgpu_connector_dvi_force, 1506 }; 1507 1508 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1509 .dpms = drm_helper_connector_dpms, 1510 .detect = amdgpu_connector_dp_detect, 1511 .fill_modes = drm_helper_probe_single_connector_modes, 1512 .set_property = amdgpu_connector_set_lcd_property, 1513 .early_unregister = amdgpu_connector_unregister, 1514 .destroy = amdgpu_connector_destroy, 1515 .force = amdgpu_connector_dvi_force, 1516 }; 1517 1518 void 1519 amdgpu_connector_add(struct amdgpu_device *adev, 1520 uint32_t connector_id, 1521 uint32_t supported_device, 1522 int connector_type, 1523 struct amdgpu_i2c_bus_rec *i2c_bus, 1524 uint16_t connector_object_id, 1525 struct amdgpu_hpd *hpd, 1526 struct amdgpu_router *router) 1527 { 1528 struct drm_device *dev = adev->ddev; 1529 struct drm_connector *connector; 1530 struct amdgpu_connector *amdgpu_connector; 1531 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1532 struct drm_encoder *encoder; 1533 struct amdgpu_encoder *amdgpu_encoder; 1534 uint32_t subpixel_order = SubPixelNone; 1535 bool shared_ddc = false; 1536 bool is_dp_bridge = false; 1537 bool has_aux = false; 1538 1539 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1540 return; 1541 1542 /* see if we already added it */ 1543 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1544 amdgpu_connector = to_amdgpu_connector(connector); 1545 if (amdgpu_connector->connector_id == connector_id) { 1546 amdgpu_connector->devices |= supported_device; 1547 return; 1548 } 1549 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1550 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1551 amdgpu_connector->shared_ddc = true; 1552 shared_ddc = true; 1553 } 1554 if (amdgpu_connector->router_bus && router->ddc_valid && 1555 (amdgpu_connector->router.router_id == router->router_id)) { 1556 amdgpu_connector->shared_ddc = false; 1557 shared_ddc = false; 1558 } 1559 } 1560 } 1561 1562 /* check if it's a dp bridge */ 1563 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1564 amdgpu_encoder = to_amdgpu_encoder(encoder); 1565 if (amdgpu_encoder->devices & supported_device) { 1566 switch (amdgpu_encoder->encoder_id) { 1567 case ENCODER_OBJECT_ID_TRAVIS: 1568 case ENCODER_OBJECT_ID_NUTMEG: 1569 is_dp_bridge = true; 1570 break; 1571 default: 1572 break; 1573 } 1574 } 1575 } 1576 1577 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1578 if (!amdgpu_connector) 1579 return; 1580 1581 connector = &amdgpu_connector->base; 1582 1583 amdgpu_connector->connector_id = connector_id; 1584 amdgpu_connector->devices = supported_device; 1585 amdgpu_connector->shared_ddc = shared_ddc; 1586 amdgpu_connector->connector_object_id = connector_object_id; 1587 amdgpu_connector->hpd = *hpd; 1588 1589 amdgpu_connector->router = *router; 1590 if (router->ddc_valid || router->cd_valid) { 1591 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1592 if (!amdgpu_connector->router_bus) 1593 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1594 } 1595 1596 if (is_dp_bridge) { 1597 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1598 if (!amdgpu_dig_connector) 1599 goto failed; 1600 amdgpu_connector->con_priv = amdgpu_dig_connector; 1601 if (i2c_bus->valid) { 1602 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1603 if (amdgpu_connector->ddc_bus) 1604 has_aux = true; 1605 else 1606 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1607 } 1608 switch (connector_type) { 1609 case DRM_MODE_CONNECTOR_VGA: 1610 case DRM_MODE_CONNECTOR_DVIA: 1611 default: 1612 drm_connector_init(dev, &amdgpu_connector->base, 1613 &amdgpu_connector_dp_funcs, connector_type); 1614 drm_connector_helper_add(&amdgpu_connector->base, 1615 &amdgpu_connector_dp_helper_funcs); 1616 connector->interlace_allowed = true; 1617 connector->doublescan_allowed = true; 1618 amdgpu_connector->dac_load_detect = true; 1619 drm_object_attach_property(&amdgpu_connector->base.base, 1620 adev->mode_info.load_detect_property, 1621 1); 1622 drm_object_attach_property(&amdgpu_connector->base.base, 1623 dev->mode_config.scaling_mode_property, 1624 DRM_MODE_SCALE_NONE); 1625 break; 1626 case DRM_MODE_CONNECTOR_DVII: 1627 case DRM_MODE_CONNECTOR_DVID: 1628 case DRM_MODE_CONNECTOR_HDMIA: 1629 case DRM_MODE_CONNECTOR_HDMIB: 1630 case DRM_MODE_CONNECTOR_DisplayPort: 1631 drm_connector_init(dev, &amdgpu_connector->base, 1632 &amdgpu_connector_dp_funcs, connector_type); 1633 drm_connector_helper_add(&amdgpu_connector->base, 1634 &amdgpu_connector_dp_helper_funcs); 1635 drm_object_attach_property(&amdgpu_connector->base.base, 1636 adev->mode_info.underscan_property, 1637 UNDERSCAN_OFF); 1638 drm_object_attach_property(&amdgpu_connector->base.base, 1639 adev->mode_info.underscan_hborder_property, 1640 0); 1641 drm_object_attach_property(&amdgpu_connector->base.base, 1642 adev->mode_info.underscan_vborder_property, 1643 0); 1644 1645 drm_object_attach_property(&amdgpu_connector->base.base, 1646 dev->mode_config.scaling_mode_property, 1647 DRM_MODE_SCALE_NONE); 1648 1649 drm_object_attach_property(&amdgpu_connector->base.base, 1650 adev->mode_info.dither_property, 1651 AMDGPU_FMT_DITHER_DISABLE); 1652 1653 if (amdgpu_audio != 0) 1654 drm_object_attach_property(&amdgpu_connector->base.base, 1655 adev->mode_info.audio_property, 1656 AMDGPU_AUDIO_AUTO); 1657 1658 subpixel_order = SubPixelHorizontalRGB; 1659 connector->interlace_allowed = true; 1660 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1661 connector->doublescan_allowed = true; 1662 else 1663 connector->doublescan_allowed = false; 1664 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1665 amdgpu_connector->dac_load_detect = true; 1666 drm_object_attach_property(&amdgpu_connector->base.base, 1667 adev->mode_info.load_detect_property, 1668 1); 1669 } 1670 break; 1671 case DRM_MODE_CONNECTOR_LVDS: 1672 case DRM_MODE_CONNECTOR_eDP: 1673 drm_connector_init(dev, &amdgpu_connector->base, 1674 &amdgpu_connector_edp_funcs, connector_type); 1675 drm_connector_helper_add(&amdgpu_connector->base, 1676 &amdgpu_connector_dp_helper_funcs); 1677 drm_object_attach_property(&amdgpu_connector->base.base, 1678 dev->mode_config.scaling_mode_property, 1679 DRM_MODE_SCALE_FULLSCREEN); 1680 subpixel_order = SubPixelHorizontalRGB; 1681 connector->interlace_allowed = false; 1682 connector->doublescan_allowed = false; 1683 break; 1684 } 1685 } else { 1686 switch (connector_type) { 1687 case DRM_MODE_CONNECTOR_VGA: 1688 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1689 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1690 if (i2c_bus->valid) { 1691 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1692 if (!amdgpu_connector->ddc_bus) 1693 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1694 } 1695 amdgpu_connector->dac_load_detect = true; 1696 drm_object_attach_property(&amdgpu_connector->base.base, 1697 adev->mode_info.load_detect_property, 1698 1); 1699 drm_object_attach_property(&amdgpu_connector->base.base, 1700 dev->mode_config.scaling_mode_property, 1701 DRM_MODE_SCALE_NONE); 1702 /* no HPD on analog connectors */ 1703 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1704 connector->interlace_allowed = true; 1705 connector->doublescan_allowed = true; 1706 break; 1707 case DRM_MODE_CONNECTOR_DVIA: 1708 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1709 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1710 if (i2c_bus->valid) { 1711 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1712 if (!amdgpu_connector->ddc_bus) 1713 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1714 } 1715 amdgpu_connector->dac_load_detect = true; 1716 drm_object_attach_property(&amdgpu_connector->base.base, 1717 adev->mode_info.load_detect_property, 1718 1); 1719 drm_object_attach_property(&amdgpu_connector->base.base, 1720 dev->mode_config.scaling_mode_property, 1721 DRM_MODE_SCALE_NONE); 1722 /* no HPD on analog connectors */ 1723 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1724 connector->interlace_allowed = true; 1725 connector->doublescan_allowed = true; 1726 break; 1727 case DRM_MODE_CONNECTOR_DVII: 1728 case DRM_MODE_CONNECTOR_DVID: 1729 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1730 if (!amdgpu_dig_connector) 1731 goto failed; 1732 amdgpu_connector->con_priv = amdgpu_dig_connector; 1733 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1734 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1735 if (i2c_bus->valid) { 1736 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1737 if (!amdgpu_connector->ddc_bus) 1738 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1739 } 1740 subpixel_order = SubPixelHorizontalRGB; 1741 drm_object_attach_property(&amdgpu_connector->base.base, 1742 adev->mode_info.coherent_mode_property, 1743 1); 1744 drm_object_attach_property(&amdgpu_connector->base.base, 1745 adev->mode_info.underscan_property, 1746 UNDERSCAN_OFF); 1747 drm_object_attach_property(&amdgpu_connector->base.base, 1748 adev->mode_info.underscan_hborder_property, 1749 0); 1750 drm_object_attach_property(&amdgpu_connector->base.base, 1751 adev->mode_info.underscan_vborder_property, 1752 0); 1753 drm_object_attach_property(&amdgpu_connector->base.base, 1754 dev->mode_config.scaling_mode_property, 1755 DRM_MODE_SCALE_NONE); 1756 1757 if (amdgpu_audio != 0) { 1758 drm_object_attach_property(&amdgpu_connector->base.base, 1759 adev->mode_info.audio_property, 1760 AMDGPU_AUDIO_AUTO); 1761 } 1762 drm_object_attach_property(&amdgpu_connector->base.base, 1763 adev->mode_info.dither_property, 1764 AMDGPU_FMT_DITHER_DISABLE); 1765 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1766 amdgpu_connector->dac_load_detect = true; 1767 drm_object_attach_property(&amdgpu_connector->base.base, 1768 adev->mode_info.load_detect_property, 1769 1); 1770 } 1771 connector->interlace_allowed = true; 1772 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1773 connector->doublescan_allowed = true; 1774 else 1775 connector->doublescan_allowed = false; 1776 break; 1777 case DRM_MODE_CONNECTOR_HDMIA: 1778 case DRM_MODE_CONNECTOR_HDMIB: 1779 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1780 if (!amdgpu_dig_connector) 1781 goto failed; 1782 amdgpu_connector->con_priv = amdgpu_dig_connector; 1783 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1784 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1785 if (i2c_bus->valid) { 1786 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1787 if (!amdgpu_connector->ddc_bus) 1788 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1789 } 1790 drm_object_attach_property(&amdgpu_connector->base.base, 1791 adev->mode_info.coherent_mode_property, 1792 1); 1793 drm_object_attach_property(&amdgpu_connector->base.base, 1794 adev->mode_info.underscan_property, 1795 UNDERSCAN_OFF); 1796 drm_object_attach_property(&amdgpu_connector->base.base, 1797 adev->mode_info.underscan_hborder_property, 1798 0); 1799 drm_object_attach_property(&amdgpu_connector->base.base, 1800 adev->mode_info.underscan_vborder_property, 1801 0); 1802 drm_object_attach_property(&amdgpu_connector->base.base, 1803 dev->mode_config.scaling_mode_property, 1804 DRM_MODE_SCALE_NONE); 1805 if (amdgpu_audio != 0) { 1806 drm_object_attach_property(&amdgpu_connector->base.base, 1807 adev->mode_info.audio_property, 1808 AMDGPU_AUDIO_AUTO); 1809 } 1810 drm_object_attach_property(&amdgpu_connector->base.base, 1811 adev->mode_info.dither_property, 1812 AMDGPU_FMT_DITHER_DISABLE); 1813 subpixel_order = SubPixelHorizontalRGB; 1814 connector->interlace_allowed = true; 1815 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1816 connector->doublescan_allowed = true; 1817 else 1818 connector->doublescan_allowed = false; 1819 break; 1820 case DRM_MODE_CONNECTOR_DisplayPort: 1821 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1822 if (!amdgpu_dig_connector) 1823 goto failed; 1824 amdgpu_connector->con_priv = amdgpu_dig_connector; 1825 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1826 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1827 if (i2c_bus->valid) { 1828 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1829 if (amdgpu_connector->ddc_bus) 1830 has_aux = true; 1831 else 1832 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1833 } 1834 subpixel_order = SubPixelHorizontalRGB; 1835 drm_object_attach_property(&amdgpu_connector->base.base, 1836 adev->mode_info.coherent_mode_property, 1837 1); 1838 drm_object_attach_property(&amdgpu_connector->base.base, 1839 adev->mode_info.underscan_property, 1840 UNDERSCAN_OFF); 1841 drm_object_attach_property(&amdgpu_connector->base.base, 1842 adev->mode_info.underscan_hborder_property, 1843 0); 1844 drm_object_attach_property(&amdgpu_connector->base.base, 1845 adev->mode_info.underscan_vborder_property, 1846 0); 1847 drm_object_attach_property(&amdgpu_connector->base.base, 1848 dev->mode_config.scaling_mode_property, 1849 DRM_MODE_SCALE_NONE); 1850 if (amdgpu_audio != 0) { 1851 drm_object_attach_property(&amdgpu_connector->base.base, 1852 adev->mode_info.audio_property, 1853 AMDGPU_AUDIO_AUTO); 1854 } 1855 drm_object_attach_property(&amdgpu_connector->base.base, 1856 adev->mode_info.dither_property, 1857 AMDGPU_FMT_DITHER_DISABLE); 1858 connector->interlace_allowed = true; 1859 /* in theory with a DP to VGA converter... */ 1860 connector->doublescan_allowed = false; 1861 break; 1862 case DRM_MODE_CONNECTOR_eDP: 1863 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1864 if (!amdgpu_dig_connector) 1865 goto failed; 1866 amdgpu_connector->con_priv = amdgpu_dig_connector; 1867 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1868 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1869 if (i2c_bus->valid) { 1870 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1871 if (amdgpu_connector->ddc_bus) 1872 has_aux = true; 1873 else 1874 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1875 } 1876 drm_object_attach_property(&amdgpu_connector->base.base, 1877 dev->mode_config.scaling_mode_property, 1878 DRM_MODE_SCALE_FULLSCREEN); 1879 subpixel_order = SubPixelHorizontalRGB; 1880 connector->interlace_allowed = false; 1881 connector->doublescan_allowed = false; 1882 break; 1883 case DRM_MODE_CONNECTOR_LVDS: 1884 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1885 if (!amdgpu_dig_connector) 1886 goto failed; 1887 amdgpu_connector->con_priv = amdgpu_dig_connector; 1888 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1889 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1890 if (i2c_bus->valid) { 1891 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1892 if (!amdgpu_connector->ddc_bus) 1893 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1894 } 1895 drm_object_attach_property(&amdgpu_connector->base.base, 1896 dev->mode_config.scaling_mode_property, 1897 DRM_MODE_SCALE_FULLSCREEN); 1898 subpixel_order = SubPixelHorizontalRGB; 1899 connector->interlace_allowed = false; 1900 connector->doublescan_allowed = false; 1901 break; 1902 } 1903 } 1904 1905 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1906 if (i2c_bus->valid) { 1907 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1908 DRM_CONNECTOR_POLL_DISCONNECT; 1909 } 1910 } else 1911 connector->polled = DRM_CONNECTOR_POLL_HPD; 1912 1913 connector->display_info.subpixel_order = subpixel_order; 1914 drm_connector_register(connector); 1915 1916 if (has_aux) 1917 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1918 1919 return; 1920 1921 failed: 1922 drm_connector_cleanup(connector); 1923 kfree(connector); 1924 } 1925