1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 250 { 251 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 252 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 253 254 if (amdgpu_connector->edid) { 255 return amdgpu_connector->edid; 256 } else if (edid_blob) { 257 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 258 if (edid) 259 amdgpu_connector->edid = edid; 260 } 261 return amdgpu_connector->edid; 262 } 263 264 static struct edid * 265 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 266 { 267 struct edid *edid; 268 269 if (adev->mode_info.bios_hardcoded_edid) { 270 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 271 if (edid) { 272 memcpy((unsigned char *)edid, 273 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 274 adev->mode_info.bios_hardcoded_edid_size); 275 return edid; 276 } 277 } 278 return NULL; 279 } 280 281 static void amdgpu_connector_get_edid(struct drm_connector *connector) 282 { 283 struct drm_device *dev = connector->dev; 284 struct amdgpu_device *adev = drm_to_adev(dev); 285 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 286 287 if (amdgpu_connector->edid) 288 return; 289 290 /* on hw with routers, select right port */ 291 if (amdgpu_connector->router.ddc_valid) 292 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 293 294 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 295 ENCODER_OBJECT_ID_NONE) && 296 amdgpu_connector->ddc_bus->has_aux) { 297 amdgpu_connector->edid = drm_get_edid(connector, 298 &amdgpu_connector->ddc_bus->aux.ddc); 299 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 300 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 301 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 302 303 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 304 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 305 amdgpu_connector->ddc_bus->has_aux) 306 amdgpu_connector->edid = drm_get_edid(connector, 307 &amdgpu_connector->ddc_bus->aux.ddc); 308 else if (amdgpu_connector->ddc_bus) 309 amdgpu_connector->edid = drm_get_edid(connector, 310 &amdgpu_connector->ddc_bus->adapter); 311 } else if (amdgpu_connector->ddc_bus) { 312 amdgpu_connector->edid = drm_get_edid(connector, 313 &amdgpu_connector->ddc_bus->adapter); 314 } 315 316 if (!amdgpu_connector->edid) { 317 /* some laptops provide a hardcoded edid in rom for LCDs */ 318 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 319 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 320 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 321 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 322 } 323 } 324 } 325 326 static void amdgpu_connector_free_edid(struct drm_connector *connector) 327 { 328 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 329 330 kfree(amdgpu_connector->edid); 331 amdgpu_connector->edid = NULL; 332 drm_connector_update_edid_property(connector, NULL); 333 } 334 335 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 336 { 337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 338 int ret; 339 340 if (amdgpu_connector->edid) { 341 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 342 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 343 return ret; 344 } 345 drm_connector_update_edid_property(connector, NULL); 346 return 0; 347 } 348 349 static struct drm_encoder * 350 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 351 { 352 struct drm_encoder *encoder; 353 354 /* pick the first one */ 355 drm_connector_for_each_possible_encoder(connector, encoder) 356 return encoder; 357 358 return NULL; 359 } 360 361 static void amdgpu_get_native_mode(struct drm_connector *connector) 362 { 363 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 364 struct amdgpu_encoder *amdgpu_encoder; 365 366 if (encoder == NULL) 367 return; 368 369 amdgpu_encoder = to_amdgpu_encoder(encoder); 370 371 if (!list_empty(&connector->probed_modes)) { 372 struct drm_display_mode *preferred_mode = 373 list_first_entry(&connector->probed_modes, 374 struct drm_display_mode, head); 375 376 amdgpu_encoder->native_mode = *preferred_mode; 377 } else { 378 amdgpu_encoder->native_mode.clock = 0; 379 } 380 } 381 382 static struct drm_display_mode * 383 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 384 { 385 struct drm_device *dev = encoder->dev; 386 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 387 struct drm_display_mode *mode = NULL; 388 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 389 390 if (native_mode->hdisplay != 0 && 391 native_mode->vdisplay != 0 && 392 native_mode->clock != 0) { 393 mode = drm_mode_duplicate(dev, native_mode); 394 if (!mode) 395 return NULL; 396 397 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 398 drm_mode_set_name(mode); 399 400 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 401 } else if (native_mode->hdisplay != 0 && 402 native_mode->vdisplay != 0) { 403 /* mac laptops without an edid */ 404 /* Note that this is not necessarily the exact panel mode, 405 * but an approximation based on the cvt formula. For these 406 * systems we should ideally read the mode info out of the 407 * registers or add a mode table, but this works and is much 408 * simpler. 409 */ 410 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 411 if (!mode) 412 return NULL; 413 414 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 415 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 416 } 417 return mode; 418 } 419 420 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 421 struct drm_connector *connector) 422 { 423 struct drm_device *dev = encoder->dev; 424 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 425 struct drm_display_mode *mode = NULL; 426 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 427 int i; 428 static const struct mode_size { 429 int w; 430 int h; 431 } common_modes[17] = { 432 { 640, 480}, 433 { 720, 480}, 434 { 800, 600}, 435 { 848, 480}, 436 {1024, 768}, 437 {1152, 768}, 438 {1280, 720}, 439 {1280, 800}, 440 {1280, 854}, 441 {1280, 960}, 442 {1280, 1024}, 443 {1440, 900}, 444 {1400, 1050}, 445 {1680, 1050}, 446 {1600, 1200}, 447 {1920, 1080}, 448 {1920, 1200} 449 }; 450 451 for (i = 0; i < 17; i++) { 452 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 453 if (common_modes[i].w > 1024 || 454 common_modes[i].h > 768) 455 continue; 456 } 457 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 458 if (common_modes[i].w > native_mode->hdisplay || 459 common_modes[i].h > native_mode->vdisplay || 460 (common_modes[i].w == native_mode->hdisplay && 461 common_modes[i].h == native_mode->vdisplay)) 462 continue; 463 } 464 if (common_modes[i].w < 320 || common_modes[i].h < 200) 465 continue; 466 467 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 468 drm_mode_probed_add(connector, mode); 469 } 470 } 471 472 static int amdgpu_connector_set_property(struct drm_connector *connector, 473 struct drm_property *property, 474 uint64_t val) 475 { 476 struct drm_device *dev = connector->dev; 477 struct amdgpu_device *adev = drm_to_adev(dev); 478 struct drm_encoder *encoder; 479 struct amdgpu_encoder *amdgpu_encoder; 480 481 if (property == adev->mode_info.coherent_mode_property) { 482 struct amdgpu_encoder_atom_dig *dig; 483 bool new_coherent_mode; 484 485 /* need to find digital encoder on connector */ 486 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 487 if (!encoder) 488 return 0; 489 490 amdgpu_encoder = to_amdgpu_encoder(encoder); 491 492 if (!amdgpu_encoder->enc_priv) 493 return 0; 494 495 dig = amdgpu_encoder->enc_priv; 496 new_coherent_mode = val ? true : false; 497 if (dig->coherent_mode != new_coherent_mode) { 498 dig->coherent_mode = new_coherent_mode; 499 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 500 } 501 } 502 503 if (property == adev->mode_info.audio_property) { 504 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 505 /* need to find digital encoder on connector */ 506 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 507 if (!encoder) 508 return 0; 509 510 amdgpu_encoder = to_amdgpu_encoder(encoder); 511 512 if (amdgpu_connector->audio != val) { 513 amdgpu_connector->audio = val; 514 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 515 } 516 } 517 518 if (property == adev->mode_info.dither_property) { 519 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 520 /* need to find digital encoder on connector */ 521 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 522 if (!encoder) 523 return 0; 524 525 amdgpu_encoder = to_amdgpu_encoder(encoder); 526 527 if (amdgpu_connector->dither != val) { 528 amdgpu_connector->dither = val; 529 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 530 } 531 } 532 533 if (property == adev->mode_info.underscan_property) { 534 /* need to find digital encoder on connector */ 535 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 536 if (!encoder) 537 return 0; 538 539 amdgpu_encoder = to_amdgpu_encoder(encoder); 540 541 if (amdgpu_encoder->underscan_type != val) { 542 amdgpu_encoder->underscan_type = val; 543 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 544 } 545 } 546 547 if (property == adev->mode_info.underscan_hborder_property) { 548 /* need to find digital encoder on connector */ 549 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 550 if (!encoder) 551 return 0; 552 553 amdgpu_encoder = to_amdgpu_encoder(encoder); 554 555 if (amdgpu_encoder->underscan_hborder != val) { 556 amdgpu_encoder->underscan_hborder = val; 557 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 558 } 559 } 560 561 if (property == adev->mode_info.underscan_vborder_property) { 562 /* need to find digital encoder on connector */ 563 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 564 if (!encoder) 565 return 0; 566 567 amdgpu_encoder = to_amdgpu_encoder(encoder); 568 569 if (amdgpu_encoder->underscan_vborder != val) { 570 amdgpu_encoder->underscan_vborder = val; 571 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 572 } 573 } 574 575 if (property == adev->mode_info.load_detect_property) { 576 struct amdgpu_connector *amdgpu_connector = 577 to_amdgpu_connector(connector); 578 579 if (val == 0) 580 amdgpu_connector->dac_load_detect = false; 581 else 582 amdgpu_connector->dac_load_detect = true; 583 } 584 585 if (property == dev->mode_config.scaling_mode_property) { 586 enum amdgpu_rmx_type rmx_type; 587 588 if (connector->encoder) { 589 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 590 } else { 591 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 592 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 593 } 594 595 switch (val) { 596 default: 597 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 598 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 599 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 600 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 601 } 602 if (amdgpu_encoder->rmx_type == rmx_type) 603 return 0; 604 605 if ((rmx_type != DRM_MODE_SCALE_NONE) && 606 (amdgpu_encoder->native_mode.clock == 0)) 607 return 0; 608 609 amdgpu_encoder->rmx_type = rmx_type; 610 611 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 612 } 613 614 return 0; 615 } 616 617 static void 618 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 619 struct drm_connector *connector) 620 { 621 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 622 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 623 struct drm_display_mode *t, *mode; 624 625 /* If the EDID preferred mode doesn't match the native mode, use it */ 626 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 627 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 628 if (mode->hdisplay != native_mode->hdisplay || 629 mode->vdisplay != native_mode->vdisplay) 630 drm_mode_copy(native_mode, mode); 631 } 632 } 633 634 /* Try to get native mode details from EDID if necessary */ 635 if (!native_mode->clock) { 636 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 637 if (mode->hdisplay == native_mode->hdisplay && 638 mode->vdisplay == native_mode->vdisplay) { 639 drm_mode_copy(native_mode, mode); 640 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 641 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 642 break; 643 } 644 } 645 } 646 647 if (!native_mode->clock) { 648 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 649 amdgpu_encoder->rmx_type = RMX_OFF; 650 } 651 } 652 653 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 654 { 655 struct drm_encoder *encoder; 656 int ret = 0; 657 struct drm_display_mode *mode; 658 659 amdgpu_connector_get_edid(connector); 660 ret = amdgpu_connector_ddc_get_modes(connector); 661 if (ret > 0) { 662 encoder = amdgpu_connector_best_single_encoder(connector); 663 if (encoder) { 664 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 665 /* add scaled modes */ 666 amdgpu_connector_add_common_modes(encoder, connector); 667 } 668 return ret; 669 } 670 671 encoder = amdgpu_connector_best_single_encoder(connector); 672 if (!encoder) 673 return 0; 674 675 /* we have no EDID modes */ 676 mode = amdgpu_connector_lcd_native_mode(encoder); 677 if (mode) { 678 ret = 1; 679 drm_mode_probed_add(connector, mode); 680 /* add the width/height from vbios tables if available */ 681 connector->display_info.width_mm = mode->width_mm; 682 connector->display_info.height_mm = mode->height_mm; 683 /* add scaled modes */ 684 amdgpu_connector_add_common_modes(encoder, connector); 685 } 686 687 return ret; 688 } 689 690 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 691 struct drm_display_mode *mode) 692 { 693 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 694 695 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 696 return MODE_PANEL; 697 698 if (encoder) { 699 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 700 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 701 702 /* AVIVO hardware supports downscaling modes larger than the panel 703 * to the panel size, but I'm not sure this is desirable. 704 */ 705 if ((mode->hdisplay > native_mode->hdisplay) || 706 (mode->vdisplay > native_mode->vdisplay)) 707 return MODE_PANEL; 708 709 /* if scaling is disabled, block non-native modes */ 710 if (amdgpu_encoder->rmx_type == RMX_OFF) { 711 if ((mode->hdisplay != native_mode->hdisplay) || 712 (mode->vdisplay != native_mode->vdisplay)) 713 return MODE_PANEL; 714 } 715 } 716 717 return MODE_OK; 718 } 719 720 static enum drm_connector_status 721 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 722 { 723 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 724 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 725 enum drm_connector_status ret = connector_status_disconnected; 726 int r; 727 728 if (!drm_kms_helper_is_poll_worker()) { 729 r = pm_runtime_get_sync(connector->dev->dev); 730 if (r < 0) { 731 pm_runtime_put_autosuspend(connector->dev->dev); 732 return connector_status_disconnected; 733 } 734 } 735 736 if (encoder) { 737 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 738 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 739 740 /* check if panel is valid */ 741 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 742 ret = connector_status_connected; 743 744 } 745 746 /* check for edid as well */ 747 amdgpu_connector_get_edid(connector); 748 if (amdgpu_connector->edid) 749 ret = connector_status_connected; 750 /* check acpi lid status ??? */ 751 752 amdgpu_connector_update_scratch_regs(connector, ret); 753 754 if (!drm_kms_helper_is_poll_worker()) { 755 pm_runtime_mark_last_busy(connector->dev->dev); 756 pm_runtime_put_autosuspend(connector->dev->dev); 757 } 758 759 return ret; 760 } 761 762 static void amdgpu_connector_unregister(struct drm_connector *connector) 763 { 764 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 765 766 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 767 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 768 amdgpu_connector->ddc_bus->has_aux = false; 769 } 770 } 771 772 static void amdgpu_connector_destroy(struct drm_connector *connector) 773 { 774 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 775 776 amdgpu_connector_free_edid(connector); 777 kfree(amdgpu_connector->con_priv); 778 drm_connector_unregister(connector); 779 drm_connector_cleanup(connector); 780 kfree(connector); 781 } 782 783 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 784 struct drm_property *property, 785 uint64_t value) 786 { 787 struct drm_device *dev = connector->dev; 788 struct amdgpu_encoder *amdgpu_encoder; 789 enum amdgpu_rmx_type rmx_type; 790 791 DRM_DEBUG_KMS("\n"); 792 if (property != dev->mode_config.scaling_mode_property) 793 return 0; 794 795 if (connector->encoder) 796 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 797 else { 798 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 799 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 800 } 801 802 switch (value) { 803 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 804 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 805 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 806 default: 807 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 808 } 809 if (amdgpu_encoder->rmx_type == rmx_type) 810 return 0; 811 812 amdgpu_encoder->rmx_type = rmx_type; 813 814 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 815 return 0; 816 } 817 818 819 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 820 .get_modes = amdgpu_connector_lvds_get_modes, 821 .mode_valid = amdgpu_connector_lvds_mode_valid, 822 .best_encoder = amdgpu_connector_best_single_encoder, 823 }; 824 825 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 826 .dpms = drm_helper_connector_dpms, 827 .detect = amdgpu_connector_lvds_detect, 828 .fill_modes = drm_helper_probe_single_connector_modes, 829 .early_unregister = amdgpu_connector_unregister, 830 .destroy = amdgpu_connector_destroy, 831 .set_property = amdgpu_connector_set_lcd_property, 832 }; 833 834 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 835 { 836 int ret; 837 838 amdgpu_connector_get_edid(connector); 839 ret = amdgpu_connector_ddc_get_modes(connector); 840 amdgpu_get_native_mode(connector); 841 842 return ret; 843 } 844 845 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 846 struct drm_display_mode *mode) 847 { 848 struct drm_device *dev = connector->dev; 849 struct amdgpu_device *adev = drm_to_adev(dev); 850 851 /* XXX check mode bandwidth */ 852 853 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 854 return MODE_CLOCK_HIGH; 855 856 return MODE_OK; 857 } 858 859 static enum drm_connector_status 860 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 861 { 862 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 863 struct drm_encoder *encoder; 864 const struct drm_encoder_helper_funcs *encoder_funcs; 865 bool dret = false; 866 enum drm_connector_status ret = connector_status_disconnected; 867 int r; 868 869 if (!drm_kms_helper_is_poll_worker()) { 870 r = pm_runtime_get_sync(connector->dev->dev); 871 if (r < 0) { 872 pm_runtime_put_autosuspend(connector->dev->dev); 873 return connector_status_disconnected; 874 } 875 } 876 877 encoder = amdgpu_connector_best_single_encoder(connector); 878 if (!encoder) 879 ret = connector_status_disconnected; 880 881 if (amdgpu_connector->ddc_bus) 882 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 883 if (dret) { 884 amdgpu_connector->detected_by_load = false; 885 amdgpu_connector_free_edid(connector); 886 amdgpu_connector_get_edid(connector); 887 888 if (!amdgpu_connector->edid) { 889 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 890 connector->name); 891 ret = connector_status_connected; 892 } else { 893 amdgpu_connector->use_digital = 894 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 895 896 /* some oems have boards with separate digital and analog connectors 897 * with a shared ddc line (often vga + hdmi) 898 */ 899 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 900 amdgpu_connector_free_edid(connector); 901 ret = connector_status_disconnected; 902 } else { 903 ret = connector_status_connected; 904 } 905 } 906 } else { 907 908 /* if we aren't forcing don't do destructive polling */ 909 if (!force) { 910 /* only return the previous status if we last 911 * detected a monitor via load. 912 */ 913 if (amdgpu_connector->detected_by_load) 914 ret = connector->status; 915 goto out; 916 } 917 918 if (amdgpu_connector->dac_load_detect && encoder) { 919 encoder_funcs = encoder->helper_private; 920 ret = encoder_funcs->detect(encoder, connector); 921 if (ret != connector_status_disconnected) 922 amdgpu_connector->detected_by_load = true; 923 } 924 } 925 926 amdgpu_connector_update_scratch_regs(connector, ret); 927 928 out: 929 if (!drm_kms_helper_is_poll_worker()) { 930 pm_runtime_mark_last_busy(connector->dev->dev); 931 pm_runtime_put_autosuspend(connector->dev->dev); 932 } 933 934 return ret; 935 } 936 937 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 938 .get_modes = amdgpu_connector_vga_get_modes, 939 .mode_valid = amdgpu_connector_vga_mode_valid, 940 .best_encoder = amdgpu_connector_best_single_encoder, 941 }; 942 943 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 944 .dpms = drm_helper_connector_dpms, 945 .detect = amdgpu_connector_vga_detect, 946 .fill_modes = drm_helper_probe_single_connector_modes, 947 .early_unregister = amdgpu_connector_unregister, 948 .destroy = amdgpu_connector_destroy, 949 .set_property = amdgpu_connector_set_property, 950 }; 951 952 static bool 953 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 954 { 955 struct drm_device *dev = connector->dev; 956 struct amdgpu_device *adev = drm_to_adev(dev); 957 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 958 enum drm_connector_status status; 959 960 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 961 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 962 status = connector_status_connected; 963 else 964 status = connector_status_disconnected; 965 if (connector->status == status) 966 return true; 967 } 968 969 return false; 970 } 971 972 /* 973 * DVI is complicated 974 * Do a DDC probe, if DDC probe passes, get the full EDID so 975 * we can do analog/digital monitor detection at this point. 976 * If the monitor is an analog monitor or we got no DDC, 977 * we need to find the DAC encoder object for this connector. 978 * If we got no DDC, we do load detection on the DAC encoder object. 979 * If we got analog DDC or load detection passes on the DAC encoder 980 * we have to check if this analog encoder is shared with anyone else (TV) 981 * if its shared we have to set the other connector to disconnected. 982 */ 983 static enum drm_connector_status 984 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 985 { 986 struct drm_device *dev = connector->dev; 987 struct amdgpu_device *adev = drm_to_adev(dev); 988 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 989 const struct drm_encoder_helper_funcs *encoder_funcs; 990 int r; 991 enum drm_connector_status ret = connector_status_disconnected; 992 bool dret = false, broken_edid = false; 993 994 if (!drm_kms_helper_is_poll_worker()) { 995 r = pm_runtime_get_sync(connector->dev->dev); 996 if (r < 0) { 997 pm_runtime_put_autosuspend(connector->dev->dev); 998 return connector_status_disconnected; 999 } 1000 } 1001 1002 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1003 ret = connector->status; 1004 goto exit; 1005 } 1006 1007 if (amdgpu_connector->ddc_bus) 1008 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1009 if (dret) { 1010 amdgpu_connector->detected_by_load = false; 1011 amdgpu_connector_free_edid(connector); 1012 amdgpu_connector_get_edid(connector); 1013 1014 if (!amdgpu_connector->edid) { 1015 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1016 connector->name); 1017 ret = connector_status_connected; 1018 broken_edid = true; /* defer use_digital to later */ 1019 } else { 1020 amdgpu_connector->use_digital = 1021 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1022 1023 /* some oems have boards with separate digital and analog connectors 1024 * with a shared ddc line (often vga + hdmi) 1025 */ 1026 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1027 amdgpu_connector_free_edid(connector); 1028 ret = connector_status_disconnected; 1029 } else { 1030 ret = connector_status_connected; 1031 } 1032 1033 /* This gets complicated. We have boards with VGA + HDMI with a 1034 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1035 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1036 * you don't really know what's connected to which port as both are digital. 1037 */ 1038 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1039 struct drm_connector *list_connector; 1040 struct drm_connector_list_iter iter; 1041 struct amdgpu_connector *list_amdgpu_connector; 1042 1043 drm_connector_list_iter_begin(dev, &iter); 1044 drm_for_each_connector_iter(list_connector, 1045 &iter) { 1046 if (connector == list_connector) 1047 continue; 1048 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1049 if (list_amdgpu_connector->shared_ddc && 1050 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1051 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1052 /* cases where both connectors are digital */ 1053 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1054 /* hpd is our only option in this case */ 1055 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1056 amdgpu_connector_free_edid(connector); 1057 ret = connector_status_disconnected; 1058 } 1059 } 1060 } 1061 } 1062 drm_connector_list_iter_end(&iter); 1063 } 1064 } 1065 } 1066 1067 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1068 goto out; 1069 1070 /* DVI-D and HDMI-A are digital only */ 1071 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1072 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1073 goto out; 1074 1075 /* if we aren't forcing don't do destructive polling */ 1076 if (!force) { 1077 /* only return the previous status if we last 1078 * detected a monitor via load. 1079 */ 1080 if (amdgpu_connector->detected_by_load) 1081 ret = connector->status; 1082 goto out; 1083 } 1084 1085 /* find analog encoder */ 1086 if (amdgpu_connector->dac_load_detect) { 1087 struct drm_encoder *encoder; 1088 1089 drm_connector_for_each_possible_encoder(connector, encoder) { 1090 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1091 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1092 continue; 1093 1094 encoder_funcs = encoder->helper_private; 1095 if (encoder_funcs->detect) { 1096 if (!broken_edid) { 1097 if (ret != connector_status_connected) { 1098 /* deal with analog monitors without DDC */ 1099 ret = encoder_funcs->detect(encoder, connector); 1100 if (ret == connector_status_connected) { 1101 amdgpu_connector->use_digital = false; 1102 } 1103 if (ret != connector_status_disconnected) 1104 amdgpu_connector->detected_by_load = true; 1105 } 1106 } else { 1107 enum drm_connector_status lret; 1108 /* assume digital unless load detected otherwise */ 1109 amdgpu_connector->use_digital = true; 1110 lret = encoder_funcs->detect(encoder, connector); 1111 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1112 if (lret == connector_status_connected) 1113 amdgpu_connector->use_digital = false; 1114 } 1115 break; 1116 } 1117 } 1118 } 1119 1120 out: 1121 /* updated in get modes as well since we need to know if it's analog or digital */ 1122 amdgpu_connector_update_scratch_regs(connector, ret); 1123 1124 exit: 1125 if (!drm_kms_helper_is_poll_worker()) { 1126 pm_runtime_mark_last_busy(connector->dev->dev); 1127 pm_runtime_put_autosuspend(connector->dev->dev); 1128 } 1129 1130 return ret; 1131 } 1132 1133 /* okay need to be smart in here about which encoder to pick */ 1134 static struct drm_encoder * 1135 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1136 { 1137 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1138 struct drm_encoder *encoder; 1139 1140 drm_connector_for_each_possible_encoder(connector, encoder) { 1141 if (amdgpu_connector->use_digital == true) { 1142 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1143 return encoder; 1144 } else { 1145 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1146 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1147 return encoder; 1148 } 1149 } 1150 1151 /* see if we have a default encoder TODO */ 1152 1153 /* then check use digitial */ 1154 /* pick the first one */ 1155 drm_connector_for_each_possible_encoder(connector, encoder) 1156 return encoder; 1157 1158 return NULL; 1159 } 1160 1161 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1162 { 1163 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1164 if (connector->force == DRM_FORCE_ON) 1165 amdgpu_connector->use_digital = false; 1166 if (connector->force == DRM_FORCE_ON_DIGITAL) 1167 amdgpu_connector->use_digital = true; 1168 } 1169 1170 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1171 struct drm_display_mode *mode) 1172 { 1173 struct drm_device *dev = connector->dev; 1174 struct amdgpu_device *adev = drm_to_adev(dev); 1175 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1176 1177 /* XXX check mode bandwidth */ 1178 1179 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1180 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1181 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1182 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1183 return MODE_OK; 1184 } else if (connector->display_info.is_hdmi) { 1185 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1186 if (mode->clock > 340000) 1187 return MODE_CLOCK_HIGH; 1188 else 1189 return MODE_OK; 1190 } else { 1191 return MODE_CLOCK_HIGH; 1192 } 1193 } 1194 1195 /* check against the max pixel clock */ 1196 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1197 return MODE_CLOCK_HIGH; 1198 1199 return MODE_OK; 1200 } 1201 1202 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1203 .get_modes = amdgpu_connector_vga_get_modes, 1204 .mode_valid = amdgpu_connector_dvi_mode_valid, 1205 .best_encoder = amdgpu_connector_dvi_encoder, 1206 }; 1207 1208 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1209 .dpms = drm_helper_connector_dpms, 1210 .detect = amdgpu_connector_dvi_detect, 1211 .fill_modes = drm_helper_probe_single_connector_modes, 1212 .set_property = amdgpu_connector_set_property, 1213 .early_unregister = amdgpu_connector_unregister, 1214 .destroy = amdgpu_connector_destroy, 1215 .force = amdgpu_connector_dvi_force, 1216 }; 1217 1218 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1219 { 1220 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1221 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1222 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1223 int ret; 1224 1225 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1226 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1227 struct drm_display_mode *mode; 1228 1229 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1230 if (!amdgpu_dig_connector->edp_on) 1231 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1232 ATOM_TRANSMITTER_ACTION_POWER_ON); 1233 amdgpu_connector_get_edid(connector); 1234 ret = amdgpu_connector_ddc_get_modes(connector); 1235 if (!amdgpu_dig_connector->edp_on) 1236 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1237 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1238 } else { 1239 /* need to setup ddc on the bridge */ 1240 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1241 ENCODER_OBJECT_ID_NONE) { 1242 if (encoder) 1243 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1244 } 1245 amdgpu_connector_get_edid(connector); 1246 ret = amdgpu_connector_ddc_get_modes(connector); 1247 } 1248 1249 if (ret > 0) { 1250 if (encoder) { 1251 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1252 /* add scaled modes */ 1253 amdgpu_connector_add_common_modes(encoder, connector); 1254 } 1255 return ret; 1256 } 1257 1258 if (!encoder) 1259 return 0; 1260 1261 /* we have no EDID modes */ 1262 mode = amdgpu_connector_lcd_native_mode(encoder); 1263 if (mode) { 1264 ret = 1; 1265 drm_mode_probed_add(connector, mode); 1266 /* add the width/height from vbios tables if available */ 1267 connector->display_info.width_mm = mode->width_mm; 1268 connector->display_info.height_mm = mode->height_mm; 1269 /* add scaled modes */ 1270 amdgpu_connector_add_common_modes(encoder, connector); 1271 } 1272 } else { 1273 /* need to setup ddc on the bridge */ 1274 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1275 ENCODER_OBJECT_ID_NONE) { 1276 if (encoder) 1277 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1278 } 1279 amdgpu_connector_get_edid(connector); 1280 ret = amdgpu_connector_ddc_get_modes(connector); 1281 1282 amdgpu_get_native_mode(connector); 1283 } 1284 1285 return ret; 1286 } 1287 1288 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1289 { 1290 struct drm_encoder *encoder; 1291 struct amdgpu_encoder *amdgpu_encoder; 1292 1293 drm_connector_for_each_possible_encoder(connector, encoder) { 1294 amdgpu_encoder = to_amdgpu_encoder(encoder); 1295 1296 switch (amdgpu_encoder->encoder_id) { 1297 case ENCODER_OBJECT_ID_TRAVIS: 1298 case ENCODER_OBJECT_ID_NUTMEG: 1299 return amdgpu_encoder->encoder_id; 1300 default: 1301 break; 1302 } 1303 } 1304 1305 return ENCODER_OBJECT_ID_NONE; 1306 } 1307 1308 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1309 { 1310 struct drm_encoder *encoder; 1311 struct amdgpu_encoder *amdgpu_encoder; 1312 bool found = false; 1313 1314 drm_connector_for_each_possible_encoder(connector, encoder) { 1315 amdgpu_encoder = to_amdgpu_encoder(encoder); 1316 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1317 found = true; 1318 } 1319 1320 return found; 1321 } 1322 1323 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1324 { 1325 struct drm_device *dev = connector->dev; 1326 struct amdgpu_device *adev = drm_to_adev(dev); 1327 1328 if ((adev->clock.default_dispclk >= 53900) && 1329 amdgpu_connector_encoder_is_hbr2(connector)) { 1330 return true; 1331 } 1332 1333 return false; 1334 } 1335 1336 static enum drm_connector_status 1337 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1338 { 1339 struct drm_device *dev = connector->dev; 1340 struct amdgpu_device *adev = drm_to_adev(dev); 1341 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1342 enum drm_connector_status ret = connector_status_disconnected; 1343 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1344 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1345 int r; 1346 1347 if (!drm_kms_helper_is_poll_worker()) { 1348 r = pm_runtime_get_sync(connector->dev->dev); 1349 if (r < 0) { 1350 pm_runtime_put_autosuspend(connector->dev->dev); 1351 return connector_status_disconnected; 1352 } 1353 } 1354 1355 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1356 ret = connector->status; 1357 goto out; 1358 } 1359 1360 amdgpu_connector_free_edid(connector); 1361 1362 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1363 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1364 if (encoder) { 1365 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1366 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1367 1368 /* check if panel is valid */ 1369 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1370 ret = connector_status_connected; 1371 } 1372 /* eDP is always DP */ 1373 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1374 if (!amdgpu_dig_connector->edp_on) 1375 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1376 ATOM_TRANSMITTER_ACTION_POWER_ON); 1377 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1378 ret = connector_status_connected; 1379 if (!amdgpu_dig_connector->edp_on) 1380 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1381 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1382 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1383 ENCODER_OBJECT_ID_NONE) { 1384 /* DP bridges are always DP */ 1385 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1386 /* get the DPCD from the bridge */ 1387 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1388 1389 if (encoder) { 1390 /* setup ddc on the bridge */ 1391 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1392 /* bridge chips are always aux */ 1393 /* try DDC */ 1394 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1395 ret = connector_status_connected; 1396 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1397 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1398 ret = encoder_funcs->detect(encoder, connector); 1399 } 1400 } 1401 } else { 1402 amdgpu_dig_connector->dp_sink_type = 1403 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1404 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1405 ret = connector_status_connected; 1406 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1407 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1408 } else { 1409 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1410 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1411 ret = connector_status_connected; 1412 } else { 1413 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1414 if (amdgpu_display_ddc_probe(amdgpu_connector, 1415 false)) 1416 ret = connector_status_connected; 1417 } 1418 } 1419 } 1420 1421 amdgpu_connector_update_scratch_regs(connector, ret); 1422 out: 1423 if (!drm_kms_helper_is_poll_worker()) { 1424 pm_runtime_mark_last_busy(connector->dev->dev); 1425 pm_runtime_put_autosuspend(connector->dev->dev); 1426 } 1427 1428 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1429 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1430 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1431 ret, 1432 amdgpu_dig_connector->dpcd, 1433 amdgpu_dig_connector->downstream_ports); 1434 return ret; 1435 } 1436 1437 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1438 struct drm_display_mode *mode) 1439 { 1440 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1441 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1442 1443 /* XXX check mode bandwidth */ 1444 1445 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1446 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1447 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1448 1449 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1450 return MODE_PANEL; 1451 1452 if (encoder) { 1453 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1454 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1455 1456 /* AVIVO hardware supports downscaling modes larger than the panel 1457 * to the panel size, but I'm not sure this is desirable. 1458 */ 1459 if ((mode->hdisplay > native_mode->hdisplay) || 1460 (mode->vdisplay > native_mode->vdisplay)) 1461 return MODE_PANEL; 1462 1463 /* if scaling is disabled, block non-native modes */ 1464 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1465 if ((mode->hdisplay != native_mode->hdisplay) || 1466 (mode->vdisplay != native_mode->vdisplay)) 1467 return MODE_PANEL; 1468 } 1469 } 1470 return MODE_OK; 1471 } else { 1472 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1473 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1474 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1475 } else { 1476 if (connector->display_info.is_hdmi) { 1477 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1478 if (mode->clock > 340000) 1479 return MODE_CLOCK_HIGH; 1480 } else { 1481 if (mode->clock > 165000) 1482 return MODE_CLOCK_HIGH; 1483 } 1484 } 1485 } 1486 1487 return MODE_OK; 1488 } 1489 1490 static int 1491 amdgpu_connector_late_register(struct drm_connector *connector) 1492 { 1493 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1494 int r = 0; 1495 1496 if (amdgpu_connector->ddc_bus->has_aux) { 1497 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1498 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1499 } 1500 1501 return r; 1502 } 1503 1504 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1505 .get_modes = amdgpu_connector_dp_get_modes, 1506 .mode_valid = amdgpu_connector_dp_mode_valid, 1507 .best_encoder = amdgpu_connector_dvi_encoder, 1508 }; 1509 1510 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1511 .dpms = drm_helper_connector_dpms, 1512 .detect = amdgpu_connector_dp_detect, 1513 .fill_modes = drm_helper_probe_single_connector_modes, 1514 .set_property = amdgpu_connector_set_property, 1515 .early_unregister = amdgpu_connector_unregister, 1516 .destroy = amdgpu_connector_destroy, 1517 .force = amdgpu_connector_dvi_force, 1518 .late_register = amdgpu_connector_late_register, 1519 }; 1520 1521 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1522 .dpms = drm_helper_connector_dpms, 1523 .detect = amdgpu_connector_dp_detect, 1524 .fill_modes = drm_helper_probe_single_connector_modes, 1525 .set_property = amdgpu_connector_set_lcd_property, 1526 .early_unregister = amdgpu_connector_unregister, 1527 .destroy = amdgpu_connector_destroy, 1528 .force = amdgpu_connector_dvi_force, 1529 .late_register = amdgpu_connector_late_register, 1530 }; 1531 1532 void 1533 amdgpu_connector_add(struct amdgpu_device *adev, 1534 uint32_t connector_id, 1535 uint32_t supported_device, 1536 int connector_type, 1537 struct amdgpu_i2c_bus_rec *i2c_bus, 1538 uint16_t connector_object_id, 1539 struct amdgpu_hpd *hpd, 1540 struct amdgpu_router *router) 1541 { 1542 struct drm_device *dev = adev_to_drm(adev); 1543 struct drm_connector *connector; 1544 struct drm_connector_list_iter iter; 1545 struct amdgpu_connector *amdgpu_connector; 1546 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1547 struct drm_encoder *encoder; 1548 struct amdgpu_encoder *amdgpu_encoder; 1549 struct i2c_adapter *ddc = NULL; 1550 uint32_t subpixel_order = SubPixelNone; 1551 bool shared_ddc = false; 1552 bool is_dp_bridge = false; 1553 bool has_aux = false; 1554 1555 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1556 return; 1557 1558 /* see if we already added it */ 1559 drm_connector_list_iter_begin(dev, &iter); 1560 drm_for_each_connector_iter(connector, &iter) { 1561 amdgpu_connector = to_amdgpu_connector(connector); 1562 if (amdgpu_connector->connector_id == connector_id) { 1563 amdgpu_connector->devices |= supported_device; 1564 drm_connector_list_iter_end(&iter); 1565 return; 1566 } 1567 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1568 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1569 amdgpu_connector->shared_ddc = true; 1570 shared_ddc = true; 1571 } 1572 if (amdgpu_connector->router_bus && router->ddc_valid && 1573 (amdgpu_connector->router.router_id == router->router_id)) { 1574 amdgpu_connector->shared_ddc = false; 1575 shared_ddc = false; 1576 } 1577 } 1578 } 1579 drm_connector_list_iter_end(&iter); 1580 1581 /* check if it's a dp bridge */ 1582 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1583 amdgpu_encoder = to_amdgpu_encoder(encoder); 1584 if (amdgpu_encoder->devices & supported_device) { 1585 switch (amdgpu_encoder->encoder_id) { 1586 case ENCODER_OBJECT_ID_TRAVIS: 1587 case ENCODER_OBJECT_ID_NUTMEG: 1588 is_dp_bridge = true; 1589 break; 1590 default: 1591 break; 1592 } 1593 } 1594 } 1595 1596 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1597 if (!amdgpu_connector) 1598 return; 1599 1600 connector = &amdgpu_connector->base; 1601 1602 amdgpu_connector->connector_id = connector_id; 1603 amdgpu_connector->devices = supported_device; 1604 amdgpu_connector->shared_ddc = shared_ddc; 1605 amdgpu_connector->connector_object_id = connector_object_id; 1606 amdgpu_connector->hpd = *hpd; 1607 1608 amdgpu_connector->router = *router; 1609 if (router->ddc_valid || router->cd_valid) { 1610 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1611 if (!amdgpu_connector->router_bus) 1612 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1613 } 1614 1615 if (is_dp_bridge) { 1616 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1617 if (!amdgpu_dig_connector) 1618 goto failed; 1619 amdgpu_connector->con_priv = amdgpu_dig_connector; 1620 if (i2c_bus->valid) { 1621 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1622 if (amdgpu_connector->ddc_bus) { 1623 has_aux = true; 1624 ddc = &amdgpu_connector->ddc_bus->adapter; 1625 } else { 1626 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1627 } 1628 } 1629 switch (connector_type) { 1630 case DRM_MODE_CONNECTOR_VGA: 1631 case DRM_MODE_CONNECTOR_DVIA: 1632 default: 1633 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1634 &amdgpu_connector_dp_funcs, 1635 connector_type, 1636 ddc); 1637 drm_connector_helper_add(&amdgpu_connector->base, 1638 &amdgpu_connector_dp_helper_funcs); 1639 connector->interlace_allowed = true; 1640 connector->doublescan_allowed = true; 1641 amdgpu_connector->dac_load_detect = true; 1642 drm_object_attach_property(&amdgpu_connector->base.base, 1643 adev->mode_info.load_detect_property, 1644 1); 1645 drm_object_attach_property(&amdgpu_connector->base.base, 1646 dev->mode_config.scaling_mode_property, 1647 DRM_MODE_SCALE_NONE); 1648 break; 1649 case DRM_MODE_CONNECTOR_DVII: 1650 case DRM_MODE_CONNECTOR_DVID: 1651 case DRM_MODE_CONNECTOR_HDMIA: 1652 case DRM_MODE_CONNECTOR_HDMIB: 1653 case DRM_MODE_CONNECTOR_DisplayPort: 1654 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1655 &amdgpu_connector_dp_funcs, 1656 connector_type, 1657 ddc); 1658 drm_connector_helper_add(&amdgpu_connector->base, 1659 &amdgpu_connector_dp_helper_funcs); 1660 drm_object_attach_property(&amdgpu_connector->base.base, 1661 adev->mode_info.underscan_property, 1662 UNDERSCAN_OFF); 1663 drm_object_attach_property(&amdgpu_connector->base.base, 1664 adev->mode_info.underscan_hborder_property, 1665 0); 1666 drm_object_attach_property(&amdgpu_connector->base.base, 1667 adev->mode_info.underscan_vborder_property, 1668 0); 1669 1670 drm_object_attach_property(&amdgpu_connector->base.base, 1671 dev->mode_config.scaling_mode_property, 1672 DRM_MODE_SCALE_NONE); 1673 1674 drm_object_attach_property(&amdgpu_connector->base.base, 1675 adev->mode_info.dither_property, 1676 AMDGPU_FMT_DITHER_DISABLE); 1677 1678 if (amdgpu_audio != 0) { 1679 drm_object_attach_property(&amdgpu_connector->base.base, 1680 adev->mode_info.audio_property, 1681 AMDGPU_AUDIO_AUTO); 1682 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1683 } 1684 1685 subpixel_order = SubPixelHorizontalRGB; 1686 connector->interlace_allowed = true; 1687 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1688 connector->doublescan_allowed = true; 1689 else 1690 connector->doublescan_allowed = false; 1691 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1692 amdgpu_connector->dac_load_detect = true; 1693 drm_object_attach_property(&amdgpu_connector->base.base, 1694 adev->mode_info.load_detect_property, 1695 1); 1696 } 1697 break; 1698 case DRM_MODE_CONNECTOR_LVDS: 1699 case DRM_MODE_CONNECTOR_eDP: 1700 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1701 &amdgpu_connector_edp_funcs, 1702 connector_type, 1703 ddc); 1704 drm_connector_helper_add(&amdgpu_connector->base, 1705 &amdgpu_connector_dp_helper_funcs); 1706 drm_object_attach_property(&amdgpu_connector->base.base, 1707 dev->mode_config.scaling_mode_property, 1708 DRM_MODE_SCALE_FULLSCREEN); 1709 subpixel_order = SubPixelHorizontalRGB; 1710 connector->interlace_allowed = false; 1711 connector->doublescan_allowed = false; 1712 break; 1713 } 1714 } else { 1715 switch (connector_type) { 1716 case DRM_MODE_CONNECTOR_VGA: 1717 if (i2c_bus->valid) { 1718 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1719 if (!amdgpu_connector->ddc_bus) 1720 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1721 else 1722 ddc = &amdgpu_connector->ddc_bus->adapter; 1723 } 1724 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1725 &amdgpu_connector_vga_funcs, 1726 connector_type, 1727 ddc); 1728 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1729 amdgpu_connector->dac_load_detect = true; 1730 drm_object_attach_property(&amdgpu_connector->base.base, 1731 adev->mode_info.load_detect_property, 1732 1); 1733 drm_object_attach_property(&amdgpu_connector->base.base, 1734 dev->mode_config.scaling_mode_property, 1735 DRM_MODE_SCALE_NONE); 1736 /* no HPD on analog connectors */ 1737 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1738 connector->interlace_allowed = true; 1739 connector->doublescan_allowed = true; 1740 break; 1741 case DRM_MODE_CONNECTOR_DVIA: 1742 if (i2c_bus->valid) { 1743 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1744 if (!amdgpu_connector->ddc_bus) 1745 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1746 else 1747 ddc = &amdgpu_connector->ddc_bus->adapter; 1748 } 1749 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1750 &amdgpu_connector_vga_funcs, 1751 connector_type, 1752 ddc); 1753 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1754 amdgpu_connector->dac_load_detect = true; 1755 drm_object_attach_property(&amdgpu_connector->base.base, 1756 adev->mode_info.load_detect_property, 1757 1); 1758 drm_object_attach_property(&amdgpu_connector->base.base, 1759 dev->mode_config.scaling_mode_property, 1760 DRM_MODE_SCALE_NONE); 1761 /* no HPD on analog connectors */ 1762 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1763 connector->interlace_allowed = true; 1764 connector->doublescan_allowed = true; 1765 break; 1766 case DRM_MODE_CONNECTOR_DVII: 1767 case DRM_MODE_CONNECTOR_DVID: 1768 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1769 if (!amdgpu_dig_connector) 1770 goto failed; 1771 amdgpu_connector->con_priv = amdgpu_dig_connector; 1772 if (i2c_bus->valid) { 1773 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1774 if (!amdgpu_connector->ddc_bus) 1775 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1776 else 1777 ddc = &amdgpu_connector->ddc_bus->adapter; 1778 } 1779 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1780 &amdgpu_connector_dvi_funcs, 1781 connector_type, 1782 ddc); 1783 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1784 subpixel_order = SubPixelHorizontalRGB; 1785 drm_object_attach_property(&amdgpu_connector->base.base, 1786 adev->mode_info.coherent_mode_property, 1787 1); 1788 drm_object_attach_property(&amdgpu_connector->base.base, 1789 adev->mode_info.underscan_property, 1790 UNDERSCAN_OFF); 1791 drm_object_attach_property(&amdgpu_connector->base.base, 1792 adev->mode_info.underscan_hborder_property, 1793 0); 1794 drm_object_attach_property(&amdgpu_connector->base.base, 1795 adev->mode_info.underscan_vborder_property, 1796 0); 1797 drm_object_attach_property(&amdgpu_connector->base.base, 1798 dev->mode_config.scaling_mode_property, 1799 DRM_MODE_SCALE_NONE); 1800 1801 if (amdgpu_audio != 0) { 1802 drm_object_attach_property(&amdgpu_connector->base.base, 1803 adev->mode_info.audio_property, 1804 AMDGPU_AUDIO_AUTO); 1805 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1806 } 1807 drm_object_attach_property(&amdgpu_connector->base.base, 1808 adev->mode_info.dither_property, 1809 AMDGPU_FMT_DITHER_DISABLE); 1810 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1811 amdgpu_connector->dac_load_detect = true; 1812 drm_object_attach_property(&amdgpu_connector->base.base, 1813 adev->mode_info.load_detect_property, 1814 1); 1815 } 1816 connector->interlace_allowed = true; 1817 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1818 connector->doublescan_allowed = true; 1819 else 1820 connector->doublescan_allowed = false; 1821 break; 1822 case DRM_MODE_CONNECTOR_HDMIA: 1823 case DRM_MODE_CONNECTOR_HDMIB: 1824 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1825 if (!amdgpu_dig_connector) 1826 goto failed; 1827 amdgpu_connector->con_priv = amdgpu_dig_connector; 1828 if (i2c_bus->valid) { 1829 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1830 if (!amdgpu_connector->ddc_bus) 1831 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1832 else 1833 ddc = &amdgpu_connector->ddc_bus->adapter; 1834 } 1835 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1836 &amdgpu_connector_dvi_funcs, 1837 connector_type, 1838 ddc); 1839 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1840 drm_object_attach_property(&amdgpu_connector->base.base, 1841 adev->mode_info.coherent_mode_property, 1842 1); 1843 drm_object_attach_property(&amdgpu_connector->base.base, 1844 adev->mode_info.underscan_property, 1845 UNDERSCAN_OFF); 1846 drm_object_attach_property(&amdgpu_connector->base.base, 1847 adev->mode_info.underscan_hborder_property, 1848 0); 1849 drm_object_attach_property(&amdgpu_connector->base.base, 1850 adev->mode_info.underscan_vborder_property, 1851 0); 1852 drm_object_attach_property(&amdgpu_connector->base.base, 1853 dev->mode_config.scaling_mode_property, 1854 DRM_MODE_SCALE_NONE); 1855 if (amdgpu_audio != 0) { 1856 drm_object_attach_property(&amdgpu_connector->base.base, 1857 adev->mode_info.audio_property, 1858 AMDGPU_AUDIO_AUTO); 1859 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1860 } 1861 drm_object_attach_property(&amdgpu_connector->base.base, 1862 adev->mode_info.dither_property, 1863 AMDGPU_FMT_DITHER_DISABLE); 1864 subpixel_order = SubPixelHorizontalRGB; 1865 connector->interlace_allowed = true; 1866 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1867 connector->doublescan_allowed = true; 1868 else 1869 connector->doublescan_allowed = false; 1870 break; 1871 case DRM_MODE_CONNECTOR_DisplayPort: 1872 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1873 if (!amdgpu_dig_connector) 1874 goto failed; 1875 amdgpu_connector->con_priv = amdgpu_dig_connector; 1876 if (i2c_bus->valid) { 1877 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1878 if (amdgpu_connector->ddc_bus) { 1879 has_aux = true; 1880 ddc = &amdgpu_connector->ddc_bus->adapter; 1881 } else { 1882 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1883 } 1884 } 1885 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1886 &amdgpu_connector_dp_funcs, 1887 connector_type, 1888 ddc); 1889 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1890 subpixel_order = SubPixelHorizontalRGB; 1891 drm_object_attach_property(&amdgpu_connector->base.base, 1892 adev->mode_info.coherent_mode_property, 1893 1); 1894 drm_object_attach_property(&amdgpu_connector->base.base, 1895 adev->mode_info.underscan_property, 1896 UNDERSCAN_OFF); 1897 drm_object_attach_property(&amdgpu_connector->base.base, 1898 adev->mode_info.underscan_hborder_property, 1899 0); 1900 drm_object_attach_property(&amdgpu_connector->base.base, 1901 adev->mode_info.underscan_vborder_property, 1902 0); 1903 drm_object_attach_property(&amdgpu_connector->base.base, 1904 dev->mode_config.scaling_mode_property, 1905 DRM_MODE_SCALE_NONE); 1906 if (amdgpu_audio != 0) { 1907 drm_object_attach_property(&amdgpu_connector->base.base, 1908 adev->mode_info.audio_property, 1909 AMDGPU_AUDIO_AUTO); 1910 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1911 } 1912 drm_object_attach_property(&amdgpu_connector->base.base, 1913 adev->mode_info.dither_property, 1914 AMDGPU_FMT_DITHER_DISABLE); 1915 connector->interlace_allowed = true; 1916 /* in theory with a DP to VGA converter... */ 1917 connector->doublescan_allowed = false; 1918 break; 1919 case DRM_MODE_CONNECTOR_eDP: 1920 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1921 if (!amdgpu_dig_connector) 1922 goto failed; 1923 amdgpu_connector->con_priv = amdgpu_dig_connector; 1924 if (i2c_bus->valid) { 1925 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1926 if (amdgpu_connector->ddc_bus) { 1927 has_aux = true; 1928 ddc = &amdgpu_connector->ddc_bus->adapter; 1929 } else { 1930 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1931 } 1932 } 1933 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1934 &amdgpu_connector_edp_funcs, 1935 connector_type, 1936 ddc); 1937 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1938 drm_object_attach_property(&amdgpu_connector->base.base, 1939 dev->mode_config.scaling_mode_property, 1940 DRM_MODE_SCALE_FULLSCREEN); 1941 subpixel_order = SubPixelHorizontalRGB; 1942 connector->interlace_allowed = false; 1943 connector->doublescan_allowed = false; 1944 break; 1945 case DRM_MODE_CONNECTOR_LVDS: 1946 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1947 if (!amdgpu_dig_connector) 1948 goto failed; 1949 amdgpu_connector->con_priv = amdgpu_dig_connector; 1950 if (i2c_bus->valid) { 1951 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1952 if (!amdgpu_connector->ddc_bus) 1953 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1954 else 1955 ddc = &amdgpu_connector->ddc_bus->adapter; 1956 } 1957 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1958 &amdgpu_connector_lvds_funcs, 1959 connector_type, 1960 ddc); 1961 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1962 drm_object_attach_property(&amdgpu_connector->base.base, 1963 dev->mode_config.scaling_mode_property, 1964 DRM_MODE_SCALE_FULLSCREEN); 1965 subpixel_order = SubPixelHorizontalRGB; 1966 connector->interlace_allowed = false; 1967 connector->doublescan_allowed = false; 1968 break; 1969 } 1970 } 1971 1972 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1973 if (i2c_bus->valid) { 1974 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1975 DRM_CONNECTOR_POLL_DISCONNECT; 1976 } 1977 } else 1978 connector->polled = DRM_CONNECTOR_POLL_HPD; 1979 1980 connector->display_info.subpixel_order = subpixel_order; 1981 1982 if (has_aux) 1983 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1984 1985 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1986 connector_type == DRM_MODE_CONNECTOR_eDP) { 1987 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 1988 } 1989 1990 return; 1991 1992 failed: 1993 drm_connector_cleanup(connector); 1994 kfree(connector); 1995 } 1996