1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73 int saved_dpms = connector->dpms; 74 /* Only turn off the display if it's physically disconnected */ 75 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't try to start link training before we 79 * have the dpcd */ 80 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 return; 82 83 /* set it to OFF so that drm_helper_connector_dpms() 84 * won't return immediately since the current state 85 * is ON at this point. 86 */ 87 connector->dpms = DRM_MODE_DPMS_OFF; 88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89 } 90 connector->dpms = saved_dpms; 91 } 92 } 93 } 94 95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 96 { 97 struct drm_crtc *crtc = encoder->crtc; 98 99 if (crtc && crtc->enabled) { 100 drm_crtc_helper_set_mode(crtc, &crtc->mode, 101 crtc->x, crtc->y, crtc->primary->fb); 102 } 103 } 104 105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 106 { 107 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 108 struct amdgpu_connector_atom_dig *dig_connector; 109 int bpc = 8; 110 unsigned mode_clock, max_tmds_clock; 111 112 switch (connector->connector_type) { 113 case DRM_MODE_CONNECTOR_DVII: 114 case DRM_MODE_CONNECTOR_HDMIB: 115 if (amdgpu_connector->use_digital) { 116 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 117 if (connector->display_info.bpc) 118 bpc = connector->display_info.bpc; 119 } 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DVID: 123 case DRM_MODE_CONNECTOR_HDMIA: 124 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 125 if (connector->display_info.bpc) 126 bpc = connector->display_info.bpc; 127 } 128 break; 129 case DRM_MODE_CONNECTOR_DisplayPort: 130 dig_connector = amdgpu_connector->con_priv; 131 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 132 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 133 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 134 if (connector->display_info.bpc) 135 bpc = connector->display_info.bpc; 136 } 137 break; 138 case DRM_MODE_CONNECTOR_eDP: 139 case DRM_MODE_CONNECTOR_LVDS: 140 if (connector->display_info.bpc) 141 bpc = connector->display_info.bpc; 142 else { 143 const struct drm_connector_helper_funcs *connector_funcs = 144 connector->helper_private; 145 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 146 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 147 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 148 149 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 150 bpc = 6; 151 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 152 bpc = 8; 153 } 154 break; 155 } 156 157 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 158 /* 159 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 160 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 161 * 12 bpc is always supported on hdmi deep color sinks, as this is 162 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 163 */ 164 if (bpc > 12) { 165 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 166 connector->name, bpc); 167 bpc = 12; 168 } 169 170 /* Any defined maximum tmds clock limit we must not exceed? */ 171 if (connector->display_info.max_tmds_clock > 0) { 172 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 173 mode_clock = amdgpu_connector->pixelclock_for_modeset; 174 175 /* Maximum allowable input clock in kHz */ 176 max_tmds_clock = connector->display_info.max_tmds_clock; 177 178 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 179 connector->name, mode_clock, max_tmds_clock); 180 181 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 182 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 183 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 184 (mode_clock * 5/4 <= max_tmds_clock)) 185 bpc = 10; 186 else 187 bpc = 8; 188 189 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 190 connector->name, bpc); 191 } 192 193 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 194 bpc = 8; 195 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 196 connector->name, bpc); 197 } 198 } else if (bpc > 8) { 199 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 200 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 201 connector->name); 202 bpc = 8; 203 } 204 } 205 206 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 207 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 208 connector->name); 209 bpc = 8; 210 } 211 212 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 213 connector->name, connector->display_info.bpc, bpc); 214 215 return bpc; 216 } 217 218 static void 219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 220 enum drm_connector_status status) 221 { 222 struct drm_encoder *best_encoder = NULL; 223 struct drm_encoder *encoder = NULL; 224 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 225 bool connected; 226 int i; 227 228 best_encoder = connector_funcs->best_encoder(connector); 229 230 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 231 if (connector->encoder_ids[i] == 0) 232 break; 233 234 encoder = drm_encoder_find(connector->dev, 235 connector->encoder_ids[i]); 236 if (!encoder) 237 continue; 238 239 if ((encoder == best_encoder) && (status == connector_status_connected)) 240 connected = true; 241 else 242 connected = false; 243 244 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 245 246 } 247 } 248 249 static struct drm_encoder * 250 amdgpu_connector_find_encoder(struct drm_connector *connector, 251 int encoder_type) 252 { 253 struct drm_encoder *encoder; 254 int i; 255 256 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 257 if (connector->encoder_ids[i] == 0) 258 break; 259 encoder = drm_encoder_find(connector->dev, 260 connector->encoder_ids[i]); 261 if (!encoder) 262 continue; 263 264 if (encoder->encoder_type == encoder_type) 265 return encoder; 266 } 267 return NULL; 268 } 269 270 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 271 { 272 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 273 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 274 275 if (amdgpu_connector->edid) { 276 return amdgpu_connector->edid; 277 } else if (edid_blob) { 278 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 279 if (edid) 280 amdgpu_connector->edid = edid; 281 } 282 return amdgpu_connector->edid; 283 } 284 285 static struct edid * 286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 287 { 288 struct edid *edid; 289 290 if (adev->mode_info.bios_hardcoded_edid) { 291 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 292 if (edid) { 293 memcpy((unsigned char *)edid, 294 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 295 adev->mode_info.bios_hardcoded_edid_size); 296 return edid; 297 } 298 } 299 return NULL; 300 } 301 302 static void amdgpu_connector_get_edid(struct drm_connector *connector) 303 { 304 struct drm_device *dev = connector->dev; 305 struct amdgpu_device *adev = dev->dev_private; 306 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307 308 if (amdgpu_connector->edid) 309 return; 310 311 /* on hw with routers, select right port */ 312 if (amdgpu_connector->router.ddc_valid) 313 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 314 315 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 316 ENCODER_OBJECT_ID_NONE) && 317 amdgpu_connector->ddc_bus->has_aux) { 318 amdgpu_connector->edid = drm_get_edid(connector, 319 &amdgpu_connector->ddc_bus->aux.ddc); 320 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 321 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 322 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 323 324 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 325 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 326 amdgpu_connector->ddc_bus->has_aux) 327 amdgpu_connector->edid = drm_get_edid(connector, 328 &amdgpu_connector->ddc_bus->aux.ddc); 329 else if (amdgpu_connector->ddc_bus) 330 amdgpu_connector->edid = drm_get_edid(connector, 331 &amdgpu_connector->ddc_bus->adapter); 332 } else if (amdgpu_connector->ddc_bus) { 333 amdgpu_connector->edid = drm_get_edid(connector, 334 &amdgpu_connector->ddc_bus->adapter); 335 } 336 337 if (!amdgpu_connector->edid) { 338 /* some laptops provide a hardcoded edid in rom for LCDs */ 339 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 340 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 341 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 342 } 343 } 344 345 static void amdgpu_connector_free_edid(struct drm_connector *connector) 346 { 347 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 348 349 if (amdgpu_connector->edid) { 350 kfree(amdgpu_connector->edid); 351 amdgpu_connector->edid = NULL; 352 } 353 } 354 355 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 356 { 357 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 358 int ret; 359 360 if (amdgpu_connector->edid) { 361 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 362 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 363 drm_edid_to_eld(connector, amdgpu_connector->edid); 364 return ret; 365 } 366 drm_mode_connector_update_edid_property(connector, NULL); 367 return 0; 368 } 369 370 static struct drm_encoder * 371 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 372 { 373 int enc_id = connector->encoder_ids[0]; 374 375 /* pick the encoder ids */ 376 if (enc_id) 377 return drm_encoder_find(connector->dev, enc_id); 378 return NULL; 379 } 380 381 static void amdgpu_get_native_mode(struct drm_connector *connector) 382 { 383 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 384 struct amdgpu_encoder *amdgpu_encoder; 385 386 if (encoder == NULL) 387 return; 388 389 amdgpu_encoder = to_amdgpu_encoder(encoder); 390 391 if (!list_empty(&connector->probed_modes)) { 392 struct drm_display_mode *preferred_mode = 393 list_first_entry(&connector->probed_modes, 394 struct drm_display_mode, head); 395 396 amdgpu_encoder->native_mode = *preferred_mode; 397 } else { 398 amdgpu_encoder->native_mode.clock = 0; 399 } 400 } 401 402 static struct drm_display_mode * 403 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 404 { 405 struct drm_device *dev = encoder->dev; 406 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 407 struct drm_display_mode *mode = NULL; 408 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 409 410 if (native_mode->hdisplay != 0 && 411 native_mode->vdisplay != 0 && 412 native_mode->clock != 0) { 413 mode = drm_mode_duplicate(dev, native_mode); 414 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 415 drm_mode_set_name(mode); 416 417 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 418 } else if (native_mode->hdisplay != 0 && 419 native_mode->vdisplay != 0) { 420 /* mac laptops without an edid */ 421 /* Note that this is not necessarily the exact panel mode, 422 * but an approximation based on the cvt formula. For these 423 * systems we should ideally read the mode info out of the 424 * registers or add a mode table, but this works and is much 425 * simpler. 426 */ 427 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 428 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 429 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 430 } 431 return mode; 432 } 433 434 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 435 struct drm_connector *connector) 436 { 437 struct drm_device *dev = encoder->dev; 438 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 439 struct drm_display_mode *mode = NULL; 440 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 441 int i; 442 static const struct mode_size { 443 int w; 444 int h; 445 } common_modes[17] = { 446 { 640, 480}, 447 { 720, 480}, 448 { 800, 600}, 449 { 848, 480}, 450 {1024, 768}, 451 {1152, 768}, 452 {1280, 720}, 453 {1280, 800}, 454 {1280, 854}, 455 {1280, 960}, 456 {1280, 1024}, 457 {1440, 900}, 458 {1400, 1050}, 459 {1680, 1050}, 460 {1600, 1200}, 461 {1920, 1080}, 462 {1920, 1200} 463 }; 464 465 for (i = 0; i < 17; i++) { 466 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 467 if (common_modes[i].w > 1024 || 468 common_modes[i].h > 768) 469 continue; 470 } 471 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 472 if (common_modes[i].w > native_mode->hdisplay || 473 common_modes[i].h > native_mode->vdisplay || 474 (common_modes[i].w == native_mode->hdisplay && 475 common_modes[i].h == native_mode->vdisplay)) 476 continue; 477 } 478 if (common_modes[i].w < 320 || common_modes[i].h < 200) 479 continue; 480 481 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 482 drm_mode_probed_add(connector, mode); 483 } 484 } 485 486 static int amdgpu_connector_set_property(struct drm_connector *connector, 487 struct drm_property *property, 488 uint64_t val) 489 { 490 struct drm_device *dev = connector->dev; 491 struct amdgpu_device *adev = dev->dev_private; 492 struct drm_encoder *encoder; 493 struct amdgpu_encoder *amdgpu_encoder; 494 495 if (property == adev->mode_info.coherent_mode_property) { 496 struct amdgpu_encoder_atom_dig *dig; 497 bool new_coherent_mode; 498 499 /* need to find digital encoder on connector */ 500 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 501 if (!encoder) 502 return 0; 503 504 amdgpu_encoder = to_amdgpu_encoder(encoder); 505 506 if (!amdgpu_encoder->enc_priv) 507 return 0; 508 509 dig = amdgpu_encoder->enc_priv; 510 new_coherent_mode = val ? true : false; 511 if (dig->coherent_mode != new_coherent_mode) { 512 dig->coherent_mode = new_coherent_mode; 513 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 514 } 515 } 516 517 if (property == adev->mode_info.audio_property) { 518 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 519 /* need to find digital encoder on connector */ 520 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 521 if (!encoder) 522 return 0; 523 524 amdgpu_encoder = to_amdgpu_encoder(encoder); 525 526 if (amdgpu_connector->audio != val) { 527 amdgpu_connector->audio = val; 528 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 529 } 530 } 531 532 if (property == adev->mode_info.dither_property) { 533 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 534 /* need to find digital encoder on connector */ 535 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 536 if (!encoder) 537 return 0; 538 539 amdgpu_encoder = to_amdgpu_encoder(encoder); 540 541 if (amdgpu_connector->dither != val) { 542 amdgpu_connector->dither = val; 543 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 544 } 545 } 546 547 if (property == adev->mode_info.underscan_property) { 548 /* need to find digital encoder on connector */ 549 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 550 if (!encoder) 551 return 0; 552 553 amdgpu_encoder = to_amdgpu_encoder(encoder); 554 555 if (amdgpu_encoder->underscan_type != val) { 556 amdgpu_encoder->underscan_type = val; 557 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 558 } 559 } 560 561 if (property == adev->mode_info.underscan_hborder_property) { 562 /* need to find digital encoder on connector */ 563 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 564 if (!encoder) 565 return 0; 566 567 amdgpu_encoder = to_amdgpu_encoder(encoder); 568 569 if (amdgpu_encoder->underscan_hborder != val) { 570 amdgpu_encoder->underscan_hborder = val; 571 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 572 } 573 } 574 575 if (property == adev->mode_info.underscan_vborder_property) { 576 /* need to find digital encoder on connector */ 577 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 578 if (!encoder) 579 return 0; 580 581 amdgpu_encoder = to_amdgpu_encoder(encoder); 582 583 if (amdgpu_encoder->underscan_vborder != val) { 584 amdgpu_encoder->underscan_vborder = val; 585 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 586 } 587 } 588 589 if (property == adev->mode_info.load_detect_property) { 590 struct amdgpu_connector *amdgpu_connector = 591 to_amdgpu_connector(connector); 592 593 if (val == 0) 594 amdgpu_connector->dac_load_detect = false; 595 else 596 amdgpu_connector->dac_load_detect = true; 597 } 598 599 if (property == dev->mode_config.scaling_mode_property) { 600 enum amdgpu_rmx_type rmx_type; 601 602 if (connector->encoder) { 603 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 604 } else { 605 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 606 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 607 } 608 609 switch (val) { 610 default: 611 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 612 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 613 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 614 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 615 } 616 if (amdgpu_encoder->rmx_type == rmx_type) 617 return 0; 618 619 if ((rmx_type != DRM_MODE_SCALE_NONE) && 620 (amdgpu_encoder->native_mode.clock == 0)) 621 return 0; 622 623 amdgpu_encoder->rmx_type = rmx_type; 624 625 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 626 } 627 628 return 0; 629 } 630 631 static void 632 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 633 struct drm_connector *connector) 634 { 635 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 636 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 637 struct drm_display_mode *t, *mode; 638 639 /* If the EDID preferred mode doesn't match the native mode, use it */ 640 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 641 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 642 if (mode->hdisplay != native_mode->hdisplay || 643 mode->vdisplay != native_mode->vdisplay) 644 memcpy(native_mode, mode, sizeof(*mode)); 645 } 646 } 647 648 /* Try to get native mode details from EDID if necessary */ 649 if (!native_mode->clock) { 650 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 651 if (mode->hdisplay == native_mode->hdisplay && 652 mode->vdisplay == native_mode->vdisplay) { 653 *native_mode = *mode; 654 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 655 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 656 break; 657 } 658 } 659 } 660 661 if (!native_mode->clock) { 662 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 663 amdgpu_encoder->rmx_type = RMX_OFF; 664 } 665 } 666 667 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 668 { 669 struct drm_encoder *encoder; 670 int ret = 0; 671 struct drm_display_mode *mode; 672 673 amdgpu_connector_get_edid(connector); 674 ret = amdgpu_connector_ddc_get_modes(connector); 675 if (ret > 0) { 676 encoder = amdgpu_connector_best_single_encoder(connector); 677 if (encoder) { 678 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 679 /* add scaled modes */ 680 amdgpu_connector_add_common_modes(encoder, connector); 681 } 682 return ret; 683 } 684 685 encoder = amdgpu_connector_best_single_encoder(connector); 686 if (!encoder) 687 return 0; 688 689 /* we have no EDID modes */ 690 mode = amdgpu_connector_lcd_native_mode(encoder); 691 if (mode) { 692 ret = 1; 693 drm_mode_probed_add(connector, mode); 694 /* add the width/height from vbios tables if available */ 695 connector->display_info.width_mm = mode->width_mm; 696 connector->display_info.height_mm = mode->height_mm; 697 /* add scaled modes */ 698 amdgpu_connector_add_common_modes(encoder, connector); 699 } 700 701 return ret; 702 } 703 704 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 705 struct drm_display_mode *mode) 706 { 707 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708 709 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 710 return MODE_PANEL; 711 712 if (encoder) { 713 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 714 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 715 716 /* AVIVO hardware supports downscaling modes larger than the panel 717 * to the panel size, but I'm not sure this is desirable. 718 */ 719 if ((mode->hdisplay > native_mode->hdisplay) || 720 (mode->vdisplay > native_mode->vdisplay)) 721 return MODE_PANEL; 722 723 /* if scaling is disabled, block non-native modes */ 724 if (amdgpu_encoder->rmx_type == RMX_OFF) { 725 if ((mode->hdisplay != native_mode->hdisplay) || 726 (mode->vdisplay != native_mode->vdisplay)) 727 return MODE_PANEL; 728 } 729 } 730 731 return MODE_OK; 732 } 733 734 static enum drm_connector_status 735 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 736 { 737 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 738 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 739 enum drm_connector_status ret = connector_status_disconnected; 740 int r; 741 742 r = pm_runtime_get_sync(connector->dev->dev); 743 if (r < 0) 744 return connector_status_disconnected; 745 746 if (encoder) { 747 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 748 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 749 750 /* check if panel is valid */ 751 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 752 ret = connector_status_connected; 753 754 } 755 756 /* check for edid as well */ 757 amdgpu_connector_get_edid(connector); 758 if (amdgpu_connector->edid) 759 ret = connector_status_connected; 760 /* check acpi lid status ??? */ 761 762 amdgpu_connector_update_scratch_regs(connector, ret); 763 pm_runtime_mark_last_busy(connector->dev->dev); 764 pm_runtime_put_autosuspend(connector->dev->dev); 765 return ret; 766 } 767 768 static void amdgpu_connector_unregister(struct drm_connector *connector) 769 { 770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 771 772 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 773 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 774 amdgpu_connector->ddc_bus->has_aux = false; 775 } 776 } 777 778 static void amdgpu_connector_destroy(struct drm_connector *connector) 779 { 780 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 781 782 amdgpu_connector_free_edid(connector); 783 kfree(amdgpu_connector->con_priv); 784 drm_connector_unregister(connector); 785 drm_connector_cleanup(connector); 786 kfree(connector); 787 } 788 789 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 790 struct drm_property *property, 791 uint64_t value) 792 { 793 struct drm_device *dev = connector->dev; 794 struct amdgpu_encoder *amdgpu_encoder; 795 enum amdgpu_rmx_type rmx_type; 796 797 DRM_DEBUG_KMS("\n"); 798 if (property != dev->mode_config.scaling_mode_property) 799 return 0; 800 801 if (connector->encoder) 802 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 803 else { 804 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 805 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 806 } 807 808 switch (value) { 809 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 810 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 811 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 812 default: 813 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 814 } 815 if (amdgpu_encoder->rmx_type == rmx_type) 816 return 0; 817 818 amdgpu_encoder->rmx_type = rmx_type; 819 820 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 821 return 0; 822 } 823 824 825 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 826 .get_modes = amdgpu_connector_lvds_get_modes, 827 .mode_valid = amdgpu_connector_lvds_mode_valid, 828 .best_encoder = amdgpu_connector_best_single_encoder, 829 }; 830 831 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 832 .dpms = drm_helper_connector_dpms, 833 .detect = amdgpu_connector_lvds_detect, 834 .fill_modes = drm_helper_probe_single_connector_modes, 835 .early_unregister = amdgpu_connector_unregister, 836 .destroy = amdgpu_connector_destroy, 837 .set_property = amdgpu_connector_set_lcd_property, 838 }; 839 840 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 841 { 842 int ret; 843 844 amdgpu_connector_get_edid(connector); 845 ret = amdgpu_connector_ddc_get_modes(connector); 846 847 return ret; 848 } 849 850 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 851 struct drm_display_mode *mode) 852 { 853 struct drm_device *dev = connector->dev; 854 struct amdgpu_device *adev = dev->dev_private; 855 856 /* XXX check mode bandwidth */ 857 858 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 859 return MODE_CLOCK_HIGH; 860 861 return MODE_OK; 862 } 863 864 static enum drm_connector_status 865 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 866 { 867 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 868 struct drm_encoder *encoder; 869 const struct drm_encoder_helper_funcs *encoder_funcs; 870 bool dret = false; 871 enum drm_connector_status ret = connector_status_disconnected; 872 int r; 873 874 r = pm_runtime_get_sync(connector->dev->dev); 875 if (r < 0) 876 return connector_status_disconnected; 877 878 encoder = amdgpu_connector_best_single_encoder(connector); 879 if (!encoder) 880 ret = connector_status_disconnected; 881 882 if (amdgpu_connector->ddc_bus) 883 dret = amdgpu_ddc_probe(amdgpu_connector, false); 884 if (dret) { 885 amdgpu_connector->detected_by_load = false; 886 amdgpu_connector_free_edid(connector); 887 amdgpu_connector_get_edid(connector); 888 889 if (!amdgpu_connector->edid) { 890 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 891 connector->name); 892 ret = connector_status_connected; 893 } else { 894 amdgpu_connector->use_digital = 895 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 896 897 /* some oems have boards with separate digital and analog connectors 898 * with a shared ddc line (often vga + hdmi) 899 */ 900 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 901 amdgpu_connector_free_edid(connector); 902 ret = connector_status_disconnected; 903 } else { 904 ret = connector_status_connected; 905 } 906 } 907 } else { 908 909 /* if we aren't forcing don't do destructive polling */ 910 if (!force) { 911 /* only return the previous status if we last 912 * detected a monitor via load. 913 */ 914 if (amdgpu_connector->detected_by_load) 915 ret = connector->status; 916 goto out; 917 } 918 919 if (amdgpu_connector->dac_load_detect && encoder) { 920 encoder_funcs = encoder->helper_private; 921 ret = encoder_funcs->detect(encoder, connector); 922 if (ret != connector_status_disconnected) 923 amdgpu_connector->detected_by_load = true; 924 } 925 } 926 927 amdgpu_connector_update_scratch_regs(connector, ret); 928 929 out: 930 pm_runtime_mark_last_busy(connector->dev->dev); 931 pm_runtime_put_autosuspend(connector->dev->dev); 932 933 return ret; 934 } 935 936 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 937 .get_modes = amdgpu_connector_vga_get_modes, 938 .mode_valid = amdgpu_connector_vga_mode_valid, 939 .best_encoder = amdgpu_connector_best_single_encoder, 940 }; 941 942 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 943 .dpms = drm_helper_connector_dpms, 944 .detect = amdgpu_connector_vga_detect, 945 .fill_modes = drm_helper_probe_single_connector_modes, 946 .early_unregister = amdgpu_connector_unregister, 947 .destroy = amdgpu_connector_destroy, 948 .set_property = amdgpu_connector_set_property, 949 }; 950 951 static bool 952 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 953 { 954 struct drm_device *dev = connector->dev; 955 struct amdgpu_device *adev = dev->dev_private; 956 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 957 enum drm_connector_status status; 958 959 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 960 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 961 status = connector_status_connected; 962 else 963 status = connector_status_disconnected; 964 if (connector->status == status) 965 return true; 966 } 967 968 return false; 969 } 970 971 /* 972 * DVI is complicated 973 * Do a DDC probe, if DDC probe passes, get the full EDID so 974 * we can do analog/digital monitor detection at this point. 975 * If the monitor is an analog monitor or we got no DDC, 976 * we need to find the DAC encoder object for this connector. 977 * If we got no DDC, we do load detection on the DAC encoder object. 978 * If we got analog DDC or load detection passes on the DAC encoder 979 * we have to check if this analog encoder is shared with anyone else (TV) 980 * if its shared we have to set the other connector to disconnected. 981 */ 982 static enum drm_connector_status 983 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 984 { 985 struct drm_device *dev = connector->dev; 986 struct amdgpu_device *adev = dev->dev_private; 987 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 988 struct drm_encoder *encoder = NULL; 989 const struct drm_encoder_helper_funcs *encoder_funcs; 990 int i, r; 991 enum drm_connector_status ret = connector_status_disconnected; 992 bool dret = false, broken_edid = false; 993 994 r = pm_runtime_get_sync(connector->dev->dev); 995 if (r < 0) 996 return connector_status_disconnected; 997 998 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 999 ret = connector->status; 1000 goto exit; 1001 } 1002 1003 if (amdgpu_connector->ddc_bus) 1004 dret = amdgpu_ddc_probe(amdgpu_connector, false); 1005 if (dret) { 1006 amdgpu_connector->detected_by_load = false; 1007 amdgpu_connector_free_edid(connector); 1008 amdgpu_connector_get_edid(connector); 1009 1010 if (!amdgpu_connector->edid) { 1011 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1012 connector->name); 1013 ret = connector_status_connected; 1014 broken_edid = true; /* defer use_digital to later */ 1015 } else { 1016 amdgpu_connector->use_digital = 1017 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1018 1019 /* some oems have boards with separate digital and analog connectors 1020 * with a shared ddc line (often vga + hdmi) 1021 */ 1022 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1023 amdgpu_connector_free_edid(connector); 1024 ret = connector_status_disconnected; 1025 } else { 1026 ret = connector_status_connected; 1027 } 1028 1029 /* This gets complicated. We have boards with VGA + HDMI with a 1030 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1031 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1032 * you don't really know what's connected to which port as both are digital. 1033 */ 1034 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1035 struct drm_connector *list_connector; 1036 struct amdgpu_connector *list_amdgpu_connector; 1037 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1038 if (connector == list_connector) 1039 continue; 1040 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1041 if (list_amdgpu_connector->shared_ddc && 1042 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1043 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1044 /* cases where both connectors are digital */ 1045 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1046 /* hpd is our only option in this case */ 1047 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1048 amdgpu_connector_free_edid(connector); 1049 ret = connector_status_disconnected; 1050 } 1051 } 1052 } 1053 } 1054 } 1055 } 1056 } 1057 1058 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1059 goto out; 1060 1061 /* DVI-D and HDMI-A are digital only */ 1062 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1063 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1064 goto out; 1065 1066 /* if we aren't forcing don't do destructive polling */ 1067 if (!force) { 1068 /* only return the previous status if we last 1069 * detected a monitor via load. 1070 */ 1071 if (amdgpu_connector->detected_by_load) 1072 ret = connector->status; 1073 goto out; 1074 } 1075 1076 /* find analog encoder */ 1077 if (amdgpu_connector->dac_load_detect) { 1078 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1079 if (connector->encoder_ids[i] == 0) 1080 break; 1081 1082 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1083 if (!encoder) 1084 continue; 1085 1086 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1087 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1088 continue; 1089 1090 encoder_funcs = encoder->helper_private; 1091 if (encoder_funcs->detect) { 1092 if (!broken_edid) { 1093 if (ret != connector_status_connected) { 1094 /* deal with analog monitors without DDC */ 1095 ret = encoder_funcs->detect(encoder, connector); 1096 if (ret == connector_status_connected) { 1097 amdgpu_connector->use_digital = false; 1098 } 1099 if (ret != connector_status_disconnected) 1100 amdgpu_connector->detected_by_load = true; 1101 } 1102 } else { 1103 enum drm_connector_status lret; 1104 /* assume digital unless load detected otherwise */ 1105 amdgpu_connector->use_digital = true; 1106 lret = encoder_funcs->detect(encoder, connector); 1107 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1108 if (lret == connector_status_connected) 1109 amdgpu_connector->use_digital = false; 1110 } 1111 break; 1112 } 1113 } 1114 } 1115 1116 out: 1117 /* updated in get modes as well since we need to know if it's analog or digital */ 1118 amdgpu_connector_update_scratch_regs(connector, ret); 1119 1120 exit: 1121 pm_runtime_mark_last_busy(connector->dev->dev); 1122 pm_runtime_put_autosuspend(connector->dev->dev); 1123 1124 return ret; 1125 } 1126 1127 /* okay need to be smart in here about which encoder to pick */ 1128 static struct drm_encoder * 1129 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1130 { 1131 int enc_id = connector->encoder_ids[0]; 1132 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1133 struct drm_encoder *encoder; 1134 int i; 1135 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1136 if (connector->encoder_ids[i] == 0) 1137 break; 1138 1139 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1140 if (!encoder) 1141 continue; 1142 1143 if (amdgpu_connector->use_digital == true) { 1144 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1145 return encoder; 1146 } else { 1147 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1148 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1149 return encoder; 1150 } 1151 } 1152 1153 /* see if we have a default encoder TODO */ 1154 1155 /* then check use digitial */ 1156 /* pick the first one */ 1157 if (enc_id) 1158 return drm_encoder_find(connector->dev, enc_id); 1159 return NULL; 1160 } 1161 1162 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1163 { 1164 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1165 if (connector->force == DRM_FORCE_ON) 1166 amdgpu_connector->use_digital = false; 1167 if (connector->force == DRM_FORCE_ON_DIGITAL) 1168 amdgpu_connector->use_digital = true; 1169 } 1170 1171 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1172 struct drm_display_mode *mode) 1173 { 1174 struct drm_device *dev = connector->dev; 1175 struct amdgpu_device *adev = dev->dev_private; 1176 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1177 1178 /* XXX check mode bandwidth */ 1179 1180 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1181 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1182 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1183 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1184 return MODE_OK; 1185 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1186 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1187 if (mode->clock > 340000) 1188 return MODE_CLOCK_HIGH; 1189 else 1190 return MODE_OK; 1191 } else { 1192 return MODE_CLOCK_HIGH; 1193 } 1194 } 1195 1196 /* check against the max pixel clock */ 1197 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1198 return MODE_CLOCK_HIGH; 1199 1200 return MODE_OK; 1201 } 1202 1203 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1204 .get_modes = amdgpu_connector_vga_get_modes, 1205 .mode_valid = amdgpu_connector_dvi_mode_valid, 1206 .best_encoder = amdgpu_connector_dvi_encoder, 1207 }; 1208 1209 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1210 .dpms = drm_helper_connector_dpms, 1211 .detect = amdgpu_connector_dvi_detect, 1212 .fill_modes = drm_helper_probe_single_connector_modes, 1213 .set_property = amdgpu_connector_set_property, 1214 .early_unregister = amdgpu_connector_unregister, 1215 .destroy = amdgpu_connector_destroy, 1216 .force = amdgpu_connector_dvi_force, 1217 }; 1218 1219 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1220 { 1221 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1222 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1223 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1224 int ret; 1225 1226 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1227 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1228 struct drm_display_mode *mode; 1229 1230 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1231 if (!amdgpu_dig_connector->edp_on) 1232 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1233 ATOM_TRANSMITTER_ACTION_POWER_ON); 1234 amdgpu_connector_get_edid(connector); 1235 ret = amdgpu_connector_ddc_get_modes(connector); 1236 if (!amdgpu_dig_connector->edp_on) 1237 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1238 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1239 } else { 1240 /* need to setup ddc on the bridge */ 1241 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1242 ENCODER_OBJECT_ID_NONE) { 1243 if (encoder) 1244 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1245 } 1246 amdgpu_connector_get_edid(connector); 1247 ret = amdgpu_connector_ddc_get_modes(connector); 1248 } 1249 1250 if (ret > 0) { 1251 if (encoder) { 1252 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1253 /* add scaled modes */ 1254 amdgpu_connector_add_common_modes(encoder, connector); 1255 } 1256 return ret; 1257 } 1258 1259 if (!encoder) 1260 return 0; 1261 1262 /* we have no EDID modes */ 1263 mode = amdgpu_connector_lcd_native_mode(encoder); 1264 if (mode) { 1265 ret = 1; 1266 drm_mode_probed_add(connector, mode); 1267 /* add the width/height from vbios tables if available */ 1268 connector->display_info.width_mm = mode->width_mm; 1269 connector->display_info.height_mm = mode->height_mm; 1270 /* add scaled modes */ 1271 amdgpu_connector_add_common_modes(encoder, connector); 1272 } 1273 } else { 1274 /* need to setup ddc on the bridge */ 1275 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1276 ENCODER_OBJECT_ID_NONE) { 1277 if (encoder) 1278 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1279 } 1280 amdgpu_connector_get_edid(connector); 1281 ret = amdgpu_connector_ddc_get_modes(connector); 1282 1283 amdgpu_get_native_mode(connector); 1284 } 1285 1286 return ret; 1287 } 1288 1289 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1290 { 1291 struct drm_encoder *encoder; 1292 struct amdgpu_encoder *amdgpu_encoder; 1293 int i; 1294 1295 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1296 if (connector->encoder_ids[i] == 0) 1297 break; 1298 1299 encoder = drm_encoder_find(connector->dev, 1300 connector->encoder_ids[i]); 1301 if (!encoder) 1302 continue; 1303 1304 amdgpu_encoder = to_amdgpu_encoder(encoder); 1305 1306 switch (amdgpu_encoder->encoder_id) { 1307 case ENCODER_OBJECT_ID_TRAVIS: 1308 case ENCODER_OBJECT_ID_NUTMEG: 1309 return amdgpu_encoder->encoder_id; 1310 default: 1311 break; 1312 } 1313 } 1314 1315 return ENCODER_OBJECT_ID_NONE; 1316 } 1317 1318 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1319 { 1320 struct drm_encoder *encoder; 1321 struct amdgpu_encoder *amdgpu_encoder; 1322 int i; 1323 bool found = false; 1324 1325 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1326 if (connector->encoder_ids[i] == 0) 1327 break; 1328 encoder = drm_encoder_find(connector->dev, 1329 connector->encoder_ids[i]); 1330 if (!encoder) 1331 continue; 1332 1333 amdgpu_encoder = to_amdgpu_encoder(encoder); 1334 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1335 found = true; 1336 } 1337 1338 return found; 1339 } 1340 1341 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1342 { 1343 struct drm_device *dev = connector->dev; 1344 struct amdgpu_device *adev = dev->dev_private; 1345 1346 if ((adev->clock.default_dispclk >= 53900) && 1347 amdgpu_connector_encoder_is_hbr2(connector)) { 1348 return true; 1349 } 1350 1351 return false; 1352 } 1353 1354 static enum drm_connector_status 1355 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1356 { 1357 struct drm_device *dev = connector->dev; 1358 struct amdgpu_device *adev = dev->dev_private; 1359 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1360 enum drm_connector_status ret = connector_status_disconnected; 1361 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1362 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1363 int r; 1364 1365 r = pm_runtime_get_sync(connector->dev->dev); 1366 if (r < 0) 1367 return connector_status_disconnected; 1368 1369 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1370 ret = connector->status; 1371 goto out; 1372 } 1373 1374 amdgpu_connector_free_edid(connector); 1375 1376 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1377 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1378 if (encoder) { 1379 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1380 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1381 1382 /* check if panel is valid */ 1383 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1384 ret = connector_status_connected; 1385 } 1386 /* eDP is always DP */ 1387 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1388 if (!amdgpu_dig_connector->edp_on) 1389 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1390 ATOM_TRANSMITTER_ACTION_POWER_ON); 1391 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1392 ret = connector_status_connected; 1393 if (!amdgpu_dig_connector->edp_on) 1394 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1395 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1396 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1397 ENCODER_OBJECT_ID_NONE) { 1398 /* DP bridges are always DP */ 1399 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1400 /* get the DPCD from the bridge */ 1401 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1402 1403 if (encoder) { 1404 /* setup ddc on the bridge */ 1405 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1406 /* bridge chips are always aux */ 1407 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1408 ret = connector_status_connected; 1409 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1410 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1411 ret = encoder_funcs->detect(encoder, connector); 1412 } 1413 } 1414 } else { 1415 amdgpu_dig_connector->dp_sink_type = 1416 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1417 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1418 ret = connector_status_connected; 1419 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1420 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1421 } else { 1422 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1423 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1424 ret = connector_status_connected; 1425 } else { 1426 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1427 if (amdgpu_ddc_probe(amdgpu_connector, false)) 1428 ret = connector_status_connected; 1429 } 1430 } 1431 } 1432 1433 amdgpu_connector_update_scratch_regs(connector, ret); 1434 out: 1435 pm_runtime_mark_last_busy(connector->dev->dev); 1436 pm_runtime_put_autosuspend(connector->dev->dev); 1437 1438 return ret; 1439 } 1440 1441 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1442 struct drm_display_mode *mode) 1443 { 1444 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1445 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1446 1447 /* XXX check mode bandwidth */ 1448 1449 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1450 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1451 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1452 1453 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1454 return MODE_PANEL; 1455 1456 if (encoder) { 1457 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1458 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1459 1460 /* AVIVO hardware supports downscaling modes larger than the panel 1461 * to the panel size, but I'm not sure this is desirable. 1462 */ 1463 if ((mode->hdisplay > native_mode->hdisplay) || 1464 (mode->vdisplay > native_mode->vdisplay)) 1465 return MODE_PANEL; 1466 1467 /* if scaling is disabled, block non-native modes */ 1468 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1469 if ((mode->hdisplay != native_mode->hdisplay) || 1470 (mode->vdisplay != native_mode->vdisplay)) 1471 return MODE_PANEL; 1472 } 1473 } 1474 return MODE_OK; 1475 } else { 1476 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1477 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1478 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1479 } else { 1480 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1481 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1482 if (mode->clock > 340000) 1483 return MODE_CLOCK_HIGH; 1484 } else { 1485 if (mode->clock > 165000) 1486 return MODE_CLOCK_HIGH; 1487 } 1488 } 1489 } 1490 1491 return MODE_OK; 1492 } 1493 1494 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1495 .get_modes = amdgpu_connector_dp_get_modes, 1496 .mode_valid = amdgpu_connector_dp_mode_valid, 1497 .best_encoder = amdgpu_connector_dvi_encoder, 1498 }; 1499 1500 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1501 .dpms = drm_helper_connector_dpms, 1502 .detect = amdgpu_connector_dp_detect, 1503 .fill_modes = drm_helper_probe_single_connector_modes, 1504 .set_property = amdgpu_connector_set_property, 1505 .early_unregister = amdgpu_connector_unregister, 1506 .destroy = amdgpu_connector_destroy, 1507 .force = amdgpu_connector_dvi_force, 1508 }; 1509 1510 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1511 .dpms = drm_helper_connector_dpms, 1512 .detect = amdgpu_connector_dp_detect, 1513 .fill_modes = drm_helper_probe_single_connector_modes, 1514 .set_property = amdgpu_connector_set_lcd_property, 1515 .early_unregister = amdgpu_connector_unregister, 1516 .destroy = amdgpu_connector_destroy, 1517 .force = amdgpu_connector_dvi_force, 1518 }; 1519 1520 static struct drm_encoder * 1521 amdgpu_connector_virtual_encoder(struct drm_connector *connector) 1522 { 1523 int enc_id = connector->encoder_ids[0]; 1524 struct drm_encoder *encoder; 1525 int i; 1526 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1527 if (connector->encoder_ids[i] == 0) 1528 break; 1529 1530 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1531 if (!encoder) 1532 continue; 1533 1534 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) 1535 return encoder; 1536 } 1537 1538 /* pick the first one */ 1539 if (enc_id) 1540 return drm_encoder_find(connector->dev, enc_id); 1541 return NULL; 1542 } 1543 1544 static int amdgpu_connector_virtual_get_modes(struct drm_connector *connector) 1545 { 1546 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1547 1548 if (encoder) { 1549 amdgpu_connector_add_common_modes(encoder, connector); 1550 } 1551 1552 return 0; 1553 } 1554 1555 static int amdgpu_connector_virtual_mode_valid(struct drm_connector *connector, 1556 struct drm_display_mode *mode) 1557 { 1558 return MODE_OK; 1559 } 1560 1561 static int 1562 amdgpu_connector_virtual_dpms(struct drm_connector *connector, int mode) 1563 { 1564 return 0; 1565 } 1566 1567 static enum drm_connector_status 1568 1569 amdgpu_connector_virtual_detect(struct drm_connector *connector, bool force) 1570 { 1571 return connector_status_connected; 1572 } 1573 1574 static int 1575 amdgpu_connector_virtual_set_property(struct drm_connector *connector, 1576 struct drm_property *property, 1577 uint64_t val) 1578 { 1579 return 0; 1580 } 1581 1582 static void amdgpu_connector_virtual_force(struct drm_connector *connector) 1583 { 1584 return; 1585 } 1586 1587 static const struct drm_connector_helper_funcs amdgpu_connector_virtual_helper_funcs = { 1588 .get_modes = amdgpu_connector_virtual_get_modes, 1589 .mode_valid = amdgpu_connector_virtual_mode_valid, 1590 .best_encoder = amdgpu_connector_virtual_encoder, 1591 }; 1592 1593 static const struct drm_connector_funcs amdgpu_connector_virtual_funcs = { 1594 .dpms = amdgpu_connector_virtual_dpms, 1595 .detect = amdgpu_connector_virtual_detect, 1596 .fill_modes = drm_helper_probe_single_connector_modes, 1597 .set_property = amdgpu_connector_virtual_set_property, 1598 .destroy = amdgpu_connector_destroy, 1599 .force = amdgpu_connector_virtual_force, 1600 }; 1601 1602 void 1603 amdgpu_connector_add(struct amdgpu_device *adev, 1604 uint32_t connector_id, 1605 uint32_t supported_device, 1606 int connector_type, 1607 struct amdgpu_i2c_bus_rec *i2c_bus, 1608 uint16_t connector_object_id, 1609 struct amdgpu_hpd *hpd, 1610 struct amdgpu_router *router) 1611 { 1612 struct drm_device *dev = adev->ddev; 1613 struct drm_connector *connector; 1614 struct amdgpu_connector *amdgpu_connector; 1615 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1616 struct drm_encoder *encoder; 1617 struct amdgpu_encoder *amdgpu_encoder; 1618 uint32_t subpixel_order = SubPixelNone; 1619 bool shared_ddc = false; 1620 bool is_dp_bridge = false; 1621 bool has_aux = false; 1622 1623 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1624 return; 1625 1626 /* see if we already added it */ 1627 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1628 amdgpu_connector = to_amdgpu_connector(connector); 1629 if (amdgpu_connector->connector_id == connector_id) { 1630 amdgpu_connector->devices |= supported_device; 1631 return; 1632 } 1633 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1634 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1635 amdgpu_connector->shared_ddc = true; 1636 shared_ddc = true; 1637 } 1638 if (amdgpu_connector->router_bus && router->ddc_valid && 1639 (amdgpu_connector->router.router_id == router->router_id)) { 1640 amdgpu_connector->shared_ddc = false; 1641 shared_ddc = false; 1642 } 1643 } 1644 } 1645 1646 /* check if it's a dp bridge */ 1647 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1648 amdgpu_encoder = to_amdgpu_encoder(encoder); 1649 if (amdgpu_encoder->devices & supported_device) { 1650 switch (amdgpu_encoder->encoder_id) { 1651 case ENCODER_OBJECT_ID_TRAVIS: 1652 case ENCODER_OBJECT_ID_NUTMEG: 1653 is_dp_bridge = true; 1654 break; 1655 default: 1656 break; 1657 } 1658 } 1659 } 1660 1661 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1662 if (!amdgpu_connector) 1663 return; 1664 1665 connector = &amdgpu_connector->base; 1666 1667 amdgpu_connector->connector_id = connector_id; 1668 amdgpu_connector->devices = supported_device; 1669 amdgpu_connector->shared_ddc = shared_ddc; 1670 amdgpu_connector->connector_object_id = connector_object_id; 1671 amdgpu_connector->hpd = *hpd; 1672 1673 amdgpu_connector->router = *router; 1674 if (router->ddc_valid || router->cd_valid) { 1675 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1676 if (!amdgpu_connector->router_bus) 1677 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1678 } 1679 1680 if (is_dp_bridge) { 1681 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1682 if (!amdgpu_dig_connector) 1683 goto failed; 1684 amdgpu_connector->con_priv = amdgpu_dig_connector; 1685 if (i2c_bus->valid) { 1686 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1687 if (amdgpu_connector->ddc_bus) 1688 has_aux = true; 1689 else 1690 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1691 } 1692 switch (connector_type) { 1693 case DRM_MODE_CONNECTOR_VGA: 1694 case DRM_MODE_CONNECTOR_DVIA: 1695 default: 1696 drm_connector_init(dev, &amdgpu_connector->base, 1697 &amdgpu_connector_dp_funcs, connector_type); 1698 drm_connector_helper_add(&amdgpu_connector->base, 1699 &amdgpu_connector_dp_helper_funcs); 1700 connector->interlace_allowed = true; 1701 connector->doublescan_allowed = true; 1702 amdgpu_connector->dac_load_detect = true; 1703 drm_object_attach_property(&amdgpu_connector->base.base, 1704 adev->mode_info.load_detect_property, 1705 1); 1706 drm_object_attach_property(&amdgpu_connector->base.base, 1707 dev->mode_config.scaling_mode_property, 1708 DRM_MODE_SCALE_NONE); 1709 break; 1710 case DRM_MODE_CONNECTOR_DVII: 1711 case DRM_MODE_CONNECTOR_DVID: 1712 case DRM_MODE_CONNECTOR_HDMIA: 1713 case DRM_MODE_CONNECTOR_HDMIB: 1714 case DRM_MODE_CONNECTOR_DisplayPort: 1715 drm_connector_init(dev, &amdgpu_connector->base, 1716 &amdgpu_connector_dp_funcs, connector_type); 1717 drm_connector_helper_add(&amdgpu_connector->base, 1718 &amdgpu_connector_dp_helper_funcs); 1719 drm_object_attach_property(&amdgpu_connector->base.base, 1720 adev->mode_info.underscan_property, 1721 UNDERSCAN_OFF); 1722 drm_object_attach_property(&amdgpu_connector->base.base, 1723 adev->mode_info.underscan_hborder_property, 1724 0); 1725 drm_object_attach_property(&amdgpu_connector->base.base, 1726 adev->mode_info.underscan_vborder_property, 1727 0); 1728 1729 drm_object_attach_property(&amdgpu_connector->base.base, 1730 dev->mode_config.scaling_mode_property, 1731 DRM_MODE_SCALE_NONE); 1732 1733 drm_object_attach_property(&amdgpu_connector->base.base, 1734 adev->mode_info.dither_property, 1735 AMDGPU_FMT_DITHER_DISABLE); 1736 1737 if (amdgpu_audio != 0) 1738 drm_object_attach_property(&amdgpu_connector->base.base, 1739 adev->mode_info.audio_property, 1740 AMDGPU_AUDIO_AUTO); 1741 1742 subpixel_order = SubPixelHorizontalRGB; 1743 connector->interlace_allowed = true; 1744 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1745 connector->doublescan_allowed = true; 1746 else 1747 connector->doublescan_allowed = false; 1748 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1749 amdgpu_connector->dac_load_detect = true; 1750 drm_object_attach_property(&amdgpu_connector->base.base, 1751 adev->mode_info.load_detect_property, 1752 1); 1753 } 1754 break; 1755 case DRM_MODE_CONNECTOR_LVDS: 1756 case DRM_MODE_CONNECTOR_eDP: 1757 drm_connector_init(dev, &amdgpu_connector->base, 1758 &amdgpu_connector_edp_funcs, connector_type); 1759 drm_connector_helper_add(&amdgpu_connector->base, 1760 &amdgpu_connector_dp_helper_funcs); 1761 drm_object_attach_property(&amdgpu_connector->base.base, 1762 dev->mode_config.scaling_mode_property, 1763 DRM_MODE_SCALE_FULLSCREEN); 1764 subpixel_order = SubPixelHorizontalRGB; 1765 connector->interlace_allowed = false; 1766 connector->doublescan_allowed = false; 1767 break; 1768 } 1769 } else { 1770 switch (connector_type) { 1771 case DRM_MODE_CONNECTOR_VGA: 1772 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1773 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1774 if (i2c_bus->valid) { 1775 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1776 if (!amdgpu_connector->ddc_bus) 1777 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1778 } 1779 amdgpu_connector->dac_load_detect = true; 1780 drm_object_attach_property(&amdgpu_connector->base.base, 1781 adev->mode_info.load_detect_property, 1782 1); 1783 drm_object_attach_property(&amdgpu_connector->base.base, 1784 dev->mode_config.scaling_mode_property, 1785 DRM_MODE_SCALE_NONE); 1786 /* no HPD on analog connectors */ 1787 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1788 connector->interlace_allowed = true; 1789 connector->doublescan_allowed = true; 1790 break; 1791 case DRM_MODE_CONNECTOR_DVIA: 1792 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1793 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1794 if (i2c_bus->valid) { 1795 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1796 if (!amdgpu_connector->ddc_bus) 1797 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1798 } 1799 amdgpu_connector->dac_load_detect = true; 1800 drm_object_attach_property(&amdgpu_connector->base.base, 1801 adev->mode_info.load_detect_property, 1802 1); 1803 drm_object_attach_property(&amdgpu_connector->base.base, 1804 dev->mode_config.scaling_mode_property, 1805 DRM_MODE_SCALE_NONE); 1806 /* no HPD on analog connectors */ 1807 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1808 connector->interlace_allowed = true; 1809 connector->doublescan_allowed = true; 1810 break; 1811 case DRM_MODE_CONNECTOR_DVII: 1812 case DRM_MODE_CONNECTOR_DVID: 1813 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1814 if (!amdgpu_dig_connector) 1815 goto failed; 1816 amdgpu_connector->con_priv = amdgpu_dig_connector; 1817 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1818 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1819 if (i2c_bus->valid) { 1820 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1821 if (!amdgpu_connector->ddc_bus) 1822 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1823 } 1824 subpixel_order = SubPixelHorizontalRGB; 1825 drm_object_attach_property(&amdgpu_connector->base.base, 1826 adev->mode_info.coherent_mode_property, 1827 1); 1828 drm_object_attach_property(&amdgpu_connector->base.base, 1829 adev->mode_info.underscan_property, 1830 UNDERSCAN_OFF); 1831 drm_object_attach_property(&amdgpu_connector->base.base, 1832 adev->mode_info.underscan_hborder_property, 1833 0); 1834 drm_object_attach_property(&amdgpu_connector->base.base, 1835 adev->mode_info.underscan_vborder_property, 1836 0); 1837 drm_object_attach_property(&amdgpu_connector->base.base, 1838 dev->mode_config.scaling_mode_property, 1839 DRM_MODE_SCALE_NONE); 1840 1841 if (amdgpu_audio != 0) { 1842 drm_object_attach_property(&amdgpu_connector->base.base, 1843 adev->mode_info.audio_property, 1844 AMDGPU_AUDIO_AUTO); 1845 } 1846 drm_object_attach_property(&amdgpu_connector->base.base, 1847 adev->mode_info.dither_property, 1848 AMDGPU_FMT_DITHER_DISABLE); 1849 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1850 amdgpu_connector->dac_load_detect = true; 1851 drm_object_attach_property(&amdgpu_connector->base.base, 1852 adev->mode_info.load_detect_property, 1853 1); 1854 } 1855 connector->interlace_allowed = true; 1856 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1857 connector->doublescan_allowed = true; 1858 else 1859 connector->doublescan_allowed = false; 1860 break; 1861 case DRM_MODE_CONNECTOR_HDMIA: 1862 case DRM_MODE_CONNECTOR_HDMIB: 1863 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1864 if (!amdgpu_dig_connector) 1865 goto failed; 1866 amdgpu_connector->con_priv = amdgpu_dig_connector; 1867 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1868 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1869 if (i2c_bus->valid) { 1870 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1871 if (!amdgpu_connector->ddc_bus) 1872 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1873 } 1874 drm_object_attach_property(&amdgpu_connector->base.base, 1875 adev->mode_info.coherent_mode_property, 1876 1); 1877 drm_object_attach_property(&amdgpu_connector->base.base, 1878 adev->mode_info.underscan_property, 1879 UNDERSCAN_OFF); 1880 drm_object_attach_property(&amdgpu_connector->base.base, 1881 adev->mode_info.underscan_hborder_property, 1882 0); 1883 drm_object_attach_property(&amdgpu_connector->base.base, 1884 adev->mode_info.underscan_vborder_property, 1885 0); 1886 drm_object_attach_property(&amdgpu_connector->base.base, 1887 dev->mode_config.scaling_mode_property, 1888 DRM_MODE_SCALE_NONE); 1889 if (amdgpu_audio != 0) { 1890 drm_object_attach_property(&amdgpu_connector->base.base, 1891 adev->mode_info.audio_property, 1892 AMDGPU_AUDIO_AUTO); 1893 } 1894 drm_object_attach_property(&amdgpu_connector->base.base, 1895 adev->mode_info.dither_property, 1896 AMDGPU_FMT_DITHER_DISABLE); 1897 subpixel_order = SubPixelHorizontalRGB; 1898 connector->interlace_allowed = true; 1899 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1900 connector->doublescan_allowed = true; 1901 else 1902 connector->doublescan_allowed = false; 1903 break; 1904 case DRM_MODE_CONNECTOR_DisplayPort: 1905 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1906 if (!amdgpu_dig_connector) 1907 goto failed; 1908 amdgpu_connector->con_priv = amdgpu_dig_connector; 1909 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1910 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1911 if (i2c_bus->valid) { 1912 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1913 if (amdgpu_connector->ddc_bus) 1914 has_aux = true; 1915 else 1916 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1917 } 1918 subpixel_order = SubPixelHorizontalRGB; 1919 drm_object_attach_property(&amdgpu_connector->base.base, 1920 adev->mode_info.coherent_mode_property, 1921 1); 1922 drm_object_attach_property(&amdgpu_connector->base.base, 1923 adev->mode_info.underscan_property, 1924 UNDERSCAN_OFF); 1925 drm_object_attach_property(&amdgpu_connector->base.base, 1926 adev->mode_info.underscan_hborder_property, 1927 0); 1928 drm_object_attach_property(&amdgpu_connector->base.base, 1929 adev->mode_info.underscan_vborder_property, 1930 0); 1931 drm_object_attach_property(&amdgpu_connector->base.base, 1932 dev->mode_config.scaling_mode_property, 1933 DRM_MODE_SCALE_NONE); 1934 if (amdgpu_audio != 0) { 1935 drm_object_attach_property(&amdgpu_connector->base.base, 1936 adev->mode_info.audio_property, 1937 AMDGPU_AUDIO_AUTO); 1938 } 1939 drm_object_attach_property(&amdgpu_connector->base.base, 1940 adev->mode_info.dither_property, 1941 AMDGPU_FMT_DITHER_DISABLE); 1942 connector->interlace_allowed = true; 1943 /* in theory with a DP to VGA converter... */ 1944 connector->doublescan_allowed = false; 1945 break; 1946 case DRM_MODE_CONNECTOR_eDP: 1947 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1948 if (!amdgpu_dig_connector) 1949 goto failed; 1950 amdgpu_connector->con_priv = amdgpu_dig_connector; 1951 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1952 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1953 if (i2c_bus->valid) { 1954 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1955 if (amdgpu_connector->ddc_bus) 1956 has_aux = true; 1957 else 1958 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1959 } 1960 drm_object_attach_property(&amdgpu_connector->base.base, 1961 dev->mode_config.scaling_mode_property, 1962 DRM_MODE_SCALE_FULLSCREEN); 1963 subpixel_order = SubPixelHorizontalRGB; 1964 connector->interlace_allowed = false; 1965 connector->doublescan_allowed = false; 1966 break; 1967 case DRM_MODE_CONNECTOR_LVDS: 1968 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1969 if (!amdgpu_dig_connector) 1970 goto failed; 1971 amdgpu_connector->con_priv = amdgpu_dig_connector; 1972 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1973 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1974 if (i2c_bus->valid) { 1975 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1976 if (!amdgpu_connector->ddc_bus) 1977 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1978 } 1979 drm_object_attach_property(&amdgpu_connector->base.base, 1980 dev->mode_config.scaling_mode_property, 1981 DRM_MODE_SCALE_FULLSCREEN); 1982 subpixel_order = SubPixelHorizontalRGB; 1983 connector->interlace_allowed = false; 1984 connector->doublescan_allowed = false; 1985 break; 1986 case DRM_MODE_CONNECTOR_VIRTUAL: 1987 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1988 if (!amdgpu_dig_connector) 1989 goto failed; 1990 amdgpu_connector->con_priv = amdgpu_dig_connector; 1991 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_virtual_funcs, connector_type); 1992 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_virtual_helper_funcs); 1993 subpixel_order = SubPixelHorizontalRGB; 1994 connector->interlace_allowed = false; 1995 connector->doublescan_allowed = false; 1996 break; 1997 } 1998 } 1999 2000 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2001 if (i2c_bus->valid) { 2002 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2003 DRM_CONNECTOR_POLL_DISCONNECT; 2004 } 2005 } else 2006 connector->polled = DRM_CONNECTOR_POLL_HPD; 2007 2008 connector->display_info.subpixel_order = subpixel_order; 2009 drm_connector_register(connector); 2010 2011 if (has_aux) 2012 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2013 2014 return; 2015 2016 failed: 2017 drm_connector_cleanup(connector); 2018 kfree(connector); 2019 } 2020