1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 75 /* Don't start link training before we have the DPCD */ 76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 77 return; 78 79 /* Turn the connector off and back on immediately, which 80 * will trigger link training 81 */ 82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 84 } 85 } 86 } 87 88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 89 { 90 struct drm_crtc *crtc = encoder->crtc; 91 92 if (crtc && crtc->enabled) { 93 drm_crtc_helper_set_mode(crtc, &crtc->mode, 94 crtc->x, crtc->y, crtc->primary->fb); 95 } 96 } 97 98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 99 { 100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 101 struct amdgpu_connector_atom_dig *dig_connector; 102 int bpc = 8; 103 unsigned mode_clock, max_tmds_clock; 104 105 switch (connector->connector_type) { 106 case DRM_MODE_CONNECTOR_DVII: 107 case DRM_MODE_CONNECTOR_HDMIB: 108 if (amdgpu_connector->use_digital) { 109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 110 if (connector->display_info.bpc) 111 bpc = connector->display_info.bpc; 112 } 113 } 114 break; 115 case DRM_MODE_CONNECTOR_DVID: 116 case DRM_MODE_CONNECTOR_HDMIA: 117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 118 if (connector->display_info.bpc) 119 bpc = connector->display_info.bpc; 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DisplayPort: 123 dig_connector = amdgpu_connector->con_priv; 124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 127 if (connector->display_info.bpc) 128 bpc = connector->display_info.bpc; 129 } 130 break; 131 case DRM_MODE_CONNECTOR_eDP: 132 case DRM_MODE_CONNECTOR_LVDS: 133 if (connector->display_info.bpc) 134 bpc = connector->display_info.bpc; 135 else { 136 const struct drm_connector_helper_funcs *connector_funcs = 137 connector->helper_private; 138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 141 142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 143 bpc = 6; 144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 145 bpc = 8; 146 } 147 break; 148 } 149 150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 151 /* 152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 154 * 12 bpc is always supported on hdmi deep color sinks, as this is 155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 156 */ 157 if (bpc > 12) { 158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 159 connector->name, bpc); 160 bpc = 12; 161 } 162 163 /* Any defined maximum tmds clock limit we must not exceed? */ 164 if (connector->display_info.max_tmds_clock > 0) { 165 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 166 mode_clock = amdgpu_connector->pixelclock_for_modeset; 167 168 /* Maximum allowable input clock in kHz */ 169 max_tmds_clock = connector->display_info.max_tmds_clock; 170 171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 172 connector->name, mode_clock, max_tmds_clock); 173 174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 177 (mode_clock * 5/4 <= max_tmds_clock)) 178 bpc = 10; 179 else 180 bpc = 8; 181 182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 183 connector->name, bpc); 184 } 185 186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 187 bpc = 8; 188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 189 connector->name, bpc); 190 } 191 } else if (bpc > 8) { 192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 194 connector->name); 195 bpc = 8; 196 } 197 } 198 199 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 201 connector->name); 202 bpc = 8; 203 } 204 205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 206 connector->name, connector->display_info.bpc, bpc); 207 208 return bpc; 209 } 210 211 static void 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 213 enum drm_connector_status status) 214 { 215 struct drm_encoder *best_encoder; 216 struct drm_encoder *encoder; 217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 218 bool connected; 219 int i; 220 221 best_encoder = connector_funcs->best_encoder(connector); 222 223 drm_connector_for_each_possible_encoder(connector, encoder, i) { 224 if ((encoder == best_encoder) && (status == connector_status_connected)) 225 connected = true; 226 else 227 connected = false; 228 229 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 230 } 231 } 232 233 static struct drm_encoder * 234 amdgpu_connector_find_encoder(struct drm_connector *connector, 235 int encoder_type) 236 { 237 struct drm_encoder *encoder; 238 int i; 239 240 drm_connector_for_each_possible_encoder(connector, encoder, i) { 241 if (encoder->encoder_type == encoder_type) 242 return encoder; 243 } 244 245 return NULL; 246 } 247 248 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 249 { 250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 251 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 252 253 if (amdgpu_connector->edid) { 254 return amdgpu_connector->edid; 255 } else if (edid_blob) { 256 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 257 if (edid) 258 amdgpu_connector->edid = edid; 259 } 260 return amdgpu_connector->edid; 261 } 262 263 static struct edid * 264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 265 { 266 struct edid *edid; 267 268 if (adev->mode_info.bios_hardcoded_edid) { 269 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 270 if (edid) { 271 memcpy((unsigned char *)edid, 272 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 273 adev->mode_info.bios_hardcoded_edid_size); 274 return edid; 275 } 276 } 277 return NULL; 278 } 279 280 static void amdgpu_connector_get_edid(struct drm_connector *connector) 281 { 282 struct drm_device *dev = connector->dev; 283 struct amdgpu_device *adev = dev->dev_private; 284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 285 286 if (amdgpu_connector->edid) 287 return; 288 289 /* on hw with routers, select right port */ 290 if (amdgpu_connector->router.ddc_valid) 291 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 292 293 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 294 ENCODER_OBJECT_ID_NONE) && 295 amdgpu_connector->ddc_bus->has_aux) { 296 amdgpu_connector->edid = drm_get_edid(connector, 297 &amdgpu_connector->ddc_bus->aux.ddc); 298 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 300 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 301 302 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 303 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 304 amdgpu_connector->ddc_bus->has_aux) 305 amdgpu_connector->edid = drm_get_edid(connector, 306 &amdgpu_connector->ddc_bus->aux.ddc); 307 else if (amdgpu_connector->ddc_bus) 308 amdgpu_connector->edid = drm_get_edid(connector, 309 &amdgpu_connector->ddc_bus->adapter); 310 } else if (amdgpu_connector->ddc_bus) { 311 amdgpu_connector->edid = drm_get_edid(connector, 312 &amdgpu_connector->ddc_bus->adapter); 313 } 314 315 if (!amdgpu_connector->edid) { 316 /* some laptops provide a hardcoded edid in rom for LCDs */ 317 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 318 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 319 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 320 } 321 } 322 323 static void amdgpu_connector_free_edid(struct drm_connector *connector) 324 { 325 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 326 327 kfree(amdgpu_connector->edid); 328 amdgpu_connector->edid = NULL; 329 } 330 331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 332 { 333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 334 int ret; 335 336 if (amdgpu_connector->edid) { 337 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 338 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 339 return ret; 340 } 341 drm_connector_update_edid_property(connector, NULL); 342 return 0; 343 } 344 345 static struct drm_encoder * 346 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 347 { 348 struct drm_encoder *encoder; 349 int i; 350 351 /* pick the first one */ 352 drm_connector_for_each_possible_encoder(connector, encoder, i) 353 return encoder; 354 355 return NULL; 356 } 357 358 static void amdgpu_get_native_mode(struct drm_connector *connector) 359 { 360 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 361 struct amdgpu_encoder *amdgpu_encoder; 362 363 if (encoder == NULL) 364 return; 365 366 amdgpu_encoder = to_amdgpu_encoder(encoder); 367 368 if (!list_empty(&connector->probed_modes)) { 369 struct drm_display_mode *preferred_mode = 370 list_first_entry(&connector->probed_modes, 371 struct drm_display_mode, head); 372 373 amdgpu_encoder->native_mode = *preferred_mode; 374 } else { 375 amdgpu_encoder->native_mode.clock = 0; 376 } 377 } 378 379 static struct drm_display_mode * 380 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 381 { 382 struct drm_device *dev = encoder->dev; 383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 384 struct drm_display_mode *mode = NULL; 385 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 386 387 if (native_mode->hdisplay != 0 && 388 native_mode->vdisplay != 0 && 389 native_mode->clock != 0) { 390 mode = drm_mode_duplicate(dev, native_mode); 391 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 392 drm_mode_set_name(mode); 393 394 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 395 } else if (native_mode->hdisplay != 0 && 396 native_mode->vdisplay != 0) { 397 /* mac laptops without an edid */ 398 /* Note that this is not necessarily the exact panel mode, 399 * but an approximation based on the cvt formula. For these 400 * systems we should ideally read the mode info out of the 401 * registers or add a mode table, but this works and is much 402 * simpler. 403 */ 404 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 405 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 406 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 407 } 408 return mode; 409 } 410 411 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 412 struct drm_connector *connector) 413 { 414 struct drm_device *dev = encoder->dev; 415 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 416 struct drm_display_mode *mode = NULL; 417 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 418 int i; 419 static const struct mode_size { 420 int w; 421 int h; 422 } common_modes[17] = { 423 { 640, 480}, 424 { 720, 480}, 425 { 800, 600}, 426 { 848, 480}, 427 {1024, 768}, 428 {1152, 768}, 429 {1280, 720}, 430 {1280, 800}, 431 {1280, 854}, 432 {1280, 960}, 433 {1280, 1024}, 434 {1440, 900}, 435 {1400, 1050}, 436 {1680, 1050}, 437 {1600, 1200}, 438 {1920, 1080}, 439 {1920, 1200} 440 }; 441 442 for (i = 0; i < 17; i++) { 443 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 444 if (common_modes[i].w > 1024 || 445 common_modes[i].h > 768) 446 continue; 447 } 448 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 449 if (common_modes[i].w > native_mode->hdisplay || 450 common_modes[i].h > native_mode->vdisplay || 451 (common_modes[i].w == native_mode->hdisplay && 452 common_modes[i].h == native_mode->vdisplay)) 453 continue; 454 } 455 if (common_modes[i].w < 320 || common_modes[i].h < 200) 456 continue; 457 458 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 459 drm_mode_probed_add(connector, mode); 460 } 461 } 462 463 static int amdgpu_connector_set_property(struct drm_connector *connector, 464 struct drm_property *property, 465 uint64_t val) 466 { 467 struct drm_device *dev = connector->dev; 468 struct amdgpu_device *adev = dev->dev_private; 469 struct drm_encoder *encoder; 470 struct amdgpu_encoder *amdgpu_encoder; 471 472 if (property == adev->mode_info.coherent_mode_property) { 473 struct amdgpu_encoder_atom_dig *dig; 474 bool new_coherent_mode; 475 476 /* need to find digital encoder on connector */ 477 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 478 if (!encoder) 479 return 0; 480 481 amdgpu_encoder = to_amdgpu_encoder(encoder); 482 483 if (!amdgpu_encoder->enc_priv) 484 return 0; 485 486 dig = amdgpu_encoder->enc_priv; 487 new_coherent_mode = val ? true : false; 488 if (dig->coherent_mode != new_coherent_mode) { 489 dig->coherent_mode = new_coherent_mode; 490 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 491 } 492 } 493 494 if (property == adev->mode_info.audio_property) { 495 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 496 /* need to find digital encoder on connector */ 497 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 498 if (!encoder) 499 return 0; 500 501 amdgpu_encoder = to_amdgpu_encoder(encoder); 502 503 if (amdgpu_connector->audio != val) { 504 amdgpu_connector->audio = val; 505 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 506 } 507 } 508 509 if (property == adev->mode_info.dither_property) { 510 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 511 /* need to find digital encoder on connector */ 512 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 513 if (!encoder) 514 return 0; 515 516 amdgpu_encoder = to_amdgpu_encoder(encoder); 517 518 if (amdgpu_connector->dither != val) { 519 amdgpu_connector->dither = val; 520 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 521 } 522 } 523 524 if (property == adev->mode_info.underscan_property) { 525 /* need to find digital encoder on connector */ 526 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 527 if (!encoder) 528 return 0; 529 530 amdgpu_encoder = to_amdgpu_encoder(encoder); 531 532 if (amdgpu_encoder->underscan_type != val) { 533 amdgpu_encoder->underscan_type = val; 534 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 535 } 536 } 537 538 if (property == adev->mode_info.underscan_hborder_property) { 539 /* need to find digital encoder on connector */ 540 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 541 if (!encoder) 542 return 0; 543 544 amdgpu_encoder = to_amdgpu_encoder(encoder); 545 546 if (amdgpu_encoder->underscan_hborder != val) { 547 amdgpu_encoder->underscan_hborder = val; 548 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 549 } 550 } 551 552 if (property == adev->mode_info.underscan_vborder_property) { 553 /* need to find digital encoder on connector */ 554 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 555 if (!encoder) 556 return 0; 557 558 amdgpu_encoder = to_amdgpu_encoder(encoder); 559 560 if (amdgpu_encoder->underscan_vborder != val) { 561 amdgpu_encoder->underscan_vborder = val; 562 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 563 } 564 } 565 566 if (property == adev->mode_info.load_detect_property) { 567 struct amdgpu_connector *amdgpu_connector = 568 to_amdgpu_connector(connector); 569 570 if (val == 0) 571 amdgpu_connector->dac_load_detect = false; 572 else 573 amdgpu_connector->dac_load_detect = true; 574 } 575 576 if (property == dev->mode_config.scaling_mode_property) { 577 enum amdgpu_rmx_type rmx_type; 578 579 if (connector->encoder) { 580 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 581 } else { 582 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 583 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 584 } 585 586 switch (val) { 587 default: 588 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 589 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 590 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 591 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 592 } 593 if (amdgpu_encoder->rmx_type == rmx_type) 594 return 0; 595 596 if ((rmx_type != DRM_MODE_SCALE_NONE) && 597 (amdgpu_encoder->native_mode.clock == 0)) 598 return 0; 599 600 amdgpu_encoder->rmx_type = rmx_type; 601 602 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 603 } 604 605 return 0; 606 } 607 608 static void 609 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 610 struct drm_connector *connector) 611 { 612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 613 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 614 struct drm_display_mode *t, *mode; 615 616 /* If the EDID preferred mode doesn't match the native mode, use it */ 617 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 618 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 619 if (mode->hdisplay != native_mode->hdisplay || 620 mode->vdisplay != native_mode->vdisplay) 621 memcpy(native_mode, mode, sizeof(*mode)); 622 } 623 } 624 625 /* Try to get native mode details from EDID if necessary */ 626 if (!native_mode->clock) { 627 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 628 if (mode->hdisplay == native_mode->hdisplay && 629 mode->vdisplay == native_mode->vdisplay) { 630 *native_mode = *mode; 631 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 632 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 633 break; 634 } 635 } 636 } 637 638 if (!native_mode->clock) { 639 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 640 amdgpu_encoder->rmx_type = RMX_OFF; 641 } 642 } 643 644 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 645 { 646 struct drm_encoder *encoder; 647 int ret = 0; 648 struct drm_display_mode *mode; 649 650 amdgpu_connector_get_edid(connector); 651 ret = amdgpu_connector_ddc_get_modes(connector); 652 if (ret > 0) { 653 encoder = amdgpu_connector_best_single_encoder(connector); 654 if (encoder) { 655 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 656 /* add scaled modes */ 657 amdgpu_connector_add_common_modes(encoder, connector); 658 } 659 return ret; 660 } 661 662 encoder = amdgpu_connector_best_single_encoder(connector); 663 if (!encoder) 664 return 0; 665 666 /* we have no EDID modes */ 667 mode = amdgpu_connector_lcd_native_mode(encoder); 668 if (mode) { 669 ret = 1; 670 drm_mode_probed_add(connector, mode); 671 /* add the width/height from vbios tables if available */ 672 connector->display_info.width_mm = mode->width_mm; 673 connector->display_info.height_mm = mode->height_mm; 674 /* add scaled modes */ 675 amdgpu_connector_add_common_modes(encoder, connector); 676 } 677 678 return ret; 679 } 680 681 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 682 struct drm_display_mode *mode) 683 { 684 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 685 686 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 687 return MODE_PANEL; 688 689 if (encoder) { 690 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 691 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 692 693 /* AVIVO hardware supports downscaling modes larger than the panel 694 * to the panel size, but I'm not sure this is desirable. 695 */ 696 if ((mode->hdisplay > native_mode->hdisplay) || 697 (mode->vdisplay > native_mode->vdisplay)) 698 return MODE_PANEL; 699 700 /* if scaling is disabled, block non-native modes */ 701 if (amdgpu_encoder->rmx_type == RMX_OFF) { 702 if ((mode->hdisplay != native_mode->hdisplay) || 703 (mode->vdisplay != native_mode->vdisplay)) 704 return MODE_PANEL; 705 } 706 } 707 708 return MODE_OK; 709 } 710 711 static enum drm_connector_status 712 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 713 { 714 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 715 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 716 enum drm_connector_status ret = connector_status_disconnected; 717 int r; 718 719 if (!drm_kms_helper_is_poll_worker()) { 720 r = pm_runtime_get_sync(connector->dev->dev); 721 if (r < 0) 722 return connector_status_disconnected; 723 } 724 725 if (encoder) { 726 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 727 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 728 729 /* check if panel is valid */ 730 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 731 ret = connector_status_connected; 732 733 } 734 735 /* check for edid as well */ 736 amdgpu_connector_get_edid(connector); 737 if (amdgpu_connector->edid) 738 ret = connector_status_connected; 739 /* check acpi lid status ??? */ 740 741 amdgpu_connector_update_scratch_regs(connector, ret); 742 743 if (!drm_kms_helper_is_poll_worker()) { 744 pm_runtime_mark_last_busy(connector->dev->dev); 745 pm_runtime_put_autosuspend(connector->dev->dev); 746 } 747 748 return ret; 749 } 750 751 static void amdgpu_connector_unregister(struct drm_connector *connector) 752 { 753 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 754 755 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 756 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 757 amdgpu_connector->ddc_bus->has_aux = false; 758 } 759 } 760 761 static void amdgpu_connector_destroy(struct drm_connector *connector) 762 { 763 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 764 765 amdgpu_connector_free_edid(connector); 766 kfree(amdgpu_connector->con_priv); 767 drm_connector_unregister(connector); 768 drm_connector_cleanup(connector); 769 kfree(connector); 770 } 771 772 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 773 struct drm_property *property, 774 uint64_t value) 775 { 776 struct drm_device *dev = connector->dev; 777 struct amdgpu_encoder *amdgpu_encoder; 778 enum amdgpu_rmx_type rmx_type; 779 780 DRM_DEBUG_KMS("\n"); 781 if (property != dev->mode_config.scaling_mode_property) 782 return 0; 783 784 if (connector->encoder) 785 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 786 else { 787 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 788 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 789 } 790 791 switch (value) { 792 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 793 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 794 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 795 default: 796 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 797 } 798 if (amdgpu_encoder->rmx_type == rmx_type) 799 return 0; 800 801 amdgpu_encoder->rmx_type = rmx_type; 802 803 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 804 return 0; 805 } 806 807 808 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 809 .get_modes = amdgpu_connector_lvds_get_modes, 810 .mode_valid = amdgpu_connector_lvds_mode_valid, 811 .best_encoder = amdgpu_connector_best_single_encoder, 812 }; 813 814 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 815 .dpms = drm_helper_connector_dpms, 816 .detect = amdgpu_connector_lvds_detect, 817 .fill_modes = drm_helper_probe_single_connector_modes, 818 .early_unregister = amdgpu_connector_unregister, 819 .destroy = amdgpu_connector_destroy, 820 .set_property = amdgpu_connector_set_lcd_property, 821 }; 822 823 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 824 { 825 int ret; 826 827 amdgpu_connector_get_edid(connector); 828 ret = amdgpu_connector_ddc_get_modes(connector); 829 830 return ret; 831 } 832 833 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 834 struct drm_display_mode *mode) 835 { 836 struct drm_device *dev = connector->dev; 837 struct amdgpu_device *adev = dev->dev_private; 838 839 /* XXX check mode bandwidth */ 840 841 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 842 return MODE_CLOCK_HIGH; 843 844 return MODE_OK; 845 } 846 847 static enum drm_connector_status 848 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 849 { 850 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 851 struct drm_encoder *encoder; 852 const struct drm_encoder_helper_funcs *encoder_funcs; 853 bool dret = false; 854 enum drm_connector_status ret = connector_status_disconnected; 855 int r; 856 857 if (!drm_kms_helper_is_poll_worker()) { 858 r = pm_runtime_get_sync(connector->dev->dev); 859 if (r < 0) 860 return connector_status_disconnected; 861 } 862 863 encoder = amdgpu_connector_best_single_encoder(connector); 864 if (!encoder) 865 ret = connector_status_disconnected; 866 867 if (amdgpu_connector->ddc_bus) 868 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 869 if (dret) { 870 amdgpu_connector->detected_by_load = false; 871 amdgpu_connector_free_edid(connector); 872 amdgpu_connector_get_edid(connector); 873 874 if (!amdgpu_connector->edid) { 875 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 876 connector->name); 877 ret = connector_status_connected; 878 } else { 879 amdgpu_connector->use_digital = 880 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 881 882 /* some oems have boards with separate digital and analog connectors 883 * with a shared ddc line (often vga + hdmi) 884 */ 885 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 886 amdgpu_connector_free_edid(connector); 887 ret = connector_status_disconnected; 888 } else { 889 ret = connector_status_connected; 890 } 891 } 892 } else { 893 894 /* if we aren't forcing don't do destructive polling */ 895 if (!force) { 896 /* only return the previous status if we last 897 * detected a monitor via load. 898 */ 899 if (amdgpu_connector->detected_by_load) 900 ret = connector->status; 901 goto out; 902 } 903 904 if (amdgpu_connector->dac_load_detect && encoder) { 905 encoder_funcs = encoder->helper_private; 906 ret = encoder_funcs->detect(encoder, connector); 907 if (ret != connector_status_disconnected) 908 amdgpu_connector->detected_by_load = true; 909 } 910 } 911 912 amdgpu_connector_update_scratch_regs(connector, ret); 913 914 out: 915 if (!drm_kms_helper_is_poll_worker()) { 916 pm_runtime_mark_last_busy(connector->dev->dev); 917 pm_runtime_put_autosuspend(connector->dev->dev); 918 } 919 920 return ret; 921 } 922 923 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 924 .get_modes = amdgpu_connector_vga_get_modes, 925 .mode_valid = amdgpu_connector_vga_mode_valid, 926 .best_encoder = amdgpu_connector_best_single_encoder, 927 }; 928 929 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 930 .dpms = drm_helper_connector_dpms, 931 .detect = amdgpu_connector_vga_detect, 932 .fill_modes = drm_helper_probe_single_connector_modes, 933 .early_unregister = amdgpu_connector_unregister, 934 .destroy = amdgpu_connector_destroy, 935 .set_property = amdgpu_connector_set_property, 936 }; 937 938 static bool 939 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 940 { 941 struct drm_device *dev = connector->dev; 942 struct amdgpu_device *adev = dev->dev_private; 943 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 944 enum drm_connector_status status; 945 946 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 947 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 948 status = connector_status_connected; 949 else 950 status = connector_status_disconnected; 951 if (connector->status == status) 952 return true; 953 } 954 955 return false; 956 } 957 958 /* 959 * DVI is complicated 960 * Do a DDC probe, if DDC probe passes, get the full EDID so 961 * we can do analog/digital monitor detection at this point. 962 * If the monitor is an analog monitor or we got no DDC, 963 * we need to find the DAC encoder object for this connector. 964 * If we got no DDC, we do load detection on the DAC encoder object. 965 * If we got analog DDC or load detection passes on the DAC encoder 966 * we have to check if this analog encoder is shared with anyone else (TV) 967 * if its shared we have to set the other connector to disconnected. 968 */ 969 static enum drm_connector_status 970 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 971 { 972 struct drm_device *dev = connector->dev; 973 struct amdgpu_device *adev = dev->dev_private; 974 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 975 const struct drm_encoder_helper_funcs *encoder_funcs; 976 int r; 977 enum drm_connector_status ret = connector_status_disconnected; 978 bool dret = false, broken_edid = false; 979 980 if (!drm_kms_helper_is_poll_worker()) { 981 r = pm_runtime_get_sync(connector->dev->dev); 982 if (r < 0) 983 return connector_status_disconnected; 984 } 985 986 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 987 ret = connector->status; 988 goto exit; 989 } 990 991 if (amdgpu_connector->ddc_bus) 992 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 993 if (dret) { 994 amdgpu_connector->detected_by_load = false; 995 amdgpu_connector_free_edid(connector); 996 amdgpu_connector_get_edid(connector); 997 998 if (!amdgpu_connector->edid) { 999 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1000 connector->name); 1001 ret = connector_status_connected; 1002 broken_edid = true; /* defer use_digital to later */ 1003 } else { 1004 amdgpu_connector->use_digital = 1005 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1006 1007 /* some oems have boards with separate digital and analog connectors 1008 * with a shared ddc line (often vga + hdmi) 1009 */ 1010 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1011 amdgpu_connector_free_edid(connector); 1012 ret = connector_status_disconnected; 1013 } else { 1014 ret = connector_status_connected; 1015 } 1016 1017 /* This gets complicated. We have boards with VGA + HDMI with a 1018 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1019 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1020 * you don't really know what's connected to which port as both are digital. 1021 */ 1022 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1023 struct drm_connector *list_connector; 1024 struct amdgpu_connector *list_amdgpu_connector; 1025 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1026 if (connector == list_connector) 1027 continue; 1028 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1029 if (list_amdgpu_connector->shared_ddc && 1030 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1031 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1032 /* cases where both connectors are digital */ 1033 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1034 /* hpd is our only option in this case */ 1035 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1036 amdgpu_connector_free_edid(connector); 1037 ret = connector_status_disconnected; 1038 } 1039 } 1040 } 1041 } 1042 } 1043 } 1044 } 1045 1046 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1047 goto out; 1048 1049 /* DVI-D and HDMI-A are digital only */ 1050 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1051 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1052 goto out; 1053 1054 /* if we aren't forcing don't do destructive polling */ 1055 if (!force) { 1056 /* only return the previous status if we last 1057 * detected a monitor via load. 1058 */ 1059 if (amdgpu_connector->detected_by_load) 1060 ret = connector->status; 1061 goto out; 1062 } 1063 1064 /* find analog encoder */ 1065 if (amdgpu_connector->dac_load_detect) { 1066 struct drm_encoder *encoder; 1067 int i; 1068 1069 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1070 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1071 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1072 continue; 1073 1074 encoder_funcs = encoder->helper_private; 1075 if (encoder_funcs->detect) { 1076 if (!broken_edid) { 1077 if (ret != connector_status_connected) { 1078 /* deal with analog monitors without DDC */ 1079 ret = encoder_funcs->detect(encoder, connector); 1080 if (ret == connector_status_connected) { 1081 amdgpu_connector->use_digital = false; 1082 } 1083 if (ret != connector_status_disconnected) 1084 amdgpu_connector->detected_by_load = true; 1085 } 1086 } else { 1087 enum drm_connector_status lret; 1088 /* assume digital unless load detected otherwise */ 1089 amdgpu_connector->use_digital = true; 1090 lret = encoder_funcs->detect(encoder, connector); 1091 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1092 if (lret == connector_status_connected) 1093 amdgpu_connector->use_digital = false; 1094 } 1095 break; 1096 } 1097 } 1098 } 1099 1100 out: 1101 /* updated in get modes as well since we need to know if it's analog or digital */ 1102 amdgpu_connector_update_scratch_regs(connector, ret); 1103 1104 exit: 1105 if (!drm_kms_helper_is_poll_worker()) { 1106 pm_runtime_mark_last_busy(connector->dev->dev); 1107 pm_runtime_put_autosuspend(connector->dev->dev); 1108 } 1109 1110 return ret; 1111 } 1112 1113 /* okay need to be smart in here about which encoder to pick */ 1114 static struct drm_encoder * 1115 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1116 { 1117 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1118 struct drm_encoder *encoder; 1119 int i; 1120 1121 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1122 if (amdgpu_connector->use_digital == true) { 1123 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1124 return encoder; 1125 } else { 1126 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1127 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1128 return encoder; 1129 } 1130 } 1131 1132 /* see if we have a default encoder TODO */ 1133 1134 /* then check use digitial */ 1135 /* pick the first one */ 1136 drm_connector_for_each_possible_encoder(connector, encoder, i) 1137 return encoder; 1138 1139 return NULL; 1140 } 1141 1142 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1143 { 1144 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1145 if (connector->force == DRM_FORCE_ON) 1146 amdgpu_connector->use_digital = false; 1147 if (connector->force == DRM_FORCE_ON_DIGITAL) 1148 amdgpu_connector->use_digital = true; 1149 } 1150 1151 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1152 struct drm_display_mode *mode) 1153 { 1154 struct drm_device *dev = connector->dev; 1155 struct amdgpu_device *adev = dev->dev_private; 1156 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1157 1158 /* XXX check mode bandwidth */ 1159 1160 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1161 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1162 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1163 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1164 return MODE_OK; 1165 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1166 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1167 if (mode->clock > 340000) 1168 return MODE_CLOCK_HIGH; 1169 else 1170 return MODE_OK; 1171 } else { 1172 return MODE_CLOCK_HIGH; 1173 } 1174 } 1175 1176 /* check against the max pixel clock */ 1177 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1178 return MODE_CLOCK_HIGH; 1179 1180 return MODE_OK; 1181 } 1182 1183 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1184 .get_modes = amdgpu_connector_vga_get_modes, 1185 .mode_valid = amdgpu_connector_dvi_mode_valid, 1186 .best_encoder = amdgpu_connector_dvi_encoder, 1187 }; 1188 1189 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1190 .dpms = drm_helper_connector_dpms, 1191 .detect = amdgpu_connector_dvi_detect, 1192 .fill_modes = drm_helper_probe_single_connector_modes, 1193 .set_property = amdgpu_connector_set_property, 1194 .early_unregister = amdgpu_connector_unregister, 1195 .destroy = amdgpu_connector_destroy, 1196 .force = amdgpu_connector_dvi_force, 1197 }; 1198 1199 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1200 { 1201 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1202 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1203 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1204 int ret; 1205 1206 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1207 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1208 struct drm_display_mode *mode; 1209 1210 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1211 if (!amdgpu_dig_connector->edp_on) 1212 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1213 ATOM_TRANSMITTER_ACTION_POWER_ON); 1214 amdgpu_connector_get_edid(connector); 1215 ret = amdgpu_connector_ddc_get_modes(connector); 1216 if (!amdgpu_dig_connector->edp_on) 1217 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1218 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1219 } else { 1220 /* need to setup ddc on the bridge */ 1221 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1222 ENCODER_OBJECT_ID_NONE) { 1223 if (encoder) 1224 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1225 } 1226 amdgpu_connector_get_edid(connector); 1227 ret = amdgpu_connector_ddc_get_modes(connector); 1228 } 1229 1230 if (ret > 0) { 1231 if (encoder) { 1232 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1233 /* add scaled modes */ 1234 amdgpu_connector_add_common_modes(encoder, connector); 1235 } 1236 return ret; 1237 } 1238 1239 if (!encoder) 1240 return 0; 1241 1242 /* we have no EDID modes */ 1243 mode = amdgpu_connector_lcd_native_mode(encoder); 1244 if (mode) { 1245 ret = 1; 1246 drm_mode_probed_add(connector, mode); 1247 /* add the width/height from vbios tables if available */ 1248 connector->display_info.width_mm = mode->width_mm; 1249 connector->display_info.height_mm = mode->height_mm; 1250 /* add scaled modes */ 1251 amdgpu_connector_add_common_modes(encoder, connector); 1252 } 1253 } else { 1254 /* need to setup ddc on the bridge */ 1255 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1256 ENCODER_OBJECT_ID_NONE) { 1257 if (encoder) 1258 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1259 } 1260 amdgpu_connector_get_edid(connector); 1261 ret = amdgpu_connector_ddc_get_modes(connector); 1262 1263 amdgpu_get_native_mode(connector); 1264 } 1265 1266 return ret; 1267 } 1268 1269 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1270 { 1271 struct drm_encoder *encoder; 1272 struct amdgpu_encoder *amdgpu_encoder; 1273 int i; 1274 1275 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1276 amdgpu_encoder = to_amdgpu_encoder(encoder); 1277 1278 switch (amdgpu_encoder->encoder_id) { 1279 case ENCODER_OBJECT_ID_TRAVIS: 1280 case ENCODER_OBJECT_ID_NUTMEG: 1281 return amdgpu_encoder->encoder_id; 1282 default: 1283 break; 1284 } 1285 } 1286 1287 return ENCODER_OBJECT_ID_NONE; 1288 } 1289 1290 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1291 { 1292 struct drm_encoder *encoder; 1293 struct amdgpu_encoder *amdgpu_encoder; 1294 int i; 1295 bool found = false; 1296 1297 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1298 amdgpu_encoder = to_amdgpu_encoder(encoder); 1299 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1300 found = true; 1301 } 1302 1303 return found; 1304 } 1305 1306 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1307 { 1308 struct drm_device *dev = connector->dev; 1309 struct amdgpu_device *adev = dev->dev_private; 1310 1311 if ((adev->clock.default_dispclk >= 53900) && 1312 amdgpu_connector_encoder_is_hbr2(connector)) { 1313 return true; 1314 } 1315 1316 return false; 1317 } 1318 1319 static enum drm_connector_status 1320 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1321 { 1322 struct drm_device *dev = connector->dev; 1323 struct amdgpu_device *adev = dev->dev_private; 1324 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1325 enum drm_connector_status ret = connector_status_disconnected; 1326 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1327 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1328 int r; 1329 1330 if (!drm_kms_helper_is_poll_worker()) { 1331 r = pm_runtime_get_sync(connector->dev->dev); 1332 if (r < 0) 1333 return connector_status_disconnected; 1334 } 1335 1336 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1337 ret = connector->status; 1338 goto out; 1339 } 1340 1341 amdgpu_connector_free_edid(connector); 1342 1343 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1344 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1345 if (encoder) { 1346 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1347 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1348 1349 /* check if panel is valid */ 1350 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1351 ret = connector_status_connected; 1352 } 1353 /* eDP is always DP */ 1354 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1355 if (!amdgpu_dig_connector->edp_on) 1356 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1357 ATOM_TRANSMITTER_ACTION_POWER_ON); 1358 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1359 ret = connector_status_connected; 1360 if (!amdgpu_dig_connector->edp_on) 1361 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1362 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1363 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1364 ENCODER_OBJECT_ID_NONE) { 1365 /* DP bridges are always DP */ 1366 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1367 /* get the DPCD from the bridge */ 1368 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1369 1370 if (encoder) { 1371 /* setup ddc on the bridge */ 1372 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1373 /* bridge chips are always aux */ 1374 /* try DDC */ 1375 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1376 ret = connector_status_connected; 1377 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1378 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1379 ret = encoder_funcs->detect(encoder, connector); 1380 } 1381 } 1382 } else { 1383 amdgpu_dig_connector->dp_sink_type = 1384 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1385 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1386 ret = connector_status_connected; 1387 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1388 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1389 } else { 1390 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1391 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1392 ret = connector_status_connected; 1393 } else { 1394 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1395 if (amdgpu_display_ddc_probe(amdgpu_connector, 1396 false)) 1397 ret = connector_status_connected; 1398 } 1399 } 1400 } 1401 1402 amdgpu_connector_update_scratch_regs(connector, ret); 1403 out: 1404 if (!drm_kms_helper_is_poll_worker()) { 1405 pm_runtime_mark_last_busy(connector->dev->dev); 1406 pm_runtime_put_autosuspend(connector->dev->dev); 1407 } 1408 1409 return ret; 1410 } 1411 1412 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1413 struct drm_display_mode *mode) 1414 { 1415 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1416 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1417 1418 /* XXX check mode bandwidth */ 1419 1420 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1421 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1422 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1423 1424 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1425 return MODE_PANEL; 1426 1427 if (encoder) { 1428 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1429 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1430 1431 /* AVIVO hardware supports downscaling modes larger than the panel 1432 * to the panel size, but I'm not sure this is desirable. 1433 */ 1434 if ((mode->hdisplay > native_mode->hdisplay) || 1435 (mode->vdisplay > native_mode->vdisplay)) 1436 return MODE_PANEL; 1437 1438 /* if scaling is disabled, block non-native modes */ 1439 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1440 if ((mode->hdisplay != native_mode->hdisplay) || 1441 (mode->vdisplay != native_mode->vdisplay)) 1442 return MODE_PANEL; 1443 } 1444 } 1445 return MODE_OK; 1446 } else { 1447 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1448 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1449 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1450 } else { 1451 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1452 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1453 if (mode->clock > 340000) 1454 return MODE_CLOCK_HIGH; 1455 } else { 1456 if (mode->clock > 165000) 1457 return MODE_CLOCK_HIGH; 1458 } 1459 } 1460 } 1461 1462 return MODE_OK; 1463 } 1464 1465 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1466 .get_modes = amdgpu_connector_dp_get_modes, 1467 .mode_valid = amdgpu_connector_dp_mode_valid, 1468 .best_encoder = amdgpu_connector_dvi_encoder, 1469 }; 1470 1471 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1472 .dpms = drm_helper_connector_dpms, 1473 .detect = amdgpu_connector_dp_detect, 1474 .fill_modes = drm_helper_probe_single_connector_modes, 1475 .set_property = amdgpu_connector_set_property, 1476 .early_unregister = amdgpu_connector_unregister, 1477 .destroy = amdgpu_connector_destroy, 1478 .force = amdgpu_connector_dvi_force, 1479 }; 1480 1481 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1482 .dpms = drm_helper_connector_dpms, 1483 .detect = amdgpu_connector_dp_detect, 1484 .fill_modes = drm_helper_probe_single_connector_modes, 1485 .set_property = amdgpu_connector_set_lcd_property, 1486 .early_unregister = amdgpu_connector_unregister, 1487 .destroy = amdgpu_connector_destroy, 1488 .force = amdgpu_connector_dvi_force, 1489 }; 1490 1491 void 1492 amdgpu_connector_add(struct amdgpu_device *adev, 1493 uint32_t connector_id, 1494 uint32_t supported_device, 1495 int connector_type, 1496 struct amdgpu_i2c_bus_rec *i2c_bus, 1497 uint16_t connector_object_id, 1498 struct amdgpu_hpd *hpd, 1499 struct amdgpu_router *router) 1500 { 1501 struct drm_device *dev = adev->ddev; 1502 struct drm_connector *connector; 1503 struct amdgpu_connector *amdgpu_connector; 1504 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1505 struct drm_encoder *encoder; 1506 struct amdgpu_encoder *amdgpu_encoder; 1507 uint32_t subpixel_order = SubPixelNone; 1508 bool shared_ddc = false; 1509 bool is_dp_bridge = false; 1510 bool has_aux = false; 1511 1512 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1513 return; 1514 1515 /* see if we already added it */ 1516 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1517 amdgpu_connector = to_amdgpu_connector(connector); 1518 if (amdgpu_connector->connector_id == connector_id) { 1519 amdgpu_connector->devices |= supported_device; 1520 return; 1521 } 1522 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1523 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1524 amdgpu_connector->shared_ddc = true; 1525 shared_ddc = true; 1526 } 1527 if (amdgpu_connector->router_bus && router->ddc_valid && 1528 (amdgpu_connector->router.router_id == router->router_id)) { 1529 amdgpu_connector->shared_ddc = false; 1530 shared_ddc = false; 1531 } 1532 } 1533 } 1534 1535 /* check if it's a dp bridge */ 1536 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1537 amdgpu_encoder = to_amdgpu_encoder(encoder); 1538 if (amdgpu_encoder->devices & supported_device) { 1539 switch (amdgpu_encoder->encoder_id) { 1540 case ENCODER_OBJECT_ID_TRAVIS: 1541 case ENCODER_OBJECT_ID_NUTMEG: 1542 is_dp_bridge = true; 1543 break; 1544 default: 1545 break; 1546 } 1547 } 1548 } 1549 1550 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1551 if (!amdgpu_connector) 1552 return; 1553 1554 connector = &amdgpu_connector->base; 1555 1556 amdgpu_connector->connector_id = connector_id; 1557 amdgpu_connector->devices = supported_device; 1558 amdgpu_connector->shared_ddc = shared_ddc; 1559 amdgpu_connector->connector_object_id = connector_object_id; 1560 amdgpu_connector->hpd = *hpd; 1561 1562 amdgpu_connector->router = *router; 1563 if (router->ddc_valid || router->cd_valid) { 1564 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1565 if (!amdgpu_connector->router_bus) 1566 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1567 } 1568 1569 if (is_dp_bridge) { 1570 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1571 if (!amdgpu_dig_connector) 1572 goto failed; 1573 amdgpu_connector->con_priv = amdgpu_dig_connector; 1574 if (i2c_bus->valid) { 1575 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1576 if (amdgpu_connector->ddc_bus) 1577 has_aux = true; 1578 else 1579 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1580 } 1581 switch (connector_type) { 1582 case DRM_MODE_CONNECTOR_VGA: 1583 case DRM_MODE_CONNECTOR_DVIA: 1584 default: 1585 drm_connector_init(dev, &amdgpu_connector->base, 1586 &amdgpu_connector_dp_funcs, connector_type); 1587 drm_connector_helper_add(&amdgpu_connector->base, 1588 &amdgpu_connector_dp_helper_funcs); 1589 connector->interlace_allowed = true; 1590 connector->doublescan_allowed = true; 1591 amdgpu_connector->dac_load_detect = true; 1592 drm_object_attach_property(&amdgpu_connector->base.base, 1593 adev->mode_info.load_detect_property, 1594 1); 1595 drm_object_attach_property(&amdgpu_connector->base.base, 1596 dev->mode_config.scaling_mode_property, 1597 DRM_MODE_SCALE_NONE); 1598 break; 1599 case DRM_MODE_CONNECTOR_DVII: 1600 case DRM_MODE_CONNECTOR_DVID: 1601 case DRM_MODE_CONNECTOR_HDMIA: 1602 case DRM_MODE_CONNECTOR_HDMIB: 1603 case DRM_MODE_CONNECTOR_DisplayPort: 1604 drm_connector_init(dev, &amdgpu_connector->base, 1605 &amdgpu_connector_dp_funcs, connector_type); 1606 drm_connector_helper_add(&amdgpu_connector->base, 1607 &amdgpu_connector_dp_helper_funcs); 1608 drm_object_attach_property(&amdgpu_connector->base.base, 1609 adev->mode_info.underscan_property, 1610 UNDERSCAN_OFF); 1611 drm_object_attach_property(&amdgpu_connector->base.base, 1612 adev->mode_info.underscan_hborder_property, 1613 0); 1614 drm_object_attach_property(&amdgpu_connector->base.base, 1615 adev->mode_info.underscan_vborder_property, 1616 0); 1617 1618 drm_object_attach_property(&amdgpu_connector->base.base, 1619 dev->mode_config.scaling_mode_property, 1620 DRM_MODE_SCALE_NONE); 1621 1622 drm_object_attach_property(&amdgpu_connector->base.base, 1623 adev->mode_info.dither_property, 1624 AMDGPU_FMT_DITHER_DISABLE); 1625 1626 if (amdgpu_audio != 0) 1627 drm_object_attach_property(&amdgpu_connector->base.base, 1628 adev->mode_info.audio_property, 1629 AMDGPU_AUDIO_AUTO); 1630 1631 subpixel_order = SubPixelHorizontalRGB; 1632 connector->interlace_allowed = true; 1633 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1634 connector->doublescan_allowed = true; 1635 else 1636 connector->doublescan_allowed = false; 1637 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1638 amdgpu_connector->dac_load_detect = true; 1639 drm_object_attach_property(&amdgpu_connector->base.base, 1640 adev->mode_info.load_detect_property, 1641 1); 1642 } 1643 break; 1644 case DRM_MODE_CONNECTOR_LVDS: 1645 case DRM_MODE_CONNECTOR_eDP: 1646 drm_connector_init(dev, &amdgpu_connector->base, 1647 &amdgpu_connector_edp_funcs, connector_type); 1648 drm_connector_helper_add(&amdgpu_connector->base, 1649 &amdgpu_connector_dp_helper_funcs); 1650 drm_object_attach_property(&amdgpu_connector->base.base, 1651 dev->mode_config.scaling_mode_property, 1652 DRM_MODE_SCALE_FULLSCREEN); 1653 subpixel_order = SubPixelHorizontalRGB; 1654 connector->interlace_allowed = false; 1655 connector->doublescan_allowed = false; 1656 break; 1657 } 1658 } else { 1659 switch (connector_type) { 1660 case DRM_MODE_CONNECTOR_VGA: 1661 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1662 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1663 if (i2c_bus->valid) { 1664 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1665 if (!amdgpu_connector->ddc_bus) 1666 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1667 } 1668 amdgpu_connector->dac_load_detect = true; 1669 drm_object_attach_property(&amdgpu_connector->base.base, 1670 adev->mode_info.load_detect_property, 1671 1); 1672 drm_object_attach_property(&amdgpu_connector->base.base, 1673 dev->mode_config.scaling_mode_property, 1674 DRM_MODE_SCALE_NONE); 1675 /* no HPD on analog connectors */ 1676 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1677 connector->interlace_allowed = true; 1678 connector->doublescan_allowed = true; 1679 break; 1680 case DRM_MODE_CONNECTOR_DVIA: 1681 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1682 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1683 if (i2c_bus->valid) { 1684 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1685 if (!amdgpu_connector->ddc_bus) 1686 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1687 } 1688 amdgpu_connector->dac_load_detect = true; 1689 drm_object_attach_property(&amdgpu_connector->base.base, 1690 adev->mode_info.load_detect_property, 1691 1); 1692 drm_object_attach_property(&amdgpu_connector->base.base, 1693 dev->mode_config.scaling_mode_property, 1694 DRM_MODE_SCALE_NONE); 1695 /* no HPD on analog connectors */ 1696 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1697 connector->interlace_allowed = true; 1698 connector->doublescan_allowed = true; 1699 break; 1700 case DRM_MODE_CONNECTOR_DVII: 1701 case DRM_MODE_CONNECTOR_DVID: 1702 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1703 if (!amdgpu_dig_connector) 1704 goto failed; 1705 amdgpu_connector->con_priv = amdgpu_dig_connector; 1706 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1707 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1708 if (i2c_bus->valid) { 1709 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1710 if (!amdgpu_connector->ddc_bus) 1711 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1712 } 1713 subpixel_order = SubPixelHorizontalRGB; 1714 drm_object_attach_property(&amdgpu_connector->base.base, 1715 adev->mode_info.coherent_mode_property, 1716 1); 1717 drm_object_attach_property(&amdgpu_connector->base.base, 1718 adev->mode_info.underscan_property, 1719 UNDERSCAN_OFF); 1720 drm_object_attach_property(&amdgpu_connector->base.base, 1721 adev->mode_info.underscan_hborder_property, 1722 0); 1723 drm_object_attach_property(&amdgpu_connector->base.base, 1724 adev->mode_info.underscan_vborder_property, 1725 0); 1726 drm_object_attach_property(&amdgpu_connector->base.base, 1727 dev->mode_config.scaling_mode_property, 1728 DRM_MODE_SCALE_NONE); 1729 1730 if (amdgpu_audio != 0) { 1731 drm_object_attach_property(&amdgpu_connector->base.base, 1732 adev->mode_info.audio_property, 1733 AMDGPU_AUDIO_AUTO); 1734 } 1735 drm_object_attach_property(&amdgpu_connector->base.base, 1736 adev->mode_info.dither_property, 1737 AMDGPU_FMT_DITHER_DISABLE); 1738 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1739 amdgpu_connector->dac_load_detect = true; 1740 drm_object_attach_property(&amdgpu_connector->base.base, 1741 adev->mode_info.load_detect_property, 1742 1); 1743 } 1744 connector->interlace_allowed = true; 1745 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1746 connector->doublescan_allowed = true; 1747 else 1748 connector->doublescan_allowed = false; 1749 break; 1750 case DRM_MODE_CONNECTOR_HDMIA: 1751 case DRM_MODE_CONNECTOR_HDMIB: 1752 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1753 if (!amdgpu_dig_connector) 1754 goto failed; 1755 amdgpu_connector->con_priv = amdgpu_dig_connector; 1756 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1757 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1758 if (i2c_bus->valid) { 1759 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1760 if (!amdgpu_connector->ddc_bus) 1761 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1762 } 1763 drm_object_attach_property(&amdgpu_connector->base.base, 1764 adev->mode_info.coherent_mode_property, 1765 1); 1766 drm_object_attach_property(&amdgpu_connector->base.base, 1767 adev->mode_info.underscan_property, 1768 UNDERSCAN_OFF); 1769 drm_object_attach_property(&amdgpu_connector->base.base, 1770 adev->mode_info.underscan_hborder_property, 1771 0); 1772 drm_object_attach_property(&amdgpu_connector->base.base, 1773 adev->mode_info.underscan_vborder_property, 1774 0); 1775 drm_object_attach_property(&amdgpu_connector->base.base, 1776 dev->mode_config.scaling_mode_property, 1777 DRM_MODE_SCALE_NONE); 1778 if (amdgpu_audio != 0) { 1779 drm_object_attach_property(&amdgpu_connector->base.base, 1780 adev->mode_info.audio_property, 1781 AMDGPU_AUDIO_AUTO); 1782 } 1783 drm_object_attach_property(&amdgpu_connector->base.base, 1784 adev->mode_info.dither_property, 1785 AMDGPU_FMT_DITHER_DISABLE); 1786 subpixel_order = SubPixelHorizontalRGB; 1787 connector->interlace_allowed = true; 1788 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1789 connector->doublescan_allowed = true; 1790 else 1791 connector->doublescan_allowed = false; 1792 break; 1793 case DRM_MODE_CONNECTOR_DisplayPort: 1794 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1795 if (!amdgpu_dig_connector) 1796 goto failed; 1797 amdgpu_connector->con_priv = amdgpu_dig_connector; 1798 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1799 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1800 if (i2c_bus->valid) { 1801 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1802 if (amdgpu_connector->ddc_bus) 1803 has_aux = true; 1804 else 1805 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1806 } 1807 subpixel_order = SubPixelHorizontalRGB; 1808 drm_object_attach_property(&amdgpu_connector->base.base, 1809 adev->mode_info.coherent_mode_property, 1810 1); 1811 drm_object_attach_property(&amdgpu_connector->base.base, 1812 adev->mode_info.underscan_property, 1813 UNDERSCAN_OFF); 1814 drm_object_attach_property(&amdgpu_connector->base.base, 1815 adev->mode_info.underscan_hborder_property, 1816 0); 1817 drm_object_attach_property(&amdgpu_connector->base.base, 1818 adev->mode_info.underscan_vborder_property, 1819 0); 1820 drm_object_attach_property(&amdgpu_connector->base.base, 1821 dev->mode_config.scaling_mode_property, 1822 DRM_MODE_SCALE_NONE); 1823 if (amdgpu_audio != 0) { 1824 drm_object_attach_property(&amdgpu_connector->base.base, 1825 adev->mode_info.audio_property, 1826 AMDGPU_AUDIO_AUTO); 1827 } 1828 drm_object_attach_property(&amdgpu_connector->base.base, 1829 adev->mode_info.dither_property, 1830 AMDGPU_FMT_DITHER_DISABLE); 1831 connector->interlace_allowed = true; 1832 /* in theory with a DP to VGA converter... */ 1833 connector->doublescan_allowed = false; 1834 break; 1835 case DRM_MODE_CONNECTOR_eDP: 1836 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1837 if (!amdgpu_dig_connector) 1838 goto failed; 1839 amdgpu_connector->con_priv = amdgpu_dig_connector; 1840 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1841 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1842 if (i2c_bus->valid) { 1843 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1844 if (amdgpu_connector->ddc_bus) 1845 has_aux = true; 1846 else 1847 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1848 } 1849 drm_object_attach_property(&amdgpu_connector->base.base, 1850 dev->mode_config.scaling_mode_property, 1851 DRM_MODE_SCALE_FULLSCREEN); 1852 subpixel_order = SubPixelHorizontalRGB; 1853 connector->interlace_allowed = false; 1854 connector->doublescan_allowed = false; 1855 break; 1856 case DRM_MODE_CONNECTOR_LVDS: 1857 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1858 if (!amdgpu_dig_connector) 1859 goto failed; 1860 amdgpu_connector->con_priv = amdgpu_dig_connector; 1861 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1862 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1863 if (i2c_bus->valid) { 1864 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1865 if (!amdgpu_connector->ddc_bus) 1866 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1867 } 1868 drm_object_attach_property(&amdgpu_connector->base.base, 1869 dev->mode_config.scaling_mode_property, 1870 DRM_MODE_SCALE_FULLSCREEN); 1871 subpixel_order = SubPixelHorizontalRGB; 1872 connector->interlace_allowed = false; 1873 connector->doublescan_allowed = false; 1874 break; 1875 } 1876 } 1877 1878 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1879 if (i2c_bus->valid) { 1880 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1881 DRM_CONNECTOR_POLL_DISCONNECT; 1882 } 1883 } else 1884 connector->polled = DRM_CONNECTOR_POLL_HPD; 1885 1886 connector->display_info.subpixel_order = subpixel_order; 1887 drm_connector_register(connector); 1888 1889 if (has_aux) 1890 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1891 1892 return; 1893 1894 failed: 1895 drm_connector_cleanup(connector); 1896 kfree(connector); 1897 } 1898