1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_probe_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 #include "amdgpu_display.h" 38 39 #include <linux/pm_runtime.h> 40 41 void amdgpu_connector_hotplug(struct drm_connector *connector) 42 { 43 struct drm_device *dev = connector->dev; 44 struct amdgpu_device *adev = drm_to_adev(dev); 45 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 46 47 /* bail if the connector does not have hpd pin, e.g., 48 * VGA, TV, etc. 49 */ 50 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 51 return; 52 53 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 54 55 /* if the connector is already off, don't turn it back on */ 56 if (connector->dpms != DRM_MODE_DPMS_ON) 57 return; 58 59 /* just deal with DP (not eDP) here. */ 60 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 61 struct amdgpu_connector_atom_dig *dig_connector = 62 amdgpu_connector->con_priv; 63 64 /* if existing sink type was not DP no need to retrain */ 65 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 66 return; 67 68 /* first get sink type as it may be reset after (un)plug */ 69 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 70 /* don't do anything if sink is not display port, i.e., 71 * passive dp->(dvi|hdmi) adaptor 72 */ 73 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 74 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 75 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 76 /* Don't start link training before we have the DPCD */ 77 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 78 return; 79 80 /* Turn the connector off and back on immediately, which 81 * will trigger link training 82 */ 83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 84 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 85 } 86 } 87 } 88 89 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 90 { 91 struct drm_crtc *crtc = encoder->crtc; 92 93 if (crtc && crtc->enabled) { 94 drm_crtc_helper_set_mode(crtc, &crtc->mode, 95 crtc->x, crtc->y, crtc->primary->fb); 96 } 97 } 98 99 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 100 { 101 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 102 struct amdgpu_connector_atom_dig *dig_connector; 103 int bpc = 8; 104 unsigned mode_clock, max_tmds_clock; 105 106 switch (connector->connector_type) { 107 case DRM_MODE_CONNECTOR_DVII: 108 case DRM_MODE_CONNECTOR_HDMIB: 109 if (amdgpu_connector->use_digital) { 110 if (connector->display_info.is_hdmi) { 111 if (connector->display_info.bpc) 112 bpc = connector->display_info.bpc; 113 } 114 } 115 break; 116 case DRM_MODE_CONNECTOR_DVID: 117 case DRM_MODE_CONNECTOR_HDMIA: 118 if (connector->display_info.is_hdmi) { 119 if (connector->display_info.bpc) 120 bpc = connector->display_info.bpc; 121 } 122 break; 123 case DRM_MODE_CONNECTOR_DisplayPort: 124 dig_connector = amdgpu_connector->con_priv; 125 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 126 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 127 connector->display_info.is_hdmi) { 128 if (connector->display_info.bpc) 129 bpc = connector->display_info.bpc; 130 } 131 break; 132 case DRM_MODE_CONNECTOR_eDP: 133 case DRM_MODE_CONNECTOR_LVDS: 134 if (connector->display_info.bpc) 135 bpc = connector->display_info.bpc; 136 else { 137 const struct drm_connector_helper_funcs *connector_funcs = 138 connector->helper_private; 139 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 140 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 141 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 142 143 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 144 bpc = 6; 145 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 146 bpc = 8; 147 } 148 break; 149 } 150 151 if (connector->display_info.is_hdmi) { 152 /* 153 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 154 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 155 * 12 bpc is always supported on hdmi deep color sinks, as this is 156 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 157 */ 158 if (bpc > 12) { 159 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 160 connector->name, bpc); 161 bpc = 12; 162 } 163 164 /* Any defined maximum tmds clock limit we must not exceed? */ 165 if (connector->display_info.max_tmds_clock > 0) { 166 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 167 mode_clock = amdgpu_connector->pixelclock_for_modeset; 168 169 /* Maximum allowable input clock in kHz */ 170 max_tmds_clock = connector->display_info.max_tmds_clock; 171 172 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 173 connector->name, mode_clock, max_tmds_clock); 174 175 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 176 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 177 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 178 (mode_clock * 5/4 <= max_tmds_clock)) 179 bpc = 10; 180 else 181 bpc = 8; 182 183 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 184 connector->name, bpc); 185 } 186 187 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 188 bpc = 8; 189 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 190 connector->name, bpc); 191 } 192 } else if (bpc > 8) { 193 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 194 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 195 connector->name); 196 bpc = 8; 197 } 198 } 199 200 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 201 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 202 connector->name); 203 bpc = 8; 204 } 205 206 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 207 connector->name, connector->display_info.bpc, bpc); 208 209 return bpc; 210 } 211 212 static void 213 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 214 enum drm_connector_status status) 215 { 216 struct drm_encoder *best_encoder; 217 struct drm_encoder *encoder; 218 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 219 bool connected; 220 221 best_encoder = connector_funcs->best_encoder(connector); 222 223 drm_connector_for_each_possible_encoder(connector, encoder) { 224 if ((encoder == best_encoder) && (status == connector_status_connected)) 225 connected = true; 226 else 227 connected = false; 228 229 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 230 } 231 } 232 233 static struct drm_encoder * 234 amdgpu_connector_find_encoder(struct drm_connector *connector, 235 int encoder_type) 236 { 237 struct drm_encoder *encoder; 238 239 drm_connector_for_each_possible_encoder(connector, encoder) { 240 if (encoder->encoder_type == encoder_type) 241 return encoder; 242 } 243 244 return NULL; 245 } 246 247 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 248 { 249 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 250 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 251 252 if (amdgpu_connector->edid) { 253 return amdgpu_connector->edid; 254 } else if (edid_blob) { 255 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 256 if (edid) 257 amdgpu_connector->edid = edid; 258 } 259 return amdgpu_connector->edid; 260 } 261 262 static struct edid * 263 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 264 { 265 struct edid *edid; 266 267 if (adev->mode_info.bios_hardcoded_edid) { 268 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 269 if (edid) { 270 memcpy((unsigned char *)edid, 271 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 272 adev->mode_info.bios_hardcoded_edid_size); 273 return edid; 274 } 275 } 276 return NULL; 277 } 278 279 static void amdgpu_connector_get_edid(struct drm_connector *connector) 280 { 281 struct drm_device *dev = connector->dev; 282 struct amdgpu_device *adev = drm_to_adev(dev); 283 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 284 285 if (amdgpu_connector->edid) 286 return; 287 288 /* on hw with routers, select right port */ 289 if (amdgpu_connector->router.ddc_valid) 290 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 291 292 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 293 ENCODER_OBJECT_ID_NONE) && 294 amdgpu_connector->ddc_bus->has_aux) { 295 amdgpu_connector->edid = drm_get_edid(connector, 296 &amdgpu_connector->ddc_bus->aux.ddc); 297 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 298 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 299 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 300 301 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 302 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 303 amdgpu_connector->ddc_bus->has_aux) 304 amdgpu_connector->edid = drm_get_edid(connector, 305 &amdgpu_connector->ddc_bus->aux.ddc); 306 else if (amdgpu_connector->ddc_bus) 307 amdgpu_connector->edid = drm_get_edid(connector, 308 &amdgpu_connector->ddc_bus->adapter); 309 } else if (amdgpu_connector->ddc_bus) { 310 amdgpu_connector->edid = drm_get_edid(connector, 311 &amdgpu_connector->ddc_bus->adapter); 312 } 313 314 if (!amdgpu_connector->edid) { 315 /* some laptops provide a hardcoded edid in rom for LCDs */ 316 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 317 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 318 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 319 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 320 } 321 } 322 } 323 324 static void amdgpu_connector_free_edid(struct drm_connector *connector) 325 { 326 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 327 328 kfree(amdgpu_connector->edid); 329 amdgpu_connector->edid = NULL; 330 } 331 332 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 333 { 334 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 335 int ret; 336 337 if (amdgpu_connector->edid) { 338 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 339 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 340 return ret; 341 } 342 drm_connector_update_edid_property(connector, NULL); 343 return 0; 344 } 345 346 static struct drm_encoder * 347 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 348 { 349 struct drm_encoder *encoder; 350 351 /* pick the first one */ 352 drm_connector_for_each_possible_encoder(connector, encoder) 353 return encoder; 354 355 return NULL; 356 } 357 358 static void amdgpu_get_native_mode(struct drm_connector *connector) 359 { 360 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 361 struct amdgpu_encoder *amdgpu_encoder; 362 363 if (encoder == NULL) 364 return; 365 366 amdgpu_encoder = to_amdgpu_encoder(encoder); 367 368 if (!list_empty(&connector->probed_modes)) { 369 struct drm_display_mode *preferred_mode = 370 list_first_entry(&connector->probed_modes, 371 struct drm_display_mode, head); 372 373 amdgpu_encoder->native_mode = *preferred_mode; 374 } else { 375 amdgpu_encoder->native_mode.clock = 0; 376 } 377 } 378 379 static struct drm_display_mode * 380 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 381 { 382 struct drm_device *dev = encoder->dev; 383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 384 struct drm_display_mode *mode = NULL; 385 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 386 387 if (native_mode->hdisplay != 0 && 388 native_mode->vdisplay != 0 && 389 native_mode->clock != 0) { 390 mode = drm_mode_duplicate(dev, native_mode); 391 if (!mode) 392 return NULL; 393 394 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 395 drm_mode_set_name(mode); 396 397 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 398 } else if (native_mode->hdisplay != 0 && 399 native_mode->vdisplay != 0) { 400 /* mac laptops without an edid */ 401 /* Note that this is not necessarily the exact panel mode, 402 * but an approximation based on the cvt formula. For these 403 * systems we should ideally read the mode info out of the 404 * registers or add a mode table, but this works and is much 405 * simpler. 406 */ 407 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 408 if (!mode) 409 return NULL; 410 411 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 412 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 413 } 414 return mode; 415 } 416 417 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 418 struct drm_connector *connector) 419 { 420 struct drm_device *dev = encoder->dev; 421 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 422 struct drm_display_mode *mode = NULL; 423 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 424 int i; 425 static const struct mode_size { 426 int w; 427 int h; 428 } common_modes[17] = { 429 { 640, 480}, 430 { 720, 480}, 431 { 800, 600}, 432 { 848, 480}, 433 {1024, 768}, 434 {1152, 768}, 435 {1280, 720}, 436 {1280, 800}, 437 {1280, 854}, 438 {1280, 960}, 439 {1280, 1024}, 440 {1440, 900}, 441 {1400, 1050}, 442 {1680, 1050}, 443 {1600, 1200}, 444 {1920, 1080}, 445 {1920, 1200} 446 }; 447 448 for (i = 0; i < 17; i++) { 449 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 450 if (common_modes[i].w > 1024 || 451 common_modes[i].h > 768) 452 continue; 453 } 454 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 455 if (common_modes[i].w > native_mode->hdisplay || 456 common_modes[i].h > native_mode->vdisplay || 457 (common_modes[i].w == native_mode->hdisplay && 458 common_modes[i].h == native_mode->vdisplay)) 459 continue; 460 } 461 if (common_modes[i].w < 320 || common_modes[i].h < 200) 462 continue; 463 464 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 465 drm_mode_probed_add(connector, mode); 466 } 467 } 468 469 static int amdgpu_connector_set_property(struct drm_connector *connector, 470 struct drm_property *property, 471 uint64_t val) 472 { 473 struct drm_device *dev = connector->dev; 474 struct amdgpu_device *adev = drm_to_adev(dev); 475 struct drm_encoder *encoder; 476 struct amdgpu_encoder *amdgpu_encoder; 477 478 if (property == adev->mode_info.coherent_mode_property) { 479 struct amdgpu_encoder_atom_dig *dig; 480 bool new_coherent_mode; 481 482 /* need to find digital encoder on connector */ 483 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 484 if (!encoder) 485 return 0; 486 487 amdgpu_encoder = to_amdgpu_encoder(encoder); 488 489 if (!amdgpu_encoder->enc_priv) 490 return 0; 491 492 dig = amdgpu_encoder->enc_priv; 493 new_coherent_mode = val ? true : false; 494 if (dig->coherent_mode != new_coherent_mode) { 495 dig->coherent_mode = new_coherent_mode; 496 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 497 } 498 } 499 500 if (property == adev->mode_info.audio_property) { 501 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 502 /* need to find digital encoder on connector */ 503 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 504 if (!encoder) 505 return 0; 506 507 amdgpu_encoder = to_amdgpu_encoder(encoder); 508 509 if (amdgpu_connector->audio != val) { 510 amdgpu_connector->audio = val; 511 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 512 } 513 } 514 515 if (property == adev->mode_info.dither_property) { 516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 517 /* need to find digital encoder on connector */ 518 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 519 if (!encoder) 520 return 0; 521 522 amdgpu_encoder = to_amdgpu_encoder(encoder); 523 524 if (amdgpu_connector->dither != val) { 525 amdgpu_connector->dither = val; 526 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 527 } 528 } 529 530 if (property == adev->mode_info.underscan_property) { 531 /* need to find digital encoder on connector */ 532 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 533 if (!encoder) 534 return 0; 535 536 amdgpu_encoder = to_amdgpu_encoder(encoder); 537 538 if (amdgpu_encoder->underscan_type != val) { 539 amdgpu_encoder->underscan_type = val; 540 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 541 } 542 } 543 544 if (property == adev->mode_info.underscan_hborder_property) { 545 /* need to find digital encoder on connector */ 546 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 547 if (!encoder) 548 return 0; 549 550 amdgpu_encoder = to_amdgpu_encoder(encoder); 551 552 if (amdgpu_encoder->underscan_hborder != val) { 553 amdgpu_encoder->underscan_hborder = val; 554 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 555 } 556 } 557 558 if (property == adev->mode_info.underscan_vborder_property) { 559 /* need to find digital encoder on connector */ 560 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 561 if (!encoder) 562 return 0; 563 564 amdgpu_encoder = to_amdgpu_encoder(encoder); 565 566 if (amdgpu_encoder->underscan_vborder != val) { 567 amdgpu_encoder->underscan_vborder = val; 568 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 569 } 570 } 571 572 if (property == adev->mode_info.load_detect_property) { 573 struct amdgpu_connector *amdgpu_connector = 574 to_amdgpu_connector(connector); 575 576 if (val == 0) 577 amdgpu_connector->dac_load_detect = false; 578 else 579 amdgpu_connector->dac_load_detect = true; 580 } 581 582 if (property == dev->mode_config.scaling_mode_property) { 583 enum amdgpu_rmx_type rmx_type; 584 585 if (connector->encoder) { 586 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 587 } else { 588 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 589 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 590 } 591 592 switch (val) { 593 default: 594 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 595 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 596 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 597 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 598 } 599 if (amdgpu_encoder->rmx_type == rmx_type) 600 return 0; 601 602 if ((rmx_type != DRM_MODE_SCALE_NONE) && 603 (amdgpu_encoder->native_mode.clock == 0)) 604 return 0; 605 606 amdgpu_encoder->rmx_type = rmx_type; 607 608 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 609 } 610 611 return 0; 612 } 613 614 static void 615 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 616 struct drm_connector *connector) 617 { 618 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 619 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 620 struct drm_display_mode *t, *mode; 621 622 /* If the EDID preferred mode doesn't match the native mode, use it */ 623 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 624 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 625 if (mode->hdisplay != native_mode->hdisplay || 626 mode->vdisplay != native_mode->vdisplay) 627 drm_mode_copy(native_mode, mode); 628 } 629 } 630 631 /* Try to get native mode details from EDID if necessary */ 632 if (!native_mode->clock) { 633 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 634 if (mode->hdisplay == native_mode->hdisplay && 635 mode->vdisplay == native_mode->vdisplay) { 636 drm_mode_copy(native_mode, mode); 637 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 638 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 639 break; 640 } 641 } 642 } 643 644 if (!native_mode->clock) { 645 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 646 amdgpu_encoder->rmx_type = RMX_OFF; 647 } 648 } 649 650 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 651 { 652 struct drm_encoder *encoder; 653 int ret = 0; 654 struct drm_display_mode *mode; 655 656 amdgpu_connector_get_edid(connector); 657 ret = amdgpu_connector_ddc_get_modes(connector); 658 if (ret > 0) { 659 encoder = amdgpu_connector_best_single_encoder(connector); 660 if (encoder) { 661 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 662 /* add scaled modes */ 663 amdgpu_connector_add_common_modes(encoder, connector); 664 } 665 return ret; 666 } 667 668 encoder = amdgpu_connector_best_single_encoder(connector); 669 if (!encoder) 670 return 0; 671 672 /* we have no EDID modes */ 673 mode = amdgpu_connector_lcd_native_mode(encoder); 674 if (mode) { 675 ret = 1; 676 drm_mode_probed_add(connector, mode); 677 /* add the width/height from vbios tables if available */ 678 connector->display_info.width_mm = mode->width_mm; 679 connector->display_info.height_mm = mode->height_mm; 680 /* add scaled modes */ 681 amdgpu_connector_add_common_modes(encoder, connector); 682 } 683 684 return ret; 685 } 686 687 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 688 struct drm_display_mode *mode) 689 { 690 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 691 692 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 693 return MODE_PANEL; 694 695 if (encoder) { 696 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 697 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 698 699 /* AVIVO hardware supports downscaling modes larger than the panel 700 * to the panel size, but I'm not sure this is desirable. 701 */ 702 if ((mode->hdisplay > native_mode->hdisplay) || 703 (mode->vdisplay > native_mode->vdisplay)) 704 return MODE_PANEL; 705 706 /* if scaling is disabled, block non-native modes */ 707 if (amdgpu_encoder->rmx_type == RMX_OFF) { 708 if ((mode->hdisplay != native_mode->hdisplay) || 709 (mode->vdisplay != native_mode->vdisplay)) 710 return MODE_PANEL; 711 } 712 } 713 714 return MODE_OK; 715 } 716 717 static enum drm_connector_status 718 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 719 { 720 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 721 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 722 enum drm_connector_status ret = connector_status_disconnected; 723 int r; 724 725 if (!drm_kms_helper_is_poll_worker()) { 726 r = pm_runtime_get_sync(connector->dev->dev); 727 if (r < 0) { 728 pm_runtime_put_autosuspend(connector->dev->dev); 729 return connector_status_disconnected; 730 } 731 } 732 733 if (encoder) { 734 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 735 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 736 737 /* check if panel is valid */ 738 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 739 ret = connector_status_connected; 740 741 } 742 743 /* check for edid as well */ 744 amdgpu_connector_get_edid(connector); 745 if (amdgpu_connector->edid) 746 ret = connector_status_connected; 747 /* check acpi lid status ??? */ 748 749 amdgpu_connector_update_scratch_regs(connector, ret); 750 751 if (!drm_kms_helper_is_poll_worker()) { 752 pm_runtime_mark_last_busy(connector->dev->dev); 753 pm_runtime_put_autosuspend(connector->dev->dev); 754 } 755 756 return ret; 757 } 758 759 static void amdgpu_connector_unregister(struct drm_connector *connector) 760 { 761 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 762 763 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 764 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 765 amdgpu_connector->ddc_bus->has_aux = false; 766 } 767 } 768 769 static void amdgpu_connector_destroy(struct drm_connector *connector) 770 { 771 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 772 773 amdgpu_connector_free_edid(connector); 774 kfree(amdgpu_connector->con_priv); 775 drm_connector_unregister(connector); 776 drm_connector_cleanup(connector); 777 kfree(connector); 778 } 779 780 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 781 struct drm_property *property, 782 uint64_t value) 783 { 784 struct drm_device *dev = connector->dev; 785 struct amdgpu_encoder *amdgpu_encoder; 786 enum amdgpu_rmx_type rmx_type; 787 788 DRM_DEBUG_KMS("\n"); 789 if (property != dev->mode_config.scaling_mode_property) 790 return 0; 791 792 if (connector->encoder) 793 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 794 else { 795 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 796 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 797 } 798 799 switch (value) { 800 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 801 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 802 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 803 default: 804 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 805 } 806 if (amdgpu_encoder->rmx_type == rmx_type) 807 return 0; 808 809 amdgpu_encoder->rmx_type = rmx_type; 810 811 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 812 return 0; 813 } 814 815 816 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 817 .get_modes = amdgpu_connector_lvds_get_modes, 818 .mode_valid = amdgpu_connector_lvds_mode_valid, 819 .best_encoder = amdgpu_connector_best_single_encoder, 820 }; 821 822 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 823 .dpms = drm_helper_connector_dpms, 824 .detect = amdgpu_connector_lvds_detect, 825 .fill_modes = drm_helper_probe_single_connector_modes, 826 .early_unregister = amdgpu_connector_unregister, 827 .destroy = amdgpu_connector_destroy, 828 .set_property = amdgpu_connector_set_lcd_property, 829 }; 830 831 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 832 { 833 int ret; 834 835 amdgpu_connector_get_edid(connector); 836 ret = amdgpu_connector_ddc_get_modes(connector); 837 amdgpu_get_native_mode(connector); 838 839 return ret; 840 } 841 842 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 843 struct drm_display_mode *mode) 844 { 845 struct drm_device *dev = connector->dev; 846 struct amdgpu_device *adev = drm_to_adev(dev); 847 848 /* XXX check mode bandwidth */ 849 850 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 851 return MODE_CLOCK_HIGH; 852 853 return MODE_OK; 854 } 855 856 static enum drm_connector_status 857 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 858 { 859 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 860 struct drm_encoder *encoder; 861 const struct drm_encoder_helper_funcs *encoder_funcs; 862 bool dret = false; 863 enum drm_connector_status ret = connector_status_disconnected; 864 int r; 865 866 if (!drm_kms_helper_is_poll_worker()) { 867 r = pm_runtime_get_sync(connector->dev->dev); 868 if (r < 0) { 869 pm_runtime_put_autosuspend(connector->dev->dev); 870 return connector_status_disconnected; 871 } 872 } 873 874 encoder = amdgpu_connector_best_single_encoder(connector); 875 if (!encoder) 876 ret = connector_status_disconnected; 877 878 if (amdgpu_connector->ddc_bus) 879 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 880 if (dret) { 881 amdgpu_connector->detected_by_load = false; 882 amdgpu_connector_free_edid(connector); 883 amdgpu_connector_get_edid(connector); 884 885 if (!amdgpu_connector->edid) { 886 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 887 connector->name); 888 ret = connector_status_connected; 889 } else { 890 amdgpu_connector->use_digital = 891 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 892 893 /* some oems have boards with separate digital and analog connectors 894 * with a shared ddc line (often vga + hdmi) 895 */ 896 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 897 amdgpu_connector_free_edid(connector); 898 ret = connector_status_disconnected; 899 } else { 900 ret = connector_status_connected; 901 } 902 } 903 } else { 904 905 /* if we aren't forcing don't do destructive polling */ 906 if (!force) { 907 /* only return the previous status if we last 908 * detected a monitor via load. 909 */ 910 if (amdgpu_connector->detected_by_load) 911 ret = connector->status; 912 goto out; 913 } 914 915 if (amdgpu_connector->dac_load_detect && encoder) { 916 encoder_funcs = encoder->helper_private; 917 ret = encoder_funcs->detect(encoder, connector); 918 if (ret != connector_status_disconnected) 919 amdgpu_connector->detected_by_load = true; 920 } 921 } 922 923 amdgpu_connector_update_scratch_regs(connector, ret); 924 925 out: 926 if (!drm_kms_helper_is_poll_worker()) { 927 pm_runtime_mark_last_busy(connector->dev->dev); 928 pm_runtime_put_autosuspend(connector->dev->dev); 929 } 930 931 return ret; 932 } 933 934 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 935 .get_modes = amdgpu_connector_vga_get_modes, 936 .mode_valid = amdgpu_connector_vga_mode_valid, 937 .best_encoder = amdgpu_connector_best_single_encoder, 938 }; 939 940 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 941 .dpms = drm_helper_connector_dpms, 942 .detect = amdgpu_connector_vga_detect, 943 .fill_modes = drm_helper_probe_single_connector_modes, 944 .early_unregister = amdgpu_connector_unregister, 945 .destroy = amdgpu_connector_destroy, 946 .set_property = amdgpu_connector_set_property, 947 }; 948 949 static bool 950 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 951 { 952 struct drm_device *dev = connector->dev; 953 struct amdgpu_device *adev = drm_to_adev(dev); 954 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 955 enum drm_connector_status status; 956 957 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 958 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 959 status = connector_status_connected; 960 else 961 status = connector_status_disconnected; 962 if (connector->status == status) 963 return true; 964 } 965 966 return false; 967 } 968 969 /* 970 * DVI is complicated 971 * Do a DDC probe, if DDC probe passes, get the full EDID so 972 * we can do analog/digital monitor detection at this point. 973 * If the monitor is an analog monitor or we got no DDC, 974 * we need to find the DAC encoder object for this connector. 975 * If we got no DDC, we do load detection on the DAC encoder object. 976 * If we got analog DDC or load detection passes on the DAC encoder 977 * we have to check if this analog encoder is shared with anyone else (TV) 978 * if its shared we have to set the other connector to disconnected. 979 */ 980 static enum drm_connector_status 981 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 982 { 983 struct drm_device *dev = connector->dev; 984 struct amdgpu_device *adev = drm_to_adev(dev); 985 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 986 const struct drm_encoder_helper_funcs *encoder_funcs; 987 int r; 988 enum drm_connector_status ret = connector_status_disconnected; 989 bool dret = false, broken_edid = false; 990 991 if (!drm_kms_helper_is_poll_worker()) { 992 r = pm_runtime_get_sync(connector->dev->dev); 993 if (r < 0) { 994 pm_runtime_put_autosuspend(connector->dev->dev); 995 return connector_status_disconnected; 996 } 997 } 998 999 if (amdgpu_connector->detected_hpd_without_ddc) { 1000 force = true; 1001 amdgpu_connector->detected_hpd_without_ddc = false; 1002 } 1003 1004 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1005 ret = connector->status; 1006 goto exit; 1007 } 1008 1009 if (amdgpu_connector->ddc_bus) { 1010 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1011 1012 /* Sometimes the pins required for the DDC probe on DVI 1013 * connectors don't make contact at the same time that the ones 1014 * for HPD do. If the DDC probe fails even though we had an HPD 1015 * signal, try again later 1016 */ 1017 if (!dret && !force && 1018 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1019 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1020 amdgpu_connector->detected_hpd_without_ddc = true; 1021 schedule_delayed_work(&adev->hotplug_work, 1022 msecs_to_jiffies(1000)); 1023 goto exit; 1024 } 1025 } 1026 if (dret) { 1027 amdgpu_connector->detected_by_load = false; 1028 amdgpu_connector_free_edid(connector); 1029 amdgpu_connector_get_edid(connector); 1030 1031 if (!amdgpu_connector->edid) { 1032 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1033 connector->name); 1034 ret = connector_status_connected; 1035 broken_edid = true; /* defer use_digital to later */ 1036 } else { 1037 amdgpu_connector->use_digital = 1038 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1039 1040 /* some oems have boards with separate digital and analog connectors 1041 * with a shared ddc line (often vga + hdmi) 1042 */ 1043 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1044 amdgpu_connector_free_edid(connector); 1045 ret = connector_status_disconnected; 1046 } else { 1047 ret = connector_status_connected; 1048 } 1049 1050 /* This gets complicated. We have boards with VGA + HDMI with a 1051 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1052 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1053 * you don't really know what's connected to which port as both are digital. 1054 */ 1055 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1056 struct drm_connector *list_connector; 1057 struct drm_connector_list_iter iter; 1058 struct amdgpu_connector *list_amdgpu_connector; 1059 1060 drm_connector_list_iter_begin(dev, &iter); 1061 drm_for_each_connector_iter(list_connector, 1062 &iter) { 1063 if (connector == list_connector) 1064 continue; 1065 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1066 if (list_amdgpu_connector->shared_ddc && 1067 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1068 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1069 /* cases where both connectors are digital */ 1070 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1071 /* hpd is our only option in this case */ 1072 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1073 amdgpu_connector_free_edid(connector); 1074 ret = connector_status_disconnected; 1075 } 1076 } 1077 } 1078 } 1079 drm_connector_list_iter_end(&iter); 1080 } 1081 } 1082 } 1083 1084 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1085 goto out; 1086 1087 /* DVI-D and HDMI-A are digital only */ 1088 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1089 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1090 goto out; 1091 1092 /* if we aren't forcing don't do destructive polling */ 1093 if (!force) { 1094 /* only return the previous status if we last 1095 * detected a monitor via load. 1096 */ 1097 if (amdgpu_connector->detected_by_load) 1098 ret = connector->status; 1099 goto out; 1100 } 1101 1102 /* find analog encoder */ 1103 if (amdgpu_connector->dac_load_detect) { 1104 struct drm_encoder *encoder; 1105 1106 drm_connector_for_each_possible_encoder(connector, encoder) { 1107 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1108 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1109 continue; 1110 1111 encoder_funcs = encoder->helper_private; 1112 if (encoder_funcs->detect) { 1113 if (!broken_edid) { 1114 if (ret != connector_status_connected) { 1115 /* deal with analog monitors without DDC */ 1116 ret = encoder_funcs->detect(encoder, connector); 1117 if (ret == connector_status_connected) { 1118 amdgpu_connector->use_digital = false; 1119 } 1120 if (ret != connector_status_disconnected) 1121 amdgpu_connector->detected_by_load = true; 1122 } 1123 } else { 1124 enum drm_connector_status lret; 1125 /* assume digital unless load detected otherwise */ 1126 amdgpu_connector->use_digital = true; 1127 lret = encoder_funcs->detect(encoder, connector); 1128 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1129 if (lret == connector_status_connected) 1130 amdgpu_connector->use_digital = false; 1131 } 1132 break; 1133 } 1134 } 1135 } 1136 1137 out: 1138 /* updated in get modes as well since we need to know if it's analog or digital */ 1139 amdgpu_connector_update_scratch_regs(connector, ret); 1140 1141 exit: 1142 if (!drm_kms_helper_is_poll_worker()) { 1143 pm_runtime_mark_last_busy(connector->dev->dev); 1144 pm_runtime_put_autosuspend(connector->dev->dev); 1145 } 1146 1147 return ret; 1148 } 1149 1150 /* okay need to be smart in here about which encoder to pick */ 1151 static struct drm_encoder * 1152 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1153 { 1154 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1155 struct drm_encoder *encoder; 1156 1157 drm_connector_for_each_possible_encoder(connector, encoder) { 1158 if (amdgpu_connector->use_digital == true) { 1159 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1160 return encoder; 1161 } else { 1162 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1163 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1164 return encoder; 1165 } 1166 } 1167 1168 /* see if we have a default encoder TODO */ 1169 1170 /* then check use digitial */ 1171 /* pick the first one */ 1172 drm_connector_for_each_possible_encoder(connector, encoder) 1173 return encoder; 1174 1175 return NULL; 1176 } 1177 1178 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1179 { 1180 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1181 if (connector->force == DRM_FORCE_ON) 1182 amdgpu_connector->use_digital = false; 1183 if (connector->force == DRM_FORCE_ON_DIGITAL) 1184 amdgpu_connector->use_digital = true; 1185 } 1186 1187 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1188 struct drm_display_mode *mode) 1189 { 1190 struct drm_device *dev = connector->dev; 1191 struct amdgpu_device *adev = drm_to_adev(dev); 1192 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1193 1194 /* XXX check mode bandwidth */ 1195 1196 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1197 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1198 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1199 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1200 return MODE_OK; 1201 } else if (connector->display_info.is_hdmi) { 1202 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1203 if (mode->clock > 340000) 1204 return MODE_CLOCK_HIGH; 1205 else 1206 return MODE_OK; 1207 } else { 1208 return MODE_CLOCK_HIGH; 1209 } 1210 } 1211 1212 /* check against the max pixel clock */ 1213 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1214 return MODE_CLOCK_HIGH; 1215 1216 return MODE_OK; 1217 } 1218 1219 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1220 .get_modes = amdgpu_connector_vga_get_modes, 1221 .mode_valid = amdgpu_connector_dvi_mode_valid, 1222 .best_encoder = amdgpu_connector_dvi_encoder, 1223 }; 1224 1225 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1226 .dpms = drm_helper_connector_dpms, 1227 .detect = amdgpu_connector_dvi_detect, 1228 .fill_modes = drm_helper_probe_single_connector_modes, 1229 .set_property = amdgpu_connector_set_property, 1230 .early_unregister = amdgpu_connector_unregister, 1231 .destroy = amdgpu_connector_destroy, 1232 .force = amdgpu_connector_dvi_force, 1233 }; 1234 1235 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1236 { 1237 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1238 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1239 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1240 int ret; 1241 1242 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1243 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1244 struct drm_display_mode *mode; 1245 1246 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1247 if (!amdgpu_dig_connector->edp_on) 1248 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1249 ATOM_TRANSMITTER_ACTION_POWER_ON); 1250 amdgpu_connector_get_edid(connector); 1251 ret = amdgpu_connector_ddc_get_modes(connector); 1252 if (!amdgpu_dig_connector->edp_on) 1253 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1254 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1255 } else { 1256 /* need to setup ddc on the bridge */ 1257 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1258 ENCODER_OBJECT_ID_NONE) { 1259 if (encoder) 1260 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1261 } 1262 amdgpu_connector_get_edid(connector); 1263 ret = amdgpu_connector_ddc_get_modes(connector); 1264 } 1265 1266 if (ret > 0) { 1267 if (encoder) { 1268 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1269 /* add scaled modes */ 1270 amdgpu_connector_add_common_modes(encoder, connector); 1271 } 1272 return ret; 1273 } 1274 1275 if (!encoder) 1276 return 0; 1277 1278 /* we have no EDID modes */ 1279 mode = amdgpu_connector_lcd_native_mode(encoder); 1280 if (mode) { 1281 ret = 1; 1282 drm_mode_probed_add(connector, mode); 1283 /* add the width/height from vbios tables if available */ 1284 connector->display_info.width_mm = mode->width_mm; 1285 connector->display_info.height_mm = mode->height_mm; 1286 /* add scaled modes */ 1287 amdgpu_connector_add_common_modes(encoder, connector); 1288 } 1289 } else { 1290 /* need to setup ddc on the bridge */ 1291 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1292 ENCODER_OBJECT_ID_NONE) { 1293 if (encoder) 1294 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1295 } 1296 amdgpu_connector_get_edid(connector); 1297 ret = amdgpu_connector_ddc_get_modes(connector); 1298 1299 amdgpu_get_native_mode(connector); 1300 } 1301 1302 return ret; 1303 } 1304 1305 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1306 { 1307 struct drm_encoder *encoder; 1308 struct amdgpu_encoder *amdgpu_encoder; 1309 1310 drm_connector_for_each_possible_encoder(connector, encoder) { 1311 amdgpu_encoder = to_amdgpu_encoder(encoder); 1312 1313 switch (amdgpu_encoder->encoder_id) { 1314 case ENCODER_OBJECT_ID_TRAVIS: 1315 case ENCODER_OBJECT_ID_NUTMEG: 1316 return amdgpu_encoder->encoder_id; 1317 default: 1318 break; 1319 } 1320 } 1321 1322 return ENCODER_OBJECT_ID_NONE; 1323 } 1324 1325 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1326 { 1327 struct drm_encoder *encoder; 1328 struct amdgpu_encoder *amdgpu_encoder; 1329 bool found = false; 1330 1331 drm_connector_for_each_possible_encoder(connector, encoder) { 1332 amdgpu_encoder = to_amdgpu_encoder(encoder); 1333 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1334 found = true; 1335 } 1336 1337 return found; 1338 } 1339 1340 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1341 { 1342 struct drm_device *dev = connector->dev; 1343 struct amdgpu_device *adev = drm_to_adev(dev); 1344 1345 if ((adev->clock.default_dispclk >= 53900) && 1346 amdgpu_connector_encoder_is_hbr2(connector)) { 1347 return true; 1348 } 1349 1350 return false; 1351 } 1352 1353 static enum drm_connector_status 1354 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1355 { 1356 struct drm_device *dev = connector->dev; 1357 struct amdgpu_device *adev = drm_to_adev(dev); 1358 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1359 enum drm_connector_status ret = connector_status_disconnected; 1360 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1361 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1362 int r; 1363 1364 if (!drm_kms_helper_is_poll_worker()) { 1365 r = pm_runtime_get_sync(connector->dev->dev); 1366 if (r < 0) { 1367 pm_runtime_put_autosuspend(connector->dev->dev); 1368 return connector_status_disconnected; 1369 } 1370 } 1371 1372 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1373 ret = connector->status; 1374 goto out; 1375 } 1376 1377 amdgpu_connector_free_edid(connector); 1378 1379 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1380 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1381 if (encoder) { 1382 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1383 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1384 1385 /* check if panel is valid */ 1386 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1387 ret = connector_status_connected; 1388 } 1389 /* eDP is always DP */ 1390 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1391 if (!amdgpu_dig_connector->edp_on) 1392 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1393 ATOM_TRANSMITTER_ACTION_POWER_ON); 1394 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1395 ret = connector_status_connected; 1396 if (!amdgpu_dig_connector->edp_on) 1397 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1398 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1399 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1400 ENCODER_OBJECT_ID_NONE) { 1401 /* DP bridges are always DP */ 1402 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1403 /* get the DPCD from the bridge */ 1404 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1405 1406 if (encoder) { 1407 /* setup ddc on the bridge */ 1408 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1409 /* bridge chips are always aux */ 1410 /* try DDC */ 1411 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1412 ret = connector_status_connected; 1413 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1414 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1415 ret = encoder_funcs->detect(encoder, connector); 1416 } 1417 } 1418 } else { 1419 amdgpu_dig_connector->dp_sink_type = 1420 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1421 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1422 ret = connector_status_connected; 1423 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1424 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1425 } else { 1426 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1427 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1428 ret = connector_status_connected; 1429 } else { 1430 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1431 if (amdgpu_display_ddc_probe(amdgpu_connector, 1432 false)) 1433 ret = connector_status_connected; 1434 } 1435 } 1436 } 1437 1438 amdgpu_connector_update_scratch_regs(connector, ret); 1439 out: 1440 if (!drm_kms_helper_is_poll_worker()) { 1441 pm_runtime_mark_last_busy(connector->dev->dev); 1442 pm_runtime_put_autosuspend(connector->dev->dev); 1443 } 1444 1445 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1446 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1447 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1448 ret, 1449 amdgpu_dig_connector->dpcd, 1450 amdgpu_dig_connector->downstream_ports); 1451 return ret; 1452 } 1453 1454 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1455 struct drm_display_mode *mode) 1456 { 1457 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1458 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1459 1460 /* XXX check mode bandwidth */ 1461 1462 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1463 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1464 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1465 1466 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1467 return MODE_PANEL; 1468 1469 if (encoder) { 1470 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1471 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1472 1473 /* AVIVO hardware supports downscaling modes larger than the panel 1474 * to the panel size, but I'm not sure this is desirable. 1475 */ 1476 if ((mode->hdisplay > native_mode->hdisplay) || 1477 (mode->vdisplay > native_mode->vdisplay)) 1478 return MODE_PANEL; 1479 1480 /* if scaling is disabled, block non-native modes */ 1481 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1482 if ((mode->hdisplay != native_mode->hdisplay) || 1483 (mode->vdisplay != native_mode->vdisplay)) 1484 return MODE_PANEL; 1485 } 1486 } 1487 return MODE_OK; 1488 } else { 1489 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1490 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1491 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1492 } else { 1493 if (connector->display_info.is_hdmi) { 1494 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1495 if (mode->clock > 340000) 1496 return MODE_CLOCK_HIGH; 1497 } else { 1498 if (mode->clock > 165000) 1499 return MODE_CLOCK_HIGH; 1500 } 1501 } 1502 } 1503 1504 return MODE_OK; 1505 } 1506 1507 static int 1508 amdgpu_connector_late_register(struct drm_connector *connector) 1509 { 1510 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1511 int r = 0; 1512 1513 if (amdgpu_connector->ddc_bus->has_aux) { 1514 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1515 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1516 } 1517 1518 return r; 1519 } 1520 1521 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1522 .get_modes = amdgpu_connector_dp_get_modes, 1523 .mode_valid = amdgpu_connector_dp_mode_valid, 1524 .best_encoder = amdgpu_connector_dvi_encoder, 1525 }; 1526 1527 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1528 .dpms = drm_helper_connector_dpms, 1529 .detect = amdgpu_connector_dp_detect, 1530 .fill_modes = drm_helper_probe_single_connector_modes, 1531 .set_property = amdgpu_connector_set_property, 1532 .early_unregister = amdgpu_connector_unregister, 1533 .destroy = amdgpu_connector_destroy, 1534 .force = amdgpu_connector_dvi_force, 1535 .late_register = amdgpu_connector_late_register, 1536 }; 1537 1538 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1539 .dpms = drm_helper_connector_dpms, 1540 .detect = amdgpu_connector_dp_detect, 1541 .fill_modes = drm_helper_probe_single_connector_modes, 1542 .set_property = amdgpu_connector_set_lcd_property, 1543 .early_unregister = amdgpu_connector_unregister, 1544 .destroy = amdgpu_connector_destroy, 1545 .force = amdgpu_connector_dvi_force, 1546 .late_register = amdgpu_connector_late_register, 1547 }; 1548 1549 void 1550 amdgpu_connector_add(struct amdgpu_device *adev, 1551 uint32_t connector_id, 1552 uint32_t supported_device, 1553 int connector_type, 1554 struct amdgpu_i2c_bus_rec *i2c_bus, 1555 uint16_t connector_object_id, 1556 struct amdgpu_hpd *hpd, 1557 struct amdgpu_router *router) 1558 { 1559 struct drm_device *dev = adev_to_drm(adev); 1560 struct drm_connector *connector; 1561 struct drm_connector_list_iter iter; 1562 struct amdgpu_connector *amdgpu_connector; 1563 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1564 struct drm_encoder *encoder; 1565 struct amdgpu_encoder *amdgpu_encoder; 1566 struct i2c_adapter *ddc = NULL; 1567 uint32_t subpixel_order = SubPixelNone; 1568 bool shared_ddc = false; 1569 bool is_dp_bridge = false; 1570 bool has_aux = false; 1571 1572 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1573 return; 1574 1575 /* see if we already added it */ 1576 drm_connector_list_iter_begin(dev, &iter); 1577 drm_for_each_connector_iter(connector, &iter) { 1578 amdgpu_connector = to_amdgpu_connector(connector); 1579 if (amdgpu_connector->connector_id == connector_id) { 1580 amdgpu_connector->devices |= supported_device; 1581 drm_connector_list_iter_end(&iter); 1582 return; 1583 } 1584 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1585 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1586 amdgpu_connector->shared_ddc = true; 1587 shared_ddc = true; 1588 } 1589 if (amdgpu_connector->router_bus && router->ddc_valid && 1590 (amdgpu_connector->router.router_id == router->router_id)) { 1591 amdgpu_connector->shared_ddc = false; 1592 shared_ddc = false; 1593 } 1594 } 1595 } 1596 drm_connector_list_iter_end(&iter); 1597 1598 /* check if it's a dp bridge */ 1599 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1600 amdgpu_encoder = to_amdgpu_encoder(encoder); 1601 if (amdgpu_encoder->devices & supported_device) { 1602 switch (amdgpu_encoder->encoder_id) { 1603 case ENCODER_OBJECT_ID_TRAVIS: 1604 case ENCODER_OBJECT_ID_NUTMEG: 1605 is_dp_bridge = true; 1606 break; 1607 default: 1608 break; 1609 } 1610 } 1611 } 1612 1613 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1614 if (!amdgpu_connector) 1615 return; 1616 1617 connector = &amdgpu_connector->base; 1618 1619 amdgpu_connector->connector_id = connector_id; 1620 amdgpu_connector->devices = supported_device; 1621 amdgpu_connector->shared_ddc = shared_ddc; 1622 amdgpu_connector->connector_object_id = connector_object_id; 1623 amdgpu_connector->hpd = *hpd; 1624 1625 amdgpu_connector->router = *router; 1626 if (router->ddc_valid || router->cd_valid) { 1627 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1628 if (!amdgpu_connector->router_bus) 1629 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1630 } 1631 1632 if (is_dp_bridge) { 1633 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1634 if (!amdgpu_dig_connector) 1635 goto failed; 1636 amdgpu_connector->con_priv = amdgpu_dig_connector; 1637 if (i2c_bus->valid) { 1638 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1639 if (amdgpu_connector->ddc_bus) { 1640 has_aux = true; 1641 ddc = &amdgpu_connector->ddc_bus->adapter; 1642 } else { 1643 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1644 } 1645 } 1646 switch (connector_type) { 1647 case DRM_MODE_CONNECTOR_VGA: 1648 case DRM_MODE_CONNECTOR_DVIA: 1649 default: 1650 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1651 &amdgpu_connector_dp_funcs, 1652 connector_type, 1653 ddc); 1654 drm_connector_helper_add(&amdgpu_connector->base, 1655 &amdgpu_connector_dp_helper_funcs); 1656 connector->interlace_allowed = true; 1657 connector->doublescan_allowed = true; 1658 amdgpu_connector->dac_load_detect = true; 1659 drm_object_attach_property(&amdgpu_connector->base.base, 1660 adev->mode_info.load_detect_property, 1661 1); 1662 drm_object_attach_property(&amdgpu_connector->base.base, 1663 dev->mode_config.scaling_mode_property, 1664 DRM_MODE_SCALE_NONE); 1665 break; 1666 case DRM_MODE_CONNECTOR_DVII: 1667 case DRM_MODE_CONNECTOR_DVID: 1668 case DRM_MODE_CONNECTOR_HDMIA: 1669 case DRM_MODE_CONNECTOR_HDMIB: 1670 case DRM_MODE_CONNECTOR_DisplayPort: 1671 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1672 &amdgpu_connector_dp_funcs, 1673 connector_type, 1674 ddc); 1675 drm_connector_helper_add(&amdgpu_connector->base, 1676 &amdgpu_connector_dp_helper_funcs); 1677 drm_object_attach_property(&amdgpu_connector->base.base, 1678 adev->mode_info.underscan_property, 1679 UNDERSCAN_OFF); 1680 drm_object_attach_property(&amdgpu_connector->base.base, 1681 adev->mode_info.underscan_hborder_property, 1682 0); 1683 drm_object_attach_property(&amdgpu_connector->base.base, 1684 adev->mode_info.underscan_vborder_property, 1685 0); 1686 1687 drm_object_attach_property(&amdgpu_connector->base.base, 1688 dev->mode_config.scaling_mode_property, 1689 DRM_MODE_SCALE_NONE); 1690 1691 drm_object_attach_property(&amdgpu_connector->base.base, 1692 adev->mode_info.dither_property, 1693 AMDGPU_FMT_DITHER_DISABLE); 1694 1695 if (amdgpu_audio != 0) { 1696 drm_object_attach_property(&amdgpu_connector->base.base, 1697 adev->mode_info.audio_property, 1698 AMDGPU_AUDIO_AUTO); 1699 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1700 } 1701 1702 subpixel_order = SubPixelHorizontalRGB; 1703 connector->interlace_allowed = true; 1704 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1705 connector->doublescan_allowed = true; 1706 else 1707 connector->doublescan_allowed = false; 1708 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1709 amdgpu_connector->dac_load_detect = true; 1710 drm_object_attach_property(&amdgpu_connector->base.base, 1711 adev->mode_info.load_detect_property, 1712 1); 1713 } 1714 break; 1715 case DRM_MODE_CONNECTOR_LVDS: 1716 case DRM_MODE_CONNECTOR_eDP: 1717 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1718 &amdgpu_connector_edp_funcs, 1719 connector_type, 1720 ddc); 1721 drm_connector_helper_add(&amdgpu_connector->base, 1722 &amdgpu_connector_dp_helper_funcs); 1723 drm_object_attach_property(&amdgpu_connector->base.base, 1724 dev->mode_config.scaling_mode_property, 1725 DRM_MODE_SCALE_FULLSCREEN); 1726 subpixel_order = SubPixelHorizontalRGB; 1727 connector->interlace_allowed = false; 1728 connector->doublescan_allowed = false; 1729 break; 1730 } 1731 } else { 1732 switch (connector_type) { 1733 case DRM_MODE_CONNECTOR_VGA: 1734 if (i2c_bus->valid) { 1735 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1736 if (!amdgpu_connector->ddc_bus) 1737 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1738 else 1739 ddc = &amdgpu_connector->ddc_bus->adapter; 1740 } 1741 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1742 &amdgpu_connector_vga_funcs, 1743 connector_type, 1744 ddc); 1745 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1746 amdgpu_connector->dac_load_detect = true; 1747 drm_object_attach_property(&amdgpu_connector->base.base, 1748 adev->mode_info.load_detect_property, 1749 1); 1750 drm_object_attach_property(&amdgpu_connector->base.base, 1751 dev->mode_config.scaling_mode_property, 1752 DRM_MODE_SCALE_NONE); 1753 /* no HPD on analog connectors */ 1754 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1755 connector->interlace_allowed = true; 1756 connector->doublescan_allowed = true; 1757 break; 1758 case DRM_MODE_CONNECTOR_DVIA: 1759 if (i2c_bus->valid) { 1760 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1761 if (!amdgpu_connector->ddc_bus) 1762 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1763 else 1764 ddc = &amdgpu_connector->ddc_bus->adapter; 1765 } 1766 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1767 &amdgpu_connector_vga_funcs, 1768 connector_type, 1769 ddc); 1770 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1771 amdgpu_connector->dac_load_detect = true; 1772 drm_object_attach_property(&amdgpu_connector->base.base, 1773 adev->mode_info.load_detect_property, 1774 1); 1775 drm_object_attach_property(&amdgpu_connector->base.base, 1776 dev->mode_config.scaling_mode_property, 1777 DRM_MODE_SCALE_NONE); 1778 /* no HPD on analog connectors */ 1779 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1780 connector->interlace_allowed = true; 1781 connector->doublescan_allowed = true; 1782 break; 1783 case DRM_MODE_CONNECTOR_DVII: 1784 case DRM_MODE_CONNECTOR_DVID: 1785 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1786 if (!amdgpu_dig_connector) 1787 goto failed; 1788 amdgpu_connector->con_priv = amdgpu_dig_connector; 1789 if (i2c_bus->valid) { 1790 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1791 if (!amdgpu_connector->ddc_bus) 1792 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1793 else 1794 ddc = &amdgpu_connector->ddc_bus->adapter; 1795 } 1796 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1797 &amdgpu_connector_dvi_funcs, 1798 connector_type, 1799 ddc); 1800 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1801 subpixel_order = SubPixelHorizontalRGB; 1802 drm_object_attach_property(&amdgpu_connector->base.base, 1803 adev->mode_info.coherent_mode_property, 1804 1); 1805 drm_object_attach_property(&amdgpu_connector->base.base, 1806 adev->mode_info.underscan_property, 1807 UNDERSCAN_OFF); 1808 drm_object_attach_property(&amdgpu_connector->base.base, 1809 adev->mode_info.underscan_hborder_property, 1810 0); 1811 drm_object_attach_property(&amdgpu_connector->base.base, 1812 adev->mode_info.underscan_vborder_property, 1813 0); 1814 drm_object_attach_property(&amdgpu_connector->base.base, 1815 dev->mode_config.scaling_mode_property, 1816 DRM_MODE_SCALE_NONE); 1817 1818 if (amdgpu_audio != 0) { 1819 drm_object_attach_property(&amdgpu_connector->base.base, 1820 adev->mode_info.audio_property, 1821 AMDGPU_AUDIO_AUTO); 1822 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1823 } 1824 drm_object_attach_property(&amdgpu_connector->base.base, 1825 adev->mode_info.dither_property, 1826 AMDGPU_FMT_DITHER_DISABLE); 1827 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1828 amdgpu_connector->dac_load_detect = true; 1829 drm_object_attach_property(&amdgpu_connector->base.base, 1830 adev->mode_info.load_detect_property, 1831 1); 1832 } 1833 connector->interlace_allowed = true; 1834 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1835 connector->doublescan_allowed = true; 1836 else 1837 connector->doublescan_allowed = false; 1838 break; 1839 case DRM_MODE_CONNECTOR_HDMIA: 1840 case DRM_MODE_CONNECTOR_HDMIB: 1841 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1842 if (!amdgpu_dig_connector) 1843 goto failed; 1844 amdgpu_connector->con_priv = amdgpu_dig_connector; 1845 if (i2c_bus->valid) { 1846 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1847 if (!amdgpu_connector->ddc_bus) 1848 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1849 else 1850 ddc = &amdgpu_connector->ddc_bus->adapter; 1851 } 1852 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1853 &amdgpu_connector_dvi_funcs, 1854 connector_type, 1855 ddc); 1856 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1857 drm_object_attach_property(&amdgpu_connector->base.base, 1858 adev->mode_info.coherent_mode_property, 1859 1); 1860 drm_object_attach_property(&amdgpu_connector->base.base, 1861 adev->mode_info.underscan_property, 1862 UNDERSCAN_OFF); 1863 drm_object_attach_property(&amdgpu_connector->base.base, 1864 adev->mode_info.underscan_hborder_property, 1865 0); 1866 drm_object_attach_property(&amdgpu_connector->base.base, 1867 adev->mode_info.underscan_vborder_property, 1868 0); 1869 drm_object_attach_property(&amdgpu_connector->base.base, 1870 dev->mode_config.scaling_mode_property, 1871 DRM_MODE_SCALE_NONE); 1872 if (amdgpu_audio != 0) { 1873 drm_object_attach_property(&amdgpu_connector->base.base, 1874 adev->mode_info.audio_property, 1875 AMDGPU_AUDIO_AUTO); 1876 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1877 } 1878 drm_object_attach_property(&amdgpu_connector->base.base, 1879 adev->mode_info.dither_property, 1880 AMDGPU_FMT_DITHER_DISABLE); 1881 subpixel_order = SubPixelHorizontalRGB; 1882 connector->interlace_allowed = true; 1883 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1884 connector->doublescan_allowed = true; 1885 else 1886 connector->doublescan_allowed = false; 1887 break; 1888 case DRM_MODE_CONNECTOR_DisplayPort: 1889 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1890 if (!amdgpu_dig_connector) 1891 goto failed; 1892 amdgpu_connector->con_priv = amdgpu_dig_connector; 1893 if (i2c_bus->valid) { 1894 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1895 if (amdgpu_connector->ddc_bus) { 1896 has_aux = true; 1897 ddc = &amdgpu_connector->ddc_bus->adapter; 1898 } else { 1899 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1900 } 1901 } 1902 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1903 &amdgpu_connector_dp_funcs, 1904 connector_type, 1905 ddc); 1906 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1907 subpixel_order = SubPixelHorizontalRGB; 1908 drm_object_attach_property(&amdgpu_connector->base.base, 1909 adev->mode_info.coherent_mode_property, 1910 1); 1911 drm_object_attach_property(&amdgpu_connector->base.base, 1912 adev->mode_info.underscan_property, 1913 UNDERSCAN_OFF); 1914 drm_object_attach_property(&amdgpu_connector->base.base, 1915 adev->mode_info.underscan_hborder_property, 1916 0); 1917 drm_object_attach_property(&amdgpu_connector->base.base, 1918 adev->mode_info.underscan_vborder_property, 1919 0); 1920 drm_object_attach_property(&amdgpu_connector->base.base, 1921 dev->mode_config.scaling_mode_property, 1922 DRM_MODE_SCALE_NONE); 1923 if (amdgpu_audio != 0) { 1924 drm_object_attach_property(&amdgpu_connector->base.base, 1925 adev->mode_info.audio_property, 1926 AMDGPU_AUDIO_AUTO); 1927 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1928 } 1929 drm_object_attach_property(&amdgpu_connector->base.base, 1930 adev->mode_info.dither_property, 1931 AMDGPU_FMT_DITHER_DISABLE); 1932 connector->interlace_allowed = true; 1933 /* in theory with a DP to VGA converter... */ 1934 connector->doublescan_allowed = false; 1935 break; 1936 case DRM_MODE_CONNECTOR_eDP: 1937 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1938 if (!amdgpu_dig_connector) 1939 goto failed; 1940 amdgpu_connector->con_priv = amdgpu_dig_connector; 1941 if (i2c_bus->valid) { 1942 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1943 if (amdgpu_connector->ddc_bus) { 1944 has_aux = true; 1945 ddc = &amdgpu_connector->ddc_bus->adapter; 1946 } else { 1947 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1948 } 1949 } 1950 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1951 &amdgpu_connector_edp_funcs, 1952 connector_type, 1953 ddc); 1954 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1955 drm_object_attach_property(&amdgpu_connector->base.base, 1956 dev->mode_config.scaling_mode_property, 1957 DRM_MODE_SCALE_FULLSCREEN); 1958 subpixel_order = SubPixelHorizontalRGB; 1959 connector->interlace_allowed = false; 1960 connector->doublescan_allowed = false; 1961 break; 1962 case DRM_MODE_CONNECTOR_LVDS: 1963 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1964 if (!amdgpu_dig_connector) 1965 goto failed; 1966 amdgpu_connector->con_priv = amdgpu_dig_connector; 1967 if (i2c_bus->valid) { 1968 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1969 if (!amdgpu_connector->ddc_bus) 1970 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1971 else 1972 ddc = &amdgpu_connector->ddc_bus->adapter; 1973 } 1974 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1975 &amdgpu_connector_lvds_funcs, 1976 connector_type, 1977 ddc); 1978 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1979 drm_object_attach_property(&amdgpu_connector->base.base, 1980 dev->mode_config.scaling_mode_property, 1981 DRM_MODE_SCALE_FULLSCREEN); 1982 subpixel_order = SubPixelHorizontalRGB; 1983 connector->interlace_allowed = false; 1984 connector->doublescan_allowed = false; 1985 break; 1986 } 1987 } 1988 1989 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1990 if (i2c_bus->valid) { 1991 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1992 DRM_CONNECTOR_POLL_DISCONNECT; 1993 } 1994 } else 1995 connector->polled = DRM_CONNECTOR_POLL_HPD; 1996 1997 connector->display_info.subpixel_order = subpixel_order; 1998 1999 if (has_aux) 2000 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2001 2002 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2003 connector_type == DRM_MODE_CONNECTOR_eDP) { 2004 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2005 } 2006 2007 return; 2008 2009 failed: 2010 drm_connector_cleanup(connector); 2011 kfree(connector); 2012 } 2013