1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 75 /* Don't start link training before we have the DPCD */ 76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 77 return; 78 79 /* Turn the connector off and back on immediately, which 80 * will trigger link training 81 */ 82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 84 } 85 } 86 } 87 88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 89 { 90 struct drm_crtc *crtc = encoder->crtc; 91 92 if (crtc && crtc->enabled) { 93 drm_crtc_helper_set_mode(crtc, &crtc->mode, 94 crtc->x, crtc->y, crtc->primary->fb); 95 } 96 } 97 98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 99 { 100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 101 struct amdgpu_connector_atom_dig *dig_connector; 102 int bpc = 8; 103 unsigned mode_clock, max_tmds_clock; 104 105 switch (connector->connector_type) { 106 case DRM_MODE_CONNECTOR_DVII: 107 case DRM_MODE_CONNECTOR_HDMIB: 108 if (amdgpu_connector->use_digital) { 109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 110 if (connector->display_info.bpc) 111 bpc = connector->display_info.bpc; 112 } 113 } 114 break; 115 case DRM_MODE_CONNECTOR_DVID: 116 case DRM_MODE_CONNECTOR_HDMIA: 117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 118 if (connector->display_info.bpc) 119 bpc = connector->display_info.bpc; 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DisplayPort: 123 dig_connector = amdgpu_connector->con_priv; 124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 127 if (connector->display_info.bpc) 128 bpc = connector->display_info.bpc; 129 } 130 break; 131 case DRM_MODE_CONNECTOR_eDP: 132 case DRM_MODE_CONNECTOR_LVDS: 133 if (connector->display_info.bpc) 134 bpc = connector->display_info.bpc; 135 else { 136 const struct drm_connector_helper_funcs *connector_funcs = 137 connector->helper_private; 138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 141 142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 143 bpc = 6; 144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 145 bpc = 8; 146 } 147 break; 148 } 149 150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 151 /* 152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 154 * 12 bpc is always supported on hdmi deep color sinks, as this is 155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 156 */ 157 if (bpc > 12) { 158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 159 connector->name, bpc); 160 bpc = 12; 161 } 162 163 /* Any defined maximum tmds clock limit we must not exceed? */ 164 if (connector->display_info.max_tmds_clock > 0) { 165 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 166 mode_clock = amdgpu_connector->pixelclock_for_modeset; 167 168 /* Maximum allowable input clock in kHz */ 169 max_tmds_clock = connector->display_info.max_tmds_clock; 170 171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 172 connector->name, mode_clock, max_tmds_clock); 173 174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 177 (mode_clock * 5/4 <= max_tmds_clock)) 178 bpc = 10; 179 else 180 bpc = 8; 181 182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 183 connector->name, bpc); 184 } 185 186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 187 bpc = 8; 188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 189 connector->name, bpc); 190 } 191 } else if (bpc > 8) { 192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 194 connector->name); 195 bpc = 8; 196 } 197 } 198 199 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 201 connector->name); 202 bpc = 8; 203 } 204 205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 206 connector->name, connector->display_info.bpc, bpc); 207 208 return bpc; 209 } 210 211 static void 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 213 enum drm_connector_status status) 214 { 215 struct drm_encoder *best_encoder = NULL; 216 struct drm_encoder *encoder = NULL; 217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 218 bool connected; 219 int i; 220 221 best_encoder = connector_funcs->best_encoder(connector); 222 223 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 224 if (connector->encoder_ids[i] == 0) 225 break; 226 227 encoder = drm_encoder_find(connector->dev, NULL, 228 connector->encoder_ids[i]); 229 if (!encoder) 230 continue; 231 232 if ((encoder == best_encoder) && (status == connector_status_connected)) 233 connected = true; 234 else 235 connected = false; 236 237 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 238 239 } 240 } 241 242 static struct drm_encoder * 243 amdgpu_connector_find_encoder(struct drm_connector *connector, 244 int encoder_type) 245 { 246 struct drm_encoder *encoder; 247 int i; 248 249 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 250 if (connector->encoder_ids[i] == 0) 251 break; 252 encoder = drm_encoder_find(connector->dev, NULL, 253 connector->encoder_ids[i]); 254 if (!encoder) 255 continue; 256 257 if (encoder->encoder_type == encoder_type) 258 return encoder; 259 } 260 return NULL; 261 } 262 263 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 264 { 265 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 266 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 267 268 if (amdgpu_connector->edid) { 269 return amdgpu_connector->edid; 270 } else if (edid_blob) { 271 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 272 if (edid) 273 amdgpu_connector->edid = edid; 274 } 275 return amdgpu_connector->edid; 276 } 277 278 static struct edid * 279 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 280 { 281 struct edid *edid; 282 283 if (adev->mode_info.bios_hardcoded_edid) { 284 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 285 if (edid) { 286 memcpy((unsigned char *)edid, 287 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 288 adev->mode_info.bios_hardcoded_edid_size); 289 return edid; 290 } 291 } 292 return NULL; 293 } 294 295 static void amdgpu_connector_get_edid(struct drm_connector *connector) 296 { 297 struct drm_device *dev = connector->dev; 298 struct amdgpu_device *adev = dev->dev_private; 299 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 300 301 if (amdgpu_connector->edid) 302 return; 303 304 /* on hw with routers, select right port */ 305 if (amdgpu_connector->router.ddc_valid) 306 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 307 308 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 309 ENCODER_OBJECT_ID_NONE) && 310 amdgpu_connector->ddc_bus->has_aux) { 311 amdgpu_connector->edid = drm_get_edid(connector, 312 &amdgpu_connector->ddc_bus->aux.ddc); 313 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 314 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 315 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 316 317 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 318 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 319 amdgpu_connector->ddc_bus->has_aux) 320 amdgpu_connector->edid = drm_get_edid(connector, 321 &amdgpu_connector->ddc_bus->aux.ddc); 322 else if (amdgpu_connector->ddc_bus) 323 amdgpu_connector->edid = drm_get_edid(connector, 324 &amdgpu_connector->ddc_bus->adapter); 325 } else if (amdgpu_connector->ddc_bus) { 326 amdgpu_connector->edid = drm_get_edid(connector, 327 &amdgpu_connector->ddc_bus->adapter); 328 } 329 330 if (!amdgpu_connector->edid) { 331 /* some laptops provide a hardcoded edid in rom for LCDs */ 332 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 333 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 334 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 335 } 336 } 337 338 static void amdgpu_connector_free_edid(struct drm_connector *connector) 339 { 340 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 341 342 kfree(amdgpu_connector->edid); 343 amdgpu_connector->edid = NULL; 344 } 345 346 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 347 { 348 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 349 int ret; 350 351 if (amdgpu_connector->edid) { 352 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 353 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 354 return ret; 355 } 356 drm_mode_connector_update_edid_property(connector, NULL); 357 return 0; 358 } 359 360 static struct drm_encoder * 361 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 362 { 363 int enc_id = connector->encoder_ids[0]; 364 365 /* pick the encoder ids */ 366 if (enc_id) 367 return drm_encoder_find(connector->dev, NULL, enc_id); 368 return NULL; 369 } 370 371 static void amdgpu_get_native_mode(struct drm_connector *connector) 372 { 373 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 374 struct amdgpu_encoder *amdgpu_encoder; 375 376 if (encoder == NULL) 377 return; 378 379 amdgpu_encoder = to_amdgpu_encoder(encoder); 380 381 if (!list_empty(&connector->probed_modes)) { 382 struct drm_display_mode *preferred_mode = 383 list_first_entry(&connector->probed_modes, 384 struct drm_display_mode, head); 385 386 amdgpu_encoder->native_mode = *preferred_mode; 387 } else { 388 amdgpu_encoder->native_mode.clock = 0; 389 } 390 } 391 392 static struct drm_display_mode * 393 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 394 { 395 struct drm_device *dev = encoder->dev; 396 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 397 struct drm_display_mode *mode = NULL; 398 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 399 400 if (native_mode->hdisplay != 0 && 401 native_mode->vdisplay != 0 && 402 native_mode->clock != 0) { 403 mode = drm_mode_duplicate(dev, native_mode); 404 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 405 drm_mode_set_name(mode); 406 407 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 408 } else if (native_mode->hdisplay != 0 && 409 native_mode->vdisplay != 0) { 410 /* mac laptops without an edid */ 411 /* Note that this is not necessarily the exact panel mode, 412 * but an approximation based on the cvt formula. For these 413 * systems we should ideally read the mode info out of the 414 * registers or add a mode table, but this works and is much 415 * simpler. 416 */ 417 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 418 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 419 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 420 } 421 return mode; 422 } 423 424 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 425 struct drm_connector *connector) 426 { 427 struct drm_device *dev = encoder->dev; 428 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 429 struct drm_display_mode *mode = NULL; 430 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 431 int i; 432 static const struct mode_size { 433 int w; 434 int h; 435 } common_modes[17] = { 436 { 640, 480}, 437 { 720, 480}, 438 { 800, 600}, 439 { 848, 480}, 440 {1024, 768}, 441 {1152, 768}, 442 {1280, 720}, 443 {1280, 800}, 444 {1280, 854}, 445 {1280, 960}, 446 {1280, 1024}, 447 {1440, 900}, 448 {1400, 1050}, 449 {1680, 1050}, 450 {1600, 1200}, 451 {1920, 1080}, 452 {1920, 1200} 453 }; 454 455 for (i = 0; i < 17; i++) { 456 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 457 if (common_modes[i].w > 1024 || 458 common_modes[i].h > 768) 459 continue; 460 } 461 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 462 if (common_modes[i].w > native_mode->hdisplay || 463 common_modes[i].h > native_mode->vdisplay || 464 (common_modes[i].w == native_mode->hdisplay && 465 common_modes[i].h == native_mode->vdisplay)) 466 continue; 467 } 468 if (common_modes[i].w < 320 || common_modes[i].h < 200) 469 continue; 470 471 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 472 drm_mode_probed_add(connector, mode); 473 } 474 } 475 476 static int amdgpu_connector_set_property(struct drm_connector *connector, 477 struct drm_property *property, 478 uint64_t val) 479 { 480 struct drm_device *dev = connector->dev; 481 struct amdgpu_device *adev = dev->dev_private; 482 struct drm_encoder *encoder; 483 struct amdgpu_encoder *amdgpu_encoder; 484 485 if (property == adev->mode_info.coherent_mode_property) { 486 struct amdgpu_encoder_atom_dig *dig; 487 bool new_coherent_mode; 488 489 /* need to find digital encoder on connector */ 490 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 491 if (!encoder) 492 return 0; 493 494 amdgpu_encoder = to_amdgpu_encoder(encoder); 495 496 if (!amdgpu_encoder->enc_priv) 497 return 0; 498 499 dig = amdgpu_encoder->enc_priv; 500 new_coherent_mode = val ? true : false; 501 if (dig->coherent_mode != new_coherent_mode) { 502 dig->coherent_mode = new_coherent_mode; 503 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 504 } 505 } 506 507 if (property == adev->mode_info.audio_property) { 508 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 509 /* need to find digital encoder on connector */ 510 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 511 if (!encoder) 512 return 0; 513 514 amdgpu_encoder = to_amdgpu_encoder(encoder); 515 516 if (amdgpu_connector->audio != val) { 517 amdgpu_connector->audio = val; 518 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 519 } 520 } 521 522 if (property == adev->mode_info.dither_property) { 523 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 524 /* need to find digital encoder on connector */ 525 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 526 if (!encoder) 527 return 0; 528 529 amdgpu_encoder = to_amdgpu_encoder(encoder); 530 531 if (amdgpu_connector->dither != val) { 532 amdgpu_connector->dither = val; 533 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 534 } 535 } 536 537 if (property == adev->mode_info.underscan_property) { 538 /* need to find digital encoder on connector */ 539 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 540 if (!encoder) 541 return 0; 542 543 amdgpu_encoder = to_amdgpu_encoder(encoder); 544 545 if (amdgpu_encoder->underscan_type != val) { 546 amdgpu_encoder->underscan_type = val; 547 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 548 } 549 } 550 551 if (property == adev->mode_info.underscan_hborder_property) { 552 /* need to find digital encoder on connector */ 553 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 554 if (!encoder) 555 return 0; 556 557 amdgpu_encoder = to_amdgpu_encoder(encoder); 558 559 if (amdgpu_encoder->underscan_hborder != val) { 560 amdgpu_encoder->underscan_hborder = val; 561 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 562 } 563 } 564 565 if (property == adev->mode_info.underscan_vborder_property) { 566 /* need to find digital encoder on connector */ 567 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 568 if (!encoder) 569 return 0; 570 571 amdgpu_encoder = to_amdgpu_encoder(encoder); 572 573 if (amdgpu_encoder->underscan_vborder != val) { 574 amdgpu_encoder->underscan_vborder = val; 575 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 576 } 577 } 578 579 if (property == adev->mode_info.load_detect_property) { 580 struct amdgpu_connector *amdgpu_connector = 581 to_amdgpu_connector(connector); 582 583 if (val == 0) 584 amdgpu_connector->dac_load_detect = false; 585 else 586 amdgpu_connector->dac_load_detect = true; 587 } 588 589 if (property == dev->mode_config.scaling_mode_property) { 590 enum amdgpu_rmx_type rmx_type; 591 592 if (connector->encoder) { 593 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 594 } else { 595 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 596 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 597 } 598 599 switch (val) { 600 default: 601 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 602 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 603 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 604 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 605 } 606 if (amdgpu_encoder->rmx_type == rmx_type) 607 return 0; 608 609 if ((rmx_type != DRM_MODE_SCALE_NONE) && 610 (amdgpu_encoder->native_mode.clock == 0)) 611 return 0; 612 613 amdgpu_encoder->rmx_type = rmx_type; 614 615 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 616 } 617 618 return 0; 619 } 620 621 static void 622 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 623 struct drm_connector *connector) 624 { 625 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 626 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 627 struct drm_display_mode *t, *mode; 628 629 /* If the EDID preferred mode doesn't match the native mode, use it */ 630 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 631 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 632 if (mode->hdisplay != native_mode->hdisplay || 633 mode->vdisplay != native_mode->vdisplay) 634 memcpy(native_mode, mode, sizeof(*mode)); 635 } 636 } 637 638 /* Try to get native mode details from EDID if necessary */ 639 if (!native_mode->clock) { 640 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 641 if (mode->hdisplay == native_mode->hdisplay && 642 mode->vdisplay == native_mode->vdisplay) { 643 *native_mode = *mode; 644 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 645 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 646 break; 647 } 648 } 649 } 650 651 if (!native_mode->clock) { 652 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 653 amdgpu_encoder->rmx_type = RMX_OFF; 654 } 655 } 656 657 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 658 { 659 struct drm_encoder *encoder; 660 int ret = 0; 661 struct drm_display_mode *mode; 662 663 amdgpu_connector_get_edid(connector); 664 ret = amdgpu_connector_ddc_get_modes(connector); 665 if (ret > 0) { 666 encoder = amdgpu_connector_best_single_encoder(connector); 667 if (encoder) { 668 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 669 /* add scaled modes */ 670 amdgpu_connector_add_common_modes(encoder, connector); 671 } 672 return ret; 673 } 674 675 encoder = amdgpu_connector_best_single_encoder(connector); 676 if (!encoder) 677 return 0; 678 679 /* we have no EDID modes */ 680 mode = amdgpu_connector_lcd_native_mode(encoder); 681 if (mode) { 682 ret = 1; 683 drm_mode_probed_add(connector, mode); 684 /* add the width/height from vbios tables if available */ 685 connector->display_info.width_mm = mode->width_mm; 686 connector->display_info.height_mm = mode->height_mm; 687 /* add scaled modes */ 688 amdgpu_connector_add_common_modes(encoder, connector); 689 } 690 691 return ret; 692 } 693 694 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 695 struct drm_display_mode *mode) 696 { 697 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 698 699 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 700 return MODE_PANEL; 701 702 if (encoder) { 703 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 704 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 705 706 /* AVIVO hardware supports downscaling modes larger than the panel 707 * to the panel size, but I'm not sure this is desirable. 708 */ 709 if ((mode->hdisplay > native_mode->hdisplay) || 710 (mode->vdisplay > native_mode->vdisplay)) 711 return MODE_PANEL; 712 713 /* if scaling is disabled, block non-native modes */ 714 if (amdgpu_encoder->rmx_type == RMX_OFF) { 715 if ((mode->hdisplay != native_mode->hdisplay) || 716 (mode->vdisplay != native_mode->vdisplay)) 717 return MODE_PANEL; 718 } 719 } 720 721 return MODE_OK; 722 } 723 724 static enum drm_connector_status 725 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 726 { 727 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 728 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 729 enum drm_connector_status ret = connector_status_disconnected; 730 int r; 731 732 r = pm_runtime_get_sync(connector->dev->dev); 733 if (r < 0) 734 return connector_status_disconnected; 735 736 if (encoder) { 737 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 738 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 739 740 /* check if panel is valid */ 741 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 742 ret = connector_status_connected; 743 744 } 745 746 /* check for edid as well */ 747 amdgpu_connector_get_edid(connector); 748 if (amdgpu_connector->edid) 749 ret = connector_status_connected; 750 /* check acpi lid status ??? */ 751 752 amdgpu_connector_update_scratch_regs(connector, ret); 753 pm_runtime_mark_last_busy(connector->dev->dev); 754 pm_runtime_put_autosuspend(connector->dev->dev); 755 return ret; 756 } 757 758 static void amdgpu_connector_unregister(struct drm_connector *connector) 759 { 760 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 761 762 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 763 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 764 amdgpu_connector->ddc_bus->has_aux = false; 765 } 766 } 767 768 static void amdgpu_connector_destroy(struct drm_connector *connector) 769 { 770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 771 772 amdgpu_connector_free_edid(connector); 773 kfree(amdgpu_connector->con_priv); 774 drm_connector_unregister(connector); 775 drm_connector_cleanup(connector); 776 kfree(connector); 777 } 778 779 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 780 struct drm_property *property, 781 uint64_t value) 782 { 783 struct drm_device *dev = connector->dev; 784 struct amdgpu_encoder *amdgpu_encoder; 785 enum amdgpu_rmx_type rmx_type; 786 787 DRM_DEBUG_KMS("\n"); 788 if (property != dev->mode_config.scaling_mode_property) 789 return 0; 790 791 if (connector->encoder) 792 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 793 else { 794 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 795 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 796 } 797 798 switch (value) { 799 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 800 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 801 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 802 default: 803 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 804 } 805 if (amdgpu_encoder->rmx_type == rmx_type) 806 return 0; 807 808 amdgpu_encoder->rmx_type = rmx_type; 809 810 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 811 return 0; 812 } 813 814 815 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 816 .get_modes = amdgpu_connector_lvds_get_modes, 817 .mode_valid = amdgpu_connector_lvds_mode_valid, 818 .best_encoder = amdgpu_connector_best_single_encoder, 819 }; 820 821 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 822 .dpms = drm_helper_connector_dpms, 823 .detect = amdgpu_connector_lvds_detect, 824 .fill_modes = drm_helper_probe_single_connector_modes, 825 .early_unregister = amdgpu_connector_unregister, 826 .destroy = amdgpu_connector_destroy, 827 .set_property = amdgpu_connector_set_lcd_property, 828 }; 829 830 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 831 { 832 int ret; 833 834 amdgpu_connector_get_edid(connector); 835 ret = amdgpu_connector_ddc_get_modes(connector); 836 837 return ret; 838 } 839 840 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 841 struct drm_display_mode *mode) 842 { 843 struct drm_device *dev = connector->dev; 844 struct amdgpu_device *adev = dev->dev_private; 845 846 /* XXX check mode bandwidth */ 847 848 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 849 return MODE_CLOCK_HIGH; 850 851 return MODE_OK; 852 } 853 854 static enum drm_connector_status 855 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 856 { 857 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 858 struct drm_encoder *encoder; 859 const struct drm_encoder_helper_funcs *encoder_funcs; 860 bool dret = false; 861 enum drm_connector_status ret = connector_status_disconnected; 862 int r; 863 864 r = pm_runtime_get_sync(connector->dev->dev); 865 if (r < 0) 866 return connector_status_disconnected; 867 868 encoder = amdgpu_connector_best_single_encoder(connector); 869 if (!encoder) 870 ret = connector_status_disconnected; 871 872 if (amdgpu_connector->ddc_bus) 873 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 874 if (dret) { 875 amdgpu_connector->detected_by_load = false; 876 amdgpu_connector_free_edid(connector); 877 amdgpu_connector_get_edid(connector); 878 879 if (!amdgpu_connector->edid) { 880 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 881 connector->name); 882 ret = connector_status_connected; 883 } else { 884 amdgpu_connector->use_digital = 885 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 886 887 /* some oems have boards with separate digital and analog connectors 888 * with a shared ddc line (often vga + hdmi) 889 */ 890 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 891 amdgpu_connector_free_edid(connector); 892 ret = connector_status_disconnected; 893 } else { 894 ret = connector_status_connected; 895 } 896 } 897 } else { 898 899 /* if we aren't forcing don't do destructive polling */ 900 if (!force) { 901 /* only return the previous status if we last 902 * detected a monitor via load. 903 */ 904 if (amdgpu_connector->detected_by_load) 905 ret = connector->status; 906 goto out; 907 } 908 909 if (amdgpu_connector->dac_load_detect && encoder) { 910 encoder_funcs = encoder->helper_private; 911 ret = encoder_funcs->detect(encoder, connector); 912 if (ret != connector_status_disconnected) 913 amdgpu_connector->detected_by_load = true; 914 } 915 } 916 917 amdgpu_connector_update_scratch_regs(connector, ret); 918 919 out: 920 pm_runtime_mark_last_busy(connector->dev->dev); 921 pm_runtime_put_autosuspend(connector->dev->dev); 922 923 return ret; 924 } 925 926 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 927 .get_modes = amdgpu_connector_vga_get_modes, 928 .mode_valid = amdgpu_connector_vga_mode_valid, 929 .best_encoder = amdgpu_connector_best_single_encoder, 930 }; 931 932 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 933 .dpms = drm_helper_connector_dpms, 934 .detect = amdgpu_connector_vga_detect, 935 .fill_modes = drm_helper_probe_single_connector_modes, 936 .early_unregister = amdgpu_connector_unregister, 937 .destroy = amdgpu_connector_destroy, 938 .set_property = amdgpu_connector_set_property, 939 }; 940 941 static bool 942 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 943 { 944 struct drm_device *dev = connector->dev; 945 struct amdgpu_device *adev = dev->dev_private; 946 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 947 enum drm_connector_status status; 948 949 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 950 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 951 status = connector_status_connected; 952 else 953 status = connector_status_disconnected; 954 if (connector->status == status) 955 return true; 956 } 957 958 return false; 959 } 960 961 /* 962 * DVI is complicated 963 * Do a DDC probe, if DDC probe passes, get the full EDID so 964 * we can do analog/digital monitor detection at this point. 965 * If the monitor is an analog monitor or we got no DDC, 966 * we need to find the DAC encoder object for this connector. 967 * If we got no DDC, we do load detection on the DAC encoder object. 968 * If we got analog DDC or load detection passes on the DAC encoder 969 * we have to check if this analog encoder is shared with anyone else (TV) 970 * if its shared we have to set the other connector to disconnected. 971 */ 972 static enum drm_connector_status 973 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 974 { 975 struct drm_device *dev = connector->dev; 976 struct amdgpu_device *adev = dev->dev_private; 977 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 978 struct drm_encoder *encoder = NULL; 979 const struct drm_encoder_helper_funcs *encoder_funcs; 980 int i, r; 981 enum drm_connector_status ret = connector_status_disconnected; 982 bool dret = false, broken_edid = false; 983 984 r = pm_runtime_get_sync(connector->dev->dev); 985 if (r < 0) 986 return connector_status_disconnected; 987 988 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 989 ret = connector->status; 990 goto exit; 991 } 992 993 if (amdgpu_connector->ddc_bus) 994 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 995 if (dret) { 996 amdgpu_connector->detected_by_load = false; 997 amdgpu_connector_free_edid(connector); 998 amdgpu_connector_get_edid(connector); 999 1000 if (!amdgpu_connector->edid) { 1001 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1002 connector->name); 1003 ret = connector_status_connected; 1004 broken_edid = true; /* defer use_digital to later */ 1005 } else { 1006 amdgpu_connector->use_digital = 1007 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1008 1009 /* some oems have boards with separate digital and analog connectors 1010 * with a shared ddc line (often vga + hdmi) 1011 */ 1012 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1013 amdgpu_connector_free_edid(connector); 1014 ret = connector_status_disconnected; 1015 } else { 1016 ret = connector_status_connected; 1017 } 1018 1019 /* This gets complicated. We have boards with VGA + HDMI with a 1020 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1021 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1022 * you don't really know what's connected to which port as both are digital. 1023 */ 1024 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1025 struct drm_connector *list_connector; 1026 struct amdgpu_connector *list_amdgpu_connector; 1027 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1028 if (connector == list_connector) 1029 continue; 1030 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1031 if (list_amdgpu_connector->shared_ddc && 1032 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1033 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1034 /* cases where both connectors are digital */ 1035 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1036 /* hpd is our only option in this case */ 1037 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1038 amdgpu_connector_free_edid(connector); 1039 ret = connector_status_disconnected; 1040 } 1041 } 1042 } 1043 } 1044 } 1045 } 1046 } 1047 1048 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1049 goto out; 1050 1051 /* DVI-D and HDMI-A are digital only */ 1052 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1053 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1054 goto out; 1055 1056 /* if we aren't forcing don't do destructive polling */ 1057 if (!force) { 1058 /* only return the previous status if we last 1059 * detected a monitor via load. 1060 */ 1061 if (amdgpu_connector->detected_by_load) 1062 ret = connector->status; 1063 goto out; 1064 } 1065 1066 /* find analog encoder */ 1067 if (amdgpu_connector->dac_load_detect) { 1068 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1069 if (connector->encoder_ids[i] == 0) 1070 break; 1071 1072 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]); 1073 if (!encoder) 1074 continue; 1075 1076 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1077 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1078 continue; 1079 1080 encoder_funcs = encoder->helper_private; 1081 if (encoder_funcs->detect) { 1082 if (!broken_edid) { 1083 if (ret != connector_status_connected) { 1084 /* deal with analog monitors without DDC */ 1085 ret = encoder_funcs->detect(encoder, connector); 1086 if (ret == connector_status_connected) { 1087 amdgpu_connector->use_digital = false; 1088 } 1089 if (ret != connector_status_disconnected) 1090 amdgpu_connector->detected_by_load = true; 1091 } 1092 } else { 1093 enum drm_connector_status lret; 1094 /* assume digital unless load detected otherwise */ 1095 amdgpu_connector->use_digital = true; 1096 lret = encoder_funcs->detect(encoder, connector); 1097 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1098 if (lret == connector_status_connected) 1099 amdgpu_connector->use_digital = false; 1100 } 1101 break; 1102 } 1103 } 1104 } 1105 1106 out: 1107 /* updated in get modes as well since we need to know if it's analog or digital */ 1108 amdgpu_connector_update_scratch_regs(connector, ret); 1109 1110 exit: 1111 pm_runtime_mark_last_busy(connector->dev->dev); 1112 pm_runtime_put_autosuspend(connector->dev->dev); 1113 1114 return ret; 1115 } 1116 1117 /* okay need to be smart in here about which encoder to pick */ 1118 static struct drm_encoder * 1119 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1120 { 1121 int enc_id = connector->encoder_ids[0]; 1122 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1123 struct drm_encoder *encoder; 1124 int i; 1125 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1126 if (connector->encoder_ids[i] == 0) 1127 break; 1128 1129 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]); 1130 if (!encoder) 1131 continue; 1132 1133 if (amdgpu_connector->use_digital == true) { 1134 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1135 return encoder; 1136 } else { 1137 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1138 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1139 return encoder; 1140 } 1141 } 1142 1143 /* see if we have a default encoder TODO */ 1144 1145 /* then check use digitial */ 1146 /* pick the first one */ 1147 if (enc_id) 1148 return drm_encoder_find(connector->dev, NULL, enc_id); 1149 return NULL; 1150 } 1151 1152 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1153 { 1154 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1155 if (connector->force == DRM_FORCE_ON) 1156 amdgpu_connector->use_digital = false; 1157 if (connector->force == DRM_FORCE_ON_DIGITAL) 1158 amdgpu_connector->use_digital = true; 1159 } 1160 1161 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1162 struct drm_display_mode *mode) 1163 { 1164 struct drm_device *dev = connector->dev; 1165 struct amdgpu_device *adev = dev->dev_private; 1166 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1167 1168 /* XXX check mode bandwidth */ 1169 1170 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1171 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1172 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1173 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1174 return MODE_OK; 1175 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1176 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1177 if (mode->clock > 340000) 1178 return MODE_CLOCK_HIGH; 1179 else 1180 return MODE_OK; 1181 } else { 1182 return MODE_CLOCK_HIGH; 1183 } 1184 } 1185 1186 /* check against the max pixel clock */ 1187 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1188 return MODE_CLOCK_HIGH; 1189 1190 return MODE_OK; 1191 } 1192 1193 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1194 .get_modes = amdgpu_connector_vga_get_modes, 1195 .mode_valid = amdgpu_connector_dvi_mode_valid, 1196 .best_encoder = amdgpu_connector_dvi_encoder, 1197 }; 1198 1199 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1200 .dpms = drm_helper_connector_dpms, 1201 .detect = amdgpu_connector_dvi_detect, 1202 .fill_modes = drm_helper_probe_single_connector_modes, 1203 .set_property = amdgpu_connector_set_property, 1204 .early_unregister = amdgpu_connector_unregister, 1205 .destroy = amdgpu_connector_destroy, 1206 .force = amdgpu_connector_dvi_force, 1207 }; 1208 1209 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1210 { 1211 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1212 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1213 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1214 int ret; 1215 1216 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1217 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1218 struct drm_display_mode *mode; 1219 1220 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1221 if (!amdgpu_dig_connector->edp_on) 1222 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1223 ATOM_TRANSMITTER_ACTION_POWER_ON); 1224 amdgpu_connector_get_edid(connector); 1225 ret = amdgpu_connector_ddc_get_modes(connector); 1226 if (!amdgpu_dig_connector->edp_on) 1227 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1228 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1229 } else { 1230 /* need to setup ddc on the bridge */ 1231 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1232 ENCODER_OBJECT_ID_NONE) { 1233 if (encoder) 1234 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1235 } 1236 amdgpu_connector_get_edid(connector); 1237 ret = amdgpu_connector_ddc_get_modes(connector); 1238 } 1239 1240 if (ret > 0) { 1241 if (encoder) { 1242 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1243 /* add scaled modes */ 1244 amdgpu_connector_add_common_modes(encoder, connector); 1245 } 1246 return ret; 1247 } 1248 1249 if (!encoder) 1250 return 0; 1251 1252 /* we have no EDID modes */ 1253 mode = amdgpu_connector_lcd_native_mode(encoder); 1254 if (mode) { 1255 ret = 1; 1256 drm_mode_probed_add(connector, mode); 1257 /* add the width/height from vbios tables if available */ 1258 connector->display_info.width_mm = mode->width_mm; 1259 connector->display_info.height_mm = mode->height_mm; 1260 /* add scaled modes */ 1261 amdgpu_connector_add_common_modes(encoder, connector); 1262 } 1263 } else { 1264 /* need to setup ddc on the bridge */ 1265 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1266 ENCODER_OBJECT_ID_NONE) { 1267 if (encoder) 1268 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1269 } 1270 amdgpu_connector_get_edid(connector); 1271 ret = amdgpu_connector_ddc_get_modes(connector); 1272 1273 amdgpu_get_native_mode(connector); 1274 } 1275 1276 return ret; 1277 } 1278 1279 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1280 { 1281 struct drm_encoder *encoder; 1282 struct amdgpu_encoder *amdgpu_encoder; 1283 int i; 1284 1285 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1286 if (connector->encoder_ids[i] == 0) 1287 break; 1288 1289 encoder = drm_encoder_find(connector->dev, NULL, 1290 connector->encoder_ids[i]); 1291 if (!encoder) 1292 continue; 1293 1294 amdgpu_encoder = to_amdgpu_encoder(encoder); 1295 1296 switch (amdgpu_encoder->encoder_id) { 1297 case ENCODER_OBJECT_ID_TRAVIS: 1298 case ENCODER_OBJECT_ID_NUTMEG: 1299 return amdgpu_encoder->encoder_id; 1300 default: 1301 break; 1302 } 1303 } 1304 1305 return ENCODER_OBJECT_ID_NONE; 1306 } 1307 1308 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1309 { 1310 struct drm_encoder *encoder; 1311 struct amdgpu_encoder *amdgpu_encoder; 1312 int i; 1313 bool found = false; 1314 1315 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1316 if (connector->encoder_ids[i] == 0) 1317 break; 1318 encoder = drm_encoder_find(connector->dev, NULL, 1319 connector->encoder_ids[i]); 1320 if (!encoder) 1321 continue; 1322 1323 amdgpu_encoder = to_amdgpu_encoder(encoder); 1324 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1325 found = true; 1326 } 1327 1328 return found; 1329 } 1330 1331 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1332 { 1333 struct drm_device *dev = connector->dev; 1334 struct amdgpu_device *adev = dev->dev_private; 1335 1336 if ((adev->clock.default_dispclk >= 53900) && 1337 amdgpu_connector_encoder_is_hbr2(connector)) { 1338 return true; 1339 } 1340 1341 return false; 1342 } 1343 1344 static enum drm_connector_status 1345 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1346 { 1347 struct drm_device *dev = connector->dev; 1348 struct amdgpu_device *adev = dev->dev_private; 1349 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1350 enum drm_connector_status ret = connector_status_disconnected; 1351 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1352 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1353 int r; 1354 1355 r = pm_runtime_get_sync(connector->dev->dev); 1356 if (r < 0) 1357 return connector_status_disconnected; 1358 1359 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1360 ret = connector->status; 1361 goto out; 1362 } 1363 1364 amdgpu_connector_free_edid(connector); 1365 1366 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1367 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1368 if (encoder) { 1369 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1370 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1371 1372 /* check if panel is valid */ 1373 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1374 ret = connector_status_connected; 1375 } 1376 /* eDP is always DP */ 1377 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1378 if (!amdgpu_dig_connector->edp_on) 1379 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1380 ATOM_TRANSMITTER_ACTION_POWER_ON); 1381 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1382 ret = connector_status_connected; 1383 if (!amdgpu_dig_connector->edp_on) 1384 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1385 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1386 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1387 ENCODER_OBJECT_ID_NONE) { 1388 /* DP bridges are always DP */ 1389 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1390 /* get the DPCD from the bridge */ 1391 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1392 1393 if (encoder) { 1394 /* setup ddc on the bridge */ 1395 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1396 /* bridge chips are always aux */ 1397 /* try DDC */ 1398 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1399 ret = connector_status_connected; 1400 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1401 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1402 ret = encoder_funcs->detect(encoder, connector); 1403 } 1404 } 1405 } else { 1406 amdgpu_dig_connector->dp_sink_type = 1407 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1408 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1409 ret = connector_status_connected; 1410 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1411 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1412 } else { 1413 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1414 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1415 ret = connector_status_connected; 1416 } else { 1417 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1418 if (amdgpu_display_ddc_probe(amdgpu_connector, 1419 false)) 1420 ret = connector_status_connected; 1421 } 1422 } 1423 } 1424 1425 amdgpu_connector_update_scratch_regs(connector, ret); 1426 out: 1427 pm_runtime_mark_last_busy(connector->dev->dev); 1428 pm_runtime_put_autosuspend(connector->dev->dev); 1429 1430 return ret; 1431 } 1432 1433 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1434 struct drm_display_mode *mode) 1435 { 1436 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1437 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1438 1439 /* XXX check mode bandwidth */ 1440 1441 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1442 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1443 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1444 1445 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1446 return MODE_PANEL; 1447 1448 if (encoder) { 1449 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1450 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1451 1452 /* AVIVO hardware supports downscaling modes larger than the panel 1453 * to the panel size, but I'm not sure this is desirable. 1454 */ 1455 if ((mode->hdisplay > native_mode->hdisplay) || 1456 (mode->vdisplay > native_mode->vdisplay)) 1457 return MODE_PANEL; 1458 1459 /* if scaling is disabled, block non-native modes */ 1460 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1461 if ((mode->hdisplay != native_mode->hdisplay) || 1462 (mode->vdisplay != native_mode->vdisplay)) 1463 return MODE_PANEL; 1464 } 1465 } 1466 return MODE_OK; 1467 } else { 1468 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1469 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1470 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1471 } else { 1472 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1473 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1474 if (mode->clock > 340000) 1475 return MODE_CLOCK_HIGH; 1476 } else { 1477 if (mode->clock > 165000) 1478 return MODE_CLOCK_HIGH; 1479 } 1480 } 1481 } 1482 1483 return MODE_OK; 1484 } 1485 1486 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1487 .get_modes = amdgpu_connector_dp_get_modes, 1488 .mode_valid = amdgpu_connector_dp_mode_valid, 1489 .best_encoder = amdgpu_connector_dvi_encoder, 1490 }; 1491 1492 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1493 .dpms = drm_helper_connector_dpms, 1494 .detect = amdgpu_connector_dp_detect, 1495 .fill_modes = drm_helper_probe_single_connector_modes, 1496 .set_property = amdgpu_connector_set_property, 1497 .early_unregister = amdgpu_connector_unregister, 1498 .destroy = amdgpu_connector_destroy, 1499 .force = amdgpu_connector_dvi_force, 1500 }; 1501 1502 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1503 .dpms = drm_helper_connector_dpms, 1504 .detect = amdgpu_connector_dp_detect, 1505 .fill_modes = drm_helper_probe_single_connector_modes, 1506 .set_property = amdgpu_connector_set_lcd_property, 1507 .early_unregister = amdgpu_connector_unregister, 1508 .destroy = amdgpu_connector_destroy, 1509 .force = amdgpu_connector_dvi_force, 1510 }; 1511 1512 void 1513 amdgpu_connector_add(struct amdgpu_device *adev, 1514 uint32_t connector_id, 1515 uint32_t supported_device, 1516 int connector_type, 1517 struct amdgpu_i2c_bus_rec *i2c_bus, 1518 uint16_t connector_object_id, 1519 struct amdgpu_hpd *hpd, 1520 struct amdgpu_router *router) 1521 { 1522 struct drm_device *dev = adev->ddev; 1523 struct drm_connector *connector; 1524 struct amdgpu_connector *amdgpu_connector; 1525 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1526 struct drm_encoder *encoder; 1527 struct amdgpu_encoder *amdgpu_encoder; 1528 uint32_t subpixel_order = SubPixelNone; 1529 bool shared_ddc = false; 1530 bool is_dp_bridge = false; 1531 bool has_aux = false; 1532 1533 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1534 return; 1535 1536 /* see if we already added it */ 1537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1538 amdgpu_connector = to_amdgpu_connector(connector); 1539 if (amdgpu_connector->connector_id == connector_id) { 1540 amdgpu_connector->devices |= supported_device; 1541 return; 1542 } 1543 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1544 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1545 amdgpu_connector->shared_ddc = true; 1546 shared_ddc = true; 1547 } 1548 if (amdgpu_connector->router_bus && router->ddc_valid && 1549 (amdgpu_connector->router.router_id == router->router_id)) { 1550 amdgpu_connector->shared_ddc = false; 1551 shared_ddc = false; 1552 } 1553 } 1554 } 1555 1556 /* check if it's a dp bridge */ 1557 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1558 amdgpu_encoder = to_amdgpu_encoder(encoder); 1559 if (amdgpu_encoder->devices & supported_device) { 1560 switch (amdgpu_encoder->encoder_id) { 1561 case ENCODER_OBJECT_ID_TRAVIS: 1562 case ENCODER_OBJECT_ID_NUTMEG: 1563 is_dp_bridge = true; 1564 break; 1565 default: 1566 break; 1567 } 1568 } 1569 } 1570 1571 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1572 if (!amdgpu_connector) 1573 return; 1574 1575 connector = &amdgpu_connector->base; 1576 1577 amdgpu_connector->connector_id = connector_id; 1578 amdgpu_connector->devices = supported_device; 1579 amdgpu_connector->shared_ddc = shared_ddc; 1580 amdgpu_connector->connector_object_id = connector_object_id; 1581 amdgpu_connector->hpd = *hpd; 1582 1583 amdgpu_connector->router = *router; 1584 if (router->ddc_valid || router->cd_valid) { 1585 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1586 if (!amdgpu_connector->router_bus) 1587 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1588 } 1589 1590 if (is_dp_bridge) { 1591 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1592 if (!amdgpu_dig_connector) 1593 goto failed; 1594 amdgpu_connector->con_priv = amdgpu_dig_connector; 1595 if (i2c_bus->valid) { 1596 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1597 if (amdgpu_connector->ddc_bus) 1598 has_aux = true; 1599 else 1600 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1601 } 1602 switch (connector_type) { 1603 case DRM_MODE_CONNECTOR_VGA: 1604 case DRM_MODE_CONNECTOR_DVIA: 1605 default: 1606 drm_connector_init(dev, &amdgpu_connector->base, 1607 &amdgpu_connector_dp_funcs, connector_type); 1608 drm_connector_helper_add(&amdgpu_connector->base, 1609 &amdgpu_connector_dp_helper_funcs); 1610 connector->interlace_allowed = true; 1611 connector->doublescan_allowed = true; 1612 amdgpu_connector->dac_load_detect = true; 1613 drm_object_attach_property(&amdgpu_connector->base.base, 1614 adev->mode_info.load_detect_property, 1615 1); 1616 drm_object_attach_property(&amdgpu_connector->base.base, 1617 dev->mode_config.scaling_mode_property, 1618 DRM_MODE_SCALE_NONE); 1619 break; 1620 case DRM_MODE_CONNECTOR_DVII: 1621 case DRM_MODE_CONNECTOR_DVID: 1622 case DRM_MODE_CONNECTOR_HDMIA: 1623 case DRM_MODE_CONNECTOR_HDMIB: 1624 case DRM_MODE_CONNECTOR_DisplayPort: 1625 drm_connector_init(dev, &amdgpu_connector->base, 1626 &amdgpu_connector_dp_funcs, connector_type); 1627 drm_connector_helper_add(&amdgpu_connector->base, 1628 &amdgpu_connector_dp_helper_funcs); 1629 drm_object_attach_property(&amdgpu_connector->base.base, 1630 adev->mode_info.underscan_property, 1631 UNDERSCAN_OFF); 1632 drm_object_attach_property(&amdgpu_connector->base.base, 1633 adev->mode_info.underscan_hborder_property, 1634 0); 1635 drm_object_attach_property(&amdgpu_connector->base.base, 1636 adev->mode_info.underscan_vborder_property, 1637 0); 1638 1639 drm_object_attach_property(&amdgpu_connector->base.base, 1640 dev->mode_config.scaling_mode_property, 1641 DRM_MODE_SCALE_NONE); 1642 1643 drm_object_attach_property(&amdgpu_connector->base.base, 1644 adev->mode_info.dither_property, 1645 AMDGPU_FMT_DITHER_DISABLE); 1646 1647 if (amdgpu_audio != 0) 1648 drm_object_attach_property(&amdgpu_connector->base.base, 1649 adev->mode_info.audio_property, 1650 AMDGPU_AUDIO_AUTO); 1651 1652 subpixel_order = SubPixelHorizontalRGB; 1653 connector->interlace_allowed = true; 1654 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1655 connector->doublescan_allowed = true; 1656 else 1657 connector->doublescan_allowed = false; 1658 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1659 amdgpu_connector->dac_load_detect = true; 1660 drm_object_attach_property(&amdgpu_connector->base.base, 1661 adev->mode_info.load_detect_property, 1662 1); 1663 } 1664 break; 1665 case DRM_MODE_CONNECTOR_LVDS: 1666 case DRM_MODE_CONNECTOR_eDP: 1667 drm_connector_init(dev, &amdgpu_connector->base, 1668 &amdgpu_connector_edp_funcs, connector_type); 1669 drm_connector_helper_add(&amdgpu_connector->base, 1670 &amdgpu_connector_dp_helper_funcs); 1671 drm_object_attach_property(&amdgpu_connector->base.base, 1672 dev->mode_config.scaling_mode_property, 1673 DRM_MODE_SCALE_FULLSCREEN); 1674 subpixel_order = SubPixelHorizontalRGB; 1675 connector->interlace_allowed = false; 1676 connector->doublescan_allowed = false; 1677 break; 1678 } 1679 } else { 1680 switch (connector_type) { 1681 case DRM_MODE_CONNECTOR_VGA: 1682 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1683 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1684 if (i2c_bus->valid) { 1685 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1686 if (!amdgpu_connector->ddc_bus) 1687 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1688 } 1689 amdgpu_connector->dac_load_detect = true; 1690 drm_object_attach_property(&amdgpu_connector->base.base, 1691 adev->mode_info.load_detect_property, 1692 1); 1693 drm_object_attach_property(&amdgpu_connector->base.base, 1694 dev->mode_config.scaling_mode_property, 1695 DRM_MODE_SCALE_NONE); 1696 /* no HPD on analog connectors */ 1697 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1698 connector->interlace_allowed = true; 1699 connector->doublescan_allowed = true; 1700 break; 1701 case DRM_MODE_CONNECTOR_DVIA: 1702 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1703 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1704 if (i2c_bus->valid) { 1705 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1706 if (!amdgpu_connector->ddc_bus) 1707 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1708 } 1709 amdgpu_connector->dac_load_detect = true; 1710 drm_object_attach_property(&amdgpu_connector->base.base, 1711 adev->mode_info.load_detect_property, 1712 1); 1713 drm_object_attach_property(&amdgpu_connector->base.base, 1714 dev->mode_config.scaling_mode_property, 1715 DRM_MODE_SCALE_NONE); 1716 /* no HPD on analog connectors */ 1717 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1718 connector->interlace_allowed = true; 1719 connector->doublescan_allowed = true; 1720 break; 1721 case DRM_MODE_CONNECTOR_DVII: 1722 case DRM_MODE_CONNECTOR_DVID: 1723 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1724 if (!amdgpu_dig_connector) 1725 goto failed; 1726 amdgpu_connector->con_priv = amdgpu_dig_connector; 1727 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1728 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1729 if (i2c_bus->valid) { 1730 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1731 if (!amdgpu_connector->ddc_bus) 1732 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1733 } 1734 subpixel_order = SubPixelHorizontalRGB; 1735 drm_object_attach_property(&amdgpu_connector->base.base, 1736 adev->mode_info.coherent_mode_property, 1737 1); 1738 drm_object_attach_property(&amdgpu_connector->base.base, 1739 adev->mode_info.underscan_property, 1740 UNDERSCAN_OFF); 1741 drm_object_attach_property(&amdgpu_connector->base.base, 1742 adev->mode_info.underscan_hborder_property, 1743 0); 1744 drm_object_attach_property(&amdgpu_connector->base.base, 1745 adev->mode_info.underscan_vborder_property, 1746 0); 1747 drm_object_attach_property(&amdgpu_connector->base.base, 1748 dev->mode_config.scaling_mode_property, 1749 DRM_MODE_SCALE_NONE); 1750 1751 if (amdgpu_audio != 0) { 1752 drm_object_attach_property(&amdgpu_connector->base.base, 1753 adev->mode_info.audio_property, 1754 AMDGPU_AUDIO_AUTO); 1755 } 1756 drm_object_attach_property(&amdgpu_connector->base.base, 1757 adev->mode_info.dither_property, 1758 AMDGPU_FMT_DITHER_DISABLE); 1759 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1760 amdgpu_connector->dac_load_detect = true; 1761 drm_object_attach_property(&amdgpu_connector->base.base, 1762 adev->mode_info.load_detect_property, 1763 1); 1764 } 1765 connector->interlace_allowed = true; 1766 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1767 connector->doublescan_allowed = true; 1768 else 1769 connector->doublescan_allowed = false; 1770 break; 1771 case DRM_MODE_CONNECTOR_HDMIA: 1772 case DRM_MODE_CONNECTOR_HDMIB: 1773 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1774 if (!amdgpu_dig_connector) 1775 goto failed; 1776 amdgpu_connector->con_priv = amdgpu_dig_connector; 1777 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1778 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1779 if (i2c_bus->valid) { 1780 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1781 if (!amdgpu_connector->ddc_bus) 1782 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1783 } 1784 drm_object_attach_property(&amdgpu_connector->base.base, 1785 adev->mode_info.coherent_mode_property, 1786 1); 1787 drm_object_attach_property(&amdgpu_connector->base.base, 1788 adev->mode_info.underscan_property, 1789 UNDERSCAN_OFF); 1790 drm_object_attach_property(&amdgpu_connector->base.base, 1791 adev->mode_info.underscan_hborder_property, 1792 0); 1793 drm_object_attach_property(&amdgpu_connector->base.base, 1794 adev->mode_info.underscan_vborder_property, 1795 0); 1796 drm_object_attach_property(&amdgpu_connector->base.base, 1797 dev->mode_config.scaling_mode_property, 1798 DRM_MODE_SCALE_NONE); 1799 if (amdgpu_audio != 0) { 1800 drm_object_attach_property(&amdgpu_connector->base.base, 1801 adev->mode_info.audio_property, 1802 AMDGPU_AUDIO_AUTO); 1803 } 1804 drm_object_attach_property(&amdgpu_connector->base.base, 1805 adev->mode_info.dither_property, 1806 AMDGPU_FMT_DITHER_DISABLE); 1807 subpixel_order = SubPixelHorizontalRGB; 1808 connector->interlace_allowed = true; 1809 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1810 connector->doublescan_allowed = true; 1811 else 1812 connector->doublescan_allowed = false; 1813 break; 1814 case DRM_MODE_CONNECTOR_DisplayPort: 1815 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1816 if (!amdgpu_dig_connector) 1817 goto failed; 1818 amdgpu_connector->con_priv = amdgpu_dig_connector; 1819 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1820 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1821 if (i2c_bus->valid) { 1822 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1823 if (amdgpu_connector->ddc_bus) 1824 has_aux = true; 1825 else 1826 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1827 } 1828 subpixel_order = SubPixelHorizontalRGB; 1829 drm_object_attach_property(&amdgpu_connector->base.base, 1830 adev->mode_info.coherent_mode_property, 1831 1); 1832 drm_object_attach_property(&amdgpu_connector->base.base, 1833 adev->mode_info.underscan_property, 1834 UNDERSCAN_OFF); 1835 drm_object_attach_property(&amdgpu_connector->base.base, 1836 adev->mode_info.underscan_hborder_property, 1837 0); 1838 drm_object_attach_property(&amdgpu_connector->base.base, 1839 adev->mode_info.underscan_vborder_property, 1840 0); 1841 drm_object_attach_property(&amdgpu_connector->base.base, 1842 dev->mode_config.scaling_mode_property, 1843 DRM_MODE_SCALE_NONE); 1844 if (amdgpu_audio != 0) { 1845 drm_object_attach_property(&amdgpu_connector->base.base, 1846 adev->mode_info.audio_property, 1847 AMDGPU_AUDIO_AUTO); 1848 } 1849 drm_object_attach_property(&amdgpu_connector->base.base, 1850 adev->mode_info.dither_property, 1851 AMDGPU_FMT_DITHER_DISABLE); 1852 connector->interlace_allowed = true; 1853 /* in theory with a DP to VGA converter... */ 1854 connector->doublescan_allowed = false; 1855 break; 1856 case DRM_MODE_CONNECTOR_eDP: 1857 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1858 if (!amdgpu_dig_connector) 1859 goto failed; 1860 amdgpu_connector->con_priv = amdgpu_dig_connector; 1861 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1862 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1863 if (i2c_bus->valid) { 1864 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1865 if (amdgpu_connector->ddc_bus) 1866 has_aux = true; 1867 else 1868 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1869 } 1870 drm_object_attach_property(&amdgpu_connector->base.base, 1871 dev->mode_config.scaling_mode_property, 1872 DRM_MODE_SCALE_FULLSCREEN); 1873 subpixel_order = SubPixelHorizontalRGB; 1874 connector->interlace_allowed = false; 1875 connector->doublescan_allowed = false; 1876 break; 1877 case DRM_MODE_CONNECTOR_LVDS: 1878 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1879 if (!amdgpu_dig_connector) 1880 goto failed; 1881 amdgpu_connector->con_priv = amdgpu_dig_connector; 1882 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1883 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1884 if (i2c_bus->valid) { 1885 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1886 if (!amdgpu_connector->ddc_bus) 1887 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1888 } 1889 drm_object_attach_property(&amdgpu_connector->base.base, 1890 dev->mode_config.scaling_mode_property, 1891 DRM_MODE_SCALE_FULLSCREEN); 1892 subpixel_order = SubPixelHorizontalRGB; 1893 connector->interlace_allowed = false; 1894 connector->doublescan_allowed = false; 1895 break; 1896 } 1897 } 1898 1899 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1900 if (i2c_bus->valid) { 1901 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1902 DRM_CONNECTOR_POLL_DISCONNECT; 1903 } 1904 } else 1905 connector->polled = DRM_CONNECTOR_POLL_HPD; 1906 1907 connector->display_info.subpixel_order = subpixel_order; 1908 drm_connector_register(connector); 1909 1910 if (has_aux) 1911 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1912 1913 return; 1914 1915 failed: 1916 drm_connector_cleanup(connector); 1917 kfree(connector); 1918 } 1919