1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher #include <drm/drmP.h> 27d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 28d38ceaf9SAlex Deucher #include <drm/drm_fb_helper.h> 29fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 30d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 31d38ceaf9SAlex Deucher #include "amdgpu.h" 32d38ceaf9SAlex Deucher #include "atom.h" 33d38ceaf9SAlex Deucher #include "atombios_encoders.h" 34d38ceaf9SAlex Deucher #include "atombios_dp.h" 35d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 36d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 375df58525SHuang Rui #include "amdgpu_display.h" 38d38ceaf9SAlex Deucher 39d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 42d38ceaf9SAlex Deucher { 43d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 44d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 45d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 46d38ceaf9SAlex Deucher 47d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 48d38ceaf9SAlex Deucher * VGA, TV, etc. 49d38ceaf9SAlex Deucher */ 50d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 51d38ceaf9SAlex Deucher return; 52d38ceaf9SAlex Deucher 53d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 54d38ceaf9SAlex Deucher 55d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 56d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 57d38ceaf9SAlex Deucher return; 58d38ceaf9SAlex Deucher 59d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 60d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 61d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 62d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 63d38ceaf9SAlex Deucher 64d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 65d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 66d38ceaf9SAlex Deucher return; 67d38ceaf9SAlex Deucher 68d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 69d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 70d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 71d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 72d38ceaf9SAlex Deucher */ 73daf88096SMichel Dänzer if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 74daf88096SMichel Dänzer amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 75daf88096SMichel Dänzer amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 76daf88096SMichel Dänzer /* Don't start link training before we have the DPCD */ 770b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 78a887adadSAlex Deucher return; 79a887adadSAlex Deucher 80daf88096SMichel Dänzer /* Turn the connector off and back on immediately, which 81daf88096SMichel Dänzer * will trigger link training 82d38ceaf9SAlex Deucher */ 83daf88096SMichel Dänzer drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 84d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 85d38ceaf9SAlex Deucher } 86d38ceaf9SAlex Deucher } 87d38ceaf9SAlex Deucher } 88d38ceaf9SAlex Deucher 89d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 90d38ceaf9SAlex Deucher { 91d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 92d38ceaf9SAlex Deucher 93d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 94d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 95d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 96d38ceaf9SAlex Deucher } 97d38ceaf9SAlex Deucher } 98d38ceaf9SAlex Deucher 99d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 100d38ceaf9SAlex Deucher { 101d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 102d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 103d38ceaf9SAlex Deucher int bpc = 8; 104d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock; 105d38ceaf9SAlex Deucher 106d38ceaf9SAlex Deucher switch (connector->connector_type) { 107d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 108d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 109d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 110d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 111d38ceaf9SAlex Deucher if (connector->display_info.bpc) 112d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 113d38ceaf9SAlex Deucher } 114d38ceaf9SAlex Deucher } 115d38ceaf9SAlex Deucher break; 116d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 117d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 118d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 119d38ceaf9SAlex Deucher if (connector->display_info.bpc) 120d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 121d38ceaf9SAlex Deucher } 122d38ceaf9SAlex Deucher break; 123d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 124d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 125d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 126d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 127d38ceaf9SAlex Deucher drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 128d38ceaf9SAlex Deucher if (connector->display_info.bpc) 129d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 130d38ceaf9SAlex Deucher } 131d38ceaf9SAlex Deucher break; 132d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 133d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 134d38ceaf9SAlex Deucher if (connector->display_info.bpc) 135d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 136d38ceaf9SAlex Deucher else { 13717b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = 138d38ceaf9SAlex Deucher connector->helper_private; 139d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 140d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 141d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 142d38ceaf9SAlex Deucher 143d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 144d38ceaf9SAlex Deucher bpc = 6; 145d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 146d38ceaf9SAlex Deucher bpc = 8; 147d38ceaf9SAlex Deucher } 148d38ceaf9SAlex Deucher break; 149d38ceaf9SAlex Deucher } 150d38ceaf9SAlex Deucher 151d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 152d38ceaf9SAlex Deucher /* 153d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 154d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 155d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 156d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 157d38ceaf9SAlex Deucher */ 158d38ceaf9SAlex Deucher if (bpc > 12) { 159d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 160d38ceaf9SAlex Deucher connector->name, bpc); 161d38ceaf9SAlex Deucher bpc = 12; 162d38ceaf9SAlex Deucher } 163d38ceaf9SAlex Deucher 164d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 1652a272ca9SVille Syrjälä if (connector->display_info.max_tmds_clock > 0) { 166d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 167d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 168d38ceaf9SAlex Deucher 169d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 1702a272ca9SVille Syrjälä max_tmds_clock = connector->display_info.max_tmds_clock; 171d38ceaf9SAlex Deucher 172d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 173d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 174d38ceaf9SAlex Deucher 175d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 176d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 177d38ceaf9SAlex Deucher if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 178d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 179d38ceaf9SAlex Deucher bpc = 10; 180d38ceaf9SAlex Deucher else 181d38ceaf9SAlex Deucher bpc = 8; 182d38ceaf9SAlex Deucher 183d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 184d38ceaf9SAlex Deucher connector->name, bpc); 185d38ceaf9SAlex Deucher } 186d38ceaf9SAlex Deucher 187d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 188d38ceaf9SAlex Deucher bpc = 8; 189d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 190d38ceaf9SAlex Deucher connector->name, bpc); 1919d746ab6SMario Kleiner } 192d38ceaf9SAlex Deucher } else if (bpc > 8) { 193d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 194d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 195d38ceaf9SAlex Deucher connector->name); 196d38ceaf9SAlex Deucher bpc = 8; 197d38ceaf9SAlex Deucher } 198d38ceaf9SAlex Deucher } 199d38ceaf9SAlex Deucher 200d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 201d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 202d38ceaf9SAlex Deucher connector->name); 203d38ceaf9SAlex Deucher bpc = 8; 204d38ceaf9SAlex Deucher } 205d38ceaf9SAlex Deucher 206d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 207d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 208d38ceaf9SAlex Deucher 209d38ceaf9SAlex Deucher return bpc; 210d38ceaf9SAlex Deucher } 211d38ceaf9SAlex Deucher 212d38ceaf9SAlex Deucher static void 213d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 214d38ceaf9SAlex Deucher enum drm_connector_status status) 215d38ceaf9SAlex Deucher { 21698c0e348SVille Syrjälä struct drm_encoder *best_encoder; 21798c0e348SVille Syrjälä struct drm_encoder *encoder; 21817b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 219d38ceaf9SAlex Deucher bool connected; 220d38ceaf9SAlex Deucher int i; 221d38ceaf9SAlex Deucher 222d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 223d38ceaf9SAlex Deucher 22498c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 225d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 226d38ceaf9SAlex Deucher connected = true; 227d38ceaf9SAlex Deucher else 228d38ceaf9SAlex Deucher connected = false; 229d38ceaf9SAlex Deucher 230d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 231d38ceaf9SAlex Deucher } 232d38ceaf9SAlex Deucher } 233d38ceaf9SAlex Deucher 234d38ceaf9SAlex Deucher static struct drm_encoder * 235d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 236d38ceaf9SAlex Deucher int encoder_type) 237d38ceaf9SAlex Deucher { 238d38ceaf9SAlex Deucher struct drm_encoder *encoder; 239d38ceaf9SAlex Deucher int i; 240d38ceaf9SAlex Deucher 24198c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 242d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 243d38ceaf9SAlex Deucher return encoder; 244d38ceaf9SAlex Deucher } 24598c0e348SVille Syrjälä 246d38ceaf9SAlex Deucher return NULL; 247d38ceaf9SAlex Deucher } 248d38ceaf9SAlex Deucher 249d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector) 250d38ceaf9SAlex Deucher { 251d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 252d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 253d38ceaf9SAlex Deucher 254d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 255d38ceaf9SAlex Deucher return amdgpu_connector->edid; 256d38ceaf9SAlex Deucher } else if (edid_blob) { 257d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 258d38ceaf9SAlex Deucher if (edid) 259d38ceaf9SAlex Deucher amdgpu_connector->edid = edid; 260d38ceaf9SAlex Deucher } 261d38ceaf9SAlex Deucher return amdgpu_connector->edid; 262d38ceaf9SAlex Deucher } 263d38ceaf9SAlex Deucher 264d38ceaf9SAlex Deucher static struct edid * 265d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 266d38ceaf9SAlex Deucher { 267d38ceaf9SAlex Deucher struct edid *edid; 268d38ceaf9SAlex Deucher 269d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 270d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 271d38ceaf9SAlex Deucher if (edid) { 272d38ceaf9SAlex Deucher memcpy((unsigned char *)edid, 273d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid, 274d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size); 275d38ceaf9SAlex Deucher return edid; 276d38ceaf9SAlex Deucher } 277d38ceaf9SAlex Deucher } 278d38ceaf9SAlex Deucher return NULL; 279d38ceaf9SAlex Deucher } 280d38ceaf9SAlex Deucher 281d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 282d38ceaf9SAlex Deucher { 283d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 284d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 285d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 286d38ceaf9SAlex Deucher 287d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 288d38ceaf9SAlex Deucher return; 289d38ceaf9SAlex Deucher 290d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 291d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 292d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 293d38ceaf9SAlex Deucher 294d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 295d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 296d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 297d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 298d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 299d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 300d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 301d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 302d38ceaf9SAlex Deucher 303d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 304d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 305d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 306d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 307d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 308d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 309d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 310d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 311d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 312d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 313d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 314d38ceaf9SAlex Deucher } 315d38ceaf9SAlex Deucher 316d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 317d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 318d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 319d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 320d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 321d38ceaf9SAlex Deucher } 322d38ceaf9SAlex Deucher } 323d38ceaf9SAlex Deucher 324d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 325d38ceaf9SAlex Deucher { 326d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 327d38ceaf9SAlex Deucher 328d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 329d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 330d38ceaf9SAlex Deucher } 331d38ceaf9SAlex Deucher 332d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 333d38ceaf9SAlex Deucher { 334d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 335d38ceaf9SAlex Deucher int ret; 336d38ceaf9SAlex Deucher 337d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 338c555f023SDaniel Vetter drm_connector_update_edid_property(connector, amdgpu_connector->edid); 339d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 340d38ceaf9SAlex Deucher return ret; 341d38ceaf9SAlex Deucher } 342c555f023SDaniel Vetter drm_connector_update_edid_property(connector, NULL); 343d38ceaf9SAlex Deucher return 0; 344d38ceaf9SAlex Deucher } 345d38ceaf9SAlex Deucher 346d38ceaf9SAlex Deucher static struct drm_encoder * 347d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 348d38ceaf9SAlex Deucher { 34998c0e348SVille Syrjälä struct drm_encoder *encoder; 35098c0e348SVille Syrjälä int i; 351d38ceaf9SAlex Deucher 35298c0e348SVille Syrjälä /* pick the first one */ 35398c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) 35498c0e348SVille Syrjälä return encoder; 35598c0e348SVille Syrjälä 356d38ceaf9SAlex Deucher return NULL; 357d38ceaf9SAlex Deucher } 358d38ceaf9SAlex Deucher 359d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 360d38ceaf9SAlex Deucher { 361d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 362d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 363d38ceaf9SAlex Deucher 364d38ceaf9SAlex Deucher if (encoder == NULL) 365d38ceaf9SAlex Deucher return; 366d38ceaf9SAlex Deucher 367d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 368d38ceaf9SAlex Deucher 369d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 370d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 371d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 372d38ceaf9SAlex Deucher struct drm_display_mode, head); 373d38ceaf9SAlex Deucher 374d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 375d38ceaf9SAlex Deucher } else { 376d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 377d38ceaf9SAlex Deucher } 378d38ceaf9SAlex Deucher } 379d38ceaf9SAlex Deucher 380d38ceaf9SAlex Deucher static struct drm_display_mode * 381d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 382d38ceaf9SAlex Deucher { 383d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 384d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 385d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 386d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 387d38ceaf9SAlex Deucher 388d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 389d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 390d38ceaf9SAlex Deucher native_mode->clock != 0) { 391d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 392d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 393d38ceaf9SAlex Deucher drm_mode_set_name(mode); 394d38ceaf9SAlex Deucher 395d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 396d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 397d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 398d38ceaf9SAlex Deucher /* mac laptops without an edid */ 399d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 400d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 401d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 402d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 403d38ceaf9SAlex Deucher * simpler. 404d38ceaf9SAlex Deucher */ 405d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 406d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 407d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 408d38ceaf9SAlex Deucher } 409d38ceaf9SAlex Deucher return mode; 410d38ceaf9SAlex Deucher } 411d38ceaf9SAlex Deucher 412d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 413d38ceaf9SAlex Deucher struct drm_connector *connector) 414d38ceaf9SAlex Deucher { 415d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 416d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 417d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 418d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 419d38ceaf9SAlex Deucher int i; 420aeba709aSNils Wallménius static const struct mode_size { 421d38ceaf9SAlex Deucher int w; 422d38ceaf9SAlex Deucher int h; 423d38ceaf9SAlex Deucher } common_modes[17] = { 424d38ceaf9SAlex Deucher { 640, 480}, 425d38ceaf9SAlex Deucher { 720, 480}, 426d38ceaf9SAlex Deucher { 800, 600}, 427d38ceaf9SAlex Deucher { 848, 480}, 428d38ceaf9SAlex Deucher {1024, 768}, 429d38ceaf9SAlex Deucher {1152, 768}, 430d38ceaf9SAlex Deucher {1280, 720}, 431d38ceaf9SAlex Deucher {1280, 800}, 432d38ceaf9SAlex Deucher {1280, 854}, 433d38ceaf9SAlex Deucher {1280, 960}, 434d38ceaf9SAlex Deucher {1280, 1024}, 435d38ceaf9SAlex Deucher {1440, 900}, 436d38ceaf9SAlex Deucher {1400, 1050}, 437d38ceaf9SAlex Deucher {1680, 1050}, 438d38ceaf9SAlex Deucher {1600, 1200}, 439d38ceaf9SAlex Deucher {1920, 1080}, 440d38ceaf9SAlex Deucher {1920, 1200} 441d38ceaf9SAlex Deucher }; 442d38ceaf9SAlex Deucher 443d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 444d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 445d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 446d38ceaf9SAlex Deucher common_modes[i].h > 768) 447d38ceaf9SAlex Deucher continue; 448d38ceaf9SAlex Deucher } 449d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 450d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 451d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 452d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 453d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 454d38ceaf9SAlex Deucher continue; 455d38ceaf9SAlex Deucher } 456d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 457d38ceaf9SAlex Deucher continue; 458d38ceaf9SAlex Deucher 459d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 460d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 461d38ceaf9SAlex Deucher } 462d38ceaf9SAlex Deucher } 463d38ceaf9SAlex Deucher 464d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 465d38ceaf9SAlex Deucher struct drm_property *property, 466d38ceaf9SAlex Deucher uint64_t val) 467d38ceaf9SAlex Deucher { 468d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 469d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 470d38ceaf9SAlex Deucher struct drm_encoder *encoder; 471d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 472d38ceaf9SAlex Deucher 473d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 474d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 475d38ceaf9SAlex Deucher bool new_coherent_mode; 476d38ceaf9SAlex Deucher 477d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 478d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 479d38ceaf9SAlex Deucher if (!encoder) 480d38ceaf9SAlex Deucher return 0; 481d38ceaf9SAlex Deucher 482d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 483d38ceaf9SAlex Deucher 484d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 485d38ceaf9SAlex Deucher return 0; 486d38ceaf9SAlex Deucher 487d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 488d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 489d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 490d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 491d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 492d38ceaf9SAlex Deucher } 493d38ceaf9SAlex Deucher } 494d38ceaf9SAlex Deucher 495d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 496d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 497d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 498d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 499d38ceaf9SAlex Deucher if (!encoder) 500d38ceaf9SAlex Deucher return 0; 501d38ceaf9SAlex Deucher 502d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 503d38ceaf9SAlex Deucher 504d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 505d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 506d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 507d38ceaf9SAlex Deucher } 508d38ceaf9SAlex Deucher } 509d38ceaf9SAlex Deucher 510d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 511d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 512d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 513d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 514d38ceaf9SAlex Deucher if (!encoder) 515d38ceaf9SAlex Deucher return 0; 516d38ceaf9SAlex Deucher 517d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 518d38ceaf9SAlex Deucher 519d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 520d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 521d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 522d38ceaf9SAlex Deucher } 523d38ceaf9SAlex Deucher } 524d38ceaf9SAlex Deucher 525d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 526d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 527d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 528d38ceaf9SAlex Deucher if (!encoder) 529d38ceaf9SAlex Deucher return 0; 530d38ceaf9SAlex Deucher 531d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 532d38ceaf9SAlex Deucher 533d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 534d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 535d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 536d38ceaf9SAlex Deucher } 537d38ceaf9SAlex Deucher } 538d38ceaf9SAlex Deucher 539d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 540d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 541d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 542d38ceaf9SAlex Deucher if (!encoder) 543d38ceaf9SAlex Deucher return 0; 544d38ceaf9SAlex Deucher 545d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 546d38ceaf9SAlex Deucher 547d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 548d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 549d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 550d38ceaf9SAlex Deucher } 551d38ceaf9SAlex Deucher } 552d38ceaf9SAlex Deucher 553d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 554d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 555d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 556d38ceaf9SAlex Deucher if (!encoder) 557d38ceaf9SAlex Deucher return 0; 558d38ceaf9SAlex Deucher 559d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 560d38ceaf9SAlex Deucher 561d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 562d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 563d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 564d38ceaf9SAlex Deucher } 565d38ceaf9SAlex Deucher } 566d38ceaf9SAlex Deucher 567d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 568d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 569d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 570d38ceaf9SAlex Deucher 571d38ceaf9SAlex Deucher if (val == 0) 572d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 573d38ceaf9SAlex Deucher else 574d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 575d38ceaf9SAlex Deucher } 576d38ceaf9SAlex Deucher 577d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 578d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 579d38ceaf9SAlex Deucher 580d38ceaf9SAlex Deucher if (connector->encoder) { 581d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 582d38ceaf9SAlex Deucher } else { 58317b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 584d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 585d38ceaf9SAlex Deucher } 586d38ceaf9SAlex Deucher 587d38ceaf9SAlex Deucher switch (val) { 588d38ceaf9SAlex Deucher default: 589d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 590d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 591d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 592d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 593d38ceaf9SAlex Deucher } 594d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 595d38ceaf9SAlex Deucher return 0; 596d38ceaf9SAlex Deucher 597d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 598d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 599d38ceaf9SAlex Deucher return 0; 600d38ceaf9SAlex Deucher 601d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 602d38ceaf9SAlex Deucher 603d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 604d38ceaf9SAlex Deucher } 605d38ceaf9SAlex Deucher 606d38ceaf9SAlex Deucher return 0; 607d38ceaf9SAlex Deucher } 608d38ceaf9SAlex Deucher 609d38ceaf9SAlex Deucher static void 610d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 611d38ceaf9SAlex Deucher struct drm_connector *connector) 612d38ceaf9SAlex Deucher { 613d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 614d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 615d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 616d38ceaf9SAlex Deucher 617d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 618d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 619d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 620d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 621d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 622d38ceaf9SAlex Deucher memcpy(native_mode, mode, sizeof(*mode)); 623d38ceaf9SAlex Deucher } 624d38ceaf9SAlex Deucher } 625d38ceaf9SAlex Deucher 626d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 627d38ceaf9SAlex Deucher if (!native_mode->clock) { 628d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 629d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 630d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 631d38ceaf9SAlex Deucher *native_mode = *mode; 632d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 633d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 634d38ceaf9SAlex Deucher break; 635d38ceaf9SAlex Deucher } 636d38ceaf9SAlex Deucher } 637d38ceaf9SAlex Deucher } 638d38ceaf9SAlex Deucher 639d38ceaf9SAlex Deucher if (!native_mode->clock) { 640d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 641d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 642d38ceaf9SAlex Deucher } 643d38ceaf9SAlex Deucher } 644d38ceaf9SAlex Deucher 645d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 646d38ceaf9SAlex Deucher { 647d38ceaf9SAlex Deucher struct drm_encoder *encoder; 648d38ceaf9SAlex Deucher int ret = 0; 649d38ceaf9SAlex Deucher struct drm_display_mode *mode; 650d38ceaf9SAlex Deucher 651d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 652d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 653d38ceaf9SAlex Deucher if (ret > 0) { 654d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 655d38ceaf9SAlex Deucher if (encoder) { 656d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 657d38ceaf9SAlex Deucher /* add scaled modes */ 658d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 659d38ceaf9SAlex Deucher } 660d38ceaf9SAlex Deucher return ret; 661d38ceaf9SAlex Deucher } 662d38ceaf9SAlex Deucher 663d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 664d38ceaf9SAlex Deucher if (!encoder) 665d38ceaf9SAlex Deucher return 0; 666d38ceaf9SAlex Deucher 667d38ceaf9SAlex Deucher /* we have no EDID modes */ 668d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 669d38ceaf9SAlex Deucher if (mode) { 670d38ceaf9SAlex Deucher ret = 1; 671d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 672d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 673d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 674d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 675d38ceaf9SAlex Deucher /* add scaled modes */ 676d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 677d38ceaf9SAlex Deucher } 678d38ceaf9SAlex Deucher 679d38ceaf9SAlex Deucher return ret; 680d38ceaf9SAlex Deucher } 681d38ceaf9SAlex Deucher 682ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 683d38ceaf9SAlex Deucher struct drm_display_mode *mode) 684d38ceaf9SAlex Deucher { 685d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 686d38ceaf9SAlex Deucher 687d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 688d38ceaf9SAlex Deucher return MODE_PANEL; 689d38ceaf9SAlex Deucher 690d38ceaf9SAlex Deucher if (encoder) { 691d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 692d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 693d38ceaf9SAlex Deucher 694d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 695d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 696d38ceaf9SAlex Deucher */ 697d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 698d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 699d38ceaf9SAlex Deucher return MODE_PANEL; 700d38ceaf9SAlex Deucher 701d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 702d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 703d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 704d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 705d38ceaf9SAlex Deucher return MODE_PANEL; 706d38ceaf9SAlex Deucher } 707d38ceaf9SAlex Deucher } 708d38ceaf9SAlex Deucher 709d38ceaf9SAlex Deucher return MODE_OK; 710d38ceaf9SAlex Deucher } 711d38ceaf9SAlex Deucher 712d38ceaf9SAlex Deucher static enum drm_connector_status 713d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 714d38ceaf9SAlex Deucher { 715d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 716d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 717d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 718d38ceaf9SAlex Deucher int r; 719d38ceaf9SAlex Deucher 720aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 721d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 722d38ceaf9SAlex Deucher if (r < 0) 723d38ceaf9SAlex Deucher return connector_status_disconnected; 724aa0aad57SLukas Wunner } 725d38ceaf9SAlex Deucher 726d38ceaf9SAlex Deucher if (encoder) { 727d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 728d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 729d38ceaf9SAlex Deucher 730d38ceaf9SAlex Deucher /* check if panel is valid */ 731d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 732d38ceaf9SAlex Deucher ret = connector_status_connected; 733d38ceaf9SAlex Deucher 734d38ceaf9SAlex Deucher } 735d38ceaf9SAlex Deucher 736d38ceaf9SAlex Deucher /* check for edid as well */ 737d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 738d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 739d38ceaf9SAlex Deucher ret = connector_status_connected; 740d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 741d38ceaf9SAlex Deucher 742d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 743aa0aad57SLukas Wunner 744aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 745d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 746d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 747aa0aad57SLukas Wunner } 748aa0aad57SLukas Wunner 749d38ceaf9SAlex Deucher return ret; 750d38ceaf9SAlex Deucher } 751d38ceaf9SAlex Deucher 75240492f60SGrazvydas Ignotas static void amdgpu_connector_unregister(struct drm_connector *connector) 753d38ceaf9SAlex Deucher { 754d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 755d38ceaf9SAlex Deucher 756eef2b411SAlex Deucher if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 757d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 7582f9ba199SGrazvydas Ignotas amdgpu_connector->ddc_bus->has_aux = false; 7592f9ba199SGrazvydas Ignotas } 76040492f60SGrazvydas Ignotas } 76140492f60SGrazvydas Ignotas 76240492f60SGrazvydas Ignotas static void amdgpu_connector_destroy(struct drm_connector *connector) 76340492f60SGrazvydas Ignotas { 76440492f60SGrazvydas Ignotas struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 76540492f60SGrazvydas Ignotas 766d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 767d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 768d38ceaf9SAlex Deucher drm_connector_unregister(connector); 769d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 770d38ceaf9SAlex Deucher kfree(connector); 771d38ceaf9SAlex Deucher } 772d38ceaf9SAlex Deucher 773d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 774d38ceaf9SAlex Deucher struct drm_property *property, 775d38ceaf9SAlex Deucher uint64_t value) 776d38ceaf9SAlex Deucher { 777d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 778d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 779d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 780d38ceaf9SAlex Deucher 781d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 782d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 783d38ceaf9SAlex Deucher return 0; 784d38ceaf9SAlex Deucher 785d38ceaf9SAlex Deucher if (connector->encoder) 786d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 787d38ceaf9SAlex Deucher else { 78817b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 789d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 790d38ceaf9SAlex Deucher } 791d38ceaf9SAlex Deucher 792d38ceaf9SAlex Deucher switch (value) { 793d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 794d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 795d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 796d38ceaf9SAlex Deucher default: 797d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 798d38ceaf9SAlex Deucher } 799d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 800d38ceaf9SAlex Deucher return 0; 801d38ceaf9SAlex Deucher 802d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 803d38ceaf9SAlex Deucher 804d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 805d38ceaf9SAlex Deucher return 0; 806d38ceaf9SAlex Deucher } 807d38ceaf9SAlex Deucher 808d38ceaf9SAlex Deucher 809d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 810d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 811d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 812d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 813d38ceaf9SAlex Deucher }; 814d38ceaf9SAlex Deucher 815d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 816d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 817d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 818d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 81940492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 820d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 821d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 822d38ceaf9SAlex Deucher }; 823d38ceaf9SAlex Deucher 824d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 825d38ceaf9SAlex Deucher { 826d38ceaf9SAlex Deucher int ret; 827d38ceaf9SAlex Deucher 828d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 829d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 830d38ceaf9SAlex Deucher 831d38ceaf9SAlex Deucher return ret; 832d38ceaf9SAlex Deucher } 833d38ceaf9SAlex Deucher 834ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 835d38ceaf9SAlex Deucher struct drm_display_mode *mode) 836d38ceaf9SAlex Deucher { 837d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 838d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 839d38ceaf9SAlex Deucher 840d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 841d38ceaf9SAlex Deucher 842d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 843d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 844d38ceaf9SAlex Deucher 845d38ceaf9SAlex Deucher return MODE_OK; 846d38ceaf9SAlex Deucher } 847d38ceaf9SAlex Deucher 848d38ceaf9SAlex Deucher static enum drm_connector_status 849d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 850d38ceaf9SAlex Deucher { 851d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 852d38ceaf9SAlex Deucher struct drm_encoder *encoder; 85317b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 854d38ceaf9SAlex Deucher bool dret = false; 855d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 856d38ceaf9SAlex Deucher int r; 857d38ceaf9SAlex Deucher 858aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 859d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 860d38ceaf9SAlex Deucher if (r < 0) 861d38ceaf9SAlex Deucher return connector_status_disconnected; 862aa0aad57SLukas Wunner } 863d38ceaf9SAlex Deucher 864d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 865d38ceaf9SAlex Deucher if (!encoder) 866d38ceaf9SAlex Deucher ret = connector_status_disconnected; 867d38ceaf9SAlex Deucher 868d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 869e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 870d38ceaf9SAlex Deucher if (dret) { 871d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 872d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 873d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 874d38ceaf9SAlex Deucher 875d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 876d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 877d38ceaf9SAlex Deucher connector->name); 878d38ceaf9SAlex Deucher ret = connector_status_connected; 879d38ceaf9SAlex Deucher } else { 880d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 881d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 882d38ceaf9SAlex Deucher 883d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 884d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 885d38ceaf9SAlex Deucher */ 886d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 887d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 888d38ceaf9SAlex Deucher ret = connector_status_disconnected; 889d38ceaf9SAlex Deucher } else { 890d38ceaf9SAlex Deucher ret = connector_status_connected; 891d38ceaf9SAlex Deucher } 892d38ceaf9SAlex Deucher } 893d38ceaf9SAlex Deucher } else { 894d38ceaf9SAlex Deucher 895d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 896d38ceaf9SAlex Deucher if (!force) { 897d38ceaf9SAlex Deucher /* only return the previous status if we last 898d38ceaf9SAlex Deucher * detected a monitor via load. 899d38ceaf9SAlex Deucher */ 900d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 901d38ceaf9SAlex Deucher ret = connector->status; 902d38ceaf9SAlex Deucher goto out; 903d38ceaf9SAlex Deucher } 904d38ceaf9SAlex Deucher 905d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 906d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 907d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 908d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 909d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 910d38ceaf9SAlex Deucher } 911d38ceaf9SAlex Deucher } 912d38ceaf9SAlex Deucher 913d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 914d38ceaf9SAlex Deucher 915d38ceaf9SAlex Deucher out: 916aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 917d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 918d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 919aa0aad57SLukas Wunner } 920d38ceaf9SAlex Deucher 921d38ceaf9SAlex Deucher return ret; 922d38ceaf9SAlex Deucher } 923d38ceaf9SAlex Deucher 924d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 925d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 926d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 927d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 928d38ceaf9SAlex Deucher }; 929d38ceaf9SAlex Deucher 930d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 931d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 932d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 933d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 93440492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 935d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 936d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 937d38ceaf9SAlex Deucher }; 938d38ceaf9SAlex Deucher 939d38ceaf9SAlex Deucher static bool 940d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 941d38ceaf9SAlex Deucher { 942d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 943d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 944d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 945d38ceaf9SAlex Deucher enum drm_connector_status status; 946d38ceaf9SAlex Deucher 947d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 948d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 949d38ceaf9SAlex Deucher status = connector_status_connected; 950d38ceaf9SAlex Deucher else 951d38ceaf9SAlex Deucher status = connector_status_disconnected; 952d38ceaf9SAlex Deucher if (connector->status == status) 953d38ceaf9SAlex Deucher return true; 954d38ceaf9SAlex Deucher } 955d38ceaf9SAlex Deucher 956d38ceaf9SAlex Deucher return false; 957d38ceaf9SAlex Deucher } 958d38ceaf9SAlex Deucher 959d38ceaf9SAlex Deucher /* 960d38ceaf9SAlex Deucher * DVI is complicated 961d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 962d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 963d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 964d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 965d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 966d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 967d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 968d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 969d38ceaf9SAlex Deucher */ 970d38ceaf9SAlex Deucher static enum drm_connector_status 971d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 972d38ceaf9SAlex Deucher { 973d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 974d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 975d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 97617b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 97798c0e348SVille Syrjälä int r; 978d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 979d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 980d38ceaf9SAlex Deucher 981aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 982d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 983d38ceaf9SAlex Deucher if (r < 0) 984d38ceaf9SAlex Deucher return connector_status_disconnected; 985aa0aad57SLukas Wunner } 986d38ceaf9SAlex Deucher 987d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 988d38ceaf9SAlex Deucher ret = connector->status; 989d38ceaf9SAlex Deucher goto exit; 990d38ceaf9SAlex Deucher } 991d38ceaf9SAlex Deucher 992d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 993e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 994d38ceaf9SAlex Deucher if (dret) { 995d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 996d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 997d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 998d38ceaf9SAlex Deucher 999d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 1000d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1001d38ceaf9SAlex Deucher connector->name); 1002d38ceaf9SAlex Deucher ret = connector_status_connected; 1003d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1004d38ceaf9SAlex Deucher } else { 1005d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1006d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1007d38ceaf9SAlex Deucher 1008d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1009d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1010d38ceaf9SAlex Deucher */ 1011d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1012d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1013d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1014d38ceaf9SAlex Deucher } else { 1015d38ceaf9SAlex Deucher ret = connector_status_connected; 1016d38ceaf9SAlex Deucher } 1017d38ceaf9SAlex Deucher 1018d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1019d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1020d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1021d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1022d38ceaf9SAlex Deucher */ 1023d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1024d38ceaf9SAlex Deucher struct drm_connector *list_connector; 1025d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector; 1026d38ceaf9SAlex Deucher list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1027d38ceaf9SAlex Deucher if (connector == list_connector) 1028d38ceaf9SAlex Deucher continue; 1029d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector); 1030d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc && 1031d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1032d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) { 1033d38ceaf9SAlex Deucher /* cases where both connectors are digital */ 1034d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1035d38ceaf9SAlex Deucher /* hpd is our only option in this case */ 1036d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1037d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1038d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1039d38ceaf9SAlex Deucher } 1040d38ceaf9SAlex Deucher } 1041d38ceaf9SAlex Deucher } 1042d38ceaf9SAlex Deucher } 1043d38ceaf9SAlex Deucher } 1044d38ceaf9SAlex Deucher } 1045d38ceaf9SAlex Deucher } 1046d38ceaf9SAlex Deucher 1047d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1048d38ceaf9SAlex Deucher goto out; 1049d38ceaf9SAlex Deucher 1050d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1051d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1052d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1053d38ceaf9SAlex Deucher goto out; 1054d38ceaf9SAlex Deucher 1055d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1056d38ceaf9SAlex Deucher if (!force) { 1057d38ceaf9SAlex Deucher /* only return the previous status if we last 1058d38ceaf9SAlex Deucher * detected a monitor via load. 1059d38ceaf9SAlex Deucher */ 1060d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1061d38ceaf9SAlex Deucher ret = connector->status; 1062d38ceaf9SAlex Deucher goto out; 1063d38ceaf9SAlex Deucher } 1064d38ceaf9SAlex Deucher 1065d38ceaf9SAlex Deucher /* find analog encoder */ 1066d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 106798c0e348SVille Syrjälä struct drm_encoder *encoder; 106898c0e348SVille Syrjälä int i; 1069d38ceaf9SAlex Deucher 107098c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1071d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1072d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1073d38ceaf9SAlex Deucher continue; 1074d38ceaf9SAlex Deucher 1075d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1076d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1077d38ceaf9SAlex Deucher if (!broken_edid) { 1078d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1079d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1080d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1081d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1082d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1083d38ceaf9SAlex Deucher } 1084d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1085d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1086d38ceaf9SAlex Deucher } 1087d38ceaf9SAlex Deucher } else { 1088d38ceaf9SAlex Deucher enum drm_connector_status lret; 1089d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1090d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1091d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1092d38ceaf9SAlex Deucher DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1093d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1094d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1095d38ceaf9SAlex Deucher } 1096d38ceaf9SAlex Deucher break; 1097d38ceaf9SAlex Deucher } 1098d38ceaf9SAlex Deucher } 1099d38ceaf9SAlex Deucher } 1100d38ceaf9SAlex Deucher 1101d38ceaf9SAlex Deucher out: 1102d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1103d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1104d38ceaf9SAlex Deucher 1105d38ceaf9SAlex Deucher exit: 1106aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1107d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1108d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1109aa0aad57SLukas Wunner } 1110d38ceaf9SAlex Deucher 1111d38ceaf9SAlex Deucher return ret; 1112d38ceaf9SAlex Deucher } 1113d38ceaf9SAlex Deucher 1114d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1115d38ceaf9SAlex Deucher static struct drm_encoder * 1116d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1117d38ceaf9SAlex Deucher { 1118d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1119d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1120d38ceaf9SAlex Deucher int i; 1121d38ceaf9SAlex Deucher 112298c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1123d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1124d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1125d38ceaf9SAlex Deucher return encoder; 1126d38ceaf9SAlex Deucher } else { 1127d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1128d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1129d38ceaf9SAlex Deucher return encoder; 1130d38ceaf9SAlex Deucher } 1131d38ceaf9SAlex Deucher } 1132d38ceaf9SAlex Deucher 1133d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1134d38ceaf9SAlex Deucher 1135d38ceaf9SAlex Deucher /* then check use digitial */ 1136d38ceaf9SAlex Deucher /* pick the first one */ 113798c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) 113898c0e348SVille Syrjälä return encoder; 113998c0e348SVille Syrjälä 1140d38ceaf9SAlex Deucher return NULL; 1141d38ceaf9SAlex Deucher } 1142d38ceaf9SAlex Deucher 1143d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1144d38ceaf9SAlex Deucher { 1145d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1146d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1147d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1148d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1149d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1150d38ceaf9SAlex Deucher } 1151d38ceaf9SAlex Deucher 1152ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1153d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1154d38ceaf9SAlex Deucher { 1155d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1156d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1157d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1158d38ceaf9SAlex Deucher 1159d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1160d38ceaf9SAlex Deucher 1161d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1162d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1163d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1164d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1165d38ceaf9SAlex Deucher return MODE_OK; 1166d38ceaf9SAlex Deucher } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1167d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1168d38ceaf9SAlex Deucher if (mode->clock > 340000) 1169d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1170d38ceaf9SAlex Deucher else 1171d38ceaf9SAlex Deucher return MODE_OK; 1172d38ceaf9SAlex Deucher } else { 1173d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1174d38ceaf9SAlex Deucher } 1175d38ceaf9SAlex Deucher } 1176d38ceaf9SAlex Deucher 1177d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1178d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1179d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1180d38ceaf9SAlex Deucher 1181d38ceaf9SAlex Deucher return MODE_OK; 1182d38ceaf9SAlex Deucher } 1183d38ceaf9SAlex Deucher 1184d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1185d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1186d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1187d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1188d38ceaf9SAlex Deucher }; 1189d38ceaf9SAlex Deucher 1190d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1191d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1192d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1193d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1194d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 119540492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1196d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1197d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1198d38ceaf9SAlex Deucher }; 1199d38ceaf9SAlex Deucher 1200d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1201d38ceaf9SAlex Deucher { 1202d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1203d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1204d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1205d38ceaf9SAlex Deucher int ret; 1206d38ceaf9SAlex Deucher 1207d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1208d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1209d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1210d38ceaf9SAlex Deucher 1211d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1212d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1213d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1214d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1215d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1216d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1217d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1218d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1219d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1220d38ceaf9SAlex Deucher } else { 1221d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1222d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1223d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1224d38ceaf9SAlex Deucher if (encoder) 1225d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1226d38ceaf9SAlex Deucher } 1227d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1228d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1229d38ceaf9SAlex Deucher } 1230d38ceaf9SAlex Deucher 1231d38ceaf9SAlex Deucher if (ret > 0) { 1232d38ceaf9SAlex Deucher if (encoder) { 1233d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1234d38ceaf9SAlex Deucher /* add scaled modes */ 1235d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1236d38ceaf9SAlex Deucher } 1237d38ceaf9SAlex Deucher return ret; 1238d38ceaf9SAlex Deucher } 1239d38ceaf9SAlex Deucher 1240d38ceaf9SAlex Deucher if (!encoder) 1241d38ceaf9SAlex Deucher return 0; 1242d38ceaf9SAlex Deucher 1243d38ceaf9SAlex Deucher /* we have no EDID modes */ 1244d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1245d38ceaf9SAlex Deucher if (mode) { 1246d38ceaf9SAlex Deucher ret = 1; 1247d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1248d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1249d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1250d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1251d38ceaf9SAlex Deucher /* add scaled modes */ 1252d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1253d38ceaf9SAlex Deucher } 1254d38ceaf9SAlex Deucher } else { 1255d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1256d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1257d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1258d38ceaf9SAlex Deucher if (encoder) 1259d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1260d38ceaf9SAlex Deucher } 1261d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1262d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1263d38ceaf9SAlex Deucher 1264d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1265d38ceaf9SAlex Deucher } 1266d38ceaf9SAlex Deucher 1267d38ceaf9SAlex Deucher return ret; 1268d38ceaf9SAlex Deucher } 1269d38ceaf9SAlex Deucher 1270d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1271d38ceaf9SAlex Deucher { 1272d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1273d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1274d38ceaf9SAlex Deucher int i; 1275d38ceaf9SAlex Deucher 127698c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1277d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1278d38ceaf9SAlex Deucher 1279d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1280d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1281d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1282d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1283d38ceaf9SAlex Deucher default: 1284d38ceaf9SAlex Deucher break; 1285d38ceaf9SAlex Deucher } 1286d38ceaf9SAlex Deucher } 1287d38ceaf9SAlex Deucher 1288d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1289d38ceaf9SAlex Deucher } 1290d38ceaf9SAlex Deucher 1291d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1292d38ceaf9SAlex Deucher { 1293d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1294d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1295d38ceaf9SAlex Deucher int i; 1296d38ceaf9SAlex Deucher bool found = false; 1297d38ceaf9SAlex Deucher 129898c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1299d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1300d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1301d38ceaf9SAlex Deucher found = true; 1302d38ceaf9SAlex Deucher } 1303d38ceaf9SAlex Deucher 1304d38ceaf9SAlex Deucher return found; 1305d38ceaf9SAlex Deucher } 1306d38ceaf9SAlex Deucher 1307d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1308d38ceaf9SAlex Deucher { 1309d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1310d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1311d38ceaf9SAlex Deucher 1312d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1313d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1314d38ceaf9SAlex Deucher return true; 1315d38ceaf9SAlex Deucher } 1316d38ceaf9SAlex Deucher 1317d38ceaf9SAlex Deucher return false; 1318d38ceaf9SAlex Deucher } 1319d38ceaf9SAlex Deucher 1320d38ceaf9SAlex Deucher static enum drm_connector_status 1321d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1322d38ceaf9SAlex Deucher { 1323d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1324d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1325d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1326d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1327d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1328d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1329d38ceaf9SAlex Deucher int r; 1330d38ceaf9SAlex Deucher 1331aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1332d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1333d38ceaf9SAlex Deucher if (r < 0) 1334d38ceaf9SAlex Deucher return connector_status_disconnected; 1335aa0aad57SLukas Wunner } 1336d38ceaf9SAlex Deucher 1337d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1338d38ceaf9SAlex Deucher ret = connector->status; 1339d38ceaf9SAlex Deucher goto out; 1340d38ceaf9SAlex Deucher } 1341d38ceaf9SAlex Deucher 1342d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1343d38ceaf9SAlex Deucher 1344d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1345d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1346d38ceaf9SAlex Deucher if (encoder) { 1347d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1348d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1349d38ceaf9SAlex Deucher 1350d38ceaf9SAlex Deucher /* check if panel is valid */ 1351d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1352d38ceaf9SAlex Deucher ret = connector_status_connected; 1353d38ceaf9SAlex Deucher } 1354d38ceaf9SAlex Deucher /* eDP is always DP */ 1355d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1356d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1357d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1358d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1359d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1360d38ceaf9SAlex Deucher ret = connector_status_connected; 1361d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1362d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1363d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1364d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1365d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1366d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1367d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1368d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1369d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1370d38ceaf9SAlex Deucher 1371d38ceaf9SAlex Deucher if (encoder) { 1372d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1373d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1374d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1375e0b5b5ecSSamuel Li /* try DDC */ 1376e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1377d38ceaf9SAlex Deucher ret = connector_status_connected; 1378d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 137917b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1380d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1381d38ceaf9SAlex Deucher } 1382d38ceaf9SAlex Deucher } 1383d38ceaf9SAlex Deucher } else { 1384d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1385d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1386d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1387d38ceaf9SAlex Deucher ret = connector_status_connected; 1388d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1389d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1390d38ceaf9SAlex Deucher } else { 1391d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1392d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1393d38ceaf9SAlex Deucher ret = connector_status_connected; 1394d38ceaf9SAlex Deucher } else { 1395d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1396e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, 1397e0b5b5ecSSamuel Li false)) 1398d38ceaf9SAlex Deucher ret = connector_status_connected; 1399d38ceaf9SAlex Deucher } 1400d38ceaf9SAlex Deucher } 1401d38ceaf9SAlex Deucher } 1402d38ceaf9SAlex Deucher 1403d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1404d38ceaf9SAlex Deucher out: 1405aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1406d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1407d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1408aa0aad57SLukas Wunner } 1409d38ceaf9SAlex Deucher 1410d38ceaf9SAlex Deucher return ret; 1411d38ceaf9SAlex Deucher } 1412d38ceaf9SAlex Deucher 1413ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1414d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1415d38ceaf9SAlex Deucher { 1416d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1417d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1418d38ceaf9SAlex Deucher 1419d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1420d38ceaf9SAlex Deucher 1421d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1422d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1423d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1424d38ceaf9SAlex Deucher 1425d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1426d38ceaf9SAlex Deucher return MODE_PANEL; 1427d38ceaf9SAlex Deucher 1428d38ceaf9SAlex Deucher if (encoder) { 1429d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1430d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1431d38ceaf9SAlex Deucher 1432d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1433d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1434d38ceaf9SAlex Deucher */ 1435d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1436d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1437d38ceaf9SAlex Deucher return MODE_PANEL; 1438d38ceaf9SAlex Deucher 1439d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1440d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1441d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1442d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1443d38ceaf9SAlex Deucher return MODE_PANEL; 1444d38ceaf9SAlex Deucher } 1445d38ceaf9SAlex Deucher } 1446d38ceaf9SAlex Deucher return MODE_OK; 1447d38ceaf9SAlex Deucher } else { 1448d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1449d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1450d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1451d38ceaf9SAlex Deucher } else { 1452d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1453d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1454d38ceaf9SAlex Deucher if (mode->clock > 340000) 1455d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1456d38ceaf9SAlex Deucher } else { 1457d38ceaf9SAlex Deucher if (mode->clock > 165000) 1458d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1459d38ceaf9SAlex Deucher } 1460d38ceaf9SAlex Deucher } 1461d38ceaf9SAlex Deucher } 1462d38ceaf9SAlex Deucher 1463d38ceaf9SAlex Deucher return MODE_OK; 1464d38ceaf9SAlex Deucher } 1465d38ceaf9SAlex Deucher 1466d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1467d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1468d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1469d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1470d38ceaf9SAlex Deucher }; 1471d38ceaf9SAlex Deucher 1472d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1473d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1474d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1475d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1476d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 147740492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1478d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1479d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1480d38ceaf9SAlex Deucher }; 1481d38ceaf9SAlex Deucher 1482d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1483d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1484d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1485d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1486d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 148740492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1488d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1489d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1490d38ceaf9SAlex Deucher }; 1491d38ceaf9SAlex Deucher 1492d38ceaf9SAlex Deucher void 1493d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1494d38ceaf9SAlex Deucher uint32_t connector_id, 1495d38ceaf9SAlex Deucher uint32_t supported_device, 1496d38ceaf9SAlex Deucher int connector_type, 1497d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1498d38ceaf9SAlex Deucher uint16_t connector_object_id, 1499d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1500d38ceaf9SAlex Deucher struct amdgpu_router *router) 1501d38ceaf9SAlex Deucher { 1502d38ceaf9SAlex Deucher struct drm_device *dev = adev->ddev; 1503d38ceaf9SAlex Deucher struct drm_connector *connector; 1504d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1505d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1506d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1507d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1508d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1509d38ceaf9SAlex Deucher bool shared_ddc = false; 1510d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1511d38ceaf9SAlex Deucher bool has_aux = false; 1512d38ceaf9SAlex Deucher 1513d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1514d38ceaf9SAlex Deucher return; 1515d38ceaf9SAlex Deucher 1516d38ceaf9SAlex Deucher /* see if we already added it */ 1517d38ceaf9SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1518d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1519d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1520d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1521d38ceaf9SAlex Deucher return; 1522d38ceaf9SAlex Deucher } 1523d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1524d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1525d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1526d38ceaf9SAlex Deucher shared_ddc = true; 1527d38ceaf9SAlex Deucher } 1528d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1529d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1530d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1531d38ceaf9SAlex Deucher shared_ddc = false; 1532d38ceaf9SAlex Deucher } 1533d38ceaf9SAlex Deucher } 1534d38ceaf9SAlex Deucher } 1535d38ceaf9SAlex Deucher 1536d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1537d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1538d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1539d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1540d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1541d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1542d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1543d38ceaf9SAlex Deucher is_dp_bridge = true; 1544d38ceaf9SAlex Deucher break; 1545d38ceaf9SAlex Deucher default: 1546d38ceaf9SAlex Deucher break; 1547d38ceaf9SAlex Deucher } 1548d38ceaf9SAlex Deucher } 1549d38ceaf9SAlex Deucher } 1550d38ceaf9SAlex Deucher 1551d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1552d38ceaf9SAlex Deucher if (!amdgpu_connector) 1553d38ceaf9SAlex Deucher return; 1554d38ceaf9SAlex Deucher 1555d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1556d38ceaf9SAlex Deucher 1557d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1558d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1559d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1560d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1561d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1562d38ceaf9SAlex Deucher 1563d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1564d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1565d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1566d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1567d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1568d38ceaf9SAlex Deucher } 1569d38ceaf9SAlex Deucher 1570d38ceaf9SAlex Deucher if (is_dp_bridge) { 1571d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1572d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1573d38ceaf9SAlex Deucher goto failed; 1574d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1575d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1576d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1577d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1578d38ceaf9SAlex Deucher has_aux = true; 1579d38ceaf9SAlex Deucher else 1580d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1581d38ceaf9SAlex Deucher } 1582d38ceaf9SAlex Deucher switch (connector_type) { 1583d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1584d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1585d38ceaf9SAlex Deucher default: 1586d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1587d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1588d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1589d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1590d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1591d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1592d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1593d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1594d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1595d38ceaf9SAlex Deucher 1); 1596d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1597d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1598d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1599d38ceaf9SAlex Deucher break; 1600d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1601d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1602d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1603d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1604d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1605d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1606d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1607d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1608d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1609d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1610d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1611d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1612d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1613d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1614d38ceaf9SAlex Deucher 0); 1615d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1616d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1617d38ceaf9SAlex Deucher 0); 1618d38ceaf9SAlex Deucher 1619d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1620d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1621d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1622d38ceaf9SAlex Deucher 1623d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1624d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1625d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1626d38ceaf9SAlex Deucher 1627d38ceaf9SAlex Deucher if (amdgpu_audio != 0) 1628d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1629d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1630d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1631d38ceaf9SAlex Deucher 1632d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1633d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1634d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1635d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1636d38ceaf9SAlex Deucher else 1637d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1638d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1639d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1640d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1641d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1642d38ceaf9SAlex Deucher 1); 1643d38ceaf9SAlex Deucher } 1644d38ceaf9SAlex Deucher break; 1645d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1646d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1647d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1648d38ceaf9SAlex Deucher &amdgpu_connector_edp_funcs, connector_type); 1649d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1650d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1651d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1652d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1653d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1654d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1655d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1656d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1657d38ceaf9SAlex Deucher break; 1658d38ceaf9SAlex Deucher } 1659d38ceaf9SAlex Deucher } else { 1660d38ceaf9SAlex Deucher switch (connector_type) { 1661d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1662d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1663d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1664d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1665d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1666d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1667d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1668d38ceaf9SAlex Deucher } 1669d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1670d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1671d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1672d38ceaf9SAlex Deucher 1); 1673d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1674d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1675d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1676d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1677d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1678d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1679d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1680d38ceaf9SAlex Deucher break; 1681d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1682d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1683d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1684d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1685d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1686d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1687d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1688d38ceaf9SAlex Deucher } 1689d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1690d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1691d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1692d38ceaf9SAlex Deucher 1); 1693d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1694d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1695d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1696d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1697d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1698d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1699d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1700d38ceaf9SAlex Deucher break; 1701d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1702d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1703d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1704d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1705d38ceaf9SAlex Deucher goto failed; 1706d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1707d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1708d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1709d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1710d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1711d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1712d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1713d38ceaf9SAlex Deucher } 1714d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1715d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1716d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1717d38ceaf9SAlex Deucher 1); 1718d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1719d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1720d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1721d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1722d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1723d38ceaf9SAlex Deucher 0); 1724d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1725d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1726d38ceaf9SAlex Deucher 0); 1727d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1728d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1729d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1730d38ceaf9SAlex Deucher 1731d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1732d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1733d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1734d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1735d38ceaf9SAlex Deucher } 1736d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1737d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1738d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1739d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1740d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1741d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1742d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1743d38ceaf9SAlex Deucher 1); 1744d38ceaf9SAlex Deucher } 1745d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1746d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1747d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1748d38ceaf9SAlex Deucher else 1749d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1750d38ceaf9SAlex Deucher break; 1751d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1752d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1753d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1754d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1755d38ceaf9SAlex Deucher goto failed; 1756d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1757d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1758d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1759d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1760d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1761d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1762d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1763d38ceaf9SAlex Deucher } 1764d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1765d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1766d38ceaf9SAlex Deucher 1); 1767d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1768d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1769d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1770d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1771d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1772d38ceaf9SAlex Deucher 0); 1773d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1774d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1775d38ceaf9SAlex Deucher 0); 1776d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1777d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1778d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1779d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1780d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1781d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1782d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1783d38ceaf9SAlex Deucher } 1784d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1785d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1786d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1787d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1788d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1789d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1790d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1791d38ceaf9SAlex Deucher else 1792d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1793d38ceaf9SAlex Deucher break; 1794d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1795d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1796d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1797d38ceaf9SAlex Deucher goto failed; 1798d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1799d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1800d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1801d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1802d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1803d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1804d38ceaf9SAlex Deucher has_aux = true; 1805d38ceaf9SAlex Deucher else 1806d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1807d38ceaf9SAlex Deucher } 1808d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1809d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1810d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1811d38ceaf9SAlex Deucher 1); 1812d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1813d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1814d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1815d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1816d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1817d38ceaf9SAlex Deucher 0); 1818d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1819d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1820d38ceaf9SAlex Deucher 0); 1821d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1822d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1823d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1824d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1825d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1826d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1827d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1828d38ceaf9SAlex Deucher } 1829d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1830d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1831d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1832d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1833d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1834d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1835d38ceaf9SAlex Deucher break; 1836d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1837d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1838d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1839d38ceaf9SAlex Deucher goto failed; 1840d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1841d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1842d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1843d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1844d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1845d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1846d38ceaf9SAlex Deucher has_aux = true; 1847d38ceaf9SAlex Deucher else 1848d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1849d38ceaf9SAlex Deucher } 1850d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1851d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1852d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1853d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1854d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1855d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1856d38ceaf9SAlex Deucher break; 1857d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1858d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1859d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1860d38ceaf9SAlex Deucher goto failed; 1861d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1862d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1863d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1864d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1865d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1866d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1867d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1868d38ceaf9SAlex Deucher } 1869d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1870d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1871d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1872d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1873d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1874d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1875d38ceaf9SAlex Deucher break; 1876d38ceaf9SAlex Deucher } 1877d38ceaf9SAlex Deucher } 1878d38ceaf9SAlex Deucher 1879d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1880b636a1b3SLyude if (i2c_bus->valid) { 1881b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1882b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT; 1883b636a1b3SLyude } 1884d38ceaf9SAlex Deucher } else 1885d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 1886d38ceaf9SAlex Deucher 1887d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 1888d38ceaf9SAlex Deucher drm_connector_register(connector); 1889d38ceaf9SAlex Deucher 1890d38ceaf9SAlex Deucher if (has_aux) 1891d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 1892d38ceaf9SAlex Deucher 1893d38ceaf9SAlex Deucher return; 1894d38ceaf9SAlex Deucher 1895d38ceaf9SAlex Deucher failed: 1896d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 1897d38ceaf9SAlex Deucher kfree(connector); 1898d38ceaf9SAlex Deucher } 1899