1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher #include <drm/drmP.h> 27d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 28d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h> 29d38ceaf9SAlex Deucher #include <drm/drm_fb_helper.h> 30d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 31d38ceaf9SAlex Deucher #include "amdgpu.h" 32d38ceaf9SAlex Deucher #include "atom.h" 33d38ceaf9SAlex Deucher #include "atombios_encoders.h" 34d38ceaf9SAlex Deucher #include "atombios_dp.h" 35d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 36d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 37d38ceaf9SAlex Deucher 38d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 39d38ceaf9SAlex Deucher 40d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 41d38ceaf9SAlex Deucher { 42d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 43d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 44d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45d38ceaf9SAlex Deucher 46d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 47d38ceaf9SAlex Deucher * VGA, TV, etc. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50d38ceaf9SAlex Deucher return; 51d38ceaf9SAlex Deucher 52d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53d38ceaf9SAlex Deucher 54d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 55d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 56d38ceaf9SAlex Deucher return; 57d38ceaf9SAlex Deucher 58d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 59d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 61d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 62d38ceaf9SAlex Deucher 63d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 64d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65d38ceaf9SAlex Deucher return; 66d38ceaf9SAlex Deucher 67d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 68d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 70d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 71d38ceaf9SAlex Deucher */ 72d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73d38ceaf9SAlex Deucher int saved_dpms = connector->dpms; 74d38ceaf9SAlex Deucher /* Only turn off the display if it's physically disconnected */ 75d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77d38ceaf9SAlex Deucher } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78d38ceaf9SAlex Deucher /* set it to OFF so that drm_helper_connector_dpms() 79d38ceaf9SAlex Deucher * won't return immediately since the current state 80d38ceaf9SAlex Deucher * is ON at this point. 81d38ceaf9SAlex Deucher */ 82d38ceaf9SAlex Deucher connector->dpms = DRM_MODE_DPMS_OFF; 83d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 84d38ceaf9SAlex Deucher } 85d38ceaf9SAlex Deucher connector->dpms = saved_dpms; 86d38ceaf9SAlex Deucher } 87d38ceaf9SAlex Deucher } 88d38ceaf9SAlex Deucher } 89d38ceaf9SAlex Deucher 90d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 91d38ceaf9SAlex Deucher { 92d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 93d38ceaf9SAlex Deucher 94d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 95d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 96d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 97d38ceaf9SAlex Deucher } 98d38ceaf9SAlex Deucher } 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 101d38ceaf9SAlex Deucher { 102d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 103d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 104d38ceaf9SAlex Deucher int bpc = 8; 105d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock; 106d38ceaf9SAlex Deucher 107d38ceaf9SAlex Deucher switch (connector->connector_type) { 108d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 109d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 110d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 111d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 112d38ceaf9SAlex Deucher if (connector->display_info.bpc) 113d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 114d38ceaf9SAlex Deucher } 115d38ceaf9SAlex Deucher } 116d38ceaf9SAlex Deucher break; 117d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 118d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 119d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 120d38ceaf9SAlex Deucher if (connector->display_info.bpc) 121d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 122d38ceaf9SAlex Deucher } 123d38ceaf9SAlex Deucher break; 124d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 125d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 126d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 127d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 128d38ceaf9SAlex Deucher drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 129d38ceaf9SAlex Deucher if (connector->display_info.bpc) 130d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 131d38ceaf9SAlex Deucher } 132d38ceaf9SAlex Deucher break; 133d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 134d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 135d38ceaf9SAlex Deucher if (connector->display_info.bpc) 136d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 137d38ceaf9SAlex Deucher else { 138d38ceaf9SAlex Deucher struct drm_connector_helper_funcs *connector_funcs = 139d38ceaf9SAlex Deucher connector->helper_private; 140d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 141d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 142d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 143d38ceaf9SAlex Deucher 144d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 145d38ceaf9SAlex Deucher bpc = 6; 146d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 147d38ceaf9SAlex Deucher bpc = 8; 148d38ceaf9SAlex Deucher } 149d38ceaf9SAlex Deucher break; 150d38ceaf9SAlex Deucher } 151d38ceaf9SAlex Deucher 152d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 153d38ceaf9SAlex Deucher /* 154d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 155d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 156d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 157d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 158d38ceaf9SAlex Deucher */ 159d38ceaf9SAlex Deucher if (bpc > 12) { 160d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 161d38ceaf9SAlex Deucher connector->name, bpc); 162d38ceaf9SAlex Deucher bpc = 12; 163d38ceaf9SAlex Deucher } 164d38ceaf9SAlex Deucher 165d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 166d38ceaf9SAlex Deucher if (connector->max_tmds_clock > 0) { 167d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 168d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 169d38ceaf9SAlex Deucher 170d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 171d38ceaf9SAlex Deucher max_tmds_clock = connector->max_tmds_clock * 1000; 172d38ceaf9SAlex Deucher 173d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 174d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 175d38ceaf9SAlex Deucher 176d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 177d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 178d38ceaf9SAlex Deucher if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 179d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 180d38ceaf9SAlex Deucher bpc = 10; 181d38ceaf9SAlex Deucher else 182d38ceaf9SAlex Deucher bpc = 8; 183d38ceaf9SAlex Deucher 184d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 185d38ceaf9SAlex Deucher connector->name, bpc); 186d38ceaf9SAlex Deucher } 187d38ceaf9SAlex Deucher 188d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 189d38ceaf9SAlex Deucher bpc = 8; 190d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 191d38ceaf9SAlex Deucher connector->name, bpc); 192d38ceaf9SAlex Deucher } else if (bpc > 8) { 193d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 194d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 195d38ceaf9SAlex Deucher connector->name); 196d38ceaf9SAlex Deucher bpc = 8; 197d38ceaf9SAlex Deucher } 198d38ceaf9SAlex Deucher } 199d38ceaf9SAlex Deucher } 200d38ceaf9SAlex Deucher 201d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 202d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 203d38ceaf9SAlex Deucher connector->name); 204d38ceaf9SAlex Deucher bpc = 8; 205d38ceaf9SAlex Deucher } 206d38ceaf9SAlex Deucher 207d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 208d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 209d38ceaf9SAlex Deucher 210d38ceaf9SAlex Deucher return bpc; 211d38ceaf9SAlex Deucher } 212d38ceaf9SAlex Deucher 213d38ceaf9SAlex Deucher static void 214d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 215d38ceaf9SAlex Deucher enum drm_connector_status status) 216d38ceaf9SAlex Deucher { 217d38ceaf9SAlex Deucher struct drm_encoder *best_encoder = NULL; 218d38ceaf9SAlex Deucher struct drm_encoder *encoder = NULL; 219d38ceaf9SAlex Deucher struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 220d38ceaf9SAlex Deucher bool connected; 221d38ceaf9SAlex Deucher int i; 222d38ceaf9SAlex Deucher 223d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 224d38ceaf9SAlex Deucher 225d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 226d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 227d38ceaf9SAlex Deucher break; 228d38ceaf9SAlex Deucher 229d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 230d38ceaf9SAlex Deucher connector->encoder_ids[i]); 231d38ceaf9SAlex Deucher if (!encoder) 232d38ceaf9SAlex Deucher continue; 233d38ceaf9SAlex Deucher 234d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 235d38ceaf9SAlex Deucher connected = true; 236d38ceaf9SAlex Deucher else 237d38ceaf9SAlex Deucher connected = false; 238d38ceaf9SAlex Deucher 239d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 240d38ceaf9SAlex Deucher 241d38ceaf9SAlex Deucher } 242d38ceaf9SAlex Deucher } 243d38ceaf9SAlex Deucher 244d38ceaf9SAlex Deucher static struct drm_encoder * 245d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 246d38ceaf9SAlex Deucher int encoder_type) 247d38ceaf9SAlex Deucher { 248d38ceaf9SAlex Deucher struct drm_encoder *encoder; 249d38ceaf9SAlex Deucher int i; 250d38ceaf9SAlex Deucher 251d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 252d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 253d38ceaf9SAlex Deucher break; 254d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 255d38ceaf9SAlex Deucher connector->encoder_ids[i]); 256d38ceaf9SAlex Deucher if (!encoder) 257d38ceaf9SAlex Deucher continue; 258d38ceaf9SAlex Deucher 259d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 260d38ceaf9SAlex Deucher return encoder; 261d38ceaf9SAlex Deucher } 262d38ceaf9SAlex Deucher return NULL; 263d38ceaf9SAlex Deucher } 264d38ceaf9SAlex Deucher 265d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector) 266d38ceaf9SAlex Deucher { 267d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 268d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 269d38ceaf9SAlex Deucher 270d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 271d38ceaf9SAlex Deucher return amdgpu_connector->edid; 272d38ceaf9SAlex Deucher } else if (edid_blob) { 273d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 274d38ceaf9SAlex Deucher if (edid) 275d38ceaf9SAlex Deucher amdgpu_connector->edid = edid; 276d38ceaf9SAlex Deucher } 277d38ceaf9SAlex Deucher return amdgpu_connector->edid; 278d38ceaf9SAlex Deucher } 279d38ceaf9SAlex Deucher 280d38ceaf9SAlex Deucher static struct edid * 281d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 282d38ceaf9SAlex Deucher { 283d38ceaf9SAlex Deucher struct edid *edid; 284d38ceaf9SAlex Deucher 285d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 286d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 287d38ceaf9SAlex Deucher if (edid) { 288d38ceaf9SAlex Deucher memcpy((unsigned char *)edid, 289d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid, 290d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size); 291d38ceaf9SAlex Deucher return edid; 292d38ceaf9SAlex Deucher } 293d38ceaf9SAlex Deucher } 294d38ceaf9SAlex Deucher return NULL; 295d38ceaf9SAlex Deucher } 296d38ceaf9SAlex Deucher 297d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 298d38ceaf9SAlex Deucher { 299d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 300d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 301d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 302d38ceaf9SAlex Deucher 303d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 304d38ceaf9SAlex Deucher return; 305d38ceaf9SAlex Deucher 306d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 307d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 308d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 309d38ceaf9SAlex Deucher 310d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 311d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 312d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 313d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 314d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 315d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 316d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 317d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 318d38ceaf9SAlex Deucher 319d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 320d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 321d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 322d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 323d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 324d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 325d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 326d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 327d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 328d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 329d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 330d38ceaf9SAlex Deucher } 331d38ceaf9SAlex Deucher 332d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 333d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 334d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 335d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 336d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 337d38ceaf9SAlex Deucher } 338d38ceaf9SAlex Deucher } 339d38ceaf9SAlex Deucher 340d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 341d38ceaf9SAlex Deucher { 342d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 343d38ceaf9SAlex Deucher 344d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 345d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 346d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 347d38ceaf9SAlex Deucher } 348d38ceaf9SAlex Deucher } 349d38ceaf9SAlex Deucher 350d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 351d38ceaf9SAlex Deucher { 352d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 353d38ceaf9SAlex Deucher int ret; 354d38ceaf9SAlex Deucher 355d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 356d38ceaf9SAlex Deucher drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 357d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 358d38ceaf9SAlex Deucher drm_edid_to_eld(connector, amdgpu_connector->edid); 359d38ceaf9SAlex Deucher return ret; 360d38ceaf9SAlex Deucher } 361d38ceaf9SAlex Deucher drm_mode_connector_update_edid_property(connector, NULL); 362d38ceaf9SAlex Deucher return 0; 363d38ceaf9SAlex Deucher } 364d38ceaf9SAlex Deucher 365d38ceaf9SAlex Deucher static struct drm_encoder * 366d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 367d38ceaf9SAlex Deucher { 368d38ceaf9SAlex Deucher int enc_id = connector->encoder_ids[0]; 369d38ceaf9SAlex Deucher 370d38ceaf9SAlex Deucher /* pick the encoder ids */ 371d38ceaf9SAlex Deucher if (enc_id) 372d38ceaf9SAlex Deucher return drm_encoder_find(connector->dev, enc_id); 373d38ceaf9SAlex Deucher return NULL; 374d38ceaf9SAlex Deucher } 375d38ceaf9SAlex Deucher 376d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 377d38ceaf9SAlex Deucher { 378d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 379d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 380d38ceaf9SAlex Deucher 381d38ceaf9SAlex Deucher if (encoder == NULL) 382d38ceaf9SAlex Deucher return; 383d38ceaf9SAlex Deucher 384d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 385d38ceaf9SAlex Deucher 386d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 387d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 388d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 389d38ceaf9SAlex Deucher struct drm_display_mode, head); 390d38ceaf9SAlex Deucher 391d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 392d38ceaf9SAlex Deucher } else { 393d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 394d38ceaf9SAlex Deucher } 395d38ceaf9SAlex Deucher } 396d38ceaf9SAlex Deucher 397d38ceaf9SAlex Deucher static struct drm_display_mode * 398d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 399d38ceaf9SAlex Deucher { 400d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 401d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 402d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 403d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 404d38ceaf9SAlex Deucher 405d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 406d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 407d38ceaf9SAlex Deucher native_mode->clock != 0) { 408d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 409d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 410d38ceaf9SAlex Deucher drm_mode_set_name(mode); 411d38ceaf9SAlex Deucher 412d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 413d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 414d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 415d38ceaf9SAlex Deucher /* mac laptops without an edid */ 416d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 417d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 418d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 419d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 420d38ceaf9SAlex Deucher * simpler. 421d38ceaf9SAlex Deucher */ 422d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 423d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 424d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 425d38ceaf9SAlex Deucher } 426d38ceaf9SAlex Deucher return mode; 427d38ceaf9SAlex Deucher } 428d38ceaf9SAlex Deucher 429d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 430d38ceaf9SAlex Deucher struct drm_connector *connector) 431d38ceaf9SAlex Deucher { 432d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 433d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 434d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 435d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 436d38ceaf9SAlex Deucher int i; 437d38ceaf9SAlex Deucher struct mode_size { 438d38ceaf9SAlex Deucher int w; 439d38ceaf9SAlex Deucher int h; 440d38ceaf9SAlex Deucher } common_modes[17] = { 441d38ceaf9SAlex Deucher { 640, 480}, 442d38ceaf9SAlex Deucher { 720, 480}, 443d38ceaf9SAlex Deucher { 800, 600}, 444d38ceaf9SAlex Deucher { 848, 480}, 445d38ceaf9SAlex Deucher {1024, 768}, 446d38ceaf9SAlex Deucher {1152, 768}, 447d38ceaf9SAlex Deucher {1280, 720}, 448d38ceaf9SAlex Deucher {1280, 800}, 449d38ceaf9SAlex Deucher {1280, 854}, 450d38ceaf9SAlex Deucher {1280, 960}, 451d38ceaf9SAlex Deucher {1280, 1024}, 452d38ceaf9SAlex Deucher {1440, 900}, 453d38ceaf9SAlex Deucher {1400, 1050}, 454d38ceaf9SAlex Deucher {1680, 1050}, 455d38ceaf9SAlex Deucher {1600, 1200}, 456d38ceaf9SAlex Deucher {1920, 1080}, 457d38ceaf9SAlex Deucher {1920, 1200} 458d38ceaf9SAlex Deucher }; 459d38ceaf9SAlex Deucher 460d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 461d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 462d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 463d38ceaf9SAlex Deucher common_modes[i].h > 768) 464d38ceaf9SAlex Deucher continue; 465d38ceaf9SAlex Deucher } 466d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 467d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 468d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 469d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 470d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 471d38ceaf9SAlex Deucher continue; 472d38ceaf9SAlex Deucher } 473d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 474d38ceaf9SAlex Deucher continue; 475d38ceaf9SAlex Deucher 476d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 477d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 478d38ceaf9SAlex Deucher } 479d38ceaf9SAlex Deucher } 480d38ceaf9SAlex Deucher 481d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 482d38ceaf9SAlex Deucher struct drm_property *property, 483d38ceaf9SAlex Deucher uint64_t val) 484d38ceaf9SAlex Deucher { 485d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 486d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 487d38ceaf9SAlex Deucher struct drm_encoder *encoder; 488d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 489d38ceaf9SAlex Deucher 490d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 491d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 492d38ceaf9SAlex Deucher bool new_coherent_mode; 493d38ceaf9SAlex Deucher 494d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 495d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 496d38ceaf9SAlex Deucher if (!encoder) 497d38ceaf9SAlex Deucher return 0; 498d38ceaf9SAlex Deucher 499d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 500d38ceaf9SAlex Deucher 501d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 502d38ceaf9SAlex Deucher return 0; 503d38ceaf9SAlex Deucher 504d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 505d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 506d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 507d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 508d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 509d38ceaf9SAlex Deucher } 510d38ceaf9SAlex Deucher } 511d38ceaf9SAlex Deucher 512d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 513d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 514d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 515d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 516d38ceaf9SAlex Deucher if (!encoder) 517d38ceaf9SAlex Deucher return 0; 518d38ceaf9SAlex Deucher 519d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 520d38ceaf9SAlex Deucher 521d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 522d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 523d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 524d38ceaf9SAlex Deucher } 525d38ceaf9SAlex Deucher } 526d38ceaf9SAlex Deucher 527d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 528d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 529d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 530d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 531d38ceaf9SAlex Deucher if (!encoder) 532d38ceaf9SAlex Deucher return 0; 533d38ceaf9SAlex Deucher 534d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 535d38ceaf9SAlex Deucher 536d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 537d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 538d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 539d38ceaf9SAlex Deucher } 540d38ceaf9SAlex Deucher } 541d38ceaf9SAlex Deucher 542d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 543d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 544d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 545d38ceaf9SAlex Deucher if (!encoder) 546d38ceaf9SAlex Deucher return 0; 547d38ceaf9SAlex Deucher 548d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 549d38ceaf9SAlex Deucher 550d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 551d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 552d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 553d38ceaf9SAlex Deucher } 554d38ceaf9SAlex Deucher } 555d38ceaf9SAlex Deucher 556d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 557d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 558d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 559d38ceaf9SAlex Deucher if (!encoder) 560d38ceaf9SAlex Deucher return 0; 561d38ceaf9SAlex Deucher 562d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 563d38ceaf9SAlex Deucher 564d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 565d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 566d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 567d38ceaf9SAlex Deucher } 568d38ceaf9SAlex Deucher } 569d38ceaf9SAlex Deucher 570d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 571d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 572d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 573d38ceaf9SAlex Deucher if (!encoder) 574d38ceaf9SAlex Deucher return 0; 575d38ceaf9SAlex Deucher 576d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 577d38ceaf9SAlex Deucher 578d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 579d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 580d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 581d38ceaf9SAlex Deucher } 582d38ceaf9SAlex Deucher } 583d38ceaf9SAlex Deucher 584d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 585d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 586d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 587d38ceaf9SAlex Deucher 588d38ceaf9SAlex Deucher if (val == 0) 589d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 590d38ceaf9SAlex Deucher else 591d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 592d38ceaf9SAlex Deucher } 593d38ceaf9SAlex Deucher 594d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 595d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 596d38ceaf9SAlex Deucher 597d38ceaf9SAlex Deucher if (connector->encoder) { 598d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 599d38ceaf9SAlex Deucher } else { 600d38ceaf9SAlex Deucher struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 601d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 602d38ceaf9SAlex Deucher } 603d38ceaf9SAlex Deucher 604d38ceaf9SAlex Deucher switch (val) { 605d38ceaf9SAlex Deucher default: 606d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 607d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 608d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 609d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 610d38ceaf9SAlex Deucher } 611d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 612d38ceaf9SAlex Deucher return 0; 613d38ceaf9SAlex Deucher 614d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 615d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 616d38ceaf9SAlex Deucher return 0; 617d38ceaf9SAlex Deucher 618d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 619d38ceaf9SAlex Deucher 620d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 621d38ceaf9SAlex Deucher } 622d38ceaf9SAlex Deucher 623d38ceaf9SAlex Deucher return 0; 624d38ceaf9SAlex Deucher } 625d38ceaf9SAlex Deucher 626d38ceaf9SAlex Deucher static void 627d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 628d38ceaf9SAlex Deucher struct drm_connector *connector) 629d38ceaf9SAlex Deucher { 630d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 631d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 632d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 633d38ceaf9SAlex Deucher 634d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 635d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 636d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 637d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 638d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 639d38ceaf9SAlex Deucher memcpy(native_mode, mode, sizeof(*mode)); 640d38ceaf9SAlex Deucher } 641d38ceaf9SAlex Deucher } 642d38ceaf9SAlex Deucher 643d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 644d38ceaf9SAlex Deucher if (!native_mode->clock) { 645d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 646d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 647d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 648d38ceaf9SAlex Deucher *native_mode = *mode; 649d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 650d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 651d38ceaf9SAlex Deucher break; 652d38ceaf9SAlex Deucher } 653d38ceaf9SAlex Deucher } 654d38ceaf9SAlex Deucher } 655d38ceaf9SAlex Deucher 656d38ceaf9SAlex Deucher if (!native_mode->clock) { 657d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 658d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 659d38ceaf9SAlex Deucher } 660d38ceaf9SAlex Deucher } 661d38ceaf9SAlex Deucher 662d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 663d38ceaf9SAlex Deucher { 664d38ceaf9SAlex Deucher struct drm_encoder *encoder; 665d38ceaf9SAlex Deucher int ret = 0; 666d38ceaf9SAlex Deucher struct drm_display_mode *mode; 667d38ceaf9SAlex Deucher 668d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 669d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 670d38ceaf9SAlex Deucher if (ret > 0) { 671d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 672d38ceaf9SAlex Deucher if (encoder) { 673d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 674d38ceaf9SAlex Deucher /* add scaled modes */ 675d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 676d38ceaf9SAlex Deucher } 677d38ceaf9SAlex Deucher return ret; 678d38ceaf9SAlex Deucher } 679d38ceaf9SAlex Deucher 680d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 681d38ceaf9SAlex Deucher if (!encoder) 682d38ceaf9SAlex Deucher return 0; 683d38ceaf9SAlex Deucher 684d38ceaf9SAlex Deucher /* we have no EDID modes */ 685d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 686d38ceaf9SAlex Deucher if (mode) { 687d38ceaf9SAlex Deucher ret = 1; 688d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 689d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 690d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 691d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 692d38ceaf9SAlex Deucher /* add scaled modes */ 693d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 694d38ceaf9SAlex Deucher } 695d38ceaf9SAlex Deucher 696d38ceaf9SAlex Deucher return ret; 697d38ceaf9SAlex Deucher } 698d38ceaf9SAlex Deucher 699d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 700d38ceaf9SAlex Deucher struct drm_display_mode *mode) 701d38ceaf9SAlex Deucher { 702d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 703d38ceaf9SAlex Deucher 704d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 705d38ceaf9SAlex Deucher return MODE_PANEL; 706d38ceaf9SAlex Deucher 707d38ceaf9SAlex Deucher if (encoder) { 708d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 709d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 710d38ceaf9SAlex Deucher 711d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 712d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 713d38ceaf9SAlex Deucher */ 714d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 715d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 716d38ceaf9SAlex Deucher return MODE_PANEL; 717d38ceaf9SAlex Deucher 718d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 719d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 720d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 721d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 722d38ceaf9SAlex Deucher return MODE_PANEL; 723d38ceaf9SAlex Deucher } 724d38ceaf9SAlex Deucher } 725d38ceaf9SAlex Deucher 726d38ceaf9SAlex Deucher return MODE_OK; 727d38ceaf9SAlex Deucher } 728d38ceaf9SAlex Deucher 729d38ceaf9SAlex Deucher static enum drm_connector_status 730d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 731d38ceaf9SAlex Deucher { 732d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 733d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 734d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 735d38ceaf9SAlex Deucher int r; 736d38ceaf9SAlex Deucher 737d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 738d38ceaf9SAlex Deucher if (r < 0) 739d38ceaf9SAlex Deucher return connector_status_disconnected; 740d38ceaf9SAlex Deucher 741d38ceaf9SAlex Deucher if (encoder) { 742d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 743d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 744d38ceaf9SAlex Deucher 745d38ceaf9SAlex Deucher /* check if panel is valid */ 746d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 747d38ceaf9SAlex Deucher ret = connector_status_connected; 748d38ceaf9SAlex Deucher 749d38ceaf9SAlex Deucher } 750d38ceaf9SAlex Deucher 751d38ceaf9SAlex Deucher /* check for edid as well */ 752d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 753d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 754d38ceaf9SAlex Deucher ret = connector_status_connected; 755d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 756d38ceaf9SAlex Deucher 757d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 758d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 759d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 760d38ceaf9SAlex Deucher return ret; 761d38ceaf9SAlex Deucher } 762d38ceaf9SAlex Deucher 763d38ceaf9SAlex Deucher static void amdgpu_connector_destroy(struct drm_connector *connector) 764d38ceaf9SAlex Deucher { 765d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 766d38ceaf9SAlex Deucher 767d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->has_aux) 768d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 769d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 770d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 771d38ceaf9SAlex Deucher drm_connector_unregister(connector); 772d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 773d38ceaf9SAlex Deucher kfree(connector); 774d38ceaf9SAlex Deucher } 775d38ceaf9SAlex Deucher 776d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 777d38ceaf9SAlex Deucher struct drm_property *property, 778d38ceaf9SAlex Deucher uint64_t value) 779d38ceaf9SAlex Deucher { 780d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 781d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 782d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 783d38ceaf9SAlex Deucher 784d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 785d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 786d38ceaf9SAlex Deucher return 0; 787d38ceaf9SAlex Deucher 788d38ceaf9SAlex Deucher if (connector->encoder) 789d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 790d38ceaf9SAlex Deucher else { 791d38ceaf9SAlex Deucher struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 792d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 793d38ceaf9SAlex Deucher } 794d38ceaf9SAlex Deucher 795d38ceaf9SAlex Deucher switch (value) { 796d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 797d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 798d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 799d38ceaf9SAlex Deucher default: 800d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 801d38ceaf9SAlex Deucher } 802d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 803d38ceaf9SAlex Deucher return 0; 804d38ceaf9SAlex Deucher 805d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 806d38ceaf9SAlex Deucher 807d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 808d38ceaf9SAlex Deucher return 0; 809d38ceaf9SAlex Deucher } 810d38ceaf9SAlex Deucher 811d38ceaf9SAlex Deucher 812d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 813d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 814d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 815d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 816d38ceaf9SAlex Deucher }; 817d38ceaf9SAlex Deucher 818d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 819d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 820d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 821d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 822d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 823d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 824d38ceaf9SAlex Deucher }; 825d38ceaf9SAlex Deucher 826d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 827d38ceaf9SAlex Deucher { 828d38ceaf9SAlex Deucher int ret; 829d38ceaf9SAlex Deucher 830d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 831d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 832d38ceaf9SAlex Deucher 833d38ceaf9SAlex Deucher return ret; 834d38ceaf9SAlex Deucher } 835d38ceaf9SAlex Deucher 836d38ceaf9SAlex Deucher static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 837d38ceaf9SAlex Deucher struct drm_display_mode *mode) 838d38ceaf9SAlex Deucher { 839d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 840d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 841d38ceaf9SAlex Deucher 842d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 843d38ceaf9SAlex Deucher 844d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 845d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 846d38ceaf9SAlex Deucher 847d38ceaf9SAlex Deucher return MODE_OK; 848d38ceaf9SAlex Deucher } 849d38ceaf9SAlex Deucher 850d38ceaf9SAlex Deucher static enum drm_connector_status 851d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 852d38ceaf9SAlex Deucher { 853d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 854d38ceaf9SAlex Deucher struct drm_encoder *encoder; 855d38ceaf9SAlex Deucher struct drm_encoder_helper_funcs *encoder_funcs; 856d38ceaf9SAlex Deucher bool dret = false; 857d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 858d38ceaf9SAlex Deucher int r; 859d38ceaf9SAlex Deucher 860d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 861d38ceaf9SAlex Deucher if (r < 0) 862d38ceaf9SAlex Deucher return connector_status_disconnected; 863d38ceaf9SAlex Deucher 864d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 865d38ceaf9SAlex Deucher if (!encoder) 866d38ceaf9SAlex Deucher ret = connector_status_disconnected; 867d38ceaf9SAlex Deucher 868d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 869d38ceaf9SAlex Deucher dret = amdgpu_ddc_probe(amdgpu_connector, false); 870d38ceaf9SAlex Deucher if (dret) { 871d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 872d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 873d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 874d38ceaf9SAlex Deucher 875d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 876d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 877d38ceaf9SAlex Deucher connector->name); 878d38ceaf9SAlex Deucher ret = connector_status_connected; 879d38ceaf9SAlex Deucher } else { 880d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 881d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 882d38ceaf9SAlex Deucher 883d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 884d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 885d38ceaf9SAlex Deucher */ 886d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 887d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 888d38ceaf9SAlex Deucher ret = connector_status_disconnected; 889d38ceaf9SAlex Deucher } else { 890d38ceaf9SAlex Deucher ret = connector_status_connected; 891d38ceaf9SAlex Deucher } 892d38ceaf9SAlex Deucher } 893d38ceaf9SAlex Deucher } else { 894d38ceaf9SAlex Deucher 895d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 896d38ceaf9SAlex Deucher if (!force) { 897d38ceaf9SAlex Deucher /* only return the previous status if we last 898d38ceaf9SAlex Deucher * detected a monitor via load. 899d38ceaf9SAlex Deucher */ 900d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 901d38ceaf9SAlex Deucher ret = connector->status; 902d38ceaf9SAlex Deucher goto out; 903d38ceaf9SAlex Deucher } 904d38ceaf9SAlex Deucher 905d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 906d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 907d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 908d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 909d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 910d38ceaf9SAlex Deucher } 911d38ceaf9SAlex Deucher } 912d38ceaf9SAlex Deucher 913d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 914d38ceaf9SAlex Deucher 915d38ceaf9SAlex Deucher out: 916d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 917d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 918d38ceaf9SAlex Deucher 919d38ceaf9SAlex Deucher return ret; 920d38ceaf9SAlex Deucher } 921d38ceaf9SAlex Deucher 922d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 923d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 924d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 925d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 926d38ceaf9SAlex Deucher }; 927d38ceaf9SAlex Deucher 928d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 929d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 930d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 931d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 932d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 933d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 934d38ceaf9SAlex Deucher }; 935d38ceaf9SAlex Deucher 936d38ceaf9SAlex Deucher static bool 937d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 938d38ceaf9SAlex Deucher { 939d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 940d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 941d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 942d38ceaf9SAlex Deucher enum drm_connector_status status; 943d38ceaf9SAlex Deucher 944d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 945d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 946d38ceaf9SAlex Deucher status = connector_status_connected; 947d38ceaf9SAlex Deucher else 948d38ceaf9SAlex Deucher status = connector_status_disconnected; 949d38ceaf9SAlex Deucher if (connector->status == status) 950d38ceaf9SAlex Deucher return true; 951d38ceaf9SAlex Deucher } 952d38ceaf9SAlex Deucher 953d38ceaf9SAlex Deucher return false; 954d38ceaf9SAlex Deucher } 955d38ceaf9SAlex Deucher 956d38ceaf9SAlex Deucher /* 957d38ceaf9SAlex Deucher * DVI is complicated 958d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 959d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 960d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 961d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 962d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 963d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 964d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 965d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 966d38ceaf9SAlex Deucher */ 967d38ceaf9SAlex Deucher static enum drm_connector_status 968d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 969d38ceaf9SAlex Deucher { 970d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 971d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 972d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 973d38ceaf9SAlex Deucher struct drm_encoder *encoder = NULL; 974d38ceaf9SAlex Deucher struct drm_encoder_helper_funcs *encoder_funcs; 975d38ceaf9SAlex Deucher int i, r; 976d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 977d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 978d38ceaf9SAlex Deucher 979d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 980d38ceaf9SAlex Deucher if (r < 0) 981d38ceaf9SAlex Deucher return connector_status_disconnected; 982d38ceaf9SAlex Deucher 983d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 984d38ceaf9SAlex Deucher ret = connector->status; 985d38ceaf9SAlex Deucher goto exit; 986d38ceaf9SAlex Deucher } 987d38ceaf9SAlex Deucher 988d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 989d38ceaf9SAlex Deucher dret = amdgpu_ddc_probe(amdgpu_connector, false); 990d38ceaf9SAlex Deucher if (dret) { 991d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 992d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 993d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 994d38ceaf9SAlex Deucher 995d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 996d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 997d38ceaf9SAlex Deucher connector->name); 998d38ceaf9SAlex Deucher ret = connector_status_connected; 999d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1000d38ceaf9SAlex Deucher } else { 1001d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1002d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1003d38ceaf9SAlex Deucher 1004d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1005d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1006d38ceaf9SAlex Deucher */ 1007d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1008d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1009d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1010d38ceaf9SAlex Deucher } else { 1011d38ceaf9SAlex Deucher ret = connector_status_connected; 1012d38ceaf9SAlex Deucher } 1013d38ceaf9SAlex Deucher 1014d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1015d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1016d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1017d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1018d38ceaf9SAlex Deucher */ 1019d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1020d38ceaf9SAlex Deucher struct drm_connector *list_connector; 1021d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector; 1022d38ceaf9SAlex Deucher list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1023d38ceaf9SAlex Deucher if (connector == list_connector) 1024d38ceaf9SAlex Deucher continue; 1025d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector); 1026d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc && 1027d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1028d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) { 1029d38ceaf9SAlex Deucher /* cases where both connectors are digital */ 1030d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1031d38ceaf9SAlex Deucher /* hpd is our only option in this case */ 1032d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1033d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1034d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1035d38ceaf9SAlex Deucher } 1036d38ceaf9SAlex Deucher } 1037d38ceaf9SAlex Deucher } 1038d38ceaf9SAlex Deucher } 1039d38ceaf9SAlex Deucher } 1040d38ceaf9SAlex Deucher } 1041d38ceaf9SAlex Deucher } 1042d38ceaf9SAlex Deucher 1043d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1044d38ceaf9SAlex Deucher goto out; 1045d38ceaf9SAlex Deucher 1046d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1047d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1048d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1049d38ceaf9SAlex Deucher goto out; 1050d38ceaf9SAlex Deucher 1051d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1052d38ceaf9SAlex Deucher if (!force) { 1053d38ceaf9SAlex Deucher /* only return the previous status if we last 1054d38ceaf9SAlex Deucher * detected a monitor via load. 1055d38ceaf9SAlex Deucher */ 1056d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1057d38ceaf9SAlex Deucher ret = connector->status; 1058d38ceaf9SAlex Deucher goto out; 1059d38ceaf9SAlex Deucher } 1060d38ceaf9SAlex Deucher 1061d38ceaf9SAlex Deucher /* find analog encoder */ 1062d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 1063d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1064d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1065d38ceaf9SAlex Deucher break; 1066d38ceaf9SAlex Deucher 1067d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1068d38ceaf9SAlex Deucher if (!encoder) 1069d38ceaf9SAlex Deucher continue; 1070d38ceaf9SAlex Deucher 1071d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1072d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1073d38ceaf9SAlex Deucher continue; 1074d38ceaf9SAlex Deucher 1075d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1076d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1077d38ceaf9SAlex Deucher if (!broken_edid) { 1078d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1079d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1080d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1081d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1082d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1083d38ceaf9SAlex Deucher } 1084d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1085d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1086d38ceaf9SAlex Deucher } 1087d38ceaf9SAlex Deucher } else { 1088d38ceaf9SAlex Deucher enum drm_connector_status lret; 1089d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1090d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1091d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1092d38ceaf9SAlex Deucher DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1093d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1094d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1095d38ceaf9SAlex Deucher } 1096d38ceaf9SAlex Deucher break; 1097d38ceaf9SAlex Deucher } 1098d38ceaf9SAlex Deucher } 1099d38ceaf9SAlex Deucher } 1100d38ceaf9SAlex Deucher 1101d38ceaf9SAlex Deucher out: 1102d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1103d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1104d38ceaf9SAlex Deucher 1105d38ceaf9SAlex Deucher exit: 1106d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1107d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1108d38ceaf9SAlex Deucher 1109d38ceaf9SAlex Deucher return ret; 1110d38ceaf9SAlex Deucher } 1111d38ceaf9SAlex Deucher 1112d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1113d38ceaf9SAlex Deucher static struct drm_encoder * 1114d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1115d38ceaf9SAlex Deucher { 1116d38ceaf9SAlex Deucher int enc_id = connector->encoder_ids[0]; 1117d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1118d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1119d38ceaf9SAlex Deucher int i; 1120d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1121d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1122d38ceaf9SAlex Deucher break; 1123d38ceaf9SAlex Deucher 1124d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1125d38ceaf9SAlex Deucher if (!encoder) 1126d38ceaf9SAlex Deucher continue; 1127d38ceaf9SAlex Deucher 1128d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1129d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1130d38ceaf9SAlex Deucher return encoder; 1131d38ceaf9SAlex Deucher } else { 1132d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1133d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1134d38ceaf9SAlex Deucher return encoder; 1135d38ceaf9SAlex Deucher } 1136d38ceaf9SAlex Deucher } 1137d38ceaf9SAlex Deucher 1138d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1139d38ceaf9SAlex Deucher 1140d38ceaf9SAlex Deucher /* then check use digitial */ 1141d38ceaf9SAlex Deucher /* pick the first one */ 1142d38ceaf9SAlex Deucher if (enc_id) 1143d38ceaf9SAlex Deucher return drm_encoder_find(connector->dev, enc_id); 1144d38ceaf9SAlex Deucher return NULL; 1145d38ceaf9SAlex Deucher } 1146d38ceaf9SAlex Deucher 1147d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1148d38ceaf9SAlex Deucher { 1149d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1150d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1151d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1152d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1153d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1154d38ceaf9SAlex Deucher } 1155d38ceaf9SAlex Deucher 1156d38ceaf9SAlex Deucher static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1157d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1158d38ceaf9SAlex Deucher { 1159d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1160d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1161d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1162d38ceaf9SAlex Deucher 1163d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1164d38ceaf9SAlex Deucher 1165d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1166d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1167d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1168d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1169d38ceaf9SAlex Deucher return MODE_OK; 1170d38ceaf9SAlex Deucher } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1171d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1172d38ceaf9SAlex Deucher if (mode->clock > 340000) 1173d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1174d38ceaf9SAlex Deucher else 1175d38ceaf9SAlex Deucher return MODE_OK; 1176d38ceaf9SAlex Deucher } else { 1177d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1178d38ceaf9SAlex Deucher } 1179d38ceaf9SAlex Deucher } 1180d38ceaf9SAlex Deucher 1181d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1182d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1183d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1184d38ceaf9SAlex Deucher 1185d38ceaf9SAlex Deucher return MODE_OK; 1186d38ceaf9SAlex Deucher } 1187d38ceaf9SAlex Deucher 1188d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1189d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1190d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1191d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1192d38ceaf9SAlex Deucher }; 1193d38ceaf9SAlex Deucher 1194d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1195d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1196d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1197d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1198d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 1199d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1200d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1201d38ceaf9SAlex Deucher }; 1202d38ceaf9SAlex Deucher 1203d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1204d38ceaf9SAlex Deucher { 1205d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1206d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1207d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1208d38ceaf9SAlex Deucher int ret; 1209d38ceaf9SAlex Deucher 1210d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1211d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1212d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1213d38ceaf9SAlex Deucher 1214d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1215d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1216d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1217d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1218d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1219d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1220d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1221d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1222d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1223d38ceaf9SAlex Deucher } else { 1224d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1225d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1226d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1227d38ceaf9SAlex Deucher if (encoder) 1228d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1229d38ceaf9SAlex Deucher } 1230d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1231d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1232d38ceaf9SAlex Deucher } 1233d38ceaf9SAlex Deucher 1234d38ceaf9SAlex Deucher if (ret > 0) { 1235d38ceaf9SAlex Deucher if (encoder) { 1236d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1237d38ceaf9SAlex Deucher /* add scaled modes */ 1238d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1239d38ceaf9SAlex Deucher } 1240d38ceaf9SAlex Deucher return ret; 1241d38ceaf9SAlex Deucher } 1242d38ceaf9SAlex Deucher 1243d38ceaf9SAlex Deucher if (!encoder) 1244d38ceaf9SAlex Deucher return 0; 1245d38ceaf9SAlex Deucher 1246d38ceaf9SAlex Deucher /* we have no EDID modes */ 1247d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1248d38ceaf9SAlex Deucher if (mode) { 1249d38ceaf9SAlex Deucher ret = 1; 1250d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1251d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1252d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1253d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1254d38ceaf9SAlex Deucher /* add scaled modes */ 1255d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1256d38ceaf9SAlex Deucher } 1257d38ceaf9SAlex Deucher } else { 1258d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1259d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1260d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1261d38ceaf9SAlex Deucher if (encoder) 1262d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1263d38ceaf9SAlex Deucher } 1264d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1265d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1266d38ceaf9SAlex Deucher 1267d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1268d38ceaf9SAlex Deucher } 1269d38ceaf9SAlex Deucher 1270d38ceaf9SAlex Deucher return ret; 1271d38ceaf9SAlex Deucher } 1272d38ceaf9SAlex Deucher 1273d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1274d38ceaf9SAlex Deucher { 1275d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1276d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1277d38ceaf9SAlex Deucher int i; 1278d38ceaf9SAlex Deucher 1279d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1280d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1281d38ceaf9SAlex Deucher break; 1282d38ceaf9SAlex Deucher 1283d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 1284d38ceaf9SAlex Deucher connector->encoder_ids[i]); 1285d38ceaf9SAlex Deucher if (!encoder) 1286d38ceaf9SAlex Deucher continue; 1287d38ceaf9SAlex Deucher 1288d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1289d38ceaf9SAlex Deucher 1290d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1291d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1292d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1293d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1294d38ceaf9SAlex Deucher default: 1295d38ceaf9SAlex Deucher break; 1296d38ceaf9SAlex Deucher } 1297d38ceaf9SAlex Deucher } 1298d38ceaf9SAlex Deucher 1299d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1300d38ceaf9SAlex Deucher } 1301d38ceaf9SAlex Deucher 1302d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1303d38ceaf9SAlex Deucher { 1304d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1305d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1306d38ceaf9SAlex Deucher int i; 1307d38ceaf9SAlex Deucher bool found = false; 1308d38ceaf9SAlex Deucher 1309d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1310d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1311d38ceaf9SAlex Deucher break; 1312d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 1313d38ceaf9SAlex Deucher connector->encoder_ids[i]); 1314d38ceaf9SAlex Deucher if (!encoder) 1315d38ceaf9SAlex Deucher continue; 1316d38ceaf9SAlex Deucher 1317d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1318d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1319d38ceaf9SAlex Deucher found = true; 1320d38ceaf9SAlex Deucher } 1321d38ceaf9SAlex Deucher 1322d38ceaf9SAlex Deucher return found; 1323d38ceaf9SAlex Deucher } 1324d38ceaf9SAlex Deucher 1325d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1326d38ceaf9SAlex Deucher { 1327d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1328d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1329d38ceaf9SAlex Deucher 1330d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1331d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1332d38ceaf9SAlex Deucher return true; 1333d38ceaf9SAlex Deucher } 1334d38ceaf9SAlex Deucher 1335d38ceaf9SAlex Deucher return false; 1336d38ceaf9SAlex Deucher } 1337d38ceaf9SAlex Deucher 1338d38ceaf9SAlex Deucher static enum drm_connector_status 1339d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1340d38ceaf9SAlex Deucher { 1341d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1342d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1343d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1344d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1345d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1346d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1347d38ceaf9SAlex Deucher int r; 1348d38ceaf9SAlex Deucher 1349d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1350d38ceaf9SAlex Deucher if (r < 0) 1351d38ceaf9SAlex Deucher return connector_status_disconnected; 1352d38ceaf9SAlex Deucher 1353d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1354d38ceaf9SAlex Deucher ret = connector->status; 1355d38ceaf9SAlex Deucher goto out; 1356d38ceaf9SAlex Deucher } 1357d38ceaf9SAlex Deucher 1358d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1359d38ceaf9SAlex Deucher 1360d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1361d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1362d38ceaf9SAlex Deucher if (encoder) { 1363d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1364d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1365d38ceaf9SAlex Deucher 1366d38ceaf9SAlex Deucher /* check if panel is valid */ 1367d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1368d38ceaf9SAlex Deucher ret = connector_status_connected; 1369d38ceaf9SAlex Deucher } 1370d38ceaf9SAlex Deucher /* eDP is always DP */ 1371d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1372d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1373d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1374d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1375d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1376d38ceaf9SAlex Deucher ret = connector_status_connected; 1377d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1378d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1379d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1380d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1381d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1382d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1383d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1384d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1385d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1386d38ceaf9SAlex Deucher 1387d38ceaf9SAlex Deucher if (encoder) { 1388d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1389d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1390d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1391d38ceaf9SAlex Deucher if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1392d38ceaf9SAlex Deucher ret = connector_status_connected; 1393d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1394d38ceaf9SAlex Deucher struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1395d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1396d38ceaf9SAlex Deucher } 1397d38ceaf9SAlex Deucher } 1398d38ceaf9SAlex Deucher } else { 1399d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1400d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1401d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1402d38ceaf9SAlex Deucher ret = connector_status_connected; 1403d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1404d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1405d38ceaf9SAlex Deucher } else { 1406d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1407d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1408d38ceaf9SAlex Deucher ret = connector_status_connected; 1409d38ceaf9SAlex Deucher } else { 1410d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1411d38ceaf9SAlex Deucher if (amdgpu_ddc_probe(amdgpu_connector, false)) 1412d38ceaf9SAlex Deucher ret = connector_status_connected; 1413d38ceaf9SAlex Deucher } 1414d38ceaf9SAlex Deucher } 1415d38ceaf9SAlex Deucher } 1416d38ceaf9SAlex Deucher 1417d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1418d38ceaf9SAlex Deucher out: 1419d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1420d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1421d38ceaf9SAlex Deucher 1422d38ceaf9SAlex Deucher return ret; 1423d38ceaf9SAlex Deucher } 1424d38ceaf9SAlex Deucher 1425d38ceaf9SAlex Deucher static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1426d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1427d38ceaf9SAlex Deucher { 1428d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1429d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1430d38ceaf9SAlex Deucher 1431d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1432d38ceaf9SAlex Deucher 1433d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1434d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1435d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1436d38ceaf9SAlex Deucher 1437d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1438d38ceaf9SAlex Deucher return MODE_PANEL; 1439d38ceaf9SAlex Deucher 1440d38ceaf9SAlex Deucher if (encoder) { 1441d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1442d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1443d38ceaf9SAlex Deucher 1444d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1445d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1446d38ceaf9SAlex Deucher */ 1447d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1448d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1449d38ceaf9SAlex Deucher return MODE_PANEL; 1450d38ceaf9SAlex Deucher 1451d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1452d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1453d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1454d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1455d38ceaf9SAlex Deucher return MODE_PANEL; 1456d38ceaf9SAlex Deucher } 1457d38ceaf9SAlex Deucher } 1458d38ceaf9SAlex Deucher return MODE_OK; 1459d38ceaf9SAlex Deucher } else { 1460d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1461d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1462d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1463d38ceaf9SAlex Deucher } else { 1464d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1465d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1466d38ceaf9SAlex Deucher if (mode->clock > 340000) 1467d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1468d38ceaf9SAlex Deucher } else { 1469d38ceaf9SAlex Deucher if (mode->clock > 165000) 1470d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1471d38ceaf9SAlex Deucher } 1472d38ceaf9SAlex Deucher } 1473d38ceaf9SAlex Deucher } 1474d38ceaf9SAlex Deucher 1475d38ceaf9SAlex Deucher return MODE_OK; 1476d38ceaf9SAlex Deucher } 1477d38ceaf9SAlex Deucher 1478d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1479d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1480d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1481d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1482d38ceaf9SAlex Deucher }; 1483d38ceaf9SAlex Deucher 1484d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1485d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1486d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1487d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1488d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 1489d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1490d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1491d38ceaf9SAlex Deucher }; 1492d38ceaf9SAlex Deucher 1493d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1494d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1495d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1496d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1497d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 1498d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1499d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1500d38ceaf9SAlex Deucher }; 1501d38ceaf9SAlex Deucher 1502d38ceaf9SAlex Deucher void 1503d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1504d38ceaf9SAlex Deucher uint32_t connector_id, 1505d38ceaf9SAlex Deucher uint32_t supported_device, 1506d38ceaf9SAlex Deucher int connector_type, 1507d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1508d38ceaf9SAlex Deucher uint16_t connector_object_id, 1509d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1510d38ceaf9SAlex Deucher struct amdgpu_router *router) 1511d38ceaf9SAlex Deucher { 1512d38ceaf9SAlex Deucher struct drm_device *dev = adev->ddev; 1513d38ceaf9SAlex Deucher struct drm_connector *connector; 1514d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1515d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1516d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1517d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1518d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1519d38ceaf9SAlex Deucher bool shared_ddc = false; 1520d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1521d38ceaf9SAlex Deucher bool has_aux = false; 1522d38ceaf9SAlex Deucher 1523d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1524d38ceaf9SAlex Deucher return; 1525d38ceaf9SAlex Deucher 1526d38ceaf9SAlex Deucher /* see if we already added it */ 1527d38ceaf9SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1528d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1529d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1530d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1531d38ceaf9SAlex Deucher return; 1532d38ceaf9SAlex Deucher } 1533d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1534d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1535d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1536d38ceaf9SAlex Deucher shared_ddc = true; 1537d38ceaf9SAlex Deucher } 1538d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1539d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1540d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1541d38ceaf9SAlex Deucher shared_ddc = false; 1542d38ceaf9SAlex Deucher } 1543d38ceaf9SAlex Deucher } 1544d38ceaf9SAlex Deucher } 1545d38ceaf9SAlex Deucher 1546d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1547d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1548d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1549d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1550d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1551d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1552d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1553d38ceaf9SAlex Deucher is_dp_bridge = true; 1554d38ceaf9SAlex Deucher break; 1555d38ceaf9SAlex Deucher default: 1556d38ceaf9SAlex Deucher break; 1557d38ceaf9SAlex Deucher } 1558d38ceaf9SAlex Deucher } 1559d38ceaf9SAlex Deucher } 1560d38ceaf9SAlex Deucher 1561d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1562d38ceaf9SAlex Deucher if (!amdgpu_connector) 1563d38ceaf9SAlex Deucher return; 1564d38ceaf9SAlex Deucher 1565d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1566d38ceaf9SAlex Deucher 1567d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1568d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1569d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1570d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1571d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1572d38ceaf9SAlex Deucher 1573d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1574d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1575d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1576d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1577d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1578d38ceaf9SAlex Deucher } 1579d38ceaf9SAlex Deucher 1580d38ceaf9SAlex Deucher if (is_dp_bridge) { 1581d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1582d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1583d38ceaf9SAlex Deucher goto failed; 1584d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1585d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1586d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1587d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1588d38ceaf9SAlex Deucher has_aux = true; 1589d38ceaf9SAlex Deucher else 1590d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1591d38ceaf9SAlex Deucher } 1592d38ceaf9SAlex Deucher switch (connector_type) { 1593d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1594d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1595d38ceaf9SAlex Deucher default: 1596d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1597d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1598d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1599d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1600d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1601d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1602d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1603d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1604d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1605d38ceaf9SAlex Deucher 1); 1606d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1607d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1608d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1609d38ceaf9SAlex Deucher break; 1610d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1611d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1612d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1613d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1614d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1615d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1616d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1617d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1618d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1619d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1620d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1621d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1622d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1623d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1624d38ceaf9SAlex Deucher 0); 1625d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1626d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1627d38ceaf9SAlex Deucher 0); 1628d38ceaf9SAlex Deucher 1629d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1630d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1631d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1632d38ceaf9SAlex Deucher 1633d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1634d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1635d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1636d38ceaf9SAlex Deucher 1637d38ceaf9SAlex Deucher if (amdgpu_audio != 0) 1638d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1639d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1640d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1641d38ceaf9SAlex Deucher 1642d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1643d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1644d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1645d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1646d38ceaf9SAlex Deucher else 1647d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1648d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1649d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1650d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1651d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1652d38ceaf9SAlex Deucher 1); 1653d38ceaf9SAlex Deucher } 1654d38ceaf9SAlex Deucher break; 1655d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1656d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1657d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1658d38ceaf9SAlex Deucher &amdgpu_connector_edp_funcs, connector_type); 1659d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1660d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1661d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1662d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1663d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1664d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1665d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1666d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1667d38ceaf9SAlex Deucher break; 1668d38ceaf9SAlex Deucher } 1669d38ceaf9SAlex Deucher } else { 1670d38ceaf9SAlex Deucher switch (connector_type) { 1671d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1672d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1673d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1674d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1675d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1676d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1677d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1678d38ceaf9SAlex Deucher } 1679d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1680d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1681d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1682d38ceaf9SAlex Deucher 1); 1683d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1684d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1685d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1686d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1687d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1688d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1689d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1690d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1691d38ceaf9SAlex Deucher break; 1692d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1693d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1694d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1695d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1696d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1697d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1698d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1699d38ceaf9SAlex Deucher } 1700d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1701d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1702d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1703d38ceaf9SAlex Deucher 1); 1704d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1705d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1706d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1707d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1708d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1709d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1710d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1711d38ceaf9SAlex Deucher break; 1712d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1713d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1714d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1715d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1716d38ceaf9SAlex Deucher goto failed; 1717d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1718d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1719d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1720d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1721d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1722d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1723d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1724d38ceaf9SAlex Deucher } 1725d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1726d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1727d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1728d38ceaf9SAlex Deucher 1); 1729d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1730d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1731d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1732d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1733d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1734d38ceaf9SAlex Deucher 0); 1735d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1736d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1737d38ceaf9SAlex Deucher 0); 1738d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1739d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1740d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1741d38ceaf9SAlex Deucher 1742d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1743d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1744d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1745d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1746d38ceaf9SAlex Deucher } 1747d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1748d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1749d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1750d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1751d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1752d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1753d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1754d38ceaf9SAlex Deucher 1); 1755d38ceaf9SAlex Deucher } 1756d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1757d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1758d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1759d38ceaf9SAlex Deucher else 1760d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1761d38ceaf9SAlex Deucher break; 1762d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1763d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1764d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1765d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1766d38ceaf9SAlex Deucher goto failed; 1767d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1768d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1769d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1770d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1771d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1772d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1773d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1774d38ceaf9SAlex Deucher } 1775d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1776d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1777d38ceaf9SAlex Deucher 1); 1778d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1779d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1780d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1781d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1782d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1783d38ceaf9SAlex Deucher 0); 1784d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1785d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1786d38ceaf9SAlex Deucher 0); 1787d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1788d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1789d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1790d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1791d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1792d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1793d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1794d38ceaf9SAlex Deucher } 1795d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1796d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1797d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1798d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1799d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1800d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1801d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1802d38ceaf9SAlex Deucher else 1803d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1804d38ceaf9SAlex Deucher break; 1805d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1806d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1807d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1808d38ceaf9SAlex Deucher goto failed; 1809d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1810d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1811d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1812d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1813d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1814d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1815d38ceaf9SAlex Deucher has_aux = true; 1816d38ceaf9SAlex Deucher else 1817d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1818d38ceaf9SAlex Deucher } 1819d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1820d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1821d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1822d38ceaf9SAlex Deucher 1); 1823d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1824d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1825d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1826d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1827d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1828d38ceaf9SAlex Deucher 0); 1829d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1830d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1831d38ceaf9SAlex Deucher 0); 1832d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1833d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1834d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1835d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1836d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1837d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1838d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1839d38ceaf9SAlex Deucher } 1840d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1841d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1842d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1843d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1844d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1845d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1846d38ceaf9SAlex Deucher break; 1847d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1848d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1849d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1850d38ceaf9SAlex Deucher goto failed; 1851d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1852d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1853d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1854d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1855d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1856d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1857d38ceaf9SAlex Deucher has_aux = true; 1858d38ceaf9SAlex Deucher else 1859d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1860d38ceaf9SAlex Deucher } 1861d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1862d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1863d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1864d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1865d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1866d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1867d38ceaf9SAlex Deucher break; 1868d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1869d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1870d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1871d38ceaf9SAlex Deucher goto failed; 1872d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1873d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1874d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1875d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1876d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1877d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1878d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1879d38ceaf9SAlex Deucher } 1880d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1881d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1882d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1883d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1884d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1885d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1886d38ceaf9SAlex Deucher break; 1887d38ceaf9SAlex Deucher } 1888d38ceaf9SAlex Deucher } 1889d38ceaf9SAlex Deucher 1890d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1891d38ceaf9SAlex Deucher if (i2c_bus->valid) 1892d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1893d38ceaf9SAlex Deucher } else 1894d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 1895d38ceaf9SAlex Deucher 1896d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 1897d38ceaf9SAlex Deucher drm_connector_register(connector); 1898d38ceaf9SAlex Deucher 1899d38ceaf9SAlex Deucher if (has_aux) 1900d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 1901d38ceaf9SAlex Deucher 1902d38ceaf9SAlex Deucher return; 1903d38ceaf9SAlex Deucher 1904d38ceaf9SAlex Deucher failed: 1905d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 1906d38ceaf9SAlex Deucher kfree(connector); 1907d38ceaf9SAlex Deucher } 1908