1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher #include <drm/drmP.h> 27d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 28d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h> 29d38ceaf9SAlex Deucher #include <drm/drm_fb_helper.h> 30d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 31d38ceaf9SAlex Deucher #include "amdgpu.h" 32d38ceaf9SAlex Deucher #include "atom.h" 33d38ceaf9SAlex Deucher #include "atombios_encoders.h" 34d38ceaf9SAlex Deucher #include "atombios_dp.h" 35d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 36d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 37d38ceaf9SAlex Deucher 38d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 39d38ceaf9SAlex Deucher 40d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 41d38ceaf9SAlex Deucher { 42d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 43d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 44d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45d38ceaf9SAlex Deucher 46d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 47d38ceaf9SAlex Deucher * VGA, TV, etc. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50d38ceaf9SAlex Deucher return; 51d38ceaf9SAlex Deucher 52d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53d38ceaf9SAlex Deucher 54d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 55d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 56d38ceaf9SAlex Deucher return; 57d38ceaf9SAlex Deucher 58d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 59d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 61d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 62d38ceaf9SAlex Deucher 63d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 64d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65d38ceaf9SAlex Deucher return; 66d38ceaf9SAlex Deucher 67d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 68d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 70d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 71d38ceaf9SAlex Deucher */ 72d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73d38ceaf9SAlex Deucher int saved_dpms = connector->dpms; 74d38ceaf9SAlex Deucher /* Only turn off the display if it's physically disconnected */ 75d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77d38ceaf9SAlex Deucher } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78a887adadSAlex Deucher /* Don't try to start link training before we 79a887adadSAlex Deucher * have the dpcd */ 800b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81a887adadSAlex Deucher return; 82a887adadSAlex Deucher 83d38ceaf9SAlex Deucher /* set it to OFF so that drm_helper_connector_dpms() 84d38ceaf9SAlex Deucher * won't return immediately since the current state 85d38ceaf9SAlex Deucher * is ON at this point. 86d38ceaf9SAlex Deucher */ 87d38ceaf9SAlex Deucher connector->dpms = DRM_MODE_DPMS_OFF; 88d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89d38ceaf9SAlex Deucher } 90d38ceaf9SAlex Deucher connector->dpms = saved_dpms; 91d38ceaf9SAlex Deucher } 92d38ceaf9SAlex Deucher } 93d38ceaf9SAlex Deucher } 94d38ceaf9SAlex Deucher 95d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 96d38ceaf9SAlex Deucher { 97d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 98d38ceaf9SAlex Deucher 99d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 100d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 101d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 102d38ceaf9SAlex Deucher } 103d38ceaf9SAlex Deucher } 104d38ceaf9SAlex Deucher 105d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 106d38ceaf9SAlex Deucher { 107d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 108d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 109d38ceaf9SAlex Deucher int bpc = 8; 110d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock; 111d38ceaf9SAlex Deucher 112d38ceaf9SAlex Deucher switch (connector->connector_type) { 113d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 114d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 115d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 116d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 117d38ceaf9SAlex Deucher if (connector->display_info.bpc) 118d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 119d38ceaf9SAlex Deucher } 120d38ceaf9SAlex Deucher } 121d38ceaf9SAlex Deucher break; 122d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 123d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 124d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 125d38ceaf9SAlex Deucher if (connector->display_info.bpc) 126d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 127d38ceaf9SAlex Deucher } 128d38ceaf9SAlex Deucher break; 129d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 130d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 131d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 132d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 133d38ceaf9SAlex Deucher drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 134d38ceaf9SAlex Deucher if (connector->display_info.bpc) 135d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 136d38ceaf9SAlex Deucher } 137d38ceaf9SAlex Deucher break; 138d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 139d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 140d38ceaf9SAlex Deucher if (connector->display_info.bpc) 141d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 142d38ceaf9SAlex Deucher else { 14317b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = 144d38ceaf9SAlex Deucher connector->helper_private; 145d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 146d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 147d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 148d38ceaf9SAlex Deucher 149d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 150d38ceaf9SAlex Deucher bpc = 6; 151d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 152d38ceaf9SAlex Deucher bpc = 8; 153d38ceaf9SAlex Deucher } 154d38ceaf9SAlex Deucher break; 155d38ceaf9SAlex Deucher } 156d38ceaf9SAlex Deucher 157d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 158d38ceaf9SAlex Deucher /* 159d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 160d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 161d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 162d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 163d38ceaf9SAlex Deucher */ 164d38ceaf9SAlex Deucher if (bpc > 12) { 165d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 166d38ceaf9SAlex Deucher connector->name, bpc); 167d38ceaf9SAlex Deucher bpc = 12; 168d38ceaf9SAlex Deucher } 169d38ceaf9SAlex Deucher 170d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 171d38ceaf9SAlex Deucher if (connector->max_tmds_clock > 0) { 172d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 173d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 174d38ceaf9SAlex Deucher 175d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 176d38ceaf9SAlex Deucher max_tmds_clock = connector->max_tmds_clock * 1000; 177d38ceaf9SAlex Deucher 178d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 179d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 180d38ceaf9SAlex Deucher 181d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 182d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 183d38ceaf9SAlex Deucher if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 184d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 185d38ceaf9SAlex Deucher bpc = 10; 186d38ceaf9SAlex Deucher else 187d38ceaf9SAlex Deucher bpc = 8; 188d38ceaf9SAlex Deucher 189d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 190d38ceaf9SAlex Deucher connector->name, bpc); 191d38ceaf9SAlex Deucher } 192d38ceaf9SAlex Deucher 193d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 194d38ceaf9SAlex Deucher bpc = 8; 195d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 196d38ceaf9SAlex Deucher connector->name, bpc); 1979d746ab6SMario Kleiner } 198d38ceaf9SAlex Deucher } else if (bpc > 8) { 199d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 200d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 201d38ceaf9SAlex Deucher connector->name); 202d38ceaf9SAlex Deucher bpc = 8; 203d38ceaf9SAlex Deucher } 204d38ceaf9SAlex Deucher } 205d38ceaf9SAlex Deucher 206d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 207d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 208d38ceaf9SAlex Deucher connector->name); 209d38ceaf9SAlex Deucher bpc = 8; 210d38ceaf9SAlex Deucher } 211d38ceaf9SAlex Deucher 212d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 213d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 214d38ceaf9SAlex Deucher 215d38ceaf9SAlex Deucher return bpc; 216d38ceaf9SAlex Deucher } 217d38ceaf9SAlex Deucher 218d38ceaf9SAlex Deucher static void 219d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 220d38ceaf9SAlex Deucher enum drm_connector_status status) 221d38ceaf9SAlex Deucher { 222d38ceaf9SAlex Deucher struct drm_encoder *best_encoder = NULL; 223d38ceaf9SAlex Deucher struct drm_encoder *encoder = NULL; 22417b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 225d38ceaf9SAlex Deucher bool connected; 226d38ceaf9SAlex Deucher int i; 227d38ceaf9SAlex Deucher 228d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 229d38ceaf9SAlex Deucher 230d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 231d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 232d38ceaf9SAlex Deucher break; 233d38ceaf9SAlex Deucher 234d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 235d38ceaf9SAlex Deucher connector->encoder_ids[i]); 236d38ceaf9SAlex Deucher if (!encoder) 237d38ceaf9SAlex Deucher continue; 238d38ceaf9SAlex Deucher 239d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 240d38ceaf9SAlex Deucher connected = true; 241d38ceaf9SAlex Deucher else 242d38ceaf9SAlex Deucher connected = false; 243d38ceaf9SAlex Deucher 244d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 245d38ceaf9SAlex Deucher 246d38ceaf9SAlex Deucher } 247d38ceaf9SAlex Deucher } 248d38ceaf9SAlex Deucher 249d38ceaf9SAlex Deucher static struct drm_encoder * 250d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 251d38ceaf9SAlex Deucher int encoder_type) 252d38ceaf9SAlex Deucher { 253d38ceaf9SAlex Deucher struct drm_encoder *encoder; 254d38ceaf9SAlex Deucher int i; 255d38ceaf9SAlex Deucher 256d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 257d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 258d38ceaf9SAlex Deucher break; 259d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 260d38ceaf9SAlex Deucher connector->encoder_ids[i]); 261d38ceaf9SAlex Deucher if (!encoder) 262d38ceaf9SAlex Deucher continue; 263d38ceaf9SAlex Deucher 264d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 265d38ceaf9SAlex Deucher return encoder; 266d38ceaf9SAlex Deucher } 267d38ceaf9SAlex Deucher return NULL; 268d38ceaf9SAlex Deucher } 269d38ceaf9SAlex Deucher 270d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector) 271d38ceaf9SAlex Deucher { 272d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 273d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 274d38ceaf9SAlex Deucher 275d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 276d38ceaf9SAlex Deucher return amdgpu_connector->edid; 277d38ceaf9SAlex Deucher } else if (edid_blob) { 278d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 279d38ceaf9SAlex Deucher if (edid) 280d38ceaf9SAlex Deucher amdgpu_connector->edid = edid; 281d38ceaf9SAlex Deucher } 282d38ceaf9SAlex Deucher return amdgpu_connector->edid; 283d38ceaf9SAlex Deucher } 284d38ceaf9SAlex Deucher 285d38ceaf9SAlex Deucher static struct edid * 286d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 287d38ceaf9SAlex Deucher { 288d38ceaf9SAlex Deucher struct edid *edid; 289d38ceaf9SAlex Deucher 290d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 291d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 292d38ceaf9SAlex Deucher if (edid) { 293d38ceaf9SAlex Deucher memcpy((unsigned char *)edid, 294d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid, 295d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size); 296d38ceaf9SAlex Deucher return edid; 297d38ceaf9SAlex Deucher } 298d38ceaf9SAlex Deucher } 299d38ceaf9SAlex Deucher return NULL; 300d38ceaf9SAlex Deucher } 301d38ceaf9SAlex Deucher 302d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 303d38ceaf9SAlex Deucher { 304d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 305d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 306d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307d38ceaf9SAlex Deucher 308d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 309d38ceaf9SAlex Deucher return; 310d38ceaf9SAlex Deucher 311d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 312d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 313d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 314d38ceaf9SAlex Deucher 315d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 316d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 317d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 318d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 319d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 320d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 321d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 322d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 323d38ceaf9SAlex Deucher 324d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 325d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 326d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 327d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 328d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 329d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 330d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 331d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 332d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 333d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 334d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 335d38ceaf9SAlex Deucher } 336d38ceaf9SAlex Deucher 337d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 338d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 339d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 340d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 341d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 342d38ceaf9SAlex Deucher } 343d38ceaf9SAlex Deucher } 344d38ceaf9SAlex Deucher 345d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 346d38ceaf9SAlex Deucher { 347d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 348d38ceaf9SAlex Deucher 349d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 350d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 351d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 352d38ceaf9SAlex Deucher } 353d38ceaf9SAlex Deucher } 354d38ceaf9SAlex Deucher 355d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 356d38ceaf9SAlex Deucher { 357d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 358d38ceaf9SAlex Deucher int ret; 359d38ceaf9SAlex Deucher 360d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 361d38ceaf9SAlex Deucher drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 362d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 363d38ceaf9SAlex Deucher drm_edid_to_eld(connector, amdgpu_connector->edid); 364d38ceaf9SAlex Deucher return ret; 365d38ceaf9SAlex Deucher } 366d38ceaf9SAlex Deucher drm_mode_connector_update_edid_property(connector, NULL); 367d38ceaf9SAlex Deucher return 0; 368d38ceaf9SAlex Deucher } 369d38ceaf9SAlex Deucher 370d38ceaf9SAlex Deucher static struct drm_encoder * 371d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 372d38ceaf9SAlex Deucher { 373d38ceaf9SAlex Deucher int enc_id = connector->encoder_ids[0]; 374d38ceaf9SAlex Deucher 375d38ceaf9SAlex Deucher /* pick the encoder ids */ 376d38ceaf9SAlex Deucher if (enc_id) 377d38ceaf9SAlex Deucher return drm_encoder_find(connector->dev, enc_id); 378d38ceaf9SAlex Deucher return NULL; 379d38ceaf9SAlex Deucher } 380d38ceaf9SAlex Deucher 381d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 382d38ceaf9SAlex Deucher { 383d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 384d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 385d38ceaf9SAlex Deucher 386d38ceaf9SAlex Deucher if (encoder == NULL) 387d38ceaf9SAlex Deucher return; 388d38ceaf9SAlex Deucher 389d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 390d38ceaf9SAlex Deucher 391d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 392d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 393d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 394d38ceaf9SAlex Deucher struct drm_display_mode, head); 395d38ceaf9SAlex Deucher 396d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 397d38ceaf9SAlex Deucher } else { 398d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 399d38ceaf9SAlex Deucher } 400d38ceaf9SAlex Deucher } 401d38ceaf9SAlex Deucher 402d38ceaf9SAlex Deucher static struct drm_display_mode * 403d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 404d38ceaf9SAlex Deucher { 405d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 406d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 407d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 408d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 409d38ceaf9SAlex Deucher 410d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 411d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 412d38ceaf9SAlex Deucher native_mode->clock != 0) { 413d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 414d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 415d38ceaf9SAlex Deucher drm_mode_set_name(mode); 416d38ceaf9SAlex Deucher 417d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 418d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 419d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 420d38ceaf9SAlex Deucher /* mac laptops without an edid */ 421d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 422d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 423d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 424d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 425d38ceaf9SAlex Deucher * simpler. 426d38ceaf9SAlex Deucher */ 427d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 428d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 429d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 430d38ceaf9SAlex Deucher } 431d38ceaf9SAlex Deucher return mode; 432d38ceaf9SAlex Deucher } 433d38ceaf9SAlex Deucher 434d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 435d38ceaf9SAlex Deucher struct drm_connector *connector) 436d38ceaf9SAlex Deucher { 437d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 438d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 439d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 440d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 441d38ceaf9SAlex Deucher int i; 442aeba709aSNils Wallménius static const struct mode_size { 443d38ceaf9SAlex Deucher int w; 444d38ceaf9SAlex Deucher int h; 445d38ceaf9SAlex Deucher } common_modes[17] = { 446d38ceaf9SAlex Deucher { 640, 480}, 447d38ceaf9SAlex Deucher { 720, 480}, 448d38ceaf9SAlex Deucher { 800, 600}, 449d38ceaf9SAlex Deucher { 848, 480}, 450d38ceaf9SAlex Deucher {1024, 768}, 451d38ceaf9SAlex Deucher {1152, 768}, 452d38ceaf9SAlex Deucher {1280, 720}, 453d38ceaf9SAlex Deucher {1280, 800}, 454d38ceaf9SAlex Deucher {1280, 854}, 455d38ceaf9SAlex Deucher {1280, 960}, 456d38ceaf9SAlex Deucher {1280, 1024}, 457d38ceaf9SAlex Deucher {1440, 900}, 458d38ceaf9SAlex Deucher {1400, 1050}, 459d38ceaf9SAlex Deucher {1680, 1050}, 460d38ceaf9SAlex Deucher {1600, 1200}, 461d38ceaf9SAlex Deucher {1920, 1080}, 462d38ceaf9SAlex Deucher {1920, 1200} 463d38ceaf9SAlex Deucher }; 464d38ceaf9SAlex Deucher 465d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 466d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 467d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 468d38ceaf9SAlex Deucher common_modes[i].h > 768) 469d38ceaf9SAlex Deucher continue; 470d38ceaf9SAlex Deucher } 471d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 472d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 473d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 474d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 475d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 476d38ceaf9SAlex Deucher continue; 477d38ceaf9SAlex Deucher } 478d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 479d38ceaf9SAlex Deucher continue; 480d38ceaf9SAlex Deucher 481d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 482d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 483d38ceaf9SAlex Deucher } 484d38ceaf9SAlex Deucher } 485d38ceaf9SAlex Deucher 486d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 487d38ceaf9SAlex Deucher struct drm_property *property, 488d38ceaf9SAlex Deucher uint64_t val) 489d38ceaf9SAlex Deucher { 490d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 491d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 492d38ceaf9SAlex Deucher struct drm_encoder *encoder; 493d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 494d38ceaf9SAlex Deucher 495d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 496d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 497d38ceaf9SAlex Deucher bool new_coherent_mode; 498d38ceaf9SAlex Deucher 499d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 500d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 501d38ceaf9SAlex Deucher if (!encoder) 502d38ceaf9SAlex Deucher return 0; 503d38ceaf9SAlex Deucher 504d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 505d38ceaf9SAlex Deucher 506d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 507d38ceaf9SAlex Deucher return 0; 508d38ceaf9SAlex Deucher 509d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 510d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 511d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 512d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 513d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 514d38ceaf9SAlex Deucher } 515d38ceaf9SAlex Deucher } 516d38ceaf9SAlex Deucher 517d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 518d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 519d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 520d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 521d38ceaf9SAlex Deucher if (!encoder) 522d38ceaf9SAlex Deucher return 0; 523d38ceaf9SAlex Deucher 524d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 525d38ceaf9SAlex Deucher 526d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 527d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 528d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 529d38ceaf9SAlex Deucher } 530d38ceaf9SAlex Deucher } 531d38ceaf9SAlex Deucher 532d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 533d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 534d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 535d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 536d38ceaf9SAlex Deucher if (!encoder) 537d38ceaf9SAlex Deucher return 0; 538d38ceaf9SAlex Deucher 539d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 540d38ceaf9SAlex Deucher 541d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 542d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 543d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 544d38ceaf9SAlex Deucher } 545d38ceaf9SAlex Deucher } 546d38ceaf9SAlex Deucher 547d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 548d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 549d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 550d38ceaf9SAlex Deucher if (!encoder) 551d38ceaf9SAlex Deucher return 0; 552d38ceaf9SAlex Deucher 553d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 554d38ceaf9SAlex Deucher 555d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 556d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 557d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 558d38ceaf9SAlex Deucher } 559d38ceaf9SAlex Deucher } 560d38ceaf9SAlex Deucher 561d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 562d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 563d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 564d38ceaf9SAlex Deucher if (!encoder) 565d38ceaf9SAlex Deucher return 0; 566d38ceaf9SAlex Deucher 567d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 568d38ceaf9SAlex Deucher 569d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 570d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 571d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 572d38ceaf9SAlex Deucher } 573d38ceaf9SAlex Deucher } 574d38ceaf9SAlex Deucher 575d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 576d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 577d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 578d38ceaf9SAlex Deucher if (!encoder) 579d38ceaf9SAlex Deucher return 0; 580d38ceaf9SAlex Deucher 581d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 582d38ceaf9SAlex Deucher 583d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 584d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 585d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 586d38ceaf9SAlex Deucher } 587d38ceaf9SAlex Deucher } 588d38ceaf9SAlex Deucher 589d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 590d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 591d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 592d38ceaf9SAlex Deucher 593d38ceaf9SAlex Deucher if (val == 0) 594d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 595d38ceaf9SAlex Deucher else 596d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 597d38ceaf9SAlex Deucher } 598d38ceaf9SAlex Deucher 599d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 600d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 601d38ceaf9SAlex Deucher 602d38ceaf9SAlex Deucher if (connector->encoder) { 603d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 604d38ceaf9SAlex Deucher } else { 60517b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 606d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 607d38ceaf9SAlex Deucher } 608d38ceaf9SAlex Deucher 609d38ceaf9SAlex Deucher switch (val) { 610d38ceaf9SAlex Deucher default: 611d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 612d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 613d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 614d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 615d38ceaf9SAlex Deucher } 616d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 617d38ceaf9SAlex Deucher return 0; 618d38ceaf9SAlex Deucher 619d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 620d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 621d38ceaf9SAlex Deucher return 0; 622d38ceaf9SAlex Deucher 623d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 624d38ceaf9SAlex Deucher 625d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 626d38ceaf9SAlex Deucher } 627d38ceaf9SAlex Deucher 628d38ceaf9SAlex Deucher return 0; 629d38ceaf9SAlex Deucher } 630d38ceaf9SAlex Deucher 631d38ceaf9SAlex Deucher static void 632d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 633d38ceaf9SAlex Deucher struct drm_connector *connector) 634d38ceaf9SAlex Deucher { 635d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 636d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 637d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 638d38ceaf9SAlex Deucher 639d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 640d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 641d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 642d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 643d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 644d38ceaf9SAlex Deucher memcpy(native_mode, mode, sizeof(*mode)); 645d38ceaf9SAlex Deucher } 646d38ceaf9SAlex Deucher } 647d38ceaf9SAlex Deucher 648d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 649d38ceaf9SAlex Deucher if (!native_mode->clock) { 650d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 651d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 652d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 653d38ceaf9SAlex Deucher *native_mode = *mode; 654d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 655d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 656d38ceaf9SAlex Deucher break; 657d38ceaf9SAlex Deucher } 658d38ceaf9SAlex Deucher } 659d38ceaf9SAlex Deucher } 660d38ceaf9SAlex Deucher 661d38ceaf9SAlex Deucher if (!native_mode->clock) { 662d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 663d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 664d38ceaf9SAlex Deucher } 665d38ceaf9SAlex Deucher } 666d38ceaf9SAlex Deucher 667d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 668d38ceaf9SAlex Deucher { 669d38ceaf9SAlex Deucher struct drm_encoder *encoder; 670d38ceaf9SAlex Deucher int ret = 0; 671d38ceaf9SAlex Deucher struct drm_display_mode *mode; 672d38ceaf9SAlex Deucher 673d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 674d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 675d38ceaf9SAlex Deucher if (ret > 0) { 676d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 677d38ceaf9SAlex Deucher if (encoder) { 678d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 679d38ceaf9SAlex Deucher /* add scaled modes */ 680d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 681d38ceaf9SAlex Deucher } 682d38ceaf9SAlex Deucher return ret; 683d38ceaf9SAlex Deucher } 684d38ceaf9SAlex Deucher 685d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 686d38ceaf9SAlex Deucher if (!encoder) 687d38ceaf9SAlex Deucher return 0; 688d38ceaf9SAlex Deucher 689d38ceaf9SAlex Deucher /* we have no EDID modes */ 690d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 691d38ceaf9SAlex Deucher if (mode) { 692d38ceaf9SAlex Deucher ret = 1; 693d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 694d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 695d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 696d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 697d38ceaf9SAlex Deucher /* add scaled modes */ 698d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 699d38ceaf9SAlex Deucher } 700d38ceaf9SAlex Deucher 701d38ceaf9SAlex Deucher return ret; 702d38ceaf9SAlex Deucher } 703d38ceaf9SAlex Deucher 704d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 705d38ceaf9SAlex Deucher struct drm_display_mode *mode) 706d38ceaf9SAlex Deucher { 707d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708d38ceaf9SAlex Deucher 709d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 710d38ceaf9SAlex Deucher return MODE_PANEL; 711d38ceaf9SAlex Deucher 712d38ceaf9SAlex Deucher if (encoder) { 713d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 714d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 715d38ceaf9SAlex Deucher 716d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 717d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 718d38ceaf9SAlex Deucher */ 719d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 720d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 721d38ceaf9SAlex Deucher return MODE_PANEL; 722d38ceaf9SAlex Deucher 723d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 724d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 725d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 726d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 727d38ceaf9SAlex Deucher return MODE_PANEL; 728d38ceaf9SAlex Deucher } 729d38ceaf9SAlex Deucher } 730d38ceaf9SAlex Deucher 731d38ceaf9SAlex Deucher return MODE_OK; 732d38ceaf9SAlex Deucher } 733d38ceaf9SAlex Deucher 734d38ceaf9SAlex Deucher static enum drm_connector_status 735d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 736d38ceaf9SAlex Deucher { 737d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 738d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 739d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 740d38ceaf9SAlex Deucher int r; 741d38ceaf9SAlex Deucher 742d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 743d38ceaf9SAlex Deucher if (r < 0) 744d38ceaf9SAlex Deucher return connector_status_disconnected; 745d38ceaf9SAlex Deucher 746d38ceaf9SAlex Deucher if (encoder) { 747d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 748d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 749d38ceaf9SAlex Deucher 750d38ceaf9SAlex Deucher /* check if panel is valid */ 751d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 752d38ceaf9SAlex Deucher ret = connector_status_connected; 753d38ceaf9SAlex Deucher 754d38ceaf9SAlex Deucher } 755d38ceaf9SAlex Deucher 756d38ceaf9SAlex Deucher /* check for edid as well */ 757d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 758d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 759d38ceaf9SAlex Deucher ret = connector_status_connected; 760d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 761d38ceaf9SAlex Deucher 762d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 763d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 764d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 765d38ceaf9SAlex Deucher return ret; 766d38ceaf9SAlex Deucher } 767d38ceaf9SAlex Deucher 768d38ceaf9SAlex Deucher static void amdgpu_connector_destroy(struct drm_connector *connector) 769d38ceaf9SAlex Deucher { 770d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 771d38ceaf9SAlex Deucher 772d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->has_aux) 773d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 774d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 775d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 776d38ceaf9SAlex Deucher drm_connector_unregister(connector); 777d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 778d38ceaf9SAlex Deucher kfree(connector); 779d38ceaf9SAlex Deucher } 780d38ceaf9SAlex Deucher 781d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 782d38ceaf9SAlex Deucher struct drm_property *property, 783d38ceaf9SAlex Deucher uint64_t value) 784d38ceaf9SAlex Deucher { 785d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 786d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 787d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 788d38ceaf9SAlex Deucher 789d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 790d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 791d38ceaf9SAlex Deucher return 0; 792d38ceaf9SAlex Deucher 793d38ceaf9SAlex Deucher if (connector->encoder) 794d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 795d38ceaf9SAlex Deucher else { 79617b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 797d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 798d38ceaf9SAlex Deucher } 799d38ceaf9SAlex Deucher 800d38ceaf9SAlex Deucher switch (value) { 801d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 802d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 803d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 804d38ceaf9SAlex Deucher default: 805d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 806d38ceaf9SAlex Deucher } 807d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 808d38ceaf9SAlex Deucher return 0; 809d38ceaf9SAlex Deucher 810d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 811d38ceaf9SAlex Deucher 812d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 813d38ceaf9SAlex Deucher return 0; 814d38ceaf9SAlex Deucher } 815d38ceaf9SAlex Deucher 816d38ceaf9SAlex Deucher 817d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 818d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 819d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 820d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 821d38ceaf9SAlex Deucher }; 822d38ceaf9SAlex Deucher 823d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 824d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 825d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 826d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 827d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 828d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 829d38ceaf9SAlex Deucher }; 830d38ceaf9SAlex Deucher 831d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 832d38ceaf9SAlex Deucher { 833d38ceaf9SAlex Deucher int ret; 834d38ceaf9SAlex Deucher 835d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 836d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 837d38ceaf9SAlex Deucher 838d38ceaf9SAlex Deucher return ret; 839d38ceaf9SAlex Deucher } 840d38ceaf9SAlex Deucher 841d38ceaf9SAlex Deucher static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 842d38ceaf9SAlex Deucher struct drm_display_mode *mode) 843d38ceaf9SAlex Deucher { 844d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 845d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 846d38ceaf9SAlex Deucher 847d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 848d38ceaf9SAlex Deucher 849d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 850d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 851d38ceaf9SAlex Deucher 852d38ceaf9SAlex Deucher return MODE_OK; 853d38ceaf9SAlex Deucher } 854d38ceaf9SAlex Deucher 855d38ceaf9SAlex Deucher static enum drm_connector_status 856d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 857d38ceaf9SAlex Deucher { 858d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 859d38ceaf9SAlex Deucher struct drm_encoder *encoder; 86017b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 861d38ceaf9SAlex Deucher bool dret = false; 862d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 863d38ceaf9SAlex Deucher int r; 864d38ceaf9SAlex Deucher 865d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 866d38ceaf9SAlex Deucher if (r < 0) 867d38ceaf9SAlex Deucher return connector_status_disconnected; 868d38ceaf9SAlex Deucher 869d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 870d38ceaf9SAlex Deucher if (!encoder) 871d38ceaf9SAlex Deucher ret = connector_status_disconnected; 872d38ceaf9SAlex Deucher 873d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 874d38ceaf9SAlex Deucher dret = amdgpu_ddc_probe(amdgpu_connector, false); 875d38ceaf9SAlex Deucher if (dret) { 876d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 877d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 878d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 879d38ceaf9SAlex Deucher 880d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 881d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 882d38ceaf9SAlex Deucher connector->name); 883d38ceaf9SAlex Deucher ret = connector_status_connected; 884d38ceaf9SAlex Deucher } else { 885d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 886d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 887d38ceaf9SAlex Deucher 888d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 889d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 890d38ceaf9SAlex Deucher */ 891d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 892d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 893d38ceaf9SAlex Deucher ret = connector_status_disconnected; 894d38ceaf9SAlex Deucher } else { 895d38ceaf9SAlex Deucher ret = connector_status_connected; 896d38ceaf9SAlex Deucher } 897d38ceaf9SAlex Deucher } 898d38ceaf9SAlex Deucher } else { 899d38ceaf9SAlex Deucher 900d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 901d38ceaf9SAlex Deucher if (!force) { 902d38ceaf9SAlex Deucher /* only return the previous status if we last 903d38ceaf9SAlex Deucher * detected a monitor via load. 904d38ceaf9SAlex Deucher */ 905d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 906d38ceaf9SAlex Deucher ret = connector->status; 907d38ceaf9SAlex Deucher goto out; 908d38ceaf9SAlex Deucher } 909d38ceaf9SAlex Deucher 910d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 911d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 912d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 913d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 914d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 915d38ceaf9SAlex Deucher } 916d38ceaf9SAlex Deucher } 917d38ceaf9SAlex Deucher 918d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 919d38ceaf9SAlex Deucher 920d38ceaf9SAlex Deucher out: 921d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 922d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 923d38ceaf9SAlex Deucher 924d38ceaf9SAlex Deucher return ret; 925d38ceaf9SAlex Deucher } 926d38ceaf9SAlex Deucher 927d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 928d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 929d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 930d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 931d38ceaf9SAlex Deucher }; 932d38ceaf9SAlex Deucher 933d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 934d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 935d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 936d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 937d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 938d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 939d38ceaf9SAlex Deucher }; 940d38ceaf9SAlex Deucher 941d38ceaf9SAlex Deucher static bool 942d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 943d38ceaf9SAlex Deucher { 944d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 945d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 946d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 947d38ceaf9SAlex Deucher enum drm_connector_status status; 948d38ceaf9SAlex Deucher 949d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 950d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 951d38ceaf9SAlex Deucher status = connector_status_connected; 952d38ceaf9SAlex Deucher else 953d38ceaf9SAlex Deucher status = connector_status_disconnected; 954d38ceaf9SAlex Deucher if (connector->status == status) 955d38ceaf9SAlex Deucher return true; 956d38ceaf9SAlex Deucher } 957d38ceaf9SAlex Deucher 958d38ceaf9SAlex Deucher return false; 959d38ceaf9SAlex Deucher } 960d38ceaf9SAlex Deucher 961d38ceaf9SAlex Deucher /* 962d38ceaf9SAlex Deucher * DVI is complicated 963d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 964d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 965d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 966d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 967d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 968d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 969d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 970d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 971d38ceaf9SAlex Deucher */ 972d38ceaf9SAlex Deucher static enum drm_connector_status 973d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 974d38ceaf9SAlex Deucher { 975d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 976d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 977d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 978d38ceaf9SAlex Deucher struct drm_encoder *encoder = NULL; 97917b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 980d38ceaf9SAlex Deucher int i, r; 981d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 982d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 983d38ceaf9SAlex Deucher 984d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 985d38ceaf9SAlex Deucher if (r < 0) 986d38ceaf9SAlex Deucher return connector_status_disconnected; 987d38ceaf9SAlex Deucher 988d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 989d38ceaf9SAlex Deucher ret = connector->status; 990d38ceaf9SAlex Deucher goto exit; 991d38ceaf9SAlex Deucher } 992d38ceaf9SAlex Deucher 993d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 994d38ceaf9SAlex Deucher dret = amdgpu_ddc_probe(amdgpu_connector, false); 995d38ceaf9SAlex Deucher if (dret) { 996d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 997d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 998d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 999d38ceaf9SAlex Deucher 1000d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 1001d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1002d38ceaf9SAlex Deucher connector->name); 1003d38ceaf9SAlex Deucher ret = connector_status_connected; 1004d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1005d38ceaf9SAlex Deucher } else { 1006d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1007d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1008d38ceaf9SAlex Deucher 1009d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1010d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1011d38ceaf9SAlex Deucher */ 1012d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1013d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1014d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1015d38ceaf9SAlex Deucher } else { 1016d38ceaf9SAlex Deucher ret = connector_status_connected; 1017d38ceaf9SAlex Deucher } 1018d38ceaf9SAlex Deucher 1019d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1020d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1021d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1022d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1023d38ceaf9SAlex Deucher */ 1024d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1025d38ceaf9SAlex Deucher struct drm_connector *list_connector; 1026d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector; 1027d38ceaf9SAlex Deucher list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1028d38ceaf9SAlex Deucher if (connector == list_connector) 1029d38ceaf9SAlex Deucher continue; 1030d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector); 1031d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc && 1032d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1033d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) { 1034d38ceaf9SAlex Deucher /* cases where both connectors are digital */ 1035d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1036d38ceaf9SAlex Deucher /* hpd is our only option in this case */ 1037d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1038d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1039d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1040d38ceaf9SAlex Deucher } 1041d38ceaf9SAlex Deucher } 1042d38ceaf9SAlex Deucher } 1043d38ceaf9SAlex Deucher } 1044d38ceaf9SAlex Deucher } 1045d38ceaf9SAlex Deucher } 1046d38ceaf9SAlex Deucher } 1047d38ceaf9SAlex Deucher 1048d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1049d38ceaf9SAlex Deucher goto out; 1050d38ceaf9SAlex Deucher 1051d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1052d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1053d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1054d38ceaf9SAlex Deucher goto out; 1055d38ceaf9SAlex Deucher 1056d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1057d38ceaf9SAlex Deucher if (!force) { 1058d38ceaf9SAlex Deucher /* only return the previous status if we last 1059d38ceaf9SAlex Deucher * detected a monitor via load. 1060d38ceaf9SAlex Deucher */ 1061d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1062d38ceaf9SAlex Deucher ret = connector->status; 1063d38ceaf9SAlex Deucher goto out; 1064d38ceaf9SAlex Deucher } 1065d38ceaf9SAlex Deucher 1066d38ceaf9SAlex Deucher /* find analog encoder */ 1067d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 1068d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1069d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1070d38ceaf9SAlex Deucher break; 1071d38ceaf9SAlex Deucher 1072d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1073d38ceaf9SAlex Deucher if (!encoder) 1074d38ceaf9SAlex Deucher continue; 1075d38ceaf9SAlex Deucher 1076d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1077d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1078d38ceaf9SAlex Deucher continue; 1079d38ceaf9SAlex Deucher 1080d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1081d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1082d38ceaf9SAlex Deucher if (!broken_edid) { 1083d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1084d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1085d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1086d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1087d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1088d38ceaf9SAlex Deucher } 1089d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1090d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1091d38ceaf9SAlex Deucher } 1092d38ceaf9SAlex Deucher } else { 1093d38ceaf9SAlex Deucher enum drm_connector_status lret; 1094d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1095d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1096d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1097d38ceaf9SAlex Deucher DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1098d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1099d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1100d38ceaf9SAlex Deucher } 1101d38ceaf9SAlex Deucher break; 1102d38ceaf9SAlex Deucher } 1103d38ceaf9SAlex Deucher } 1104d38ceaf9SAlex Deucher } 1105d38ceaf9SAlex Deucher 1106d38ceaf9SAlex Deucher out: 1107d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1108d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1109d38ceaf9SAlex Deucher 1110d38ceaf9SAlex Deucher exit: 1111d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1112d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1113d38ceaf9SAlex Deucher 1114d38ceaf9SAlex Deucher return ret; 1115d38ceaf9SAlex Deucher } 1116d38ceaf9SAlex Deucher 1117d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1118d38ceaf9SAlex Deucher static struct drm_encoder * 1119d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1120d38ceaf9SAlex Deucher { 1121d38ceaf9SAlex Deucher int enc_id = connector->encoder_ids[0]; 1122d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1123d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1124d38ceaf9SAlex Deucher int i; 1125d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1126d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1127d38ceaf9SAlex Deucher break; 1128d38ceaf9SAlex Deucher 1129d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); 1130d38ceaf9SAlex Deucher if (!encoder) 1131d38ceaf9SAlex Deucher continue; 1132d38ceaf9SAlex Deucher 1133d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1134d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1135d38ceaf9SAlex Deucher return encoder; 1136d38ceaf9SAlex Deucher } else { 1137d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1138d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1139d38ceaf9SAlex Deucher return encoder; 1140d38ceaf9SAlex Deucher } 1141d38ceaf9SAlex Deucher } 1142d38ceaf9SAlex Deucher 1143d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1144d38ceaf9SAlex Deucher 1145d38ceaf9SAlex Deucher /* then check use digitial */ 1146d38ceaf9SAlex Deucher /* pick the first one */ 1147d38ceaf9SAlex Deucher if (enc_id) 1148d38ceaf9SAlex Deucher return drm_encoder_find(connector->dev, enc_id); 1149d38ceaf9SAlex Deucher return NULL; 1150d38ceaf9SAlex Deucher } 1151d38ceaf9SAlex Deucher 1152d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1153d38ceaf9SAlex Deucher { 1154d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1155d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1156d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1157d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1158d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1159d38ceaf9SAlex Deucher } 1160d38ceaf9SAlex Deucher 1161d38ceaf9SAlex Deucher static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1162d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1163d38ceaf9SAlex Deucher { 1164d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1165d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1166d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1167d38ceaf9SAlex Deucher 1168d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1169d38ceaf9SAlex Deucher 1170d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1171d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1172d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1173d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1174d38ceaf9SAlex Deucher return MODE_OK; 1175d38ceaf9SAlex Deucher } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1176d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1177d38ceaf9SAlex Deucher if (mode->clock > 340000) 1178d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1179d38ceaf9SAlex Deucher else 1180d38ceaf9SAlex Deucher return MODE_OK; 1181d38ceaf9SAlex Deucher } else { 1182d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1183d38ceaf9SAlex Deucher } 1184d38ceaf9SAlex Deucher } 1185d38ceaf9SAlex Deucher 1186d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1187d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1188d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1189d38ceaf9SAlex Deucher 1190d38ceaf9SAlex Deucher return MODE_OK; 1191d38ceaf9SAlex Deucher } 1192d38ceaf9SAlex Deucher 1193d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1194d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1195d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1196d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1197d38ceaf9SAlex Deucher }; 1198d38ceaf9SAlex Deucher 1199d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1200d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1201d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1202d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1203d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 1204d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1205d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1206d38ceaf9SAlex Deucher }; 1207d38ceaf9SAlex Deucher 1208d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1209d38ceaf9SAlex Deucher { 1210d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1211d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1212d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1213d38ceaf9SAlex Deucher int ret; 1214d38ceaf9SAlex Deucher 1215d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1216d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1217d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1218d38ceaf9SAlex Deucher 1219d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1220d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1221d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1222d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1223d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1224d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1225d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1226d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1227d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1228d38ceaf9SAlex Deucher } else { 1229d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1230d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1231d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1232d38ceaf9SAlex Deucher if (encoder) 1233d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1234d38ceaf9SAlex Deucher } 1235d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1236d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1237d38ceaf9SAlex Deucher } 1238d38ceaf9SAlex Deucher 1239d38ceaf9SAlex Deucher if (ret > 0) { 1240d38ceaf9SAlex Deucher if (encoder) { 1241d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1242d38ceaf9SAlex Deucher /* add scaled modes */ 1243d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1244d38ceaf9SAlex Deucher } 1245d38ceaf9SAlex Deucher return ret; 1246d38ceaf9SAlex Deucher } 1247d38ceaf9SAlex Deucher 1248d38ceaf9SAlex Deucher if (!encoder) 1249d38ceaf9SAlex Deucher return 0; 1250d38ceaf9SAlex Deucher 1251d38ceaf9SAlex Deucher /* we have no EDID modes */ 1252d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1253d38ceaf9SAlex Deucher if (mode) { 1254d38ceaf9SAlex Deucher ret = 1; 1255d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1256d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1257d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1258d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1259d38ceaf9SAlex Deucher /* add scaled modes */ 1260d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1261d38ceaf9SAlex Deucher } 1262d38ceaf9SAlex Deucher } else { 1263d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1264d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1265d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1266d38ceaf9SAlex Deucher if (encoder) 1267d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1268d38ceaf9SAlex Deucher } 1269d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1270d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1271d38ceaf9SAlex Deucher 1272d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1273d38ceaf9SAlex Deucher } 1274d38ceaf9SAlex Deucher 1275d38ceaf9SAlex Deucher return ret; 1276d38ceaf9SAlex Deucher } 1277d38ceaf9SAlex Deucher 1278d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1279d38ceaf9SAlex Deucher { 1280d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1281d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1282d38ceaf9SAlex Deucher int i; 1283d38ceaf9SAlex Deucher 1284d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1285d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1286d38ceaf9SAlex Deucher break; 1287d38ceaf9SAlex Deucher 1288d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 1289d38ceaf9SAlex Deucher connector->encoder_ids[i]); 1290d38ceaf9SAlex Deucher if (!encoder) 1291d38ceaf9SAlex Deucher continue; 1292d38ceaf9SAlex Deucher 1293d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1294d38ceaf9SAlex Deucher 1295d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1296d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1297d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1298d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1299d38ceaf9SAlex Deucher default: 1300d38ceaf9SAlex Deucher break; 1301d38ceaf9SAlex Deucher } 1302d38ceaf9SAlex Deucher } 1303d38ceaf9SAlex Deucher 1304d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1305d38ceaf9SAlex Deucher } 1306d38ceaf9SAlex Deucher 1307d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1308d38ceaf9SAlex Deucher { 1309d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1310d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1311d38ceaf9SAlex Deucher int i; 1312d38ceaf9SAlex Deucher bool found = false; 1313d38ceaf9SAlex Deucher 1314d38ceaf9SAlex Deucher for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1315d38ceaf9SAlex Deucher if (connector->encoder_ids[i] == 0) 1316d38ceaf9SAlex Deucher break; 1317d38ceaf9SAlex Deucher encoder = drm_encoder_find(connector->dev, 1318d38ceaf9SAlex Deucher connector->encoder_ids[i]); 1319d38ceaf9SAlex Deucher if (!encoder) 1320d38ceaf9SAlex Deucher continue; 1321d38ceaf9SAlex Deucher 1322d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1323d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1324d38ceaf9SAlex Deucher found = true; 1325d38ceaf9SAlex Deucher } 1326d38ceaf9SAlex Deucher 1327d38ceaf9SAlex Deucher return found; 1328d38ceaf9SAlex Deucher } 1329d38ceaf9SAlex Deucher 1330d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1331d38ceaf9SAlex Deucher { 1332d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1333d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1334d38ceaf9SAlex Deucher 1335d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1336d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1337d38ceaf9SAlex Deucher return true; 1338d38ceaf9SAlex Deucher } 1339d38ceaf9SAlex Deucher 1340d38ceaf9SAlex Deucher return false; 1341d38ceaf9SAlex Deucher } 1342d38ceaf9SAlex Deucher 1343d38ceaf9SAlex Deucher static enum drm_connector_status 1344d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1345d38ceaf9SAlex Deucher { 1346d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1347d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1348d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1349d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1350d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1351d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1352d38ceaf9SAlex Deucher int r; 1353d38ceaf9SAlex Deucher 1354d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1355d38ceaf9SAlex Deucher if (r < 0) 1356d38ceaf9SAlex Deucher return connector_status_disconnected; 1357d38ceaf9SAlex Deucher 1358d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1359d38ceaf9SAlex Deucher ret = connector->status; 1360d38ceaf9SAlex Deucher goto out; 1361d38ceaf9SAlex Deucher } 1362d38ceaf9SAlex Deucher 1363d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1364d38ceaf9SAlex Deucher 1365d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1366d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1367d38ceaf9SAlex Deucher if (encoder) { 1368d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1369d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1370d38ceaf9SAlex Deucher 1371d38ceaf9SAlex Deucher /* check if panel is valid */ 1372d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1373d38ceaf9SAlex Deucher ret = connector_status_connected; 1374d38ceaf9SAlex Deucher } 1375d38ceaf9SAlex Deucher /* eDP is always DP */ 1376d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1377d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1378d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1379d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1380d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1381d38ceaf9SAlex Deucher ret = connector_status_connected; 1382d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1383d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1384d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1385d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1386d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1387d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1388d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1389d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1390d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1391d38ceaf9SAlex Deucher 1392d38ceaf9SAlex Deucher if (encoder) { 1393d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1394d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1395d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1396d38ceaf9SAlex Deucher if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1397d38ceaf9SAlex Deucher ret = connector_status_connected; 1398d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 139917b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1400d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1401d38ceaf9SAlex Deucher } 1402d38ceaf9SAlex Deucher } 1403d38ceaf9SAlex Deucher } else { 1404d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1405d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1406d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1407d38ceaf9SAlex Deucher ret = connector_status_connected; 1408d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1409d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1410d38ceaf9SAlex Deucher } else { 1411d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1412d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1413d38ceaf9SAlex Deucher ret = connector_status_connected; 1414d38ceaf9SAlex Deucher } else { 1415d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1416d38ceaf9SAlex Deucher if (amdgpu_ddc_probe(amdgpu_connector, false)) 1417d38ceaf9SAlex Deucher ret = connector_status_connected; 1418d38ceaf9SAlex Deucher } 1419d38ceaf9SAlex Deucher } 1420d38ceaf9SAlex Deucher } 1421d38ceaf9SAlex Deucher 1422d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1423d38ceaf9SAlex Deucher out: 1424d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1425d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1426d38ceaf9SAlex Deucher 1427d38ceaf9SAlex Deucher return ret; 1428d38ceaf9SAlex Deucher } 1429d38ceaf9SAlex Deucher 1430d38ceaf9SAlex Deucher static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1431d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1432d38ceaf9SAlex Deucher { 1433d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1434d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1435d38ceaf9SAlex Deucher 1436d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1437d38ceaf9SAlex Deucher 1438d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1439d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1440d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1441d38ceaf9SAlex Deucher 1442d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1443d38ceaf9SAlex Deucher return MODE_PANEL; 1444d38ceaf9SAlex Deucher 1445d38ceaf9SAlex Deucher if (encoder) { 1446d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1447d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1448d38ceaf9SAlex Deucher 1449d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1450d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1451d38ceaf9SAlex Deucher */ 1452d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1453d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1454d38ceaf9SAlex Deucher return MODE_PANEL; 1455d38ceaf9SAlex Deucher 1456d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1457d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1458d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1459d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1460d38ceaf9SAlex Deucher return MODE_PANEL; 1461d38ceaf9SAlex Deucher } 1462d38ceaf9SAlex Deucher } 1463d38ceaf9SAlex Deucher return MODE_OK; 1464d38ceaf9SAlex Deucher } else { 1465d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1466d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1467d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1468d38ceaf9SAlex Deucher } else { 1469d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1470d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1471d38ceaf9SAlex Deucher if (mode->clock > 340000) 1472d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1473d38ceaf9SAlex Deucher } else { 1474d38ceaf9SAlex Deucher if (mode->clock > 165000) 1475d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1476d38ceaf9SAlex Deucher } 1477d38ceaf9SAlex Deucher } 1478d38ceaf9SAlex Deucher } 1479d38ceaf9SAlex Deucher 1480d38ceaf9SAlex Deucher return MODE_OK; 1481d38ceaf9SAlex Deucher } 1482d38ceaf9SAlex Deucher 1483d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1484d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1485d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1486d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1487d38ceaf9SAlex Deucher }; 1488d38ceaf9SAlex Deucher 1489d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1490d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1491d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1492d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1493d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 1494d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1495d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1496d38ceaf9SAlex Deucher }; 1497d38ceaf9SAlex Deucher 1498d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1499d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1500d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1501d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1502d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 1503d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1504d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1505d38ceaf9SAlex Deucher }; 1506d38ceaf9SAlex Deucher 1507d38ceaf9SAlex Deucher void 1508d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1509d38ceaf9SAlex Deucher uint32_t connector_id, 1510d38ceaf9SAlex Deucher uint32_t supported_device, 1511d38ceaf9SAlex Deucher int connector_type, 1512d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1513d38ceaf9SAlex Deucher uint16_t connector_object_id, 1514d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1515d38ceaf9SAlex Deucher struct amdgpu_router *router) 1516d38ceaf9SAlex Deucher { 1517d38ceaf9SAlex Deucher struct drm_device *dev = adev->ddev; 1518d38ceaf9SAlex Deucher struct drm_connector *connector; 1519d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1520d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1521d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1522d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1523d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1524d38ceaf9SAlex Deucher bool shared_ddc = false; 1525d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1526d38ceaf9SAlex Deucher bool has_aux = false; 1527d38ceaf9SAlex Deucher 1528d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1529d38ceaf9SAlex Deucher return; 1530d38ceaf9SAlex Deucher 1531d38ceaf9SAlex Deucher /* see if we already added it */ 1532d38ceaf9SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1533d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1534d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1535d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1536d38ceaf9SAlex Deucher return; 1537d38ceaf9SAlex Deucher } 1538d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1539d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1540d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1541d38ceaf9SAlex Deucher shared_ddc = true; 1542d38ceaf9SAlex Deucher } 1543d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1544d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1545d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1546d38ceaf9SAlex Deucher shared_ddc = false; 1547d38ceaf9SAlex Deucher } 1548d38ceaf9SAlex Deucher } 1549d38ceaf9SAlex Deucher } 1550d38ceaf9SAlex Deucher 1551d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1552d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1553d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1554d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1555d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1556d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1557d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1558d38ceaf9SAlex Deucher is_dp_bridge = true; 1559d38ceaf9SAlex Deucher break; 1560d38ceaf9SAlex Deucher default: 1561d38ceaf9SAlex Deucher break; 1562d38ceaf9SAlex Deucher } 1563d38ceaf9SAlex Deucher } 1564d38ceaf9SAlex Deucher } 1565d38ceaf9SAlex Deucher 1566d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1567d38ceaf9SAlex Deucher if (!amdgpu_connector) 1568d38ceaf9SAlex Deucher return; 1569d38ceaf9SAlex Deucher 1570d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1571d38ceaf9SAlex Deucher 1572d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1573d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1574d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1575d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1576d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1577d38ceaf9SAlex Deucher 1578d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1579d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1580d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1581d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1582d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1583d38ceaf9SAlex Deucher } 1584d38ceaf9SAlex Deucher 1585d38ceaf9SAlex Deucher if (is_dp_bridge) { 1586d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1587d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1588d38ceaf9SAlex Deucher goto failed; 1589d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1590d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1591d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1592d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1593d38ceaf9SAlex Deucher has_aux = true; 1594d38ceaf9SAlex Deucher else 1595d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1596d38ceaf9SAlex Deucher } 1597d38ceaf9SAlex Deucher switch (connector_type) { 1598d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1599d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1600d38ceaf9SAlex Deucher default: 1601d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1602d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1603d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1604d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1605d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1606d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1607d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1608d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1609d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1610d38ceaf9SAlex Deucher 1); 1611d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1612d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1613d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1614d38ceaf9SAlex Deucher break; 1615d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1616d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1617d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1618d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1619d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1620d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1621d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1622d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1623d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1624d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1625d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1626d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1627d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1628d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1629d38ceaf9SAlex Deucher 0); 1630d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1631d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1632d38ceaf9SAlex Deucher 0); 1633d38ceaf9SAlex Deucher 1634d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1635d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1636d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1637d38ceaf9SAlex Deucher 1638d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1639d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1640d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1641d38ceaf9SAlex Deucher 1642d38ceaf9SAlex Deucher if (amdgpu_audio != 0) 1643d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1644d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1645d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1646d38ceaf9SAlex Deucher 1647d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1648d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1649d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1650d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1651d38ceaf9SAlex Deucher else 1652d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1653d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1654d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1655d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1656d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1657d38ceaf9SAlex Deucher 1); 1658d38ceaf9SAlex Deucher } 1659d38ceaf9SAlex Deucher break; 1660d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1661d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1662d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1663d38ceaf9SAlex Deucher &amdgpu_connector_edp_funcs, connector_type); 1664d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1665d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1666d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1667d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1668d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1669d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1670d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1671d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1672d38ceaf9SAlex Deucher break; 1673d38ceaf9SAlex Deucher } 1674d38ceaf9SAlex Deucher } else { 1675d38ceaf9SAlex Deucher switch (connector_type) { 1676d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1677d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1678d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1679d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1680d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1681d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1682d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1683d38ceaf9SAlex Deucher } 1684d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1685d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1686d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1687d38ceaf9SAlex Deucher 1); 1688d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1689d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1690d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1691d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1692d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1693d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1694d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1695d38ceaf9SAlex Deucher break; 1696d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1697d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1698d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1699d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1700d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1701d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1702d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1703d38ceaf9SAlex Deucher } 1704d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1705d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1706d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1707d38ceaf9SAlex Deucher 1); 1708d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1709d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1710d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1711d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1712d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1713d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1714d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1715d38ceaf9SAlex Deucher break; 1716d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1717d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1718d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1719d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1720d38ceaf9SAlex Deucher goto failed; 1721d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1722d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1723d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1724d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1725d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1726d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1727d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1728d38ceaf9SAlex Deucher } 1729d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1730d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1731d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1732d38ceaf9SAlex Deucher 1); 1733d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1734d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1735d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1736d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1737d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1738d38ceaf9SAlex Deucher 0); 1739d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1740d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1741d38ceaf9SAlex Deucher 0); 1742d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1743d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1744d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1745d38ceaf9SAlex Deucher 1746d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1747d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1748d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1749d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1750d38ceaf9SAlex Deucher } 1751d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1752d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1753d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1754d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1755d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1756d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1757d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1758d38ceaf9SAlex Deucher 1); 1759d38ceaf9SAlex Deucher } 1760d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1761d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1762d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1763d38ceaf9SAlex Deucher else 1764d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1765d38ceaf9SAlex Deucher break; 1766d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1767d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1768d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1769d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1770d38ceaf9SAlex Deucher goto failed; 1771d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1772d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1773d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1774d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1775d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1776d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1777d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1778d38ceaf9SAlex Deucher } 1779d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1780d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1781d38ceaf9SAlex Deucher 1); 1782d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1783d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1784d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1785d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1786d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1787d38ceaf9SAlex Deucher 0); 1788d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1789d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1790d38ceaf9SAlex Deucher 0); 1791d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1792d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1793d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1794d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1795d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1796d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1797d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1798d38ceaf9SAlex Deucher } 1799d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1800d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1801d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1802d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1803d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1804d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1805d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1806d38ceaf9SAlex Deucher else 1807d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1808d38ceaf9SAlex Deucher break; 1809d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1810d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1811d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1812d38ceaf9SAlex Deucher goto failed; 1813d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1814d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1815d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1816d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1817d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1818d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1819d38ceaf9SAlex Deucher has_aux = true; 1820d38ceaf9SAlex Deucher else 1821d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1822d38ceaf9SAlex Deucher } 1823d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1824d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1825d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1826d38ceaf9SAlex Deucher 1); 1827d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1828d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1829d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1830d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1831d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1832d38ceaf9SAlex Deucher 0); 1833d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1834d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1835d38ceaf9SAlex Deucher 0); 1836d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1837d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1838d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1839d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1840d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1841d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1842d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1843d38ceaf9SAlex Deucher } 1844d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1845d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1846d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1847d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1848d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1849d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1850d38ceaf9SAlex Deucher break; 1851d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1852d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1853d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1854d38ceaf9SAlex Deucher goto failed; 1855d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1856d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1857d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1858d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1859d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1860d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1861d38ceaf9SAlex Deucher has_aux = true; 1862d38ceaf9SAlex Deucher else 1863d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1864d38ceaf9SAlex Deucher } 1865d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1866d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1867d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1868d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1869d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1870d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1871d38ceaf9SAlex Deucher break; 1872d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1873d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1874d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1875d38ceaf9SAlex Deucher goto failed; 1876d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1877d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1878d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1879d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1880d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1881d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1882d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1883d38ceaf9SAlex Deucher } 1884d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1885d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1886d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1887d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1888d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1889d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1890d38ceaf9SAlex Deucher break; 1891d38ceaf9SAlex Deucher } 1892d38ceaf9SAlex Deucher } 1893d38ceaf9SAlex Deucher 1894d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1895b636a1b3SLyude if (i2c_bus->valid) { 1896b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1897b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT; 1898b636a1b3SLyude } 1899d38ceaf9SAlex Deucher } else 1900d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 1901d38ceaf9SAlex Deucher 1902d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 1903d38ceaf9SAlex Deucher drm_connector_register(connector); 1904d38ceaf9SAlex Deucher 1905d38ceaf9SAlex Deucher if (has_aux) 1906d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 1907d38ceaf9SAlex Deucher 1908d38ceaf9SAlex Deucher return; 1909d38ceaf9SAlex Deucher 1910d38ceaf9SAlex Deucher failed: 1911d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 1912d38ceaf9SAlex Deucher kfree(connector); 1913d38ceaf9SAlex Deucher } 1914