1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher #include <drm/drmP.h> 27d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 28d38ceaf9SAlex Deucher #include <drm/drm_crtc_helper.h> 29d38ceaf9SAlex Deucher #include <drm/drm_fb_helper.h> 30d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 31d38ceaf9SAlex Deucher #include "amdgpu.h" 32d38ceaf9SAlex Deucher #include "atom.h" 33d38ceaf9SAlex Deucher #include "atombios_encoders.h" 34d38ceaf9SAlex Deucher #include "atombios_dp.h" 35d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 36d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 37d38ceaf9SAlex Deucher 38d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 39d38ceaf9SAlex Deucher 40d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 41d38ceaf9SAlex Deucher { 42d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 43d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 44d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45d38ceaf9SAlex Deucher 46d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 47d38ceaf9SAlex Deucher * VGA, TV, etc. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50d38ceaf9SAlex Deucher return; 51d38ceaf9SAlex Deucher 52d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53d38ceaf9SAlex Deucher 54d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 55d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 56d38ceaf9SAlex Deucher return; 57d38ceaf9SAlex Deucher 58d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 59d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 61d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 62d38ceaf9SAlex Deucher 63d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 64d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65d38ceaf9SAlex Deucher return; 66d38ceaf9SAlex Deucher 67d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 68d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 70d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 71d38ceaf9SAlex Deucher */ 72daf88096SMichel Dänzer if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 73daf88096SMichel Dänzer amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 74daf88096SMichel Dänzer amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 75daf88096SMichel Dänzer /* Don't start link training before we have the DPCD */ 760b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 77a887adadSAlex Deucher return; 78a887adadSAlex Deucher 79daf88096SMichel Dänzer /* Turn the connector off and back on immediately, which 80daf88096SMichel Dänzer * will trigger link training 81d38ceaf9SAlex Deucher */ 82daf88096SMichel Dänzer drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 83d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 84d38ceaf9SAlex Deucher } 85d38ceaf9SAlex Deucher } 86d38ceaf9SAlex Deucher } 87d38ceaf9SAlex Deucher 88d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 89d38ceaf9SAlex Deucher { 90d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 91d38ceaf9SAlex Deucher 92d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 93d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 94d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 95d38ceaf9SAlex Deucher } 96d38ceaf9SAlex Deucher } 97d38ceaf9SAlex Deucher 98d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 99d38ceaf9SAlex Deucher { 100d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 101d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 102d38ceaf9SAlex Deucher int bpc = 8; 103d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock; 104d38ceaf9SAlex Deucher 105d38ceaf9SAlex Deucher switch (connector->connector_type) { 106d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 107d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 108d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 109d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 110d38ceaf9SAlex Deucher if (connector->display_info.bpc) 111d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 112d38ceaf9SAlex Deucher } 113d38ceaf9SAlex Deucher } 114d38ceaf9SAlex Deucher break; 115d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 116d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 117d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 118d38ceaf9SAlex Deucher if (connector->display_info.bpc) 119d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 120d38ceaf9SAlex Deucher } 121d38ceaf9SAlex Deucher break; 122d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 123d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 124d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 125d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 126d38ceaf9SAlex Deucher drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 127d38ceaf9SAlex Deucher if (connector->display_info.bpc) 128d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 129d38ceaf9SAlex Deucher } 130d38ceaf9SAlex Deucher break; 131d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 132d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 133d38ceaf9SAlex Deucher if (connector->display_info.bpc) 134d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 135d38ceaf9SAlex Deucher else { 13617b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = 137d38ceaf9SAlex Deucher connector->helper_private; 138d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 139d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 140d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 141d38ceaf9SAlex Deucher 142d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 143d38ceaf9SAlex Deucher bpc = 6; 144d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 145d38ceaf9SAlex Deucher bpc = 8; 146d38ceaf9SAlex Deucher } 147d38ceaf9SAlex Deucher break; 148d38ceaf9SAlex Deucher } 149d38ceaf9SAlex Deucher 150d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 151d38ceaf9SAlex Deucher /* 152d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 153d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 154d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 155d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 156d38ceaf9SAlex Deucher */ 157d38ceaf9SAlex Deucher if (bpc > 12) { 158d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 159d38ceaf9SAlex Deucher connector->name, bpc); 160d38ceaf9SAlex Deucher bpc = 12; 161d38ceaf9SAlex Deucher } 162d38ceaf9SAlex Deucher 163d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 1642a272ca9SVille Syrjälä if (connector->display_info.max_tmds_clock > 0) { 165d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 166d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 167d38ceaf9SAlex Deucher 168d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 1692a272ca9SVille Syrjälä max_tmds_clock = connector->display_info.max_tmds_clock; 170d38ceaf9SAlex Deucher 171d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 172d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 173d38ceaf9SAlex Deucher 174d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 175d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 176d38ceaf9SAlex Deucher if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 177d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 178d38ceaf9SAlex Deucher bpc = 10; 179d38ceaf9SAlex Deucher else 180d38ceaf9SAlex Deucher bpc = 8; 181d38ceaf9SAlex Deucher 182d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 183d38ceaf9SAlex Deucher connector->name, bpc); 184d38ceaf9SAlex Deucher } 185d38ceaf9SAlex Deucher 186d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 187d38ceaf9SAlex Deucher bpc = 8; 188d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 189d38ceaf9SAlex Deucher connector->name, bpc); 1909d746ab6SMario Kleiner } 191d38ceaf9SAlex Deucher } else if (bpc > 8) { 192d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 193d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 194d38ceaf9SAlex Deucher connector->name); 195d38ceaf9SAlex Deucher bpc = 8; 196d38ceaf9SAlex Deucher } 197d38ceaf9SAlex Deucher } 198d38ceaf9SAlex Deucher 199d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 200d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 201d38ceaf9SAlex Deucher connector->name); 202d38ceaf9SAlex Deucher bpc = 8; 203d38ceaf9SAlex Deucher } 204d38ceaf9SAlex Deucher 205d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 206d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 207d38ceaf9SAlex Deucher 208d38ceaf9SAlex Deucher return bpc; 209d38ceaf9SAlex Deucher } 210d38ceaf9SAlex Deucher 211d38ceaf9SAlex Deucher static void 212d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 213d38ceaf9SAlex Deucher enum drm_connector_status status) 214d38ceaf9SAlex Deucher { 21598c0e348SVille Syrjälä struct drm_encoder *best_encoder; 21698c0e348SVille Syrjälä struct drm_encoder *encoder; 21717b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 218d38ceaf9SAlex Deucher bool connected; 219d38ceaf9SAlex Deucher int i; 220d38ceaf9SAlex Deucher 221d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 222d38ceaf9SAlex Deucher 22398c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 224d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 225d38ceaf9SAlex Deucher connected = true; 226d38ceaf9SAlex Deucher else 227d38ceaf9SAlex Deucher connected = false; 228d38ceaf9SAlex Deucher 229d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 230d38ceaf9SAlex Deucher } 231d38ceaf9SAlex Deucher } 232d38ceaf9SAlex Deucher 233d38ceaf9SAlex Deucher static struct drm_encoder * 234d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 235d38ceaf9SAlex Deucher int encoder_type) 236d38ceaf9SAlex Deucher { 237d38ceaf9SAlex Deucher struct drm_encoder *encoder; 238d38ceaf9SAlex Deucher int i; 239d38ceaf9SAlex Deucher 24098c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 241d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 242d38ceaf9SAlex Deucher return encoder; 243d38ceaf9SAlex Deucher } 24498c0e348SVille Syrjälä 245d38ceaf9SAlex Deucher return NULL; 246d38ceaf9SAlex Deucher } 247d38ceaf9SAlex Deucher 248d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector) 249d38ceaf9SAlex Deucher { 250d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 251d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 252d38ceaf9SAlex Deucher 253d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 254d38ceaf9SAlex Deucher return amdgpu_connector->edid; 255d38ceaf9SAlex Deucher } else if (edid_blob) { 256d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 257d38ceaf9SAlex Deucher if (edid) 258d38ceaf9SAlex Deucher amdgpu_connector->edid = edid; 259d38ceaf9SAlex Deucher } 260d38ceaf9SAlex Deucher return amdgpu_connector->edid; 261d38ceaf9SAlex Deucher } 262d38ceaf9SAlex Deucher 263d38ceaf9SAlex Deucher static struct edid * 264d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 265d38ceaf9SAlex Deucher { 266d38ceaf9SAlex Deucher struct edid *edid; 267d38ceaf9SAlex Deucher 268d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 269d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 270d38ceaf9SAlex Deucher if (edid) { 271d38ceaf9SAlex Deucher memcpy((unsigned char *)edid, 272d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid, 273d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size); 274d38ceaf9SAlex Deucher return edid; 275d38ceaf9SAlex Deucher } 276d38ceaf9SAlex Deucher } 277d38ceaf9SAlex Deucher return NULL; 278d38ceaf9SAlex Deucher } 279d38ceaf9SAlex Deucher 280d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 281d38ceaf9SAlex Deucher { 282d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 283d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 284d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 285d38ceaf9SAlex Deucher 286d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 287d38ceaf9SAlex Deucher return; 288d38ceaf9SAlex Deucher 289d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 290d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 291d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 292d38ceaf9SAlex Deucher 293d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 294d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 295d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 296d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 297d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 298d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 299d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 300d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 301d38ceaf9SAlex Deucher 302d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 303d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 304d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 305d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 306d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 307d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 308d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 309d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 310d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 311d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 312d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 313d38ceaf9SAlex Deucher } 314d38ceaf9SAlex Deucher 315d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 316d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 317d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 318d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 319d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 320d38ceaf9SAlex Deucher } 321d38ceaf9SAlex Deucher } 322d38ceaf9SAlex Deucher 323d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 324d38ceaf9SAlex Deucher { 325d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 326d38ceaf9SAlex Deucher 327d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 328d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 329d38ceaf9SAlex Deucher } 330d38ceaf9SAlex Deucher 331d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 332d38ceaf9SAlex Deucher { 333d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 334d38ceaf9SAlex Deucher int ret; 335d38ceaf9SAlex Deucher 336d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 337d38ceaf9SAlex Deucher drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 338d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 339d38ceaf9SAlex Deucher return ret; 340d38ceaf9SAlex Deucher } 341d38ceaf9SAlex Deucher drm_mode_connector_update_edid_property(connector, NULL); 342d38ceaf9SAlex Deucher return 0; 343d38ceaf9SAlex Deucher } 344d38ceaf9SAlex Deucher 345d38ceaf9SAlex Deucher static struct drm_encoder * 346d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 347d38ceaf9SAlex Deucher { 34898c0e348SVille Syrjälä struct drm_encoder *encoder; 34998c0e348SVille Syrjälä int i; 350d38ceaf9SAlex Deucher 35198c0e348SVille Syrjälä /* pick the first one */ 35298c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) 35398c0e348SVille Syrjälä return encoder; 35498c0e348SVille Syrjälä 355d38ceaf9SAlex Deucher return NULL; 356d38ceaf9SAlex Deucher } 357d38ceaf9SAlex Deucher 358d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 359d38ceaf9SAlex Deucher { 360d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 361d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 362d38ceaf9SAlex Deucher 363d38ceaf9SAlex Deucher if (encoder == NULL) 364d38ceaf9SAlex Deucher return; 365d38ceaf9SAlex Deucher 366d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 367d38ceaf9SAlex Deucher 368d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 369d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 370d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 371d38ceaf9SAlex Deucher struct drm_display_mode, head); 372d38ceaf9SAlex Deucher 373d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 374d38ceaf9SAlex Deucher } else { 375d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 376d38ceaf9SAlex Deucher } 377d38ceaf9SAlex Deucher } 378d38ceaf9SAlex Deucher 379d38ceaf9SAlex Deucher static struct drm_display_mode * 380d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 381d38ceaf9SAlex Deucher { 382d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 383d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 384d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 385d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 386d38ceaf9SAlex Deucher 387d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 388d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 389d38ceaf9SAlex Deucher native_mode->clock != 0) { 390d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 391d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 392d38ceaf9SAlex Deucher drm_mode_set_name(mode); 393d38ceaf9SAlex Deucher 394d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 395d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 396d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 397d38ceaf9SAlex Deucher /* mac laptops without an edid */ 398d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 399d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 400d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 401d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 402d38ceaf9SAlex Deucher * simpler. 403d38ceaf9SAlex Deucher */ 404d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 405d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 406d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 407d38ceaf9SAlex Deucher } 408d38ceaf9SAlex Deucher return mode; 409d38ceaf9SAlex Deucher } 410d38ceaf9SAlex Deucher 411d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 412d38ceaf9SAlex Deucher struct drm_connector *connector) 413d38ceaf9SAlex Deucher { 414d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 415d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 416d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 417d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 418d38ceaf9SAlex Deucher int i; 419aeba709aSNils Wallménius static const struct mode_size { 420d38ceaf9SAlex Deucher int w; 421d38ceaf9SAlex Deucher int h; 422d38ceaf9SAlex Deucher } common_modes[17] = { 423d38ceaf9SAlex Deucher { 640, 480}, 424d38ceaf9SAlex Deucher { 720, 480}, 425d38ceaf9SAlex Deucher { 800, 600}, 426d38ceaf9SAlex Deucher { 848, 480}, 427d38ceaf9SAlex Deucher {1024, 768}, 428d38ceaf9SAlex Deucher {1152, 768}, 429d38ceaf9SAlex Deucher {1280, 720}, 430d38ceaf9SAlex Deucher {1280, 800}, 431d38ceaf9SAlex Deucher {1280, 854}, 432d38ceaf9SAlex Deucher {1280, 960}, 433d38ceaf9SAlex Deucher {1280, 1024}, 434d38ceaf9SAlex Deucher {1440, 900}, 435d38ceaf9SAlex Deucher {1400, 1050}, 436d38ceaf9SAlex Deucher {1680, 1050}, 437d38ceaf9SAlex Deucher {1600, 1200}, 438d38ceaf9SAlex Deucher {1920, 1080}, 439d38ceaf9SAlex Deucher {1920, 1200} 440d38ceaf9SAlex Deucher }; 441d38ceaf9SAlex Deucher 442d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 443d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 444d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 445d38ceaf9SAlex Deucher common_modes[i].h > 768) 446d38ceaf9SAlex Deucher continue; 447d38ceaf9SAlex Deucher } 448d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 449d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 450d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 451d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 452d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 453d38ceaf9SAlex Deucher continue; 454d38ceaf9SAlex Deucher } 455d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 456d38ceaf9SAlex Deucher continue; 457d38ceaf9SAlex Deucher 458d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 459d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 460d38ceaf9SAlex Deucher } 461d38ceaf9SAlex Deucher } 462d38ceaf9SAlex Deucher 463d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 464d38ceaf9SAlex Deucher struct drm_property *property, 465d38ceaf9SAlex Deucher uint64_t val) 466d38ceaf9SAlex Deucher { 467d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 468d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 469d38ceaf9SAlex Deucher struct drm_encoder *encoder; 470d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 471d38ceaf9SAlex Deucher 472d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 473d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 474d38ceaf9SAlex Deucher bool new_coherent_mode; 475d38ceaf9SAlex Deucher 476d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 477d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 478d38ceaf9SAlex Deucher if (!encoder) 479d38ceaf9SAlex Deucher return 0; 480d38ceaf9SAlex Deucher 481d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 482d38ceaf9SAlex Deucher 483d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 484d38ceaf9SAlex Deucher return 0; 485d38ceaf9SAlex Deucher 486d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 487d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 488d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 489d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 490d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 491d38ceaf9SAlex Deucher } 492d38ceaf9SAlex Deucher } 493d38ceaf9SAlex Deucher 494d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 495d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 496d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 497d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 498d38ceaf9SAlex Deucher if (!encoder) 499d38ceaf9SAlex Deucher return 0; 500d38ceaf9SAlex Deucher 501d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 502d38ceaf9SAlex Deucher 503d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 504d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 505d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 506d38ceaf9SAlex Deucher } 507d38ceaf9SAlex Deucher } 508d38ceaf9SAlex Deucher 509d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 510d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 511d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 512d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 513d38ceaf9SAlex Deucher if (!encoder) 514d38ceaf9SAlex Deucher return 0; 515d38ceaf9SAlex Deucher 516d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 517d38ceaf9SAlex Deucher 518d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 519d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 520d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 521d38ceaf9SAlex Deucher } 522d38ceaf9SAlex Deucher } 523d38ceaf9SAlex Deucher 524d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 525d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 526d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 527d38ceaf9SAlex Deucher if (!encoder) 528d38ceaf9SAlex Deucher return 0; 529d38ceaf9SAlex Deucher 530d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 531d38ceaf9SAlex Deucher 532d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 533d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 534d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 535d38ceaf9SAlex Deucher } 536d38ceaf9SAlex Deucher } 537d38ceaf9SAlex Deucher 538d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 539d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 540d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 541d38ceaf9SAlex Deucher if (!encoder) 542d38ceaf9SAlex Deucher return 0; 543d38ceaf9SAlex Deucher 544d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 545d38ceaf9SAlex Deucher 546d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 547d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 548d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 549d38ceaf9SAlex Deucher } 550d38ceaf9SAlex Deucher } 551d38ceaf9SAlex Deucher 552d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 553d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 554d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 555d38ceaf9SAlex Deucher if (!encoder) 556d38ceaf9SAlex Deucher return 0; 557d38ceaf9SAlex Deucher 558d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 559d38ceaf9SAlex Deucher 560d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 561d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 562d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 563d38ceaf9SAlex Deucher } 564d38ceaf9SAlex Deucher } 565d38ceaf9SAlex Deucher 566d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 567d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 568d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 569d38ceaf9SAlex Deucher 570d38ceaf9SAlex Deucher if (val == 0) 571d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 572d38ceaf9SAlex Deucher else 573d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 574d38ceaf9SAlex Deucher } 575d38ceaf9SAlex Deucher 576d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 577d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 578d38ceaf9SAlex Deucher 579d38ceaf9SAlex Deucher if (connector->encoder) { 580d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 581d38ceaf9SAlex Deucher } else { 58217b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 583d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 584d38ceaf9SAlex Deucher } 585d38ceaf9SAlex Deucher 586d38ceaf9SAlex Deucher switch (val) { 587d38ceaf9SAlex Deucher default: 588d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 589d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 590d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 591d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 592d38ceaf9SAlex Deucher } 593d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 594d38ceaf9SAlex Deucher return 0; 595d38ceaf9SAlex Deucher 596d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 597d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 598d38ceaf9SAlex Deucher return 0; 599d38ceaf9SAlex Deucher 600d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 601d38ceaf9SAlex Deucher 602d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 603d38ceaf9SAlex Deucher } 604d38ceaf9SAlex Deucher 605d38ceaf9SAlex Deucher return 0; 606d38ceaf9SAlex Deucher } 607d38ceaf9SAlex Deucher 608d38ceaf9SAlex Deucher static void 609d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 610d38ceaf9SAlex Deucher struct drm_connector *connector) 611d38ceaf9SAlex Deucher { 612d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 613d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 614d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 615d38ceaf9SAlex Deucher 616d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 617d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 618d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 619d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 620d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 621d38ceaf9SAlex Deucher memcpy(native_mode, mode, sizeof(*mode)); 622d38ceaf9SAlex Deucher } 623d38ceaf9SAlex Deucher } 624d38ceaf9SAlex Deucher 625d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 626d38ceaf9SAlex Deucher if (!native_mode->clock) { 627d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 628d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 629d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 630d38ceaf9SAlex Deucher *native_mode = *mode; 631d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 632d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 633d38ceaf9SAlex Deucher break; 634d38ceaf9SAlex Deucher } 635d38ceaf9SAlex Deucher } 636d38ceaf9SAlex Deucher } 637d38ceaf9SAlex Deucher 638d38ceaf9SAlex Deucher if (!native_mode->clock) { 639d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 640d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 641d38ceaf9SAlex Deucher } 642d38ceaf9SAlex Deucher } 643d38ceaf9SAlex Deucher 644d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 645d38ceaf9SAlex Deucher { 646d38ceaf9SAlex Deucher struct drm_encoder *encoder; 647d38ceaf9SAlex Deucher int ret = 0; 648d38ceaf9SAlex Deucher struct drm_display_mode *mode; 649d38ceaf9SAlex Deucher 650d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 651d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 652d38ceaf9SAlex Deucher if (ret > 0) { 653d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 654d38ceaf9SAlex Deucher if (encoder) { 655d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 656d38ceaf9SAlex Deucher /* add scaled modes */ 657d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 658d38ceaf9SAlex Deucher } 659d38ceaf9SAlex Deucher return ret; 660d38ceaf9SAlex Deucher } 661d38ceaf9SAlex Deucher 662d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 663d38ceaf9SAlex Deucher if (!encoder) 664d38ceaf9SAlex Deucher return 0; 665d38ceaf9SAlex Deucher 666d38ceaf9SAlex Deucher /* we have no EDID modes */ 667d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 668d38ceaf9SAlex Deucher if (mode) { 669d38ceaf9SAlex Deucher ret = 1; 670d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 671d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 672d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 673d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 674d38ceaf9SAlex Deucher /* add scaled modes */ 675d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 676d38ceaf9SAlex Deucher } 677d38ceaf9SAlex Deucher 678d38ceaf9SAlex Deucher return ret; 679d38ceaf9SAlex Deucher } 680d38ceaf9SAlex Deucher 681ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 682d38ceaf9SAlex Deucher struct drm_display_mode *mode) 683d38ceaf9SAlex Deucher { 684d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 685d38ceaf9SAlex Deucher 686d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 687d38ceaf9SAlex Deucher return MODE_PANEL; 688d38ceaf9SAlex Deucher 689d38ceaf9SAlex Deucher if (encoder) { 690d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 691d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 692d38ceaf9SAlex Deucher 693d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 694d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 695d38ceaf9SAlex Deucher */ 696d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 697d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 698d38ceaf9SAlex Deucher return MODE_PANEL; 699d38ceaf9SAlex Deucher 700d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 701d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 702d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 703d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 704d38ceaf9SAlex Deucher return MODE_PANEL; 705d38ceaf9SAlex Deucher } 706d38ceaf9SAlex Deucher } 707d38ceaf9SAlex Deucher 708d38ceaf9SAlex Deucher return MODE_OK; 709d38ceaf9SAlex Deucher } 710d38ceaf9SAlex Deucher 711d38ceaf9SAlex Deucher static enum drm_connector_status 712d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 713d38ceaf9SAlex Deucher { 714d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 715d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 716d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 717d38ceaf9SAlex Deucher int r; 718d38ceaf9SAlex Deucher 719aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 720d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 721d38ceaf9SAlex Deucher if (r < 0) 722d38ceaf9SAlex Deucher return connector_status_disconnected; 723aa0aad57SLukas Wunner } 724d38ceaf9SAlex Deucher 725d38ceaf9SAlex Deucher if (encoder) { 726d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 727d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 728d38ceaf9SAlex Deucher 729d38ceaf9SAlex Deucher /* check if panel is valid */ 730d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 731d38ceaf9SAlex Deucher ret = connector_status_connected; 732d38ceaf9SAlex Deucher 733d38ceaf9SAlex Deucher } 734d38ceaf9SAlex Deucher 735d38ceaf9SAlex Deucher /* check for edid as well */ 736d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 737d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 738d38ceaf9SAlex Deucher ret = connector_status_connected; 739d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 740d38ceaf9SAlex Deucher 741d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 742aa0aad57SLukas Wunner 743aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 744d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 745d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 746aa0aad57SLukas Wunner } 747aa0aad57SLukas Wunner 748d38ceaf9SAlex Deucher return ret; 749d38ceaf9SAlex Deucher } 750d38ceaf9SAlex Deucher 75140492f60SGrazvydas Ignotas static void amdgpu_connector_unregister(struct drm_connector *connector) 752d38ceaf9SAlex Deucher { 753d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 754d38ceaf9SAlex Deucher 755eef2b411SAlex Deucher if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 756d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 7572f9ba199SGrazvydas Ignotas amdgpu_connector->ddc_bus->has_aux = false; 7582f9ba199SGrazvydas Ignotas } 75940492f60SGrazvydas Ignotas } 76040492f60SGrazvydas Ignotas 76140492f60SGrazvydas Ignotas static void amdgpu_connector_destroy(struct drm_connector *connector) 76240492f60SGrazvydas Ignotas { 76340492f60SGrazvydas Ignotas struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 76440492f60SGrazvydas Ignotas 765d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 766d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 767d38ceaf9SAlex Deucher drm_connector_unregister(connector); 768d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 769d38ceaf9SAlex Deucher kfree(connector); 770d38ceaf9SAlex Deucher } 771d38ceaf9SAlex Deucher 772d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 773d38ceaf9SAlex Deucher struct drm_property *property, 774d38ceaf9SAlex Deucher uint64_t value) 775d38ceaf9SAlex Deucher { 776d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 777d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 778d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 779d38ceaf9SAlex Deucher 780d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 781d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 782d38ceaf9SAlex Deucher return 0; 783d38ceaf9SAlex Deucher 784d38ceaf9SAlex Deucher if (connector->encoder) 785d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 786d38ceaf9SAlex Deucher else { 78717b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 788d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 789d38ceaf9SAlex Deucher } 790d38ceaf9SAlex Deucher 791d38ceaf9SAlex Deucher switch (value) { 792d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 793d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 794d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 795d38ceaf9SAlex Deucher default: 796d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 797d38ceaf9SAlex Deucher } 798d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 799d38ceaf9SAlex Deucher return 0; 800d38ceaf9SAlex Deucher 801d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 802d38ceaf9SAlex Deucher 803d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 804d38ceaf9SAlex Deucher return 0; 805d38ceaf9SAlex Deucher } 806d38ceaf9SAlex Deucher 807d38ceaf9SAlex Deucher 808d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 809d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 810d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 811d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 812d38ceaf9SAlex Deucher }; 813d38ceaf9SAlex Deucher 814d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 815d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 816d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 817d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 81840492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 819d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 820d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 821d38ceaf9SAlex Deucher }; 822d38ceaf9SAlex Deucher 823d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 824d38ceaf9SAlex Deucher { 825d38ceaf9SAlex Deucher int ret; 826d38ceaf9SAlex Deucher 827d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 828d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 829d38ceaf9SAlex Deucher 830d38ceaf9SAlex Deucher return ret; 831d38ceaf9SAlex Deucher } 832d38ceaf9SAlex Deucher 833ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 834d38ceaf9SAlex Deucher struct drm_display_mode *mode) 835d38ceaf9SAlex Deucher { 836d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 837d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 838d38ceaf9SAlex Deucher 839d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 840d38ceaf9SAlex Deucher 841d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 842d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 843d38ceaf9SAlex Deucher 844d38ceaf9SAlex Deucher return MODE_OK; 845d38ceaf9SAlex Deucher } 846d38ceaf9SAlex Deucher 847d38ceaf9SAlex Deucher static enum drm_connector_status 848d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 849d38ceaf9SAlex Deucher { 850d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 851d38ceaf9SAlex Deucher struct drm_encoder *encoder; 85217b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 853d38ceaf9SAlex Deucher bool dret = false; 854d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 855d38ceaf9SAlex Deucher int r; 856d38ceaf9SAlex Deucher 857aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 858d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 859d38ceaf9SAlex Deucher if (r < 0) 860d38ceaf9SAlex Deucher return connector_status_disconnected; 861aa0aad57SLukas Wunner } 862d38ceaf9SAlex Deucher 863d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 864d38ceaf9SAlex Deucher if (!encoder) 865d38ceaf9SAlex Deucher ret = connector_status_disconnected; 866d38ceaf9SAlex Deucher 867d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 868e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 869d38ceaf9SAlex Deucher if (dret) { 870d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 871d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 872d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 873d38ceaf9SAlex Deucher 874d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 875d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 876d38ceaf9SAlex Deucher connector->name); 877d38ceaf9SAlex Deucher ret = connector_status_connected; 878d38ceaf9SAlex Deucher } else { 879d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 880d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 881d38ceaf9SAlex Deucher 882d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 883d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 884d38ceaf9SAlex Deucher */ 885d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 886d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 887d38ceaf9SAlex Deucher ret = connector_status_disconnected; 888d38ceaf9SAlex Deucher } else { 889d38ceaf9SAlex Deucher ret = connector_status_connected; 890d38ceaf9SAlex Deucher } 891d38ceaf9SAlex Deucher } 892d38ceaf9SAlex Deucher } else { 893d38ceaf9SAlex Deucher 894d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 895d38ceaf9SAlex Deucher if (!force) { 896d38ceaf9SAlex Deucher /* only return the previous status if we last 897d38ceaf9SAlex Deucher * detected a monitor via load. 898d38ceaf9SAlex Deucher */ 899d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 900d38ceaf9SAlex Deucher ret = connector->status; 901d38ceaf9SAlex Deucher goto out; 902d38ceaf9SAlex Deucher } 903d38ceaf9SAlex Deucher 904d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 905d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 906d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 907d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 908d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 909d38ceaf9SAlex Deucher } 910d38ceaf9SAlex Deucher } 911d38ceaf9SAlex Deucher 912d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 913d38ceaf9SAlex Deucher 914d38ceaf9SAlex Deucher out: 915aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 916d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 917d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 918aa0aad57SLukas Wunner } 919d38ceaf9SAlex Deucher 920d38ceaf9SAlex Deucher return ret; 921d38ceaf9SAlex Deucher } 922d38ceaf9SAlex Deucher 923d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 924d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 925d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 926d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 927d38ceaf9SAlex Deucher }; 928d38ceaf9SAlex Deucher 929d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 930d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 931d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 932d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 93340492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 934d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 935d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 936d38ceaf9SAlex Deucher }; 937d38ceaf9SAlex Deucher 938d38ceaf9SAlex Deucher static bool 939d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 940d38ceaf9SAlex Deucher { 941d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 942d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 943d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 944d38ceaf9SAlex Deucher enum drm_connector_status status; 945d38ceaf9SAlex Deucher 946d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 947d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 948d38ceaf9SAlex Deucher status = connector_status_connected; 949d38ceaf9SAlex Deucher else 950d38ceaf9SAlex Deucher status = connector_status_disconnected; 951d38ceaf9SAlex Deucher if (connector->status == status) 952d38ceaf9SAlex Deucher return true; 953d38ceaf9SAlex Deucher } 954d38ceaf9SAlex Deucher 955d38ceaf9SAlex Deucher return false; 956d38ceaf9SAlex Deucher } 957d38ceaf9SAlex Deucher 958d38ceaf9SAlex Deucher /* 959d38ceaf9SAlex Deucher * DVI is complicated 960d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 961d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 962d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 963d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 964d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 965d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 966d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 967d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 968d38ceaf9SAlex Deucher */ 969d38ceaf9SAlex Deucher static enum drm_connector_status 970d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 971d38ceaf9SAlex Deucher { 972d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 973d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 974d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 97517b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 97698c0e348SVille Syrjälä int r; 977d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 978d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 979d38ceaf9SAlex Deucher 980aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 981d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 982d38ceaf9SAlex Deucher if (r < 0) 983d38ceaf9SAlex Deucher return connector_status_disconnected; 984aa0aad57SLukas Wunner } 985d38ceaf9SAlex Deucher 986d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 987d38ceaf9SAlex Deucher ret = connector->status; 988d38ceaf9SAlex Deucher goto exit; 989d38ceaf9SAlex Deucher } 990d38ceaf9SAlex Deucher 991d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 992e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 993d38ceaf9SAlex Deucher if (dret) { 994d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 995d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 996d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 997d38ceaf9SAlex Deucher 998d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 999d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1000d38ceaf9SAlex Deucher connector->name); 1001d38ceaf9SAlex Deucher ret = connector_status_connected; 1002d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1003d38ceaf9SAlex Deucher } else { 1004d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1005d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1006d38ceaf9SAlex Deucher 1007d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1008d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1009d38ceaf9SAlex Deucher */ 1010d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1011d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1012d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1013d38ceaf9SAlex Deucher } else { 1014d38ceaf9SAlex Deucher ret = connector_status_connected; 1015d38ceaf9SAlex Deucher } 1016d38ceaf9SAlex Deucher 1017d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1018d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1019d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1020d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1021d38ceaf9SAlex Deucher */ 1022d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1023d38ceaf9SAlex Deucher struct drm_connector *list_connector; 1024d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector; 1025d38ceaf9SAlex Deucher list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1026d38ceaf9SAlex Deucher if (connector == list_connector) 1027d38ceaf9SAlex Deucher continue; 1028d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector); 1029d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc && 1030d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1031d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) { 1032d38ceaf9SAlex Deucher /* cases where both connectors are digital */ 1033d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1034d38ceaf9SAlex Deucher /* hpd is our only option in this case */ 1035d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1036d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1037d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1038d38ceaf9SAlex Deucher } 1039d38ceaf9SAlex Deucher } 1040d38ceaf9SAlex Deucher } 1041d38ceaf9SAlex Deucher } 1042d38ceaf9SAlex Deucher } 1043d38ceaf9SAlex Deucher } 1044d38ceaf9SAlex Deucher } 1045d38ceaf9SAlex Deucher 1046d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1047d38ceaf9SAlex Deucher goto out; 1048d38ceaf9SAlex Deucher 1049d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1050d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1051d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1052d38ceaf9SAlex Deucher goto out; 1053d38ceaf9SAlex Deucher 1054d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1055d38ceaf9SAlex Deucher if (!force) { 1056d38ceaf9SAlex Deucher /* only return the previous status if we last 1057d38ceaf9SAlex Deucher * detected a monitor via load. 1058d38ceaf9SAlex Deucher */ 1059d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1060d38ceaf9SAlex Deucher ret = connector->status; 1061d38ceaf9SAlex Deucher goto out; 1062d38ceaf9SAlex Deucher } 1063d38ceaf9SAlex Deucher 1064d38ceaf9SAlex Deucher /* find analog encoder */ 1065d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 106698c0e348SVille Syrjälä struct drm_encoder *encoder; 106798c0e348SVille Syrjälä int i; 1068d38ceaf9SAlex Deucher 106998c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1070d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1071d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1072d38ceaf9SAlex Deucher continue; 1073d38ceaf9SAlex Deucher 1074d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1075d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1076d38ceaf9SAlex Deucher if (!broken_edid) { 1077d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1078d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1079d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1080d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1081d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1082d38ceaf9SAlex Deucher } 1083d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1084d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1085d38ceaf9SAlex Deucher } 1086d38ceaf9SAlex Deucher } else { 1087d38ceaf9SAlex Deucher enum drm_connector_status lret; 1088d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1089d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1090d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1091d38ceaf9SAlex Deucher DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1092d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1093d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1094d38ceaf9SAlex Deucher } 1095d38ceaf9SAlex Deucher break; 1096d38ceaf9SAlex Deucher } 1097d38ceaf9SAlex Deucher } 1098d38ceaf9SAlex Deucher } 1099d38ceaf9SAlex Deucher 1100d38ceaf9SAlex Deucher out: 1101d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1102d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1103d38ceaf9SAlex Deucher 1104d38ceaf9SAlex Deucher exit: 1105aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1106d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1107d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1108aa0aad57SLukas Wunner } 1109d38ceaf9SAlex Deucher 1110d38ceaf9SAlex Deucher return ret; 1111d38ceaf9SAlex Deucher } 1112d38ceaf9SAlex Deucher 1113d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1114d38ceaf9SAlex Deucher static struct drm_encoder * 1115d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1116d38ceaf9SAlex Deucher { 1117d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1118d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1119d38ceaf9SAlex Deucher int i; 1120d38ceaf9SAlex Deucher 112198c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1122d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1123d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1124d38ceaf9SAlex Deucher return encoder; 1125d38ceaf9SAlex Deucher } else { 1126d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1127d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1128d38ceaf9SAlex Deucher return encoder; 1129d38ceaf9SAlex Deucher } 1130d38ceaf9SAlex Deucher } 1131d38ceaf9SAlex Deucher 1132d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1133d38ceaf9SAlex Deucher 1134d38ceaf9SAlex Deucher /* then check use digitial */ 1135d38ceaf9SAlex Deucher /* pick the first one */ 113698c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) 113798c0e348SVille Syrjälä return encoder; 113898c0e348SVille Syrjälä 1139d38ceaf9SAlex Deucher return NULL; 1140d38ceaf9SAlex Deucher } 1141d38ceaf9SAlex Deucher 1142d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1143d38ceaf9SAlex Deucher { 1144d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1145d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1146d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1147d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1148d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1149d38ceaf9SAlex Deucher } 1150d38ceaf9SAlex Deucher 1151ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1152d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1153d38ceaf9SAlex Deucher { 1154d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1155d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1156d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1157d38ceaf9SAlex Deucher 1158d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1159d38ceaf9SAlex Deucher 1160d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1161d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1162d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1163d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1164d38ceaf9SAlex Deucher return MODE_OK; 1165d38ceaf9SAlex Deucher } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1166d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1167d38ceaf9SAlex Deucher if (mode->clock > 340000) 1168d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1169d38ceaf9SAlex Deucher else 1170d38ceaf9SAlex Deucher return MODE_OK; 1171d38ceaf9SAlex Deucher } else { 1172d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1173d38ceaf9SAlex Deucher } 1174d38ceaf9SAlex Deucher } 1175d38ceaf9SAlex Deucher 1176d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1177d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1178d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1179d38ceaf9SAlex Deucher 1180d38ceaf9SAlex Deucher return MODE_OK; 1181d38ceaf9SAlex Deucher } 1182d38ceaf9SAlex Deucher 1183d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1184d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1185d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1186d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1187d38ceaf9SAlex Deucher }; 1188d38ceaf9SAlex Deucher 1189d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1190d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1191d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1192d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1193d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 119440492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1195d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1196d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1197d38ceaf9SAlex Deucher }; 1198d38ceaf9SAlex Deucher 1199d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1200d38ceaf9SAlex Deucher { 1201d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1202d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1203d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1204d38ceaf9SAlex Deucher int ret; 1205d38ceaf9SAlex Deucher 1206d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1207d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1208d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1209d38ceaf9SAlex Deucher 1210d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1211d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1212d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1213d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1214d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1215d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1216d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1217d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1218d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1219d38ceaf9SAlex Deucher } else { 1220d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1221d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1222d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1223d38ceaf9SAlex Deucher if (encoder) 1224d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1225d38ceaf9SAlex Deucher } 1226d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1227d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1228d38ceaf9SAlex Deucher } 1229d38ceaf9SAlex Deucher 1230d38ceaf9SAlex Deucher if (ret > 0) { 1231d38ceaf9SAlex Deucher if (encoder) { 1232d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1233d38ceaf9SAlex Deucher /* add scaled modes */ 1234d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1235d38ceaf9SAlex Deucher } 1236d38ceaf9SAlex Deucher return ret; 1237d38ceaf9SAlex Deucher } 1238d38ceaf9SAlex Deucher 1239d38ceaf9SAlex Deucher if (!encoder) 1240d38ceaf9SAlex Deucher return 0; 1241d38ceaf9SAlex Deucher 1242d38ceaf9SAlex Deucher /* we have no EDID modes */ 1243d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1244d38ceaf9SAlex Deucher if (mode) { 1245d38ceaf9SAlex Deucher ret = 1; 1246d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1247d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1248d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1249d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1250d38ceaf9SAlex Deucher /* add scaled modes */ 1251d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1252d38ceaf9SAlex Deucher } 1253d38ceaf9SAlex Deucher } else { 1254d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1255d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1256d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1257d38ceaf9SAlex Deucher if (encoder) 1258d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1259d38ceaf9SAlex Deucher } 1260d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1261d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1262d38ceaf9SAlex Deucher 1263d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1264d38ceaf9SAlex Deucher } 1265d38ceaf9SAlex Deucher 1266d38ceaf9SAlex Deucher return ret; 1267d38ceaf9SAlex Deucher } 1268d38ceaf9SAlex Deucher 1269d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1270d38ceaf9SAlex Deucher { 1271d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1272d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1273d38ceaf9SAlex Deucher int i; 1274d38ceaf9SAlex Deucher 127598c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1276d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1277d38ceaf9SAlex Deucher 1278d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1279d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1280d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1281d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1282d38ceaf9SAlex Deucher default: 1283d38ceaf9SAlex Deucher break; 1284d38ceaf9SAlex Deucher } 1285d38ceaf9SAlex Deucher } 1286d38ceaf9SAlex Deucher 1287d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1288d38ceaf9SAlex Deucher } 1289d38ceaf9SAlex Deucher 1290d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1291d38ceaf9SAlex Deucher { 1292d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1293d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1294d38ceaf9SAlex Deucher int i; 1295d38ceaf9SAlex Deucher bool found = false; 1296d38ceaf9SAlex Deucher 129798c0e348SVille Syrjälä drm_connector_for_each_possible_encoder(connector, encoder, i) { 1298d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1299d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1300d38ceaf9SAlex Deucher found = true; 1301d38ceaf9SAlex Deucher } 1302d38ceaf9SAlex Deucher 1303d38ceaf9SAlex Deucher return found; 1304d38ceaf9SAlex Deucher } 1305d38ceaf9SAlex Deucher 1306d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1307d38ceaf9SAlex Deucher { 1308d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1309d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1310d38ceaf9SAlex Deucher 1311d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1312d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1313d38ceaf9SAlex Deucher return true; 1314d38ceaf9SAlex Deucher } 1315d38ceaf9SAlex Deucher 1316d38ceaf9SAlex Deucher return false; 1317d38ceaf9SAlex Deucher } 1318d38ceaf9SAlex Deucher 1319d38ceaf9SAlex Deucher static enum drm_connector_status 1320d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1321d38ceaf9SAlex Deucher { 1322d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 1323d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 1324d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1325d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1326d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1327d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1328d38ceaf9SAlex Deucher int r; 1329d38ceaf9SAlex Deucher 1330aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1331d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1332d38ceaf9SAlex Deucher if (r < 0) 1333d38ceaf9SAlex Deucher return connector_status_disconnected; 1334aa0aad57SLukas Wunner } 1335d38ceaf9SAlex Deucher 1336d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1337d38ceaf9SAlex Deucher ret = connector->status; 1338d38ceaf9SAlex Deucher goto out; 1339d38ceaf9SAlex Deucher } 1340d38ceaf9SAlex Deucher 1341d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1342d38ceaf9SAlex Deucher 1343d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1344d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1345d38ceaf9SAlex Deucher if (encoder) { 1346d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1347d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1348d38ceaf9SAlex Deucher 1349d38ceaf9SAlex Deucher /* check if panel is valid */ 1350d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1351d38ceaf9SAlex Deucher ret = connector_status_connected; 1352d38ceaf9SAlex Deucher } 1353d38ceaf9SAlex Deucher /* eDP is always DP */ 1354d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1355d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1356d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1357d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1358d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1359d38ceaf9SAlex Deucher ret = connector_status_connected; 1360d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1361d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1362d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1363d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1364d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1365d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1366d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1367d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1368d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1369d38ceaf9SAlex Deucher 1370d38ceaf9SAlex Deucher if (encoder) { 1371d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1372d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1373d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1374e0b5b5ecSSamuel Li /* try DDC */ 1375e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1376d38ceaf9SAlex Deucher ret = connector_status_connected; 1377d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 137817b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1379d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1380d38ceaf9SAlex Deucher } 1381d38ceaf9SAlex Deucher } 1382d38ceaf9SAlex Deucher } else { 1383d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1384d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1385d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1386d38ceaf9SAlex Deucher ret = connector_status_connected; 1387d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1388d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1389d38ceaf9SAlex Deucher } else { 1390d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1391d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1392d38ceaf9SAlex Deucher ret = connector_status_connected; 1393d38ceaf9SAlex Deucher } else { 1394d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1395e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, 1396e0b5b5ecSSamuel Li false)) 1397d38ceaf9SAlex Deucher ret = connector_status_connected; 1398d38ceaf9SAlex Deucher } 1399d38ceaf9SAlex Deucher } 1400d38ceaf9SAlex Deucher } 1401d38ceaf9SAlex Deucher 1402d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1403d38ceaf9SAlex Deucher out: 1404aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1405d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1406d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1407aa0aad57SLukas Wunner } 1408d38ceaf9SAlex Deucher 1409d38ceaf9SAlex Deucher return ret; 1410d38ceaf9SAlex Deucher } 1411d38ceaf9SAlex Deucher 1412ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1413d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1414d38ceaf9SAlex Deucher { 1415d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1416d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1417d38ceaf9SAlex Deucher 1418d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1419d38ceaf9SAlex Deucher 1420d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1421d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1422d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1423d38ceaf9SAlex Deucher 1424d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1425d38ceaf9SAlex Deucher return MODE_PANEL; 1426d38ceaf9SAlex Deucher 1427d38ceaf9SAlex Deucher if (encoder) { 1428d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1429d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1430d38ceaf9SAlex Deucher 1431d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1432d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1433d38ceaf9SAlex Deucher */ 1434d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1435d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1436d38ceaf9SAlex Deucher return MODE_PANEL; 1437d38ceaf9SAlex Deucher 1438d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1439d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1440d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1441d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1442d38ceaf9SAlex Deucher return MODE_PANEL; 1443d38ceaf9SAlex Deucher } 1444d38ceaf9SAlex Deucher } 1445d38ceaf9SAlex Deucher return MODE_OK; 1446d38ceaf9SAlex Deucher } else { 1447d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1448d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1449d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1450d38ceaf9SAlex Deucher } else { 1451d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1452d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1453d38ceaf9SAlex Deucher if (mode->clock > 340000) 1454d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1455d38ceaf9SAlex Deucher } else { 1456d38ceaf9SAlex Deucher if (mode->clock > 165000) 1457d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1458d38ceaf9SAlex Deucher } 1459d38ceaf9SAlex Deucher } 1460d38ceaf9SAlex Deucher } 1461d38ceaf9SAlex Deucher 1462d38ceaf9SAlex Deucher return MODE_OK; 1463d38ceaf9SAlex Deucher } 1464d38ceaf9SAlex Deucher 1465d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1466d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1467d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1468d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1469d38ceaf9SAlex Deucher }; 1470d38ceaf9SAlex Deucher 1471d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1472d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1473d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1474d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1475d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 147640492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1477d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1478d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1479d38ceaf9SAlex Deucher }; 1480d38ceaf9SAlex Deucher 1481d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1482d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1483d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1484d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1485d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 148640492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1487d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1488d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1489d38ceaf9SAlex Deucher }; 1490d38ceaf9SAlex Deucher 1491d38ceaf9SAlex Deucher void 1492d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1493d38ceaf9SAlex Deucher uint32_t connector_id, 1494d38ceaf9SAlex Deucher uint32_t supported_device, 1495d38ceaf9SAlex Deucher int connector_type, 1496d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1497d38ceaf9SAlex Deucher uint16_t connector_object_id, 1498d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1499d38ceaf9SAlex Deucher struct amdgpu_router *router) 1500d38ceaf9SAlex Deucher { 1501d38ceaf9SAlex Deucher struct drm_device *dev = adev->ddev; 1502d38ceaf9SAlex Deucher struct drm_connector *connector; 1503d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1504d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1505d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1506d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1507d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1508d38ceaf9SAlex Deucher bool shared_ddc = false; 1509d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1510d38ceaf9SAlex Deucher bool has_aux = false; 1511d38ceaf9SAlex Deucher 1512d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1513d38ceaf9SAlex Deucher return; 1514d38ceaf9SAlex Deucher 1515d38ceaf9SAlex Deucher /* see if we already added it */ 1516d38ceaf9SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1517d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1518d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1519d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1520d38ceaf9SAlex Deucher return; 1521d38ceaf9SAlex Deucher } 1522d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1523d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1524d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1525d38ceaf9SAlex Deucher shared_ddc = true; 1526d38ceaf9SAlex Deucher } 1527d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1528d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1529d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1530d38ceaf9SAlex Deucher shared_ddc = false; 1531d38ceaf9SAlex Deucher } 1532d38ceaf9SAlex Deucher } 1533d38ceaf9SAlex Deucher } 1534d38ceaf9SAlex Deucher 1535d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1536d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1537d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1538d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1539d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1540d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1541d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1542d38ceaf9SAlex Deucher is_dp_bridge = true; 1543d38ceaf9SAlex Deucher break; 1544d38ceaf9SAlex Deucher default: 1545d38ceaf9SAlex Deucher break; 1546d38ceaf9SAlex Deucher } 1547d38ceaf9SAlex Deucher } 1548d38ceaf9SAlex Deucher } 1549d38ceaf9SAlex Deucher 1550d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1551d38ceaf9SAlex Deucher if (!amdgpu_connector) 1552d38ceaf9SAlex Deucher return; 1553d38ceaf9SAlex Deucher 1554d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1555d38ceaf9SAlex Deucher 1556d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1557d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1558d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1559d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1560d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1561d38ceaf9SAlex Deucher 1562d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1563d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1564d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1565d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1566d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1567d38ceaf9SAlex Deucher } 1568d38ceaf9SAlex Deucher 1569d38ceaf9SAlex Deucher if (is_dp_bridge) { 1570d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1571d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1572d38ceaf9SAlex Deucher goto failed; 1573d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1574d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1575d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1576d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1577d38ceaf9SAlex Deucher has_aux = true; 1578d38ceaf9SAlex Deucher else 1579d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1580d38ceaf9SAlex Deucher } 1581d38ceaf9SAlex Deucher switch (connector_type) { 1582d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1583d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1584d38ceaf9SAlex Deucher default: 1585d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1586d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1587d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1588d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1589d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1590d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1591d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1592d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1593d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1594d38ceaf9SAlex Deucher 1); 1595d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1596d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1597d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1598d38ceaf9SAlex Deucher break; 1599d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1600d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1601d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1602d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1603d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1604d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1605d38ceaf9SAlex Deucher &amdgpu_connector_dp_funcs, connector_type); 1606d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1607d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1608d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1609d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1610d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1611d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1612d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1613d38ceaf9SAlex Deucher 0); 1614d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1615d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1616d38ceaf9SAlex Deucher 0); 1617d38ceaf9SAlex Deucher 1618d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1619d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1620d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1621d38ceaf9SAlex Deucher 1622d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1623d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1624d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1625d38ceaf9SAlex Deucher 1626d38ceaf9SAlex Deucher if (amdgpu_audio != 0) 1627d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1628d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1629d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1630d38ceaf9SAlex Deucher 1631d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1632d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1633d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1634d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1635d38ceaf9SAlex Deucher else 1636d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1637d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1638d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1639d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1640d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1641d38ceaf9SAlex Deucher 1); 1642d38ceaf9SAlex Deucher } 1643d38ceaf9SAlex Deucher break; 1644d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1645d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1646d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, 1647d38ceaf9SAlex Deucher &amdgpu_connector_edp_funcs, connector_type); 1648d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1649d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1650d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1651d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1652d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1653d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1654d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1655d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1656d38ceaf9SAlex Deucher break; 1657d38ceaf9SAlex Deucher } 1658d38ceaf9SAlex Deucher } else { 1659d38ceaf9SAlex Deucher switch (connector_type) { 1660d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1661d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1662d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1663d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1664d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1665d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1666d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1667d38ceaf9SAlex Deucher } 1668d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1669d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1670d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1671d38ceaf9SAlex Deucher 1); 1672d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1673d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1674d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1675d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1676d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1677d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1678d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1679d38ceaf9SAlex Deucher break; 1680d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1681d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1682d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1683d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1684d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1685d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1686d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1687d38ceaf9SAlex Deucher } 1688d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1689d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1690d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1691d38ceaf9SAlex Deucher 1); 1692d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1693d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1694d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1695d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1696d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1697d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1698d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1699d38ceaf9SAlex Deucher break; 1700d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1701d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1702d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1703d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1704d38ceaf9SAlex Deucher goto failed; 1705d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1706d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1707d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1708d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1709d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1710d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1711d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1712d38ceaf9SAlex Deucher } 1713d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1714d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1715d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1716d38ceaf9SAlex Deucher 1); 1717d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1718d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1719d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1720d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1721d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1722d38ceaf9SAlex Deucher 0); 1723d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1724d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1725d38ceaf9SAlex Deucher 0); 1726d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1727d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1728d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1729d38ceaf9SAlex Deucher 1730d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1731d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1732d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1733d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1734d38ceaf9SAlex Deucher } 1735d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1736d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1737d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1738d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1739d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1740d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1741d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1742d38ceaf9SAlex Deucher 1); 1743d38ceaf9SAlex Deucher } 1744d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1745d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1746d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1747d38ceaf9SAlex Deucher else 1748d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1749d38ceaf9SAlex Deucher break; 1750d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1751d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1752d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1753d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1754d38ceaf9SAlex Deucher goto failed; 1755d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1756d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1757d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1758d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1759d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1760d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1761d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1762d38ceaf9SAlex Deucher } 1763d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1764d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1765d38ceaf9SAlex Deucher 1); 1766d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1767d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1768d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1769d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1770d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1771d38ceaf9SAlex Deucher 0); 1772d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1773d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1774d38ceaf9SAlex Deucher 0); 1775d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1776d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1777d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1778d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1779d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1780d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1781d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1782d38ceaf9SAlex Deucher } 1783d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1784d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1785d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1786d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1787d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1788d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1789d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1790d38ceaf9SAlex Deucher else 1791d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1792d38ceaf9SAlex Deucher break; 1793d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1794d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1795d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1796d38ceaf9SAlex Deucher goto failed; 1797d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1798d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1799d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1800d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1801d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1802d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1803d38ceaf9SAlex Deucher has_aux = true; 1804d38ceaf9SAlex Deucher else 1805d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1806d38ceaf9SAlex Deucher } 1807d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1808d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1809d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1810d38ceaf9SAlex Deucher 1); 1811d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1812d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1813d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1814d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1815d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1816d38ceaf9SAlex Deucher 0); 1817d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1818d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1819d38ceaf9SAlex Deucher 0); 1820d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1821d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1822d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1823d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1824d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1825d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1826d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1827d38ceaf9SAlex Deucher } 1828d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1829d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1830d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1831d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1832d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1833d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1834d38ceaf9SAlex Deucher break; 1835d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1836d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1837d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1838d38ceaf9SAlex Deucher goto failed; 1839d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1840d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1841d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1842d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1843d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1844d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1845d38ceaf9SAlex Deucher has_aux = true; 1846d38ceaf9SAlex Deucher else 1847d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1848d38ceaf9SAlex Deucher } 1849d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1850d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1851d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1852d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1853d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1854d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1855d38ceaf9SAlex Deucher break; 1856d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1857d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1858d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1859d38ceaf9SAlex Deucher goto failed; 1860d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1861d38ceaf9SAlex Deucher drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1862d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1863d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1864d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1865d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1866d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1867d38ceaf9SAlex Deucher } 1868d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1869d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1870d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1871d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1872d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1873d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1874d38ceaf9SAlex Deucher break; 1875d38ceaf9SAlex Deucher } 1876d38ceaf9SAlex Deucher } 1877d38ceaf9SAlex Deucher 1878d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1879b636a1b3SLyude if (i2c_bus->valid) { 1880b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1881b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT; 1882b636a1b3SLyude } 1883d38ceaf9SAlex Deucher } else 1884d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 1885d38ceaf9SAlex Deucher 1886d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 1887d38ceaf9SAlex Deucher drm_connector_register(connector); 1888d38ceaf9SAlex Deucher 1889d38ceaf9SAlex Deucher if (has_aux) 1890d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 1891d38ceaf9SAlex Deucher 1892d38ceaf9SAlex Deucher return; 1893d38ceaf9SAlex Deucher 1894d38ceaf9SAlex Deucher failed: 1895d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 1896d38ceaf9SAlex Deucher kfree(connector); 1897d38ceaf9SAlex Deucher } 1898