1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26fdf2f6c5SSam Ravnborg 27d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 28d38ceaf9SAlex Deucher #include <drm/drm_fb_helper.h> 2965bf2cf9SOleg Vasilev #include <drm/drm_dp_helper.h> 30fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 31d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 32d38ceaf9SAlex Deucher #include "amdgpu.h" 33d38ceaf9SAlex Deucher #include "atom.h" 34d38ceaf9SAlex Deucher #include "atombios_encoders.h" 35d38ceaf9SAlex Deucher #include "atombios_dp.h" 36d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 37d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 385df58525SHuang Rui #include "amdgpu_display.h" 39d38ceaf9SAlex Deucher 40d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 41d38ceaf9SAlex Deucher 42d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 43d38ceaf9SAlex Deucher { 44d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 451348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 46d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 47d38ceaf9SAlex Deucher 48d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 49d38ceaf9SAlex Deucher * VGA, TV, etc. 50d38ceaf9SAlex Deucher */ 51d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 52d38ceaf9SAlex Deucher return; 53d38ceaf9SAlex Deucher 54d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 55d38ceaf9SAlex Deucher 56d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 57d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 58d38ceaf9SAlex Deucher return; 59d38ceaf9SAlex Deucher 60d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 61d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 62d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 63d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 64d38ceaf9SAlex Deucher 65d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 66d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 67d38ceaf9SAlex Deucher return; 68d38ceaf9SAlex Deucher 69d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 70d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 71d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 72d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 73d38ceaf9SAlex Deucher */ 74daf88096SMichel Dänzer if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 75daf88096SMichel Dänzer amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 76daf88096SMichel Dänzer amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 77daf88096SMichel Dänzer /* Don't start link training before we have the DPCD */ 780b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 79a887adadSAlex Deucher return; 80a887adadSAlex Deucher 81daf88096SMichel Dänzer /* Turn the connector off and back on immediately, which 82daf88096SMichel Dänzer * will trigger link training 83d38ceaf9SAlex Deucher */ 84daf88096SMichel Dänzer drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 85d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 86d38ceaf9SAlex Deucher } 87d38ceaf9SAlex Deucher } 88d38ceaf9SAlex Deucher } 89d38ceaf9SAlex Deucher 90d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 91d38ceaf9SAlex Deucher { 92d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 93d38ceaf9SAlex Deucher 94d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 95d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 96d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 97d38ceaf9SAlex Deucher } 98d38ceaf9SAlex Deucher } 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 101d38ceaf9SAlex Deucher { 102d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 103d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 104d38ceaf9SAlex Deucher int bpc = 8; 105d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock; 106d38ceaf9SAlex Deucher 107d38ceaf9SAlex Deucher switch (connector->connector_type) { 108d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 109d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 110d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 111*3c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 112d38ceaf9SAlex Deucher if (connector->display_info.bpc) 113d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 114d38ceaf9SAlex Deucher } 115d38ceaf9SAlex Deucher } 116d38ceaf9SAlex Deucher break; 117d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 118d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 119*3c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 120d38ceaf9SAlex Deucher if (connector->display_info.bpc) 121d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 122d38ceaf9SAlex Deucher } 123d38ceaf9SAlex Deucher break; 124d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 125d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 126d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 127d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 128*3c021931SClaudio Suarez connector->display_info.is_hdmi) { 129d38ceaf9SAlex Deucher if (connector->display_info.bpc) 130d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 131d38ceaf9SAlex Deucher } 132d38ceaf9SAlex Deucher break; 133d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 134d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 135d38ceaf9SAlex Deucher if (connector->display_info.bpc) 136d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 137d38ceaf9SAlex Deucher else { 13817b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = 139d38ceaf9SAlex Deucher connector->helper_private; 140d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 141d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 142d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 143d38ceaf9SAlex Deucher 144d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 145d38ceaf9SAlex Deucher bpc = 6; 146d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 147d38ceaf9SAlex Deucher bpc = 8; 148d38ceaf9SAlex Deucher } 149d38ceaf9SAlex Deucher break; 150d38ceaf9SAlex Deucher } 151d38ceaf9SAlex Deucher 152*3c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 153d38ceaf9SAlex Deucher /* 154d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 155d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 156d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 157d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 158d38ceaf9SAlex Deucher */ 159d38ceaf9SAlex Deucher if (bpc > 12) { 160d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 161d38ceaf9SAlex Deucher connector->name, bpc); 162d38ceaf9SAlex Deucher bpc = 12; 163d38ceaf9SAlex Deucher } 164d38ceaf9SAlex Deucher 165d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 1662a272ca9SVille Syrjälä if (connector->display_info.max_tmds_clock > 0) { 167d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 168d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 169d38ceaf9SAlex Deucher 170d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 1712a272ca9SVille Syrjälä max_tmds_clock = connector->display_info.max_tmds_clock; 172d38ceaf9SAlex Deucher 173d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 174d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 175d38ceaf9SAlex Deucher 176d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 177d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 178d38ceaf9SAlex Deucher if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 179d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 180d38ceaf9SAlex Deucher bpc = 10; 181d38ceaf9SAlex Deucher else 182d38ceaf9SAlex Deucher bpc = 8; 183d38ceaf9SAlex Deucher 184d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 185d38ceaf9SAlex Deucher connector->name, bpc); 186d38ceaf9SAlex Deucher } 187d38ceaf9SAlex Deucher 188d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 189d38ceaf9SAlex Deucher bpc = 8; 190d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 191d38ceaf9SAlex Deucher connector->name, bpc); 1929d746ab6SMario Kleiner } 193d38ceaf9SAlex Deucher } else if (bpc > 8) { 194d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 195d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 196d38ceaf9SAlex Deucher connector->name); 197d38ceaf9SAlex Deucher bpc = 8; 198d38ceaf9SAlex Deucher } 199d38ceaf9SAlex Deucher } 200d38ceaf9SAlex Deucher 201d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 202d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 203d38ceaf9SAlex Deucher connector->name); 204d38ceaf9SAlex Deucher bpc = 8; 205d38ceaf9SAlex Deucher } 206d38ceaf9SAlex Deucher 207d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 208d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 209d38ceaf9SAlex Deucher 210d38ceaf9SAlex Deucher return bpc; 211d38ceaf9SAlex Deucher } 212d38ceaf9SAlex Deucher 213d38ceaf9SAlex Deucher static void 214d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 215d38ceaf9SAlex Deucher enum drm_connector_status status) 216d38ceaf9SAlex Deucher { 21798c0e348SVille Syrjälä struct drm_encoder *best_encoder; 21898c0e348SVille Syrjälä struct drm_encoder *encoder; 21917b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 220d38ceaf9SAlex Deucher bool connected; 221d38ceaf9SAlex Deucher 222d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 223d38ceaf9SAlex Deucher 22462afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 225d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 226d38ceaf9SAlex Deucher connected = true; 227d38ceaf9SAlex Deucher else 228d38ceaf9SAlex Deucher connected = false; 229d38ceaf9SAlex Deucher 230d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 231d38ceaf9SAlex Deucher } 232d38ceaf9SAlex Deucher } 233d38ceaf9SAlex Deucher 234d38ceaf9SAlex Deucher static struct drm_encoder * 235d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 236d38ceaf9SAlex Deucher int encoder_type) 237d38ceaf9SAlex Deucher { 238d38ceaf9SAlex Deucher struct drm_encoder *encoder; 239d38ceaf9SAlex Deucher 24062afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 241d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 242d38ceaf9SAlex Deucher return encoder; 243d38ceaf9SAlex Deucher } 24498c0e348SVille Syrjälä 245d38ceaf9SAlex Deucher return NULL; 246d38ceaf9SAlex Deucher } 247d38ceaf9SAlex Deucher 248d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector) 249d38ceaf9SAlex Deucher { 250d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 251d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 252d38ceaf9SAlex Deucher 253d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 254d38ceaf9SAlex Deucher return amdgpu_connector->edid; 255d38ceaf9SAlex Deucher } else if (edid_blob) { 256d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 257d38ceaf9SAlex Deucher if (edid) 258d38ceaf9SAlex Deucher amdgpu_connector->edid = edid; 259d38ceaf9SAlex Deucher } 260d38ceaf9SAlex Deucher return amdgpu_connector->edid; 261d38ceaf9SAlex Deucher } 262d38ceaf9SAlex Deucher 263d38ceaf9SAlex Deucher static struct edid * 264d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 265d38ceaf9SAlex Deucher { 266d38ceaf9SAlex Deucher struct edid *edid; 267d38ceaf9SAlex Deucher 268d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 269d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 270d38ceaf9SAlex Deucher if (edid) { 271d38ceaf9SAlex Deucher memcpy((unsigned char *)edid, 272d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid, 273d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size); 274d38ceaf9SAlex Deucher return edid; 275d38ceaf9SAlex Deucher } 276d38ceaf9SAlex Deucher } 277d38ceaf9SAlex Deucher return NULL; 278d38ceaf9SAlex Deucher } 279d38ceaf9SAlex Deucher 280d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 281d38ceaf9SAlex Deucher { 282d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 2831348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 284d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 285d38ceaf9SAlex Deucher 286d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 287d38ceaf9SAlex Deucher return; 288d38ceaf9SAlex Deucher 289d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 290d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 291d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 292d38ceaf9SAlex Deucher 293d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 294d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 295d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 296d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 297d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 298d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 299d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 300d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 301d38ceaf9SAlex Deucher 302d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 303d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 304d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 305d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 306d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 307d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 308d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 309d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 310d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 311d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 312d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 313d38ceaf9SAlex Deucher } 314d38ceaf9SAlex Deucher 315d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 316d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 317d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 31820543be9SClaudio Suarez (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 319d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 32020543be9SClaudio Suarez drm_connector_update_edid_property(connector, amdgpu_connector->edid); 32120543be9SClaudio Suarez } 322d38ceaf9SAlex Deucher } 323d38ceaf9SAlex Deucher } 324d38ceaf9SAlex Deucher 325d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 326d38ceaf9SAlex Deucher { 327d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 328d38ceaf9SAlex Deucher 329d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 330d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 33120543be9SClaudio Suarez drm_connector_update_edid_property(connector, NULL); 332d38ceaf9SAlex Deucher } 333d38ceaf9SAlex Deucher 334d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 335d38ceaf9SAlex Deucher { 336d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 337d38ceaf9SAlex Deucher int ret; 338d38ceaf9SAlex Deucher 339d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 340c555f023SDaniel Vetter drm_connector_update_edid_property(connector, amdgpu_connector->edid); 341d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 342d38ceaf9SAlex Deucher return ret; 343d38ceaf9SAlex Deucher } 344c555f023SDaniel Vetter drm_connector_update_edid_property(connector, NULL); 345d38ceaf9SAlex Deucher return 0; 346d38ceaf9SAlex Deucher } 347d38ceaf9SAlex Deucher 348d38ceaf9SAlex Deucher static struct drm_encoder * 349d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 350d38ceaf9SAlex Deucher { 35198c0e348SVille Syrjälä struct drm_encoder *encoder; 352d38ceaf9SAlex Deucher 35398c0e348SVille Syrjälä /* pick the first one */ 35462afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) 35598c0e348SVille Syrjälä return encoder; 35698c0e348SVille Syrjälä 357d38ceaf9SAlex Deucher return NULL; 358d38ceaf9SAlex Deucher } 359d38ceaf9SAlex Deucher 360d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 361d38ceaf9SAlex Deucher { 362d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 363d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 364d38ceaf9SAlex Deucher 365d38ceaf9SAlex Deucher if (encoder == NULL) 366d38ceaf9SAlex Deucher return; 367d38ceaf9SAlex Deucher 368d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 369d38ceaf9SAlex Deucher 370d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 371d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 372d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 373d38ceaf9SAlex Deucher struct drm_display_mode, head); 374d38ceaf9SAlex Deucher 375d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 376d38ceaf9SAlex Deucher } else { 377d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 378d38ceaf9SAlex Deucher } 379d38ceaf9SAlex Deucher } 380d38ceaf9SAlex Deucher 381d38ceaf9SAlex Deucher static struct drm_display_mode * 382d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 383d38ceaf9SAlex Deucher { 384d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 385d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 386d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 387d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 388d38ceaf9SAlex Deucher 389d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 390d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 391d38ceaf9SAlex Deucher native_mode->clock != 0) { 392d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 393b220110eSZhou Qingyang if (!mode) 394b220110eSZhou Qingyang return NULL; 395b220110eSZhou Qingyang 396d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 397d38ceaf9SAlex Deucher drm_mode_set_name(mode); 398d38ceaf9SAlex Deucher 399d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 400d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 401d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 402d38ceaf9SAlex Deucher /* mac laptops without an edid */ 403d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 404d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 405d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 406d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 407d38ceaf9SAlex Deucher * simpler. 408d38ceaf9SAlex Deucher */ 409d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 410b220110eSZhou Qingyang if (!mode) 411b220110eSZhou Qingyang return NULL; 412b220110eSZhou Qingyang 413d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 414d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 415d38ceaf9SAlex Deucher } 416d38ceaf9SAlex Deucher return mode; 417d38ceaf9SAlex Deucher } 418d38ceaf9SAlex Deucher 419d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 420d38ceaf9SAlex Deucher struct drm_connector *connector) 421d38ceaf9SAlex Deucher { 422d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 423d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 424d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 425d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 426d38ceaf9SAlex Deucher int i; 427aeba709aSNils Wallménius static const struct mode_size { 428d38ceaf9SAlex Deucher int w; 429d38ceaf9SAlex Deucher int h; 430d38ceaf9SAlex Deucher } common_modes[17] = { 431d38ceaf9SAlex Deucher { 640, 480}, 432d38ceaf9SAlex Deucher { 720, 480}, 433d38ceaf9SAlex Deucher { 800, 600}, 434d38ceaf9SAlex Deucher { 848, 480}, 435d38ceaf9SAlex Deucher {1024, 768}, 436d38ceaf9SAlex Deucher {1152, 768}, 437d38ceaf9SAlex Deucher {1280, 720}, 438d38ceaf9SAlex Deucher {1280, 800}, 439d38ceaf9SAlex Deucher {1280, 854}, 440d38ceaf9SAlex Deucher {1280, 960}, 441d38ceaf9SAlex Deucher {1280, 1024}, 442d38ceaf9SAlex Deucher {1440, 900}, 443d38ceaf9SAlex Deucher {1400, 1050}, 444d38ceaf9SAlex Deucher {1680, 1050}, 445d38ceaf9SAlex Deucher {1600, 1200}, 446d38ceaf9SAlex Deucher {1920, 1080}, 447d38ceaf9SAlex Deucher {1920, 1200} 448d38ceaf9SAlex Deucher }; 449d38ceaf9SAlex Deucher 450d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 451d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 452d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 453d38ceaf9SAlex Deucher common_modes[i].h > 768) 454d38ceaf9SAlex Deucher continue; 455d38ceaf9SAlex Deucher } 456d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 457d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 458d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 459d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 460d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 461d38ceaf9SAlex Deucher continue; 462d38ceaf9SAlex Deucher } 463d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 464d38ceaf9SAlex Deucher continue; 465d38ceaf9SAlex Deucher 466d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 467d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 468d38ceaf9SAlex Deucher } 469d38ceaf9SAlex Deucher } 470d38ceaf9SAlex Deucher 471d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 472d38ceaf9SAlex Deucher struct drm_property *property, 473d38ceaf9SAlex Deucher uint64_t val) 474d38ceaf9SAlex Deucher { 475d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 4761348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 477d38ceaf9SAlex Deucher struct drm_encoder *encoder; 478d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 479d38ceaf9SAlex Deucher 480d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 481d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 482d38ceaf9SAlex Deucher bool new_coherent_mode; 483d38ceaf9SAlex Deucher 484d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 485d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 486d38ceaf9SAlex Deucher if (!encoder) 487d38ceaf9SAlex Deucher return 0; 488d38ceaf9SAlex Deucher 489d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 490d38ceaf9SAlex Deucher 491d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 492d38ceaf9SAlex Deucher return 0; 493d38ceaf9SAlex Deucher 494d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 495d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 496d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 497d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 498d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 499d38ceaf9SAlex Deucher } 500d38ceaf9SAlex Deucher } 501d38ceaf9SAlex Deucher 502d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 503d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 504d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 505d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 506d38ceaf9SAlex Deucher if (!encoder) 507d38ceaf9SAlex Deucher return 0; 508d38ceaf9SAlex Deucher 509d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 510d38ceaf9SAlex Deucher 511d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 512d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 513d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 514d38ceaf9SAlex Deucher } 515d38ceaf9SAlex Deucher } 516d38ceaf9SAlex Deucher 517d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 518d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 519d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 520d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 521d38ceaf9SAlex Deucher if (!encoder) 522d38ceaf9SAlex Deucher return 0; 523d38ceaf9SAlex Deucher 524d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 525d38ceaf9SAlex Deucher 526d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 527d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 528d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 529d38ceaf9SAlex Deucher } 530d38ceaf9SAlex Deucher } 531d38ceaf9SAlex Deucher 532d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 533d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 534d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 535d38ceaf9SAlex Deucher if (!encoder) 536d38ceaf9SAlex Deucher return 0; 537d38ceaf9SAlex Deucher 538d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 539d38ceaf9SAlex Deucher 540d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 541d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 542d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 543d38ceaf9SAlex Deucher } 544d38ceaf9SAlex Deucher } 545d38ceaf9SAlex Deucher 546d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 547d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 548d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 549d38ceaf9SAlex Deucher if (!encoder) 550d38ceaf9SAlex Deucher return 0; 551d38ceaf9SAlex Deucher 552d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 553d38ceaf9SAlex Deucher 554d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 555d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 556d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 557d38ceaf9SAlex Deucher } 558d38ceaf9SAlex Deucher } 559d38ceaf9SAlex Deucher 560d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 561d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 562d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 563d38ceaf9SAlex Deucher if (!encoder) 564d38ceaf9SAlex Deucher return 0; 565d38ceaf9SAlex Deucher 566d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 567d38ceaf9SAlex Deucher 568d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 569d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 570d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 571d38ceaf9SAlex Deucher } 572d38ceaf9SAlex Deucher } 573d38ceaf9SAlex Deucher 574d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 575d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 576d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 577d38ceaf9SAlex Deucher 578d38ceaf9SAlex Deucher if (val == 0) 579d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 580d38ceaf9SAlex Deucher else 581d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 582d38ceaf9SAlex Deucher } 583d38ceaf9SAlex Deucher 584d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 585d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 586d38ceaf9SAlex Deucher 587d38ceaf9SAlex Deucher if (connector->encoder) { 588d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 589d38ceaf9SAlex Deucher } else { 59017b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 591d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 592d38ceaf9SAlex Deucher } 593d38ceaf9SAlex Deucher 594d38ceaf9SAlex Deucher switch (val) { 595d38ceaf9SAlex Deucher default: 596d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 597d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 598d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 599d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 600d38ceaf9SAlex Deucher } 601d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 602d38ceaf9SAlex Deucher return 0; 603d38ceaf9SAlex Deucher 604d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 605d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 606d38ceaf9SAlex Deucher return 0; 607d38ceaf9SAlex Deucher 608d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 609d38ceaf9SAlex Deucher 610d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 611d38ceaf9SAlex Deucher } 612d38ceaf9SAlex Deucher 613d38ceaf9SAlex Deucher return 0; 614d38ceaf9SAlex Deucher } 615d38ceaf9SAlex Deucher 616d38ceaf9SAlex Deucher static void 617d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 618d38ceaf9SAlex Deucher struct drm_connector *connector) 619d38ceaf9SAlex Deucher { 620d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 621d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 622d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 623d38ceaf9SAlex Deucher 624d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 625d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 626d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 627d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 628d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 629d38ceaf9SAlex Deucher memcpy(native_mode, mode, sizeof(*mode)); 630d38ceaf9SAlex Deucher } 631d38ceaf9SAlex Deucher } 632d38ceaf9SAlex Deucher 633d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 634d38ceaf9SAlex Deucher if (!native_mode->clock) { 635d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 636d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 637d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 638d38ceaf9SAlex Deucher *native_mode = *mode; 639d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 640d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 641d38ceaf9SAlex Deucher break; 642d38ceaf9SAlex Deucher } 643d38ceaf9SAlex Deucher } 644d38ceaf9SAlex Deucher } 645d38ceaf9SAlex Deucher 646d38ceaf9SAlex Deucher if (!native_mode->clock) { 647d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 648d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 649d38ceaf9SAlex Deucher } 650d38ceaf9SAlex Deucher } 651d38ceaf9SAlex Deucher 652d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 653d38ceaf9SAlex Deucher { 654d38ceaf9SAlex Deucher struct drm_encoder *encoder; 655d38ceaf9SAlex Deucher int ret = 0; 656d38ceaf9SAlex Deucher struct drm_display_mode *mode; 657d38ceaf9SAlex Deucher 658d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 659d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 660d38ceaf9SAlex Deucher if (ret > 0) { 661d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 662d38ceaf9SAlex Deucher if (encoder) { 663d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 664d38ceaf9SAlex Deucher /* add scaled modes */ 665d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 666d38ceaf9SAlex Deucher } 667d38ceaf9SAlex Deucher return ret; 668d38ceaf9SAlex Deucher } 669d38ceaf9SAlex Deucher 670d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 671d38ceaf9SAlex Deucher if (!encoder) 672d38ceaf9SAlex Deucher return 0; 673d38ceaf9SAlex Deucher 674d38ceaf9SAlex Deucher /* we have no EDID modes */ 675d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 676d38ceaf9SAlex Deucher if (mode) { 677d38ceaf9SAlex Deucher ret = 1; 678d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 679d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 680d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 681d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 682d38ceaf9SAlex Deucher /* add scaled modes */ 683d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 684d38ceaf9SAlex Deucher } 685d38ceaf9SAlex Deucher 686d38ceaf9SAlex Deucher return ret; 687d38ceaf9SAlex Deucher } 688d38ceaf9SAlex Deucher 689ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 690d38ceaf9SAlex Deucher struct drm_display_mode *mode) 691d38ceaf9SAlex Deucher { 692d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 693d38ceaf9SAlex Deucher 694d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 695d38ceaf9SAlex Deucher return MODE_PANEL; 696d38ceaf9SAlex Deucher 697d38ceaf9SAlex Deucher if (encoder) { 698d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 699d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 700d38ceaf9SAlex Deucher 701d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 702d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 703d38ceaf9SAlex Deucher */ 704d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 705d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 706d38ceaf9SAlex Deucher return MODE_PANEL; 707d38ceaf9SAlex Deucher 708d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 709d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 710d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 711d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 712d38ceaf9SAlex Deucher return MODE_PANEL; 713d38ceaf9SAlex Deucher } 714d38ceaf9SAlex Deucher } 715d38ceaf9SAlex Deucher 716d38ceaf9SAlex Deucher return MODE_OK; 717d38ceaf9SAlex Deucher } 718d38ceaf9SAlex Deucher 719d38ceaf9SAlex Deucher static enum drm_connector_status 720d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 721d38ceaf9SAlex Deucher { 722d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 723d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 724d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 725d38ceaf9SAlex Deucher int r; 726d38ceaf9SAlex Deucher 727aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 728d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 729f79f9476SNavid Emamdoost if (r < 0) { 730f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 731d38ceaf9SAlex Deucher return connector_status_disconnected; 732aa0aad57SLukas Wunner } 733f79f9476SNavid Emamdoost } 734d38ceaf9SAlex Deucher 735d38ceaf9SAlex Deucher if (encoder) { 736d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 737d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 738d38ceaf9SAlex Deucher 739d38ceaf9SAlex Deucher /* check if panel is valid */ 740d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 741d38ceaf9SAlex Deucher ret = connector_status_connected; 742d38ceaf9SAlex Deucher 743d38ceaf9SAlex Deucher } 744d38ceaf9SAlex Deucher 745d38ceaf9SAlex Deucher /* check for edid as well */ 746d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 747d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 748d38ceaf9SAlex Deucher ret = connector_status_connected; 749d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 750d38ceaf9SAlex Deucher 751d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 752aa0aad57SLukas Wunner 753aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 754d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 755d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 756aa0aad57SLukas Wunner } 757aa0aad57SLukas Wunner 758d38ceaf9SAlex Deucher return ret; 759d38ceaf9SAlex Deucher } 760d38ceaf9SAlex Deucher 76140492f60SGrazvydas Ignotas static void amdgpu_connector_unregister(struct drm_connector *connector) 762d38ceaf9SAlex Deucher { 763d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 764d38ceaf9SAlex Deucher 765eef2b411SAlex Deucher if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 766d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 7672f9ba199SGrazvydas Ignotas amdgpu_connector->ddc_bus->has_aux = false; 7682f9ba199SGrazvydas Ignotas } 76940492f60SGrazvydas Ignotas } 77040492f60SGrazvydas Ignotas 77140492f60SGrazvydas Ignotas static void amdgpu_connector_destroy(struct drm_connector *connector) 77240492f60SGrazvydas Ignotas { 77340492f60SGrazvydas Ignotas struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 77440492f60SGrazvydas Ignotas 775d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 776d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 777d38ceaf9SAlex Deucher drm_connector_unregister(connector); 778d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 779d38ceaf9SAlex Deucher kfree(connector); 780d38ceaf9SAlex Deucher } 781d38ceaf9SAlex Deucher 782d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 783d38ceaf9SAlex Deucher struct drm_property *property, 784d38ceaf9SAlex Deucher uint64_t value) 785d38ceaf9SAlex Deucher { 786d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 787d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 788d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 789d38ceaf9SAlex Deucher 790d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 791d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 792d38ceaf9SAlex Deucher return 0; 793d38ceaf9SAlex Deucher 794d38ceaf9SAlex Deucher if (connector->encoder) 795d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 796d38ceaf9SAlex Deucher else { 79717b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 798d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 799d38ceaf9SAlex Deucher } 800d38ceaf9SAlex Deucher 801d38ceaf9SAlex Deucher switch (value) { 802d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 803d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 804d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 805d38ceaf9SAlex Deucher default: 806d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 807d38ceaf9SAlex Deucher } 808d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 809d38ceaf9SAlex Deucher return 0; 810d38ceaf9SAlex Deucher 811d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 812d38ceaf9SAlex Deucher 813d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 814d38ceaf9SAlex Deucher return 0; 815d38ceaf9SAlex Deucher } 816d38ceaf9SAlex Deucher 817d38ceaf9SAlex Deucher 818d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 819d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 820d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 821d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 822d38ceaf9SAlex Deucher }; 823d38ceaf9SAlex Deucher 824d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 825d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 826d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 827d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 82840492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 829d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 830d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 831d38ceaf9SAlex Deucher }; 832d38ceaf9SAlex Deucher 833d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 834d38ceaf9SAlex Deucher { 835d38ceaf9SAlex Deucher int ret; 836d38ceaf9SAlex Deucher 837d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 838d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 8396c5af7d2Shongao amdgpu_get_native_mode(connector); 840d38ceaf9SAlex Deucher 841d38ceaf9SAlex Deucher return ret; 842d38ceaf9SAlex Deucher } 843d38ceaf9SAlex Deucher 844ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 845d38ceaf9SAlex Deucher struct drm_display_mode *mode) 846d38ceaf9SAlex Deucher { 847d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 8481348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 849d38ceaf9SAlex Deucher 850d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 851d38ceaf9SAlex Deucher 852d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 853d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 854d38ceaf9SAlex Deucher 855d38ceaf9SAlex Deucher return MODE_OK; 856d38ceaf9SAlex Deucher } 857d38ceaf9SAlex Deucher 858d38ceaf9SAlex Deucher static enum drm_connector_status 859d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 860d38ceaf9SAlex Deucher { 861d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 862d38ceaf9SAlex Deucher struct drm_encoder *encoder; 86317b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 864d38ceaf9SAlex Deucher bool dret = false; 865d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 866d38ceaf9SAlex Deucher int r; 867d38ceaf9SAlex Deucher 868aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 869d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 870f79f9476SNavid Emamdoost if (r < 0) { 871f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 872d38ceaf9SAlex Deucher return connector_status_disconnected; 873aa0aad57SLukas Wunner } 874f79f9476SNavid Emamdoost } 875d38ceaf9SAlex Deucher 876d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 877d38ceaf9SAlex Deucher if (!encoder) 878d38ceaf9SAlex Deucher ret = connector_status_disconnected; 879d38ceaf9SAlex Deucher 880d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 881e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 882d38ceaf9SAlex Deucher if (dret) { 883d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 884d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 885d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 886d38ceaf9SAlex Deucher 887d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 888d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 889d38ceaf9SAlex Deucher connector->name); 890d38ceaf9SAlex Deucher ret = connector_status_connected; 891d38ceaf9SAlex Deucher } else { 892d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 893d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 894d38ceaf9SAlex Deucher 895d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 896d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 897d38ceaf9SAlex Deucher */ 898d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 899d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 900d38ceaf9SAlex Deucher ret = connector_status_disconnected; 901d38ceaf9SAlex Deucher } else { 902d38ceaf9SAlex Deucher ret = connector_status_connected; 903d38ceaf9SAlex Deucher } 904d38ceaf9SAlex Deucher } 905d38ceaf9SAlex Deucher } else { 906d38ceaf9SAlex Deucher 907d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 908d38ceaf9SAlex Deucher if (!force) { 909d38ceaf9SAlex Deucher /* only return the previous status if we last 910d38ceaf9SAlex Deucher * detected a monitor via load. 911d38ceaf9SAlex Deucher */ 912d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 913d38ceaf9SAlex Deucher ret = connector->status; 914d38ceaf9SAlex Deucher goto out; 915d38ceaf9SAlex Deucher } 916d38ceaf9SAlex Deucher 917d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 918d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 919d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 920d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 921d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 922d38ceaf9SAlex Deucher } 923d38ceaf9SAlex Deucher } 924d38ceaf9SAlex Deucher 925d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 926d38ceaf9SAlex Deucher 927d38ceaf9SAlex Deucher out: 928aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 929d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 930d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 931aa0aad57SLukas Wunner } 932d38ceaf9SAlex Deucher 933d38ceaf9SAlex Deucher return ret; 934d38ceaf9SAlex Deucher } 935d38ceaf9SAlex Deucher 936d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 937d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 938d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 939d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 940d38ceaf9SAlex Deucher }; 941d38ceaf9SAlex Deucher 942d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 943d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 944d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 945d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 94640492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 947d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 948d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 949d38ceaf9SAlex Deucher }; 950d38ceaf9SAlex Deucher 951d38ceaf9SAlex Deucher static bool 952d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 953d38ceaf9SAlex Deucher { 954d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 9551348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 956d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 957d38ceaf9SAlex Deucher enum drm_connector_status status; 958d38ceaf9SAlex Deucher 959d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 960d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 961d38ceaf9SAlex Deucher status = connector_status_connected; 962d38ceaf9SAlex Deucher else 963d38ceaf9SAlex Deucher status = connector_status_disconnected; 964d38ceaf9SAlex Deucher if (connector->status == status) 965d38ceaf9SAlex Deucher return true; 966d38ceaf9SAlex Deucher } 967d38ceaf9SAlex Deucher 968d38ceaf9SAlex Deucher return false; 969d38ceaf9SAlex Deucher } 970d38ceaf9SAlex Deucher 971d38ceaf9SAlex Deucher /* 972d38ceaf9SAlex Deucher * DVI is complicated 973d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 974d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 975d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 976d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 977d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 978d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 979d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 980d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 981d38ceaf9SAlex Deucher */ 982d38ceaf9SAlex Deucher static enum drm_connector_status 983d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 984d38ceaf9SAlex Deucher { 985d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 9861348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 987d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 98817b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 98998c0e348SVille Syrjälä int r; 990d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 991d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 992d38ceaf9SAlex Deucher 993aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 994d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 995f79f9476SNavid Emamdoost if (r < 0) { 996f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 997d38ceaf9SAlex Deucher return connector_status_disconnected; 998aa0aad57SLukas Wunner } 999f79f9476SNavid Emamdoost } 1000d38ceaf9SAlex Deucher 1001d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1002d38ceaf9SAlex Deucher ret = connector->status; 1003d38ceaf9SAlex Deucher goto exit; 1004d38ceaf9SAlex Deucher } 1005d38ceaf9SAlex Deucher 1006d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 1007e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1008d38ceaf9SAlex Deucher if (dret) { 1009d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 1010d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1011d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1012d38ceaf9SAlex Deucher 1013d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 1014d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1015d38ceaf9SAlex Deucher connector->name); 1016d38ceaf9SAlex Deucher ret = connector_status_connected; 1017d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1018d38ceaf9SAlex Deucher } else { 1019d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1020d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1021d38ceaf9SAlex Deucher 1022d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1023d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1024d38ceaf9SAlex Deucher */ 1025d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1026d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1027d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1028d38ceaf9SAlex Deucher } else { 1029d38ceaf9SAlex Deucher ret = connector_status_connected; 1030d38ceaf9SAlex Deucher } 1031d38ceaf9SAlex Deucher 1032d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1033d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1034d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1035d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1036d38ceaf9SAlex Deucher */ 1037d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1038d38ceaf9SAlex Deucher struct drm_connector *list_connector; 1039f8d2d39eSLyude Paul struct drm_connector_list_iter iter; 1040d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector; 1041f8d2d39eSLyude Paul 1042f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter); 1043f8d2d39eSLyude Paul drm_for_each_connector_iter(list_connector, 1044f8d2d39eSLyude Paul &iter) { 1045d38ceaf9SAlex Deucher if (connector == list_connector) 1046d38ceaf9SAlex Deucher continue; 1047d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector); 1048d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc && 1049d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1050d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) { 1051d38ceaf9SAlex Deucher /* cases where both connectors are digital */ 1052d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1053d38ceaf9SAlex Deucher /* hpd is our only option in this case */ 1054d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1055d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1056d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1057d38ceaf9SAlex Deucher } 1058d38ceaf9SAlex Deucher } 1059d38ceaf9SAlex Deucher } 1060d38ceaf9SAlex Deucher } 1061f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1062d38ceaf9SAlex Deucher } 1063d38ceaf9SAlex Deucher } 1064d38ceaf9SAlex Deucher } 1065d38ceaf9SAlex Deucher 1066d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1067d38ceaf9SAlex Deucher goto out; 1068d38ceaf9SAlex Deucher 1069d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1070d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1071d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1072d38ceaf9SAlex Deucher goto out; 1073d38ceaf9SAlex Deucher 1074d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1075d38ceaf9SAlex Deucher if (!force) { 1076d38ceaf9SAlex Deucher /* only return the previous status if we last 1077d38ceaf9SAlex Deucher * detected a monitor via load. 1078d38ceaf9SAlex Deucher */ 1079d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1080d38ceaf9SAlex Deucher ret = connector->status; 1081d38ceaf9SAlex Deucher goto out; 1082d38ceaf9SAlex Deucher } 1083d38ceaf9SAlex Deucher 1084d38ceaf9SAlex Deucher /* find analog encoder */ 1085d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 108698c0e348SVille Syrjälä struct drm_encoder *encoder; 1087d38ceaf9SAlex Deucher 108862afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1089d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1090d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1091d38ceaf9SAlex Deucher continue; 1092d38ceaf9SAlex Deucher 1093d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1094d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1095d38ceaf9SAlex Deucher if (!broken_edid) { 1096d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1097d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1098d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1099d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1100d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1101d38ceaf9SAlex Deucher } 1102d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1103d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1104d38ceaf9SAlex Deucher } 1105d38ceaf9SAlex Deucher } else { 1106d38ceaf9SAlex Deucher enum drm_connector_status lret; 1107d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1108d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1109d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1110d38ceaf9SAlex Deucher DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1111d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1112d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1113d38ceaf9SAlex Deucher } 1114d38ceaf9SAlex Deucher break; 1115d38ceaf9SAlex Deucher } 1116d38ceaf9SAlex Deucher } 1117d38ceaf9SAlex Deucher } 1118d38ceaf9SAlex Deucher 1119d38ceaf9SAlex Deucher out: 1120d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1121d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1122d38ceaf9SAlex Deucher 1123d38ceaf9SAlex Deucher exit: 1124aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1125d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1126d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1127aa0aad57SLukas Wunner } 1128d38ceaf9SAlex Deucher 1129d38ceaf9SAlex Deucher return ret; 1130d38ceaf9SAlex Deucher } 1131d38ceaf9SAlex Deucher 1132d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1133d38ceaf9SAlex Deucher static struct drm_encoder * 1134d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1135d38ceaf9SAlex Deucher { 1136d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1137d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1138d38ceaf9SAlex Deucher 113962afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1140d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1141d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1142d38ceaf9SAlex Deucher return encoder; 1143d38ceaf9SAlex Deucher } else { 1144d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1145d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1146d38ceaf9SAlex Deucher return encoder; 1147d38ceaf9SAlex Deucher } 1148d38ceaf9SAlex Deucher } 1149d38ceaf9SAlex Deucher 1150d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1151d38ceaf9SAlex Deucher 1152d38ceaf9SAlex Deucher /* then check use digitial */ 1153d38ceaf9SAlex Deucher /* pick the first one */ 115462afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) 115598c0e348SVille Syrjälä return encoder; 115698c0e348SVille Syrjälä 1157d38ceaf9SAlex Deucher return NULL; 1158d38ceaf9SAlex Deucher } 1159d38ceaf9SAlex Deucher 1160d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1161d38ceaf9SAlex Deucher { 1162d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1163d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1164d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1165d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1166d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1167d38ceaf9SAlex Deucher } 1168d38ceaf9SAlex Deucher 1169ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1170d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1171d38ceaf9SAlex Deucher { 1172d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 11731348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1174d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1175d38ceaf9SAlex Deucher 1176d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1177d38ceaf9SAlex Deucher 1178d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1179d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1180d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1181d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1182d38ceaf9SAlex Deucher return MODE_OK; 1183*3c021931SClaudio Suarez } else if (connector->display_info.is_hdmi) { 1184d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1185d38ceaf9SAlex Deucher if (mode->clock > 340000) 1186d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1187d38ceaf9SAlex Deucher else 1188d38ceaf9SAlex Deucher return MODE_OK; 1189d38ceaf9SAlex Deucher } else { 1190d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1191d38ceaf9SAlex Deucher } 1192d38ceaf9SAlex Deucher } 1193d38ceaf9SAlex Deucher 1194d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1195d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1196d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1197d38ceaf9SAlex Deucher 1198d38ceaf9SAlex Deucher return MODE_OK; 1199d38ceaf9SAlex Deucher } 1200d38ceaf9SAlex Deucher 1201d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1202d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1203d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1204d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1205d38ceaf9SAlex Deucher }; 1206d38ceaf9SAlex Deucher 1207d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1208d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1209d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1210d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1211d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 121240492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1213d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1214d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1215d38ceaf9SAlex Deucher }; 1216d38ceaf9SAlex Deucher 1217d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1218d38ceaf9SAlex Deucher { 1219d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1220d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1221d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1222d38ceaf9SAlex Deucher int ret; 1223d38ceaf9SAlex Deucher 1224d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1225d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1226d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1227d38ceaf9SAlex Deucher 1228d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1229d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1230d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1231d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1232d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1233d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1234d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1235d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1236d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1237d38ceaf9SAlex Deucher } else { 1238d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1239d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1240d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1241d38ceaf9SAlex Deucher if (encoder) 1242d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1243d38ceaf9SAlex Deucher } 1244d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1245d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1246d38ceaf9SAlex Deucher } 1247d38ceaf9SAlex Deucher 1248d38ceaf9SAlex Deucher if (ret > 0) { 1249d38ceaf9SAlex Deucher if (encoder) { 1250d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1251d38ceaf9SAlex Deucher /* add scaled modes */ 1252d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1253d38ceaf9SAlex Deucher } 1254d38ceaf9SAlex Deucher return ret; 1255d38ceaf9SAlex Deucher } 1256d38ceaf9SAlex Deucher 1257d38ceaf9SAlex Deucher if (!encoder) 1258d38ceaf9SAlex Deucher return 0; 1259d38ceaf9SAlex Deucher 1260d38ceaf9SAlex Deucher /* we have no EDID modes */ 1261d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1262d38ceaf9SAlex Deucher if (mode) { 1263d38ceaf9SAlex Deucher ret = 1; 1264d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1265d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1266d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1267d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1268d38ceaf9SAlex Deucher /* add scaled modes */ 1269d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1270d38ceaf9SAlex Deucher } 1271d38ceaf9SAlex Deucher } else { 1272d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1273d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1274d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1275d38ceaf9SAlex Deucher if (encoder) 1276d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1277d38ceaf9SAlex Deucher } 1278d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1279d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1280d38ceaf9SAlex Deucher 1281d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1282d38ceaf9SAlex Deucher } 1283d38ceaf9SAlex Deucher 1284d38ceaf9SAlex Deucher return ret; 1285d38ceaf9SAlex Deucher } 1286d38ceaf9SAlex Deucher 1287d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1288d38ceaf9SAlex Deucher { 1289d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1290d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1291d38ceaf9SAlex Deucher 129262afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1293d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1294d38ceaf9SAlex Deucher 1295d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1296d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1297d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1298d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1299d38ceaf9SAlex Deucher default: 1300d38ceaf9SAlex Deucher break; 1301d38ceaf9SAlex Deucher } 1302d38ceaf9SAlex Deucher } 1303d38ceaf9SAlex Deucher 1304d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1305d38ceaf9SAlex Deucher } 1306d38ceaf9SAlex Deucher 1307d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1308d38ceaf9SAlex Deucher { 1309d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1310d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1311d38ceaf9SAlex Deucher bool found = false; 1312d38ceaf9SAlex Deucher 131362afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1314d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1315d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1316d38ceaf9SAlex Deucher found = true; 1317d38ceaf9SAlex Deucher } 1318d38ceaf9SAlex Deucher 1319d38ceaf9SAlex Deucher return found; 1320d38ceaf9SAlex Deucher } 1321d38ceaf9SAlex Deucher 1322d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1323d38ceaf9SAlex Deucher { 1324d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 13251348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1326d38ceaf9SAlex Deucher 1327d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1328d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1329d38ceaf9SAlex Deucher return true; 1330d38ceaf9SAlex Deucher } 1331d38ceaf9SAlex Deucher 1332d38ceaf9SAlex Deucher return false; 1333d38ceaf9SAlex Deucher } 1334d38ceaf9SAlex Deucher 1335d38ceaf9SAlex Deucher static enum drm_connector_status 1336d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1337d38ceaf9SAlex Deucher { 1338d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 13391348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1340d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1341d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1342d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1343d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1344d38ceaf9SAlex Deucher int r; 1345d38ceaf9SAlex Deucher 1346aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1347d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1348f79f9476SNavid Emamdoost if (r < 0) { 1349f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 1350d38ceaf9SAlex Deucher return connector_status_disconnected; 1351aa0aad57SLukas Wunner } 1352f79f9476SNavid Emamdoost } 1353d38ceaf9SAlex Deucher 1354d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1355d38ceaf9SAlex Deucher ret = connector->status; 1356d38ceaf9SAlex Deucher goto out; 1357d38ceaf9SAlex Deucher } 1358d38ceaf9SAlex Deucher 1359d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1360d38ceaf9SAlex Deucher 1361d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1362d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1363d38ceaf9SAlex Deucher if (encoder) { 1364d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1365d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1366d38ceaf9SAlex Deucher 1367d38ceaf9SAlex Deucher /* check if panel is valid */ 1368d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1369d38ceaf9SAlex Deucher ret = connector_status_connected; 1370d38ceaf9SAlex Deucher } 1371d38ceaf9SAlex Deucher /* eDP is always DP */ 1372d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1373d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1374d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1375d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1376d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1377d38ceaf9SAlex Deucher ret = connector_status_connected; 1378d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1379d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1380d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1381d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1382d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1383d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1384d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1385d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1386d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1387d38ceaf9SAlex Deucher 1388d38ceaf9SAlex Deucher if (encoder) { 1389d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1390d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1391d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1392e0b5b5ecSSamuel Li /* try DDC */ 1393e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1394d38ceaf9SAlex Deucher ret = connector_status_connected; 1395d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 139617b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1397d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1398d38ceaf9SAlex Deucher } 1399d38ceaf9SAlex Deucher } 1400d38ceaf9SAlex Deucher } else { 1401d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1402d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1403d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1404d38ceaf9SAlex Deucher ret = connector_status_connected; 1405d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1406d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1407d38ceaf9SAlex Deucher } else { 1408d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1409d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1410d38ceaf9SAlex Deucher ret = connector_status_connected; 1411d38ceaf9SAlex Deucher } else { 1412d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1413e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, 1414e0b5b5ecSSamuel Li false)) 1415d38ceaf9SAlex Deucher ret = connector_status_connected; 1416d38ceaf9SAlex Deucher } 1417d38ceaf9SAlex Deucher } 1418d38ceaf9SAlex Deucher } 1419d38ceaf9SAlex Deucher 1420d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1421d38ceaf9SAlex Deucher out: 1422aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1423d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1424d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1425aa0aad57SLukas Wunner } 1426d38ceaf9SAlex Deucher 142705211e7fSAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 142805211e7fSAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_eDP) 142965bf2cf9SOleg Vasilev drm_dp_set_subconnector_property(&amdgpu_connector->base, 143065bf2cf9SOleg Vasilev ret, 143165bf2cf9SOleg Vasilev amdgpu_dig_connector->dpcd, 143265bf2cf9SOleg Vasilev amdgpu_dig_connector->downstream_ports); 1433d38ceaf9SAlex Deucher return ret; 1434d38ceaf9SAlex Deucher } 1435d38ceaf9SAlex Deucher 1436ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1437d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1438d38ceaf9SAlex Deucher { 1439d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1440d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1441d38ceaf9SAlex Deucher 1442d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1443d38ceaf9SAlex Deucher 1444d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1445d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1446d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1447d38ceaf9SAlex Deucher 1448d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1449d38ceaf9SAlex Deucher return MODE_PANEL; 1450d38ceaf9SAlex Deucher 1451d38ceaf9SAlex Deucher if (encoder) { 1452d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1453d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1454d38ceaf9SAlex Deucher 1455d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1456d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1457d38ceaf9SAlex Deucher */ 1458d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1459d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1460d38ceaf9SAlex Deucher return MODE_PANEL; 1461d38ceaf9SAlex Deucher 1462d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1463d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1464d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1465d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1466d38ceaf9SAlex Deucher return MODE_PANEL; 1467d38ceaf9SAlex Deucher } 1468d38ceaf9SAlex Deucher } 1469d38ceaf9SAlex Deucher return MODE_OK; 1470d38ceaf9SAlex Deucher } else { 1471d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1472d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1473d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1474d38ceaf9SAlex Deucher } else { 1475*3c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 1476d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1477d38ceaf9SAlex Deucher if (mode->clock > 340000) 1478d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1479d38ceaf9SAlex Deucher } else { 1480d38ceaf9SAlex Deucher if (mode->clock > 165000) 1481d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1482d38ceaf9SAlex Deucher } 1483d38ceaf9SAlex Deucher } 1484d38ceaf9SAlex Deucher } 1485d38ceaf9SAlex Deucher 1486d38ceaf9SAlex Deucher return MODE_OK; 1487d38ceaf9SAlex Deucher } 1488d38ceaf9SAlex Deucher 1489405a1f90SAlex Deucher static int 1490405a1f90SAlex Deucher amdgpu_connector_late_register(struct drm_connector *connector) 1491405a1f90SAlex Deucher { 1492405a1f90SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1493405a1f90SAlex Deucher int r = 0; 1494405a1f90SAlex Deucher 1495405a1f90SAlex Deucher if (amdgpu_connector->ddc_bus->has_aux) { 1496405a1f90SAlex Deucher amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1497405a1f90SAlex Deucher r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1498405a1f90SAlex Deucher } 1499405a1f90SAlex Deucher 1500405a1f90SAlex Deucher return r; 1501405a1f90SAlex Deucher } 1502405a1f90SAlex Deucher 1503d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1504d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1505d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1506d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1507d38ceaf9SAlex Deucher }; 1508d38ceaf9SAlex Deucher 1509d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1510d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1511d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1512d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1513d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 151440492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1515d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1516d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1517405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register, 1518d38ceaf9SAlex Deucher }; 1519d38ceaf9SAlex Deucher 1520d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1521d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1522d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1523d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1524d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 152540492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1526d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1527d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1528405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register, 1529d38ceaf9SAlex Deucher }; 1530d38ceaf9SAlex Deucher 1531d38ceaf9SAlex Deucher void 1532d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1533d38ceaf9SAlex Deucher uint32_t connector_id, 1534d38ceaf9SAlex Deucher uint32_t supported_device, 1535d38ceaf9SAlex Deucher int connector_type, 1536d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1537d38ceaf9SAlex Deucher uint16_t connector_object_id, 1538d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1539d38ceaf9SAlex Deucher struct amdgpu_router *router) 1540d38ceaf9SAlex Deucher { 15414a580877SLuben Tuikov struct drm_device *dev = adev_to_drm(adev); 1542d38ceaf9SAlex Deucher struct drm_connector *connector; 1543f8d2d39eSLyude Paul struct drm_connector_list_iter iter; 1544d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1545d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1546d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1547d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 15485b50fa2bSAndrzej Pietrasiewicz struct i2c_adapter *ddc = NULL; 1549d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1550d38ceaf9SAlex Deucher bool shared_ddc = false; 1551d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1552d38ceaf9SAlex Deucher bool has_aux = false; 1553d38ceaf9SAlex Deucher 1554d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1555d38ceaf9SAlex Deucher return; 1556d38ceaf9SAlex Deucher 1557d38ceaf9SAlex Deucher /* see if we already added it */ 1558f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter); 1559f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) { 1560d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1561d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1562d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1563f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1564d38ceaf9SAlex Deucher return; 1565d38ceaf9SAlex Deucher } 1566d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1567d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1568d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1569d38ceaf9SAlex Deucher shared_ddc = true; 1570d38ceaf9SAlex Deucher } 1571d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1572d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1573d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1574d38ceaf9SAlex Deucher shared_ddc = false; 1575d38ceaf9SAlex Deucher } 1576d38ceaf9SAlex Deucher } 1577d38ceaf9SAlex Deucher } 1578f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1579d38ceaf9SAlex Deucher 1580d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1581d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1582d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1583d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1584d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1585d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1586d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1587d38ceaf9SAlex Deucher is_dp_bridge = true; 1588d38ceaf9SAlex Deucher break; 1589d38ceaf9SAlex Deucher default: 1590d38ceaf9SAlex Deucher break; 1591d38ceaf9SAlex Deucher } 1592d38ceaf9SAlex Deucher } 1593d38ceaf9SAlex Deucher } 1594d38ceaf9SAlex Deucher 1595d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1596d38ceaf9SAlex Deucher if (!amdgpu_connector) 1597d38ceaf9SAlex Deucher return; 1598d38ceaf9SAlex Deucher 1599d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1600d38ceaf9SAlex Deucher 1601d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1602d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1603d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1604d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1605d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1606d38ceaf9SAlex Deucher 1607d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1608d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1609d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1610d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1611d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1612d38ceaf9SAlex Deucher } 1613d38ceaf9SAlex Deucher 1614d38ceaf9SAlex Deucher if (is_dp_bridge) { 1615d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1616d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1617d38ceaf9SAlex Deucher goto failed; 1618d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1619d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1620d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 16215b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1622d38ceaf9SAlex Deucher has_aux = true; 16235b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 16245b50fa2bSAndrzej Pietrasiewicz } else { 1625d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1626d38ceaf9SAlex Deucher } 16275b50fa2bSAndrzej Pietrasiewicz } 1628d38ceaf9SAlex Deucher switch (connector_type) { 1629d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1630d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1631d38ceaf9SAlex Deucher default: 16325b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16335b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 16345b50fa2bSAndrzej Pietrasiewicz connector_type, 16355b50fa2bSAndrzej Pietrasiewicz ddc); 1636d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1637d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1638d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1639d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1640d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1641d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1642d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1643d38ceaf9SAlex Deucher 1); 1644d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1645d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1646d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1647d38ceaf9SAlex Deucher break; 1648d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1649d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1650d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1651d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1652d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 16535b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16545b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 16555b50fa2bSAndrzej Pietrasiewicz connector_type, 16565b50fa2bSAndrzej Pietrasiewicz ddc); 1657d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1658d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1659d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1660d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1661d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1662d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1663d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1664d38ceaf9SAlex Deucher 0); 1665d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1666d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1667d38ceaf9SAlex Deucher 0); 1668d38ceaf9SAlex Deucher 1669d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1670d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1671d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1672d38ceaf9SAlex Deucher 1673d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1674d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1675d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1676d38ceaf9SAlex Deucher 1677d38ceaf9SAlex Deucher if (amdgpu_audio != 0) 1678d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1679d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1680d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1681d38ceaf9SAlex Deucher 1682d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1683d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1684d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1685d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1686d38ceaf9SAlex Deucher else 1687d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1688d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1689d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1690d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1691d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1692d38ceaf9SAlex Deucher 1); 1693d38ceaf9SAlex Deucher } 1694d38ceaf9SAlex Deucher break; 1695d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1696d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 16975b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16985b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs, 16995b50fa2bSAndrzej Pietrasiewicz connector_type, 17005b50fa2bSAndrzej Pietrasiewicz ddc); 1701d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1702d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1703d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1704d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1705d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1706d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1707d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1708d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1709d38ceaf9SAlex Deucher break; 1710d38ceaf9SAlex Deucher } 1711d38ceaf9SAlex Deucher } else { 1712d38ceaf9SAlex Deucher switch (connector_type) { 1713d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1714d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1715d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1716d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1717d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17185b50fa2bSAndrzej Pietrasiewicz else 17195b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1720d38ceaf9SAlex Deucher } 17215b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17225b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs, 17235b50fa2bSAndrzej Pietrasiewicz connector_type, 17245b50fa2bSAndrzej Pietrasiewicz ddc); 17255b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1726d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1727d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1728d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1729d38ceaf9SAlex Deucher 1); 1730d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1731d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1732d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1733d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1734d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1735d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1736d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1737d38ceaf9SAlex Deucher break; 1738d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1739d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1740d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1741d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1742d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17435b50fa2bSAndrzej Pietrasiewicz else 17445b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1745d38ceaf9SAlex Deucher } 17465b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17475b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs, 17485b50fa2bSAndrzej Pietrasiewicz connector_type, 17495b50fa2bSAndrzej Pietrasiewicz ddc); 17505b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1751d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1752d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1753d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1754d38ceaf9SAlex Deucher 1); 1755d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1756d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1757d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1758d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1759d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1760d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1761d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1762d38ceaf9SAlex Deucher break; 1763d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1764d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1765d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1766d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1767d38ceaf9SAlex Deucher goto failed; 1768d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1769d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1770d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1771d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1772d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17735b50fa2bSAndrzej Pietrasiewicz else 17745b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1775d38ceaf9SAlex Deucher } 17765b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17775b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs, 17785b50fa2bSAndrzej Pietrasiewicz connector_type, 17795b50fa2bSAndrzej Pietrasiewicz ddc); 17805b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1781d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1782d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1783d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1784d38ceaf9SAlex Deucher 1); 1785d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1786d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1787d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1788d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1789d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1790d38ceaf9SAlex Deucher 0); 1791d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1792d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1793d38ceaf9SAlex Deucher 0); 1794d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1795d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1796d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1797d38ceaf9SAlex Deucher 1798d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1799d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1800d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1801d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1802d38ceaf9SAlex Deucher } 1803d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1804d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1805d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1806d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1807d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1808d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1809d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1810d38ceaf9SAlex Deucher 1); 1811d38ceaf9SAlex Deucher } 1812d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1813d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1814d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1815d38ceaf9SAlex Deucher else 1816d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1817d38ceaf9SAlex Deucher break; 1818d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1819d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1820d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1821d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1822d38ceaf9SAlex Deucher goto failed; 1823d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1824d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1825d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1826d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1827d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 18285b50fa2bSAndrzej Pietrasiewicz else 18295b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1830d38ceaf9SAlex Deucher } 18315b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 18325b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs, 18335b50fa2bSAndrzej Pietrasiewicz connector_type, 18345b50fa2bSAndrzej Pietrasiewicz ddc); 18355b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1836d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1837d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1838d38ceaf9SAlex Deucher 1); 1839d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1840d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1841d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1842d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1843d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1844d38ceaf9SAlex Deucher 0); 1845d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1846d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1847d38ceaf9SAlex Deucher 0); 1848d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1849d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1850d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1851d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1852d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1853d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1854d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1855d38ceaf9SAlex Deucher } 1856d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1857d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1858d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1859d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1860d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1861d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1862d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1863d38ceaf9SAlex Deucher else 1864d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1865d38ceaf9SAlex Deucher break; 1866d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1867d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1868d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1869d38ceaf9SAlex Deucher goto failed; 1870d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1871d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1872d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 18735b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1874d38ceaf9SAlex Deucher has_aux = true; 18755b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 18765b50fa2bSAndrzej Pietrasiewicz } else { 1877d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1878d38ceaf9SAlex Deucher } 18795b50fa2bSAndrzej Pietrasiewicz } 18805b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 18815b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 18825b50fa2bSAndrzej Pietrasiewicz connector_type, 18835b50fa2bSAndrzej Pietrasiewicz ddc); 18845b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1885d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1886d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1887d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1888d38ceaf9SAlex Deucher 1); 1889d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1890d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1891d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1892d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1893d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1894d38ceaf9SAlex Deucher 0); 1895d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1896d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1897d38ceaf9SAlex Deucher 0); 1898d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1899d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1900d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1901d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1902d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1903d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1904d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1905d38ceaf9SAlex Deucher } 1906d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1907d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1908d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1909d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1910d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1911d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1912d38ceaf9SAlex Deucher break; 1913d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1914d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1915d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1916d38ceaf9SAlex Deucher goto failed; 1917d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1918d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1919d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 19205b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1921d38ceaf9SAlex Deucher has_aux = true; 19225b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 19235b50fa2bSAndrzej Pietrasiewicz } else { 1924d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1925d38ceaf9SAlex Deucher } 19265b50fa2bSAndrzej Pietrasiewicz } 19275b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19285b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs, 19295b50fa2bSAndrzej Pietrasiewicz connector_type, 19305b50fa2bSAndrzej Pietrasiewicz ddc); 19315b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1932d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1933d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1934d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1935d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1936d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1937d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1938d38ceaf9SAlex Deucher break; 1939d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1940d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1941d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1942d38ceaf9SAlex Deucher goto failed; 1943d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1944d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1945d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1946d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1947d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 19485b50fa2bSAndrzej Pietrasiewicz else 19495b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1950d38ceaf9SAlex Deucher } 19515b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19525b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_lvds_funcs, 19535b50fa2bSAndrzej Pietrasiewicz connector_type, 19545b50fa2bSAndrzej Pietrasiewicz ddc); 19555b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1956d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1957d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1958d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1959d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1960d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1961d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1962d38ceaf9SAlex Deucher break; 1963d38ceaf9SAlex Deucher } 1964d38ceaf9SAlex Deucher } 1965d38ceaf9SAlex Deucher 1966d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1967b636a1b3SLyude if (i2c_bus->valid) { 1968b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1969b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT; 1970b636a1b3SLyude } 1971d38ceaf9SAlex Deucher } else 1972d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 1973d38ceaf9SAlex Deucher 1974d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 1975d38ceaf9SAlex Deucher 1976d38ceaf9SAlex Deucher if (has_aux) 1977d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 1978d38ceaf9SAlex Deucher 197965bf2cf9SOleg Vasilev if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 198065bf2cf9SOleg Vasilev connector_type == DRM_MODE_CONNECTOR_eDP) { 198165bf2cf9SOleg Vasilev drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 198265bf2cf9SOleg Vasilev } 198365bf2cf9SOleg Vasilev 1984d38ceaf9SAlex Deucher return; 1985d38ceaf9SAlex Deucher 1986d38ceaf9SAlex Deucher failed: 1987d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 1988d38ceaf9SAlex Deucher kfree(connector); 1989d38ceaf9SAlex Deucher } 1990