1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26fdf2f6c5SSam Ravnborg 27d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 28d38ceaf9SAlex Deucher #include <drm/drm_fb_helper.h> 29fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 30d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 31d38ceaf9SAlex Deucher #include "amdgpu.h" 32d38ceaf9SAlex Deucher #include "atom.h" 33d38ceaf9SAlex Deucher #include "atombios_encoders.h" 34d38ceaf9SAlex Deucher #include "atombios_dp.h" 35d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 36d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 375df58525SHuang Rui #include "amdgpu_display.h" 38d38ceaf9SAlex Deucher 39d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 42d38ceaf9SAlex Deucher { 43d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 441348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 45d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 46d38ceaf9SAlex Deucher 47d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 48d38ceaf9SAlex Deucher * VGA, TV, etc. 49d38ceaf9SAlex Deucher */ 50d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 51d38ceaf9SAlex Deucher return; 52d38ceaf9SAlex Deucher 53d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 54d38ceaf9SAlex Deucher 55d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 56d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 57d38ceaf9SAlex Deucher return; 58d38ceaf9SAlex Deucher 59d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 60d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 61d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 62d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 63d38ceaf9SAlex Deucher 64d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 65d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 66d38ceaf9SAlex Deucher return; 67d38ceaf9SAlex Deucher 68d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 69d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 70d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 71d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 72d38ceaf9SAlex Deucher */ 73daf88096SMichel Dänzer if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 74daf88096SMichel Dänzer amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 75daf88096SMichel Dänzer amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 76daf88096SMichel Dänzer /* Don't start link training before we have the DPCD */ 770b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 78a887adadSAlex Deucher return; 79a887adadSAlex Deucher 80daf88096SMichel Dänzer /* Turn the connector off and back on immediately, which 81daf88096SMichel Dänzer * will trigger link training 82d38ceaf9SAlex Deucher */ 83daf88096SMichel Dänzer drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 84d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 85d38ceaf9SAlex Deucher } 86d38ceaf9SAlex Deucher } 87d38ceaf9SAlex Deucher } 88d38ceaf9SAlex Deucher 89d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 90d38ceaf9SAlex Deucher { 91d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 92d38ceaf9SAlex Deucher 93d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 94d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 95d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 96d38ceaf9SAlex Deucher } 97d38ceaf9SAlex Deucher } 98d38ceaf9SAlex Deucher 99d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 100d38ceaf9SAlex Deucher { 101d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 102d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 103d38ceaf9SAlex Deucher int bpc = 8; 104d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock; 105d38ceaf9SAlex Deucher 106d38ceaf9SAlex Deucher switch (connector->connector_type) { 107d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 108d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 109d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 110d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 111d38ceaf9SAlex Deucher if (connector->display_info.bpc) 112d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 113d38ceaf9SAlex Deucher } 114d38ceaf9SAlex Deucher } 115d38ceaf9SAlex Deucher break; 116d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 117d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 118d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 119d38ceaf9SAlex Deucher if (connector->display_info.bpc) 120d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 121d38ceaf9SAlex Deucher } 122d38ceaf9SAlex Deucher break; 123d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 124d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 125d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 126d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 127d38ceaf9SAlex Deucher drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 128d38ceaf9SAlex Deucher if (connector->display_info.bpc) 129d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 130d38ceaf9SAlex Deucher } 131d38ceaf9SAlex Deucher break; 132d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 133d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 134d38ceaf9SAlex Deucher if (connector->display_info.bpc) 135d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 136d38ceaf9SAlex Deucher else { 13717b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = 138d38ceaf9SAlex Deucher connector->helper_private; 139d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 140d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 141d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 142d38ceaf9SAlex Deucher 143d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 144d38ceaf9SAlex Deucher bpc = 6; 145d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 146d38ceaf9SAlex Deucher bpc = 8; 147d38ceaf9SAlex Deucher } 148d38ceaf9SAlex Deucher break; 149d38ceaf9SAlex Deucher } 150d38ceaf9SAlex Deucher 151d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 152d38ceaf9SAlex Deucher /* 153d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 154d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 155d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 156d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 157d38ceaf9SAlex Deucher */ 158d38ceaf9SAlex Deucher if (bpc > 12) { 159d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 160d38ceaf9SAlex Deucher connector->name, bpc); 161d38ceaf9SAlex Deucher bpc = 12; 162d38ceaf9SAlex Deucher } 163d38ceaf9SAlex Deucher 164d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 1652a272ca9SVille Syrjälä if (connector->display_info.max_tmds_clock > 0) { 166d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 167d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 168d38ceaf9SAlex Deucher 169d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 1702a272ca9SVille Syrjälä max_tmds_clock = connector->display_info.max_tmds_clock; 171d38ceaf9SAlex Deucher 172d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 173d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 174d38ceaf9SAlex Deucher 175d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 176d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 177d38ceaf9SAlex Deucher if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 178d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 179d38ceaf9SAlex Deucher bpc = 10; 180d38ceaf9SAlex Deucher else 181d38ceaf9SAlex Deucher bpc = 8; 182d38ceaf9SAlex Deucher 183d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 184d38ceaf9SAlex Deucher connector->name, bpc); 185d38ceaf9SAlex Deucher } 186d38ceaf9SAlex Deucher 187d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 188d38ceaf9SAlex Deucher bpc = 8; 189d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 190d38ceaf9SAlex Deucher connector->name, bpc); 1919d746ab6SMario Kleiner } 192d38ceaf9SAlex Deucher } else if (bpc > 8) { 193d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 194d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 195d38ceaf9SAlex Deucher connector->name); 196d38ceaf9SAlex Deucher bpc = 8; 197d38ceaf9SAlex Deucher } 198d38ceaf9SAlex Deucher } 199d38ceaf9SAlex Deucher 200d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 201d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 202d38ceaf9SAlex Deucher connector->name); 203d38ceaf9SAlex Deucher bpc = 8; 204d38ceaf9SAlex Deucher } 205d38ceaf9SAlex Deucher 206d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 207d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 208d38ceaf9SAlex Deucher 209d38ceaf9SAlex Deucher return bpc; 210d38ceaf9SAlex Deucher } 211d38ceaf9SAlex Deucher 212d38ceaf9SAlex Deucher static void 213d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 214d38ceaf9SAlex Deucher enum drm_connector_status status) 215d38ceaf9SAlex Deucher { 21698c0e348SVille Syrjälä struct drm_encoder *best_encoder; 21798c0e348SVille Syrjälä struct drm_encoder *encoder; 21817b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 219d38ceaf9SAlex Deucher bool connected; 220d38ceaf9SAlex Deucher 221d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 222d38ceaf9SAlex Deucher 22362afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 224d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 225d38ceaf9SAlex Deucher connected = true; 226d38ceaf9SAlex Deucher else 227d38ceaf9SAlex Deucher connected = false; 228d38ceaf9SAlex Deucher 229d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 230d38ceaf9SAlex Deucher } 231d38ceaf9SAlex Deucher } 232d38ceaf9SAlex Deucher 233d38ceaf9SAlex Deucher static struct drm_encoder * 234d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 235d38ceaf9SAlex Deucher int encoder_type) 236d38ceaf9SAlex Deucher { 237d38ceaf9SAlex Deucher struct drm_encoder *encoder; 238d38ceaf9SAlex Deucher 23962afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 240d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 241d38ceaf9SAlex Deucher return encoder; 242d38ceaf9SAlex Deucher } 24398c0e348SVille Syrjälä 244d38ceaf9SAlex Deucher return NULL; 245d38ceaf9SAlex Deucher } 246d38ceaf9SAlex Deucher 247d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector) 248d38ceaf9SAlex Deucher { 249d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 250d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 251d38ceaf9SAlex Deucher 252d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 253d38ceaf9SAlex Deucher return amdgpu_connector->edid; 254d38ceaf9SAlex Deucher } else if (edid_blob) { 255d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 256d38ceaf9SAlex Deucher if (edid) 257d38ceaf9SAlex Deucher amdgpu_connector->edid = edid; 258d38ceaf9SAlex Deucher } 259d38ceaf9SAlex Deucher return amdgpu_connector->edid; 260d38ceaf9SAlex Deucher } 261d38ceaf9SAlex Deucher 262d38ceaf9SAlex Deucher static struct edid * 263d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 264d38ceaf9SAlex Deucher { 265d38ceaf9SAlex Deucher struct edid *edid; 266d38ceaf9SAlex Deucher 267d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 268d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 269d38ceaf9SAlex Deucher if (edid) { 270d38ceaf9SAlex Deucher memcpy((unsigned char *)edid, 271d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid, 272d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size); 273d38ceaf9SAlex Deucher return edid; 274d38ceaf9SAlex Deucher } 275d38ceaf9SAlex Deucher } 276d38ceaf9SAlex Deucher return NULL; 277d38ceaf9SAlex Deucher } 278d38ceaf9SAlex Deucher 279d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 280d38ceaf9SAlex Deucher { 281d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 2821348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 283d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 284d38ceaf9SAlex Deucher 285d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 286d38ceaf9SAlex Deucher return; 287d38ceaf9SAlex Deucher 288d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 289d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 290d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 291d38ceaf9SAlex Deucher 292d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 293d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 294d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 295d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 296d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 297d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 298d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 299d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 300d38ceaf9SAlex Deucher 301d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 302d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 303d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 304d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 305d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 306d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 307d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 308d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 309d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 310d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 311d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 312d38ceaf9SAlex Deucher } 313d38ceaf9SAlex Deucher 314d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 315d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 316d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 317d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 318d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 319d38ceaf9SAlex Deucher } 320d38ceaf9SAlex Deucher } 321d38ceaf9SAlex Deucher 322d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 323d38ceaf9SAlex Deucher { 324d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 325d38ceaf9SAlex Deucher 326d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 327d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 328d38ceaf9SAlex Deucher } 329d38ceaf9SAlex Deucher 330d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 331d38ceaf9SAlex Deucher { 332d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 333d38ceaf9SAlex Deucher int ret; 334d38ceaf9SAlex Deucher 335d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 336c555f023SDaniel Vetter drm_connector_update_edid_property(connector, amdgpu_connector->edid); 337d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 338d38ceaf9SAlex Deucher return ret; 339d38ceaf9SAlex Deucher } 340c555f023SDaniel Vetter drm_connector_update_edid_property(connector, NULL); 341d38ceaf9SAlex Deucher return 0; 342d38ceaf9SAlex Deucher } 343d38ceaf9SAlex Deucher 344d38ceaf9SAlex Deucher static struct drm_encoder * 345d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 346d38ceaf9SAlex Deucher { 34798c0e348SVille Syrjälä struct drm_encoder *encoder; 348d38ceaf9SAlex Deucher 34998c0e348SVille Syrjälä /* pick the first one */ 35062afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) 35198c0e348SVille Syrjälä return encoder; 35298c0e348SVille Syrjälä 353d38ceaf9SAlex Deucher return NULL; 354d38ceaf9SAlex Deucher } 355d38ceaf9SAlex Deucher 356d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 357d38ceaf9SAlex Deucher { 358d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 359d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 360d38ceaf9SAlex Deucher 361d38ceaf9SAlex Deucher if (encoder == NULL) 362d38ceaf9SAlex Deucher return; 363d38ceaf9SAlex Deucher 364d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 365d38ceaf9SAlex Deucher 366d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 367d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 368d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 369d38ceaf9SAlex Deucher struct drm_display_mode, head); 370d38ceaf9SAlex Deucher 371d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 372d38ceaf9SAlex Deucher } else { 373d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 374d38ceaf9SAlex Deucher } 375d38ceaf9SAlex Deucher } 376d38ceaf9SAlex Deucher 377d38ceaf9SAlex Deucher static struct drm_display_mode * 378d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 379d38ceaf9SAlex Deucher { 380d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 381d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 382d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 383d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 384d38ceaf9SAlex Deucher 385d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 386d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 387d38ceaf9SAlex Deucher native_mode->clock != 0) { 388d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 389d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 390d38ceaf9SAlex Deucher drm_mode_set_name(mode); 391d38ceaf9SAlex Deucher 392d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 393d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 394d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 395d38ceaf9SAlex Deucher /* mac laptops without an edid */ 396d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 397d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 398d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 399d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 400d38ceaf9SAlex Deucher * simpler. 401d38ceaf9SAlex Deucher */ 402d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 403d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 404d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 405d38ceaf9SAlex Deucher } 406d38ceaf9SAlex Deucher return mode; 407d38ceaf9SAlex Deucher } 408d38ceaf9SAlex Deucher 409d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 410d38ceaf9SAlex Deucher struct drm_connector *connector) 411d38ceaf9SAlex Deucher { 412d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 413d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 414d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 415d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 416d38ceaf9SAlex Deucher int i; 417aeba709aSNils Wallménius static const struct mode_size { 418d38ceaf9SAlex Deucher int w; 419d38ceaf9SAlex Deucher int h; 420d38ceaf9SAlex Deucher } common_modes[17] = { 421d38ceaf9SAlex Deucher { 640, 480}, 422d38ceaf9SAlex Deucher { 720, 480}, 423d38ceaf9SAlex Deucher { 800, 600}, 424d38ceaf9SAlex Deucher { 848, 480}, 425d38ceaf9SAlex Deucher {1024, 768}, 426d38ceaf9SAlex Deucher {1152, 768}, 427d38ceaf9SAlex Deucher {1280, 720}, 428d38ceaf9SAlex Deucher {1280, 800}, 429d38ceaf9SAlex Deucher {1280, 854}, 430d38ceaf9SAlex Deucher {1280, 960}, 431d38ceaf9SAlex Deucher {1280, 1024}, 432d38ceaf9SAlex Deucher {1440, 900}, 433d38ceaf9SAlex Deucher {1400, 1050}, 434d38ceaf9SAlex Deucher {1680, 1050}, 435d38ceaf9SAlex Deucher {1600, 1200}, 436d38ceaf9SAlex Deucher {1920, 1080}, 437d38ceaf9SAlex Deucher {1920, 1200} 438d38ceaf9SAlex Deucher }; 439d38ceaf9SAlex Deucher 440d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 441d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 442d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 443d38ceaf9SAlex Deucher common_modes[i].h > 768) 444d38ceaf9SAlex Deucher continue; 445d38ceaf9SAlex Deucher } 446d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 447d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 448d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 449d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 450d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 451d38ceaf9SAlex Deucher continue; 452d38ceaf9SAlex Deucher } 453d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 454d38ceaf9SAlex Deucher continue; 455d38ceaf9SAlex Deucher 456d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 457d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 458d38ceaf9SAlex Deucher } 459d38ceaf9SAlex Deucher } 460d38ceaf9SAlex Deucher 461d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 462d38ceaf9SAlex Deucher struct drm_property *property, 463d38ceaf9SAlex Deucher uint64_t val) 464d38ceaf9SAlex Deucher { 465d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 4661348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 467d38ceaf9SAlex Deucher struct drm_encoder *encoder; 468d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 469d38ceaf9SAlex Deucher 470d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 471d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 472d38ceaf9SAlex Deucher bool new_coherent_mode; 473d38ceaf9SAlex Deucher 474d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 475d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 476d38ceaf9SAlex Deucher if (!encoder) 477d38ceaf9SAlex Deucher return 0; 478d38ceaf9SAlex Deucher 479d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 480d38ceaf9SAlex Deucher 481d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 482d38ceaf9SAlex Deucher return 0; 483d38ceaf9SAlex Deucher 484d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 485d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 486d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 487d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 488d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 489d38ceaf9SAlex Deucher } 490d38ceaf9SAlex Deucher } 491d38ceaf9SAlex Deucher 492d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 493d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 494d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 495d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 496d38ceaf9SAlex Deucher if (!encoder) 497d38ceaf9SAlex Deucher return 0; 498d38ceaf9SAlex Deucher 499d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 500d38ceaf9SAlex Deucher 501d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 502d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 503d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 504d38ceaf9SAlex Deucher } 505d38ceaf9SAlex Deucher } 506d38ceaf9SAlex Deucher 507d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 508d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 509d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 510d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 511d38ceaf9SAlex Deucher if (!encoder) 512d38ceaf9SAlex Deucher return 0; 513d38ceaf9SAlex Deucher 514d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 515d38ceaf9SAlex Deucher 516d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 517d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 518d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 519d38ceaf9SAlex Deucher } 520d38ceaf9SAlex Deucher } 521d38ceaf9SAlex Deucher 522d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 523d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 524d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 525d38ceaf9SAlex Deucher if (!encoder) 526d38ceaf9SAlex Deucher return 0; 527d38ceaf9SAlex Deucher 528d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 529d38ceaf9SAlex Deucher 530d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 531d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 532d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 533d38ceaf9SAlex Deucher } 534d38ceaf9SAlex Deucher } 535d38ceaf9SAlex Deucher 536d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 537d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 538d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 539d38ceaf9SAlex Deucher if (!encoder) 540d38ceaf9SAlex Deucher return 0; 541d38ceaf9SAlex Deucher 542d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 543d38ceaf9SAlex Deucher 544d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 545d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 546d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 547d38ceaf9SAlex Deucher } 548d38ceaf9SAlex Deucher } 549d38ceaf9SAlex Deucher 550d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 551d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 552d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 553d38ceaf9SAlex Deucher if (!encoder) 554d38ceaf9SAlex Deucher return 0; 555d38ceaf9SAlex Deucher 556d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 557d38ceaf9SAlex Deucher 558d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 559d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 560d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 561d38ceaf9SAlex Deucher } 562d38ceaf9SAlex Deucher } 563d38ceaf9SAlex Deucher 564d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 565d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 566d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 567d38ceaf9SAlex Deucher 568d38ceaf9SAlex Deucher if (val == 0) 569d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 570d38ceaf9SAlex Deucher else 571d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 572d38ceaf9SAlex Deucher } 573d38ceaf9SAlex Deucher 574d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 575d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 576d38ceaf9SAlex Deucher 577d38ceaf9SAlex Deucher if (connector->encoder) { 578d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 579d38ceaf9SAlex Deucher } else { 58017b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 581d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 582d38ceaf9SAlex Deucher } 583d38ceaf9SAlex Deucher 584d38ceaf9SAlex Deucher switch (val) { 585d38ceaf9SAlex Deucher default: 586d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 587d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 588d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 589d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 590d38ceaf9SAlex Deucher } 591d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 592d38ceaf9SAlex Deucher return 0; 593d38ceaf9SAlex Deucher 594d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 595d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 596d38ceaf9SAlex Deucher return 0; 597d38ceaf9SAlex Deucher 598d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 599d38ceaf9SAlex Deucher 600d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 601d38ceaf9SAlex Deucher } 602d38ceaf9SAlex Deucher 603d38ceaf9SAlex Deucher return 0; 604d38ceaf9SAlex Deucher } 605d38ceaf9SAlex Deucher 606d38ceaf9SAlex Deucher static void 607d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 608d38ceaf9SAlex Deucher struct drm_connector *connector) 609d38ceaf9SAlex Deucher { 610d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 611d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 612d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 613d38ceaf9SAlex Deucher 614d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 615d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 616d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 617d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 618d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 619d38ceaf9SAlex Deucher memcpy(native_mode, mode, sizeof(*mode)); 620d38ceaf9SAlex Deucher } 621d38ceaf9SAlex Deucher } 622d38ceaf9SAlex Deucher 623d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 624d38ceaf9SAlex Deucher if (!native_mode->clock) { 625d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 626d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 627d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 628d38ceaf9SAlex Deucher *native_mode = *mode; 629d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 630d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 631d38ceaf9SAlex Deucher break; 632d38ceaf9SAlex Deucher } 633d38ceaf9SAlex Deucher } 634d38ceaf9SAlex Deucher } 635d38ceaf9SAlex Deucher 636d38ceaf9SAlex Deucher if (!native_mode->clock) { 637d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 638d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 639d38ceaf9SAlex Deucher } 640d38ceaf9SAlex Deucher } 641d38ceaf9SAlex Deucher 642d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 643d38ceaf9SAlex Deucher { 644d38ceaf9SAlex Deucher struct drm_encoder *encoder; 645d38ceaf9SAlex Deucher int ret = 0; 646d38ceaf9SAlex Deucher struct drm_display_mode *mode; 647d38ceaf9SAlex Deucher 648d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 649d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 650d38ceaf9SAlex Deucher if (ret > 0) { 651d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 652d38ceaf9SAlex Deucher if (encoder) { 653d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 654d38ceaf9SAlex Deucher /* add scaled modes */ 655d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 656d38ceaf9SAlex Deucher } 657d38ceaf9SAlex Deucher return ret; 658d38ceaf9SAlex Deucher } 659d38ceaf9SAlex Deucher 660d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 661d38ceaf9SAlex Deucher if (!encoder) 662d38ceaf9SAlex Deucher return 0; 663d38ceaf9SAlex Deucher 664d38ceaf9SAlex Deucher /* we have no EDID modes */ 665d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 666d38ceaf9SAlex Deucher if (mode) { 667d38ceaf9SAlex Deucher ret = 1; 668d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 669d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 670d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 671d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 672d38ceaf9SAlex Deucher /* add scaled modes */ 673d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 674d38ceaf9SAlex Deucher } 675d38ceaf9SAlex Deucher 676d38ceaf9SAlex Deucher return ret; 677d38ceaf9SAlex Deucher } 678d38ceaf9SAlex Deucher 679ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 680d38ceaf9SAlex Deucher struct drm_display_mode *mode) 681d38ceaf9SAlex Deucher { 682d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 683d38ceaf9SAlex Deucher 684d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 685d38ceaf9SAlex Deucher return MODE_PANEL; 686d38ceaf9SAlex Deucher 687d38ceaf9SAlex Deucher if (encoder) { 688d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 689d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 690d38ceaf9SAlex Deucher 691d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 692d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 693d38ceaf9SAlex Deucher */ 694d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 695d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 696d38ceaf9SAlex Deucher return MODE_PANEL; 697d38ceaf9SAlex Deucher 698d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 699d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 700d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 701d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 702d38ceaf9SAlex Deucher return MODE_PANEL; 703d38ceaf9SAlex Deucher } 704d38ceaf9SAlex Deucher } 705d38ceaf9SAlex Deucher 706d38ceaf9SAlex Deucher return MODE_OK; 707d38ceaf9SAlex Deucher } 708d38ceaf9SAlex Deucher 709d38ceaf9SAlex Deucher static enum drm_connector_status 710d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 711d38ceaf9SAlex Deucher { 712d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 713d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 714d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 715d38ceaf9SAlex Deucher int r; 716d38ceaf9SAlex Deucher 717aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 718d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 719f79f9476SNavid Emamdoost if (r < 0) { 720f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 721d38ceaf9SAlex Deucher return connector_status_disconnected; 722aa0aad57SLukas Wunner } 723f79f9476SNavid Emamdoost } 724d38ceaf9SAlex Deucher 725d38ceaf9SAlex Deucher if (encoder) { 726d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 727d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 728d38ceaf9SAlex Deucher 729d38ceaf9SAlex Deucher /* check if panel is valid */ 730d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 731d38ceaf9SAlex Deucher ret = connector_status_connected; 732d38ceaf9SAlex Deucher 733d38ceaf9SAlex Deucher } 734d38ceaf9SAlex Deucher 735d38ceaf9SAlex Deucher /* check for edid as well */ 736d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 737d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 738d38ceaf9SAlex Deucher ret = connector_status_connected; 739d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 740d38ceaf9SAlex Deucher 741d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 742aa0aad57SLukas Wunner 743aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 744d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 745d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 746aa0aad57SLukas Wunner } 747aa0aad57SLukas Wunner 748d38ceaf9SAlex Deucher return ret; 749d38ceaf9SAlex Deucher } 750d38ceaf9SAlex Deucher 75140492f60SGrazvydas Ignotas static void amdgpu_connector_unregister(struct drm_connector *connector) 752d38ceaf9SAlex Deucher { 753d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 754d38ceaf9SAlex Deucher 755eef2b411SAlex Deucher if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 756d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 7572f9ba199SGrazvydas Ignotas amdgpu_connector->ddc_bus->has_aux = false; 7582f9ba199SGrazvydas Ignotas } 75940492f60SGrazvydas Ignotas } 76040492f60SGrazvydas Ignotas 76140492f60SGrazvydas Ignotas static void amdgpu_connector_destroy(struct drm_connector *connector) 76240492f60SGrazvydas Ignotas { 76340492f60SGrazvydas Ignotas struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 76440492f60SGrazvydas Ignotas 765d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 766d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 767d38ceaf9SAlex Deucher drm_connector_unregister(connector); 768d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 769d38ceaf9SAlex Deucher kfree(connector); 770d38ceaf9SAlex Deucher } 771d38ceaf9SAlex Deucher 772d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 773d38ceaf9SAlex Deucher struct drm_property *property, 774d38ceaf9SAlex Deucher uint64_t value) 775d38ceaf9SAlex Deucher { 776d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 777d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 778d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 779d38ceaf9SAlex Deucher 780d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 781d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 782d38ceaf9SAlex Deucher return 0; 783d38ceaf9SAlex Deucher 784d38ceaf9SAlex Deucher if (connector->encoder) 785d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 786d38ceaf9SAlex Deucher else { 78717b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 788d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 789d38ceaf9SAlex Deucher } 790d38ceaf9SAlex Deucher 791d38ceaf9SAlex Deucher switch (value) { 792d38ceaf9SAlex Deucher case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 793d38ceaf9SAlex Deucher case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 794d38ceaf9SAlex Deucher case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 795d38ceaf9SAlex Deucher default: 796d38ceaf9SAlex Deucher case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 797d38ceaf9SAlex Deucher } 798d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 799d38ceaf9SAlex Deucher return 0; 800d38ceaf9SAlex Deucher 801d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 802d38ceaf9SAlex Deucher 803d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 804d38ceaf9SAlex Deucher return 0; 805d38ceaf9SAlex Deucher } 806d38ceaf9SAlex Deucher 807d38ceaf9SAlex Deucher 808d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 809d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 810d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 811d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 812d38ceaf9SAlex Deucher }; 813d38ceaf9SAlex Deucher 814d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 815d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 816d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 817d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 81840492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 819d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 820d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 821d38ceaf9SAlex Deucher }; 822d38ceaf9SAlex Deucher 823d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 824d38ceaf9SAlex Deucher { 825d38ceaf9SAlex Deucher int ret; 826d38ceaf9SAlex Deucher 827d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 828d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 829d38ceaf9SAlex Deucher 830d38ceaf9SAlex Deucher return ret; 831d38ceaf9SAlex Deucher } 832d38ceaf9SAlex Deucher 833ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 834d38ceaf9SAlex Deucher struct drm_display_mode *mode) 835d38ceaf9SAlex Deucher { 836d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 8371348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 838d38ceaf9SAlex Deucher 839d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 840d38ceaf9SAlex Deucher 841d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 842d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 843d38ceaf9SAlex Deucher 844d38ceaf9SAlex Deucher return MODE_OK; 845d38ceaf9SAlex Deucher } 846d38ceaf9SAlex Deucher 847d38ceaf9SAlex Deucher static enum drm_connector_status 848d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 849d38ceaf9SAlex Deucher { 850d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 851d38ceaf9SAlex Deucher struct drm_encoder *encoder; 85217b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 853d38ceaf9SAlex Deucher bool dret = false; 854d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 855d38ceaf9SAlex Deucher int r; 856d38ceaf9SAlex Deucher 857aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 858d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 859f79f9476SNavid Emamdoost if (r < 0) { 860f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 861d38ceaf9SAlex Deucher return connector_status_disconnected; 862aa0aad57SLukas Wunner } 863f79f9476SNavid Emamdoost } 864d38ceaf9SAlex Deucher 865d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 866d38ceaf9SAlex Deucher if (!encoder) 867d38ceaf9SAlex Deucher ret = connector_status_disconnected; 868d38ceaf9SAlex Deucher 869d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 870e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 871d38ceaf9SAlex Deucher if (dret) { 872d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 873d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 874d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 875d38ceaf9SAlex Deucher 876d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 877d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 878d38ceaf9SAlex Deucher connector->name); 879d38ceaf9SAlex Deucher ret = connector_status_connected; 880d38ceaf9SAlex Deucher } else { 881d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 882d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 883d38ceaf9SAlex Deucher 884d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 885d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 886d38ceaf9SAlex Deucher */ 887d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 888d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 889d38ceaf9SAlex Deucher ret = connector_status_disconnected; 890d38ceaf9SAlex Deucher } else { 891d38ceaf9SAlex Deucher ret = connector_status_connected; 892d38ceaf9SAlex Deucher } 893d38ceaf9SAlex Deucher } 894d38ceaf9SAlex Deucher } else { 895d38ceaf9SAlex Deucher 896d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 897d38ceaf9SAlex Deucher if (!force) { 898d38ceaf9SAlex Deucher /* only return the previous status if we last 899d38ceaf9SAlex Deucher * detected a monitor via load. 900d38ceaf9SAlex Deucher */ 901d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 902d38ceaf9SAlex Deucher ret = connector->status; 903d38ceaf9SAlex Deucher goto out; 904d38ceaf9SAlex Deucher } 905d38ceaf9SAlex Deucher 906d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 907d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 908d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 909d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 910d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 911d38ceaf9SAlex Deucher } 912d38ceaf9SAlex Deucher } 913d38ceaf9SAlex Deucher 914d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 915d38ceaf9SAlex Deucher 916d38ceaf9SAlex Deucher out: 917aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 918d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 919d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 920aa0aad57SLukas Wunner } 921d38ceaf9SAlex Deucher 922d38ceaf9SAlex Deucher return ret; 923d38ceaf9SAlex Deucher } 924d38ceaf9SAlex Deucher 925d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 926d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 927d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 928d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 929d38ceaf9SAlex Deucher }; 930d38ceaf9SAlex Deucher 931d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 932d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 933d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 934d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 93540492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 936d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 937d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 938d38ceaf9SAlex Deucher }; 939d38ceaf9SAlex Deucher 940d38ceaf9SAlex Deucher static bool 941d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 942d38ceaf9SAlex Deucher { 943d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 9441348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 945d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 946d38ceaf9SAlex Deucher enum drm_connector_status status; 947d38ceaf9SAlex Deucher 948d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 949d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 950d38ceaf9SAlex Deucher status = connector_status_connected; 951d38ceaf9SAlex Deucher else 952d38ceaf9SAlex Deucher status = connector_status_disconnected; 953d38ceaf9SAlex Deucher if (connector->status == status) 954d38ceaf9SAlex Deucher return true; 955d38ceaf9SAlex Deucher } 956d38ceaf9SAlex Deucher 957d38ceaf9SAlex Deucher return false; 958d38ceaf9SAlex Deucher } 959d38ceaf9SAlex Deucher 960d38ceaf9SAlex Deucher /* 961d38ceaf9SAlex Deucher * DVI is complicated 962d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 963d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 964d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 965d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 966d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 967d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 968d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 969d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 970d38ceaf9SAlex Deucher */ 971d38ceaf9SAlex Deucher static enum drm_connector_status 972d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 973d38ceaf9SAlex Deucher { 974d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 9751348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 976d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 97717b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 97898c0e348SVille Syrjälä int r; 979d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 980d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 981d38ceaf9SAlex Deucher 982aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 983d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 984f79f9476SNavid Emamdoost if (r < 0) { 985f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 986d38ceaf9SAlex Deucher return connector_status_disconnected; 987aa0aad57SLukas Wunner } 988f79f9476SNavid Emamdoost } 989d38ceaf9SAlex Deucher 990d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 991d38ceaf9SAlex Deucher ret = connector->status; 992d38ceaf9SAlex Deucher goto exit; 993d38ceaf9SAlex Deucher } 994d38ceaf9SAlex Deucher 995d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 996e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 997d38ceaf9SAlex Deucher if (dret) { 998d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 999d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1000d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1001d38ceaf9SAlex Deucher 1002d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 1003d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1004d38ceaf9SAlex Deucher connector->name); 1005d38ceaf9SAlex Deucher ret = connector_status_connected; 1006d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1007d38ceaf9SAlex Deucher } else { 1008d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1009d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1010d38ceaf9SAlex Deucher 1011d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1012d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1013d38ceaf9SAlex Deucher */ 1014d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1015d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1016d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1017d38ceaf9SAlex Deucher } else { 1018d38ceaf9SAlex Deucher ret = connector_status_connected; 1019d38ceaf9SAlex Deucher } 1020d38ceaf9SAlex Deucher 1021d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1022d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1023d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1024d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1025d38ceaf9SAlex Deucher */ 1026d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1027d38ceaf9SAlex Deucher struct drm_connector *list_connector; 1028f8d2d39eSLyude Paul struct drm_connector_list_iter iter; 1029d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector; 1030f8d2d39eSLyude Paul 1031f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter); 1032f8d2d39eSLyude Paul drm_for_each_connector_iter(list_connector, 1033f8d2d39eSLyude Paul &iter) { 1034d38ceaf9SAlex Deucher if (connector == list_connector) 1035d38ceaf9SAlex Deucher continue; 1036d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector); 1037d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc && 1038d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1039d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) { 1040d38ceaf9SAlex Deucher /* cases where both connectors are digital */ 1041d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1042d38ceaf9SAlex Deucher /* hpd is our only option in this case */ 1043d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1044d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1045d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1046d38ceaf9SAlex Deucher } 1047d38ceaf9SAlex Deucher } 1048d38ceaf9SAlex Deucher } 1049d38ceaf9SAlex Deucher } 1050f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1051d38ceaf9SAlex Deucher } 1052d38ceaf9SAlex Deucher } 1053d38ceaf9SAlex Deucher } 1054d38ceaf9SAlex Deucher 1055d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1056d38ceaf9SAlex Deucher goto out; 1057d38ceaf9SAlex Deucher 1058d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1059d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1060d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1061d38ceaf9SAlex Deucher goto out; 1062d38ceaf9SAlex Deucher 1063d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1064d38ceaf9SAlex Deucher if (!force) { 1065d38ceaf9SAlex Deucher /* only return the previous status if we last 1066d38ceaf9SAlex Deucher * detected a monitor via load. 1067d38ceaf9SAlex Deucher */ 1068d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1069d38ceaf9SAlex Deucher ret = connector->status; 1070d38ceaf9SAlex Deucher goto out; 1071d38ceaf9SAlex Deucher } 1072d38ceaf9SAlex Deucher 1073d38ceaf9SAlex Deucher /* find analog encoder */ 1074d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 107598c0e348SVille Syrjälä struct drm_encoder *encoder; 1076d38ceaf9SAlex Deucher 107762afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1078d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1079d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1080d38ceaf9SAlex Deucher continue; 1081d38ceaf9SAlex Deucher 1082d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1083d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1084d38ceaf9SAlex Deucher if (!broken_edid) { 1085d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1086d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1087d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1088d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1089d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1090d38ceaf9SAlex Deucher } 1091d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1092d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1093d38ceaf9SAlex Deucher } 1094d38ceaf9SAlex Deucher } else { 1095d38ceaf9SAlex Deucher enum drm_connector_status lret; 1096d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1097d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1098d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1099d38ceaf9SAlex Deucher DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1100d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1101d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1102d38ceaf9SAlex Deucher } 1103d38ceaf9SAlex Deucher break; 1104d38ceaf9SAlex Deucher } 1105d38ceaf9SAlex Deucher } 1106d38ceaf9SAlex Deucher } 1107d38ceaf9SAlex Deucher 1108d38ceaf9SAlex Deucher out: 1109d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1110d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1111d38ceaf9SAlex Deucher 1112d38ceaf9SAlex Deucher exit: 1113aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1114d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1115d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1116aa0aad57SLukas Wunner } 1117d38ceaf9SAlex Deucher 1118d38ceaf9SAlex Deucher return ret; 1119d38ceaf9SAlex Deucher } 1120d38ceaf9SAlex Deucher 1121d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1122d38ceaf9SAlex Deucher static struct drm_encoder * 1123d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1124d38ceaf9SAlex Deucher { 1125d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1126d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1127d38ceaf9SAlex Deucher 112862afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1129d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1130d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1131d38ceaf9SAlex Deucher return encoder; 1132d38ceaf9SAlex Deucher } else { 1133d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1134d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1135d38ceaf9SAlex Deucher return encoder; 1136d38ceaf9SAlex Deucher } 1137d38ceaf9SAlex Deucher } 1138d38ceaf9SAlex Deucher 1139d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1140d38ceaf9SAlex Deucher 1141d38ceaf9SAlex Deucher /* then check use digitial */ 1142d38ceaf9SAlex Deucher /* pick the first one */ 114362afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) 114498c0e348SVille Syrjälä return encoder; 114598c0e348SVille Syrjälä 1146d38ceaf9SAlex Deucher return NULL; 1147d38ceaf9SAlex Deucher } 1148d38ceaf9SAlex Deucher 1149d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1150d38ceaf9SAlex Deucher { 1151d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1152d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1153d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1154d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1155d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1156d38ceaf9SAlex Deucher } 1157d38ceaf9SAlex Deucher 1158ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1159d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1160d38ceaf9SAlex Deucher { 1161d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 11621348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1163d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1164d38ceaf9SAlex Deucher 1165d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1166d38ceaf9SAlex Deucher 1167d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1168d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1169d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1170d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1171d38ceaf9SAlex Deucher return MODE_OK; 1172d38ceaf9SAlex Deucher } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1173d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1174d38ceaf9SAlex Deucher if (mode->clock > 340000) 1175d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1176d38ceaf9SAlex Deucher else 1177d38ceaf9SAlex Deucher return MODE_OK; 1178d38ceaf9SAlex Deucher } else { 1179d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1180d38ceaf9SAlex Deucher } 1181d38ceaf9SAlex Deucher } 1182d38ceaf9SAlex Deucher 1183d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1184d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1185d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1186d38ceaf9SAlex Deucher 1187d38ceaf9SAlex Deucher return MODE_OK; 1188d38ceaf9SAlex Deucher } 1189d38ceaf9SAlex Deucher 1190d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1191d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1192d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1193d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1194d38ceaf9SAlex Deucher }; 1195d38ceaf9SAlex Deucher 1196d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1197d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1198d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1199d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1200d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 120140492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1202d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1203d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1204d38ceaf9SAlex Deucher }; 1205d38ceaf9SAlex Deucher 1206d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1207d38ceaf9SAlex Deucher { 1208d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1209d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1210d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1211d38ceaf9SAlex Deucher int ret; 1212d38ceaf9SAlex Deucher 1213d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1214d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1215d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1216d38ceaf9SAlex Deucher 1217d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1218d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1219d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1220d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1221d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1222d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1223d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1224d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1225d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1226d38ceaf9SAlex Deucher } else { 1227d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1228d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1229d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1230d38ceaf9SAlex Deucher if (encoder) 1231d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1232d38ceaf9SAlex Deucher } 1233d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1234d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1235d38ceaf9SAlex Deucher } 1236d38ceaf9SAlex Deucher 1237d38ceaf9SAlex Deucher if (ret > 0) { 1238d38ceaf9SAlex Deucher if (encoder) { 1239d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1240d38ceaf9SAlex Deucher /* add scaled modes */ 1241d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1242d38ceaf9SAlex Deucher } 1243d38ceaf9SAlex Deucher return ret; 1244d38ceaf9SAlex Deucher } 1245d38ceaf9SAlex Deucher 1246d38ceaf9SAlex Deucher if (!encoder) 1247d38ceaf9SAlex Deucher return 0; 1248d38ceaf9SAlex Deucher 1249d38ceaf9SAlex Deucher /* we have no EDID modes */ 1250d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1251d38ceaf9SAlex Deucher if (mode) { 1252d38ceaf9SAlex Deucher ret = 1; 1253d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1254d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1255d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1256d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1257d38ceaf9SAlex Deucher /* add scaled modes */ 1258d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1259d38ceaf9SAlex Deucher } 1260d38ceaf9SAlex Deucher } else { 1261d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1262d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1263d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1264d38ceaf9SAlex Deucher if (encoder) 1265d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1266d38ceaf9SAlex Deucher } 1267d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1268d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1269d38ceaf9SAlex Deucher 1270d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1271d38ceaf9SAlex Deucher } 1272d38ceaf9SAlex Deucher 1273d38ceaf9SAlex Deucher return ret; 1274d38ceaf9SAlex Deucher } 1275d38ceaf9SAlex Deucher 1276d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1277d38ceaf9SAlex Deucher { 1278d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1279d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1280d38ceaf9SAlex Deucher 128162afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1282d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1283d38ceaf9SAlex Deucher 1284d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1285d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1286d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1287d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1288d38ceaf9SAlex Deucher default: 1289d38ceaf9SAlex Deucher break; 1290d38ceaf9SAlex Deucher } 1291d38ceaf9SAlex Deucher } 1292d38ceaf9SAlex Deucher 1293d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1294d38ceaf9SAlex Deucher } 1295d38ceaf9SAlex Deucher 1296d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1297d38ceaf9SAlex Deucher { 1298d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1299d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1300d38ceaf9SAlex Deucher bool found = false; 1301d38ceaf9SAlex Deucher 130262afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1303d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1304d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1305d38ceaf9SAlex Deucher found = true; 1306d38ceaf9SAlex Deucher } 1307d38ceaf9SAlex Deucher 1308d38ceaf9SAlex Deucher return found; 1309d38ceaf9SAlex Deucher } 1310d38ceaf9SAlex Deucher 1311d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1312d38ceaf9SAlex Deucher { 1313d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 13141348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1315d38ceaf9SAlex Deucher 1316d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1317d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1318d38ceaf9SAlex Deucher return true; 1319d38ceaf9SAlex Deucher } 1320d38ceaf9SAlex Deucher 1321d38ceaf9SAlex Deucher return false; 1322d38ceaf9SAlex Deucher } 1323d38ceaf9SAlex Deucher 1324d38ceaf9SAlex Deucher static enum drm_connector_status 1325d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1326d38ceaf9SAlex Deucher { 1327d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 13281348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1329d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1330d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1331d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1332d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1333d38ceaf9SAlex Deucher int r; 1334d38ceaf9SAlex Deucher 1335aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1336d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1337f79f9476SNavid Emamdoost if (r < 0) { 1338f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 1339d38ceaf9SAlex Deucher return connector_status_disconnected; 1340aa0aad57SLukas Wunner } 1341f79f9476SNavid Emamdoost } 1342d38ceaf9SAlex Deucher 1343d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1344d38ceaf9SAlex Deucher ret = connector->status; 1345d38ceaf9SAlex Deucher goto out; 1346d38ceaf9SAlex Deucher } 1347d38ceaf9SAlex Deucher 1348d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1349d38ceaf9SAlex Deucher 1350d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1351d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1352d38ceaf9SAlex Deucher if (encoder) { 1353d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1354d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1355d38ceaf9SAlex Deucher 1356d38ceaf9SAlex Deucher /* check if panel is valid */ 1357d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1358d38ceaf9SAlex Deucher ret = connector_status_connected; 1359d38ceaf9SAlex Deucher } 1360d38ceaf9SAlex Deucher /* eDP is always DP */ 1361d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1362d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1363d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1364d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1365d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1366d38ceaf9SAlex Deucher ret = connector_status_connected; 1367d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1368d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1369d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1370d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1371d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1372d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1373d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1374d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1375d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1376d38ceaf9SAlex Deucher 1377d38ceaf9SAlex Deucher if (encoder) { 1378d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1379d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1380d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1381e0b5b5ecSSamuel Li /* try DDC */ 1382e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1383d38ceaf9SAlex Deucher ret = connector_status_connected; 1384d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 138517b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1386d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1387d38ceaf9SAlex Deucher } 1388d38ceaf9SAlex Deucher } 1389d38ceaf9SAlex Deucher } else { 1390d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1391d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1392d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1393d38ceaf9SAlex Deucher ret = connector_status_connected; 1394d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1395d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1396d38ceaf9SAlex Deucher } else { 1397d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1398d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1399d38ceaf9SAlex Deucher ret = connector_status_connected; 1400d38ceaf9SAlex Deucher } else { 1401d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1402e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, 1403e0b5b5ecSSamuel Li false)) 1404d38ceaf9SAlex Deucher ret = connector_status_connected; 1405d38ceaf9SAlex Deucher } 1406d38ceaf9SAlex Deucher } 1407d38ceaf9SAlex Deucher } 1408d38ceaf9SAlex Deucher 1409d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1410d38ceaf9SAlex Deucher out: 1411aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1412d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1413d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1414aa0aad57SLukas Wunner } 1415d38ceaf9SAlex Deucher 1416d38ceaf9SAlex Deucher return ret; 1417d38ceaf9SAlex Deucher } 1418d38ceaf9SAlex Deucher 1419ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1420d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1421d38ceaf9SAlex Deucher { 1422d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1423d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1424d38ceaf9SAlex Deucher 1425d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1426d38ceaf9SAlex Deucher 1427d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1428d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1429d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1430d38ceaf9SAlex Deucher 1431d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1432d38ceaf9SAlex Deucher return MODE_PANEL; 1433d38ceaf9SAlex Deucher 1434d38ceaf9SAlex Deucher if (encoder) { 1435d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1436d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1437d38ceaf9SAlex Deucher 1438d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1439d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1440d38ceaf9SAlex Deucher */ 1441d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1442d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1443d38ceaf9SAlex Deucher return MODE_PANEL; 1444d38ceaf9SAlex Deucher 1445d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1446d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1447d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1448d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1449d38ceaf9SAlex Deucher return MODE_PANEL; 1450d38ceaf9SAlex Deucher } 1451d38ceaf9SAlex Deucher } 1452d38ceaf9SAlex Deucher return MODE_OK; 1453d38ceaf9SAlex Deucher } else { 1454d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1455d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1456d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1457d38ceaf9SAlex Deucher } else { 1458d38ceaf9SAlex Deucher if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1459d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1460d38ceaf9SAlex Deucher if (mode->clock > 340000) 1461d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1462d38ceaf9SAlex Deucher } else { 1463d38ceaf9SAlex Deucher if (mode->clock > 165000) 1464d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1465d38ceaf9SAlex Deucher } 1466d38ceaf9SAlex Deucher } 1467d38ceaf9SAlex Deucher } 1468d38ceaf9SAlex Deucher 1469d38ceaf9SAlex Deucher return MODE_OK; 1470d38ceaf9SAlex Deucher } 1471d38ceaf9SAlex Deucher 1472405a1f90SAlex Deucher static int 1473405a1f90SAlex Deucher amdgpu_connector_late_register(struct drm_connector *connector) 1474405a1f90SAlex Deucher { 1475405a1f90SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1476405a1f90SAlex Deucher int r = 0; 1477405a1f90SAlex Deucher 1478405a1f90SAlex Deucher if (amdgpu_connector->ddc_bus->has_aux) { 1479405a1f90SAlex Deucher amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1480405a1f90SAlex Deucher r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1481405a1f90SAlex Deucher } 1482405a1f90SAlex Deucher 1483405a1f90SAlex Deucher return r; 1484405a1f90SAlex Deucher } 1485405a1f90SAlex Deucher 1486d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1487d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1488d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1489d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1490d38ceaf9SAlex Deucher }; 1491d38ceaf9SAlex Deucher 1492d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1493d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1494d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1495d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1496d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 149740492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1498d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1499d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1500405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register, 1501d38ceaf9SAlex Deucher }; 1502d38ceaf9SAlex Deucher 1503d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1504d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1505d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1506d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1507d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 150840492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1509d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1510d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1511405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register, 1512d38ceaf9SAlex Deucher }; 1513d38ceaf9SAlex Deucher 1514d38ceaf9SAlex Deucher void 1515d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1516d38ceaf9SAlex Deucher uint32_t connector_id, 1517d38ceaf9SAlex Deucher uint32_t supported_device, 1518d38ceaf9SAlex Deucher int connector_type, 1519d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1520d38ceaf9SAlex Deucher uint16_t connector_object_id, 1521d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1522d38ceaf9SAlex Deucher struct amdgpu_router *router) 1523d38ceaf9SAlex Deucher { 1524d38ceaf9SAlex Deucher struct drm_device *dev = adev->ddev; 1525d38ceaf9SAlex Deucher struct drm_connector *connector; 1526f8d2d39eSLyude Paul struct drm_connector_list_iter iter; 1527d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1528d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1529d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1530d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 15315b50fa2bSAndrzej Pietrasiewicz struct i2c_adapter *ddc = NULL; 1532d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1533d38ceaf9SAlex Deucher bool shared_ddc = false; 1534d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1535d38ceaf9SAlex Deucher bool has_aux = false; 1536d38ceaf9SAlex Deucher 1537d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1538d38ceaf9SAlex Deucher return; 1539d38ceaf9SAlex Deucher 1540d38ceaf9SAlex Deucher /* see if we already added it */ 1541f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter); 1542f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) { 1543d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1544d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1545d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1546f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1547d38ceaf9SAlex Deucher return; 1548d38ceaf9SAlex Deucher } 1549d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1550d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1551d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1552d38ceaf9SAlex Deucher shared_ddc = true; 1553d38ceaf9SAlex Deucher } 1554d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1555d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1556d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1557d38ceaf9SAlex Deucher shared_ddc = false; 1558d38ceaf9SAlex Deucher } 1559d38ceaf9SAlex Deucher } 1560d38ceaf9SAlex Deucher } 1561f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1562d38ceaf9SAlex Deucher 1563d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1564d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1565d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1566d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1567d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1568d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1569d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1570d38ceaf9SAlex Deucher is_dp_bridge = true; 1571d38ceaf9SAlex Deucher break; 1572d38ceaf9SAlex Deucher default: 1573d38ceaf9SAlex Deucher break; 1574d38ceaf9SAlex Deucher } 1575d38ceaf9SAlex Deucher } 1576d38ceaf9SAlex Deucher } 1577d38ceaf9SAlex Deucher 1578d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1579d38ceaf9SAlex Deucher if (!amdgpu_connector) 1580d38ceaf9SAlex Deucher return; 1581d38ceaf9SAlex Deucher 1582d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1583d38ceaf9SAlex Deucher 1584d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1585d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1586d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1587d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1588d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1589d38ceaf9SAlex Deucher 1590d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1591d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1592d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1593d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1594d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1595d38ceaf9SAlex Deucher } 1596d38ceaf9SAlex Deucher 1597d38ceaf9SAlex Deucher if (is_dp_bridge) { 1598d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1599d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1600d38ceaf9SAlex Deucher goto failed; 1601d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1602d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1603d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 16045b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1605d38ceaf9SAlex Deucher has_aux = true; 16065b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 16075b50fa2bSAndrzej Pietrasiewicz } else { 1608d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1609d38ceaf9SAlex Deucher } 16105b50fa2bSAndrzej Pietrasiewicz } 1611d38ceaf9SAlex Deucher switch (connector_type) { 1612d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1613d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1614d38ceaf9SAlex Deucher default: 16155b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16165b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 16175b50fa2bSAndrzej Pietrasiewicz connector_type, 16185b50fa2bSAndrzej Pietrasiewicz ddc); 1619d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1620d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1621d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1622d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1623d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1624d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1625d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1626d38ceaf9SAlex Deucher 1); 1627d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1628d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1629d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1630d38ceaf9SAlex Deucher break; 1631d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1632d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1633d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1634d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1635d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 16365b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16375b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 16385b50fa2bSAndrzej Pietrasiewicz connector_type, 16395b50fa2bSAndrzej Pietrasiewicz ddc); 1640d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1641d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1642d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1643d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1644d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1645d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1646d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1647d38ceaf9SAlex Deucher 0); 1648d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1649d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1650d38ceaf9SAlex Deucher 0); 1651d38ceaf9SAlex Deucher 1652d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1653d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1654d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1655d38ceaf9SAlex Deucher 1656d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1657d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1658d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1659d38ceaf9SAlex Deucher 1660d38ceaf9SAlex Deucher if (amdgpu_audio != 0) 1661d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1662d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1663d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1664d38ceaf9SAlex Deucher 1665d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1666d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1667d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1668d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1669d38ceaf9SAlex Deucher else 1670d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1671d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1672d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1673d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1674d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1675d38ceaf9SAlex Deucher 1); 1676d38ceaf9SAlex Deucher } 1677d38ceaf9SAlex Deucher break; 1678d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1679d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 16805b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16815b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs, 16825b50fa2bSAndrzej Pietrasiewicz connector_type, 16835b50fa2bSAndrzej Pietrasiewicz ddc); 1684d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1685d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1686d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1687d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1688d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1689d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1690d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1691d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1692d38ceaf9SAlex Deucher break; 1693d38ceaf9SAlex Deucher } 1694d38ceaf9SAlex Deucher } else { 1695d38ceaf9SAlex Deucher switch (connector_type) { 1696d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1697d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1698d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1699d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1700d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17015b50fa2bSAndrzej Pietrasiewicz else 17025b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1703d38ceaf9SAlex Deucher } 17045b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17055b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs, 17065b50fa2bSAndrzej Pietrasiewicz connector_type, 17075b50fa2bSAndrzej Pietrasiewicz ddc); 17085b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1709d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1710d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1711d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1712d38ceaf9SAlex Deucher 1); 1713d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1714d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1715d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1716d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1717d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1718d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1719d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1720d38ceaf9SAlex Deucher break; 1721d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1722d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1723d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1724d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1725d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17265b50fa2bSAndrzej Pietrasiewicz else 17275b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1728d38ceaf9SAlex Deucher } 17295b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17305b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs, 17315b50fa2bSAndrzej Pietrasiewicz connector_type, 17325b50fa2bSAndrzej Pietrasiewicz ddc); 17335b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1734d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1735d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1736d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1737d38ceaf9SAlex Deucher 1); 1738d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1739d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1740d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1741d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1742d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1743d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1744d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1745d38ceaf9SAlex Deucher break; 1746d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1747d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1748d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1749d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1750d38ceaf9SAlex Deucher goto failed; 1751d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1752d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1753d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1754d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1755d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17565b50fa2bSAndrzej Pietrasiewicz else 17575b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1758d38ceaf9SAlex Deucher } 17595b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17605b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs, 17615b50fa2bSAndrzej Pietrasiewicz connector_type, 17625b50fa2bSAndrzej Pietrasiewicz ddc); 17635b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1764d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1765d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1766d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1767d38ceaf9SAlex Deucher 1); 1768d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1769d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1770d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1771d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1772d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1773d38ceaf9SAlex Deucher 0); 1774d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1775d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1776d38ceaf9SAlex Deucher 0); 1777d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1778d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1779d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1780d38ceaf9SAlex Deucher 1781d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1782d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1783d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1784d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1785d38ceaf9SAlex Deucher } 1786d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1787d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1788d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1789d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1790d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1791d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1792d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1793d38ceaf9SAlex Deucher 1); 1794d38ceaf9SAlex Deucher } 1795d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1796d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1797d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1798d38ceaf9SAlex Deucher else 1799d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1800d38ceaf9SAlex Deucher break; 1801d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1802d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1803d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1804d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1805d38ceaf9SAlex Deucher goto failed; 1806d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1807d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1808d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1809d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1810d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 18115b50fa2bSAndrzej Pietrasiewicz else 18125b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1813d38ceaf9SAlex Deucher } 18145b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 18155b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs, 18165b50fa2bSAndrzej Pietrasiewicz connector_type, 18175b50fa2bSAndrzej Pietrasiewicz ddc); 18185b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1819d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1820d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1821d38ceaf9SAlex Deucher 1); 1822d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1823d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1824d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1825d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1826d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1827d38ceaf9SAlex Deucher 0); 1828d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1829d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1830d38ceaf9SAlex Deucher 0); 1831d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1832d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1833d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1834d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1835d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1836d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1837d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1838d38ceaf9SAlex Deucher } 1839d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1840d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1841d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1842d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1843d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1844d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1845d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1846d38ceaf9SAlex Deucher else 1847d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1848d38ceaf9SAlex Deucher break; 1849d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1850d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1851d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1852d38ceaf9SAlex Deucher goto failed; 1853d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1854d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1855d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 18565b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1857d38ceaf9SAlex Deucher has_aux = true; 18585b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 18595b50fa2bSAndrzej Pietrasiewicz } else { 1860d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1861d38ceaf9SAlex Deucher } 18625b50fa2bSAndrzej Pietrasiewicz } 18635b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 18645b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 18655b50fa2bSAndrzej Pietrasiewicz connector_type, 18665b50fa2bSAndrzej Pietrasiewicz ddc); 18675b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1868d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1869d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1870d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1871d38ceaf9SAlex Deucher 1); 1872d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1873d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1874d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1875d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1876d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1877d38ceaf9SAlex Deucher 0); 1878d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1879d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1880d38ceaf9SAlex Deucher 0); 1881d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1882d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1883d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1884d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1885d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1886d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1887d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 1888d38ceaf9SAlex Deucher } 1889d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1890d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1891d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1892d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1893d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1894d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1895d38ceaf9SAlex Deucher break; 1896d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1897d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1898d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1899d38ceaf9SAlex Deucher goto failed; 1900d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1901d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1902d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 19035b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1904d38ceaf9SAlex Deucher has_aux = true; 19055b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 19065b50fa2bSAndrzej Pietrasiewicz } else { 1907d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1908d38ceaf9SAlex Deucher } 19095b50fa2bSAndrzej Pietrasiewicz } 19105b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19115b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs, 19125b50fa2bSAndrzej Pietrasiewicz connector_type, 19135b50fa2bSAndrzej Pietrasiewicz ddc); 19145b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1915d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1916d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1917d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1918d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1919d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1920d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1921d38ceaf9SAlex Deucher break; 1922d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1923d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1924d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1925d38ceaf9SAlex Deucher goto failed; 1926d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1927d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1928d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1929d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1930d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 19315b50fa2bSAndrzej Pietrasiewicz else 19325b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1933d38ceaf9SAlex Deucher } 19345b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19355b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_lvds_funcs, 19365b50fa2bSAndrzej Pietrasiewicz connector_type, 19375b50fa2bSAndrzej Pietrasiewicz ddc); 19385b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1939d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1940d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1941d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1942d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1943d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1944d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1945d38ceaf9SAlex Deucher break; 1946d38ceaf9SAlex Deucher } 1947d38ceaf9SAlex Deucher } 1948d38ceaf9SAlex Deucher 1949d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1950b636a1b3SLyude if (i2c_bus->valid) { 1951b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1952b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT; 1953b636a1b3SLyude } 1954d38ceaf9SAlex Deucher } else 1955d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 1956d38ceaf9SAlex Deucher 1957d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 1958d38ceaf9SAlex Deucher 1959d38ceaf9SAlex Deucher if (has_aux) 1960d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 1961d38ceaf9SAlex Deucher 1962d38ceaf9SAlex Deucher return; 1963d38ceaf9SAlex Deucher 1964d38ceaf9SAlex Deucher failed: 1965d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 1966d38ceaf9SAlex Deucher kfree(connector); 1967d38ceaf9SAlex Deucher } 1968