1d38ceaf9SAlex Deucher /*
2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc.
3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc.
4d38ceaf9SAlex Deucher *
5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a
6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"),
7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation
8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the
10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions:
11d38ceaf9SAlex Deucher *
12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in
13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software.
14d38ceaf9SAlex Deucher *
15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE.
22d38ceaf9SAlex Deucher *
23d38ceaf9SAlex Deucher * Authors: Dave Airlie
24d38ceaf9SAlex Deucher * Alex Deucher
25d38ceaf9SAlex Deucher */
26fdf2f6c5SSam Ravnborg
27da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h>
28973ad627SThomas Zimmermann #include <drm/drm_crtc_helper.h>
29d38ceaf9SAlex Deucher #include <drm/drm_edid.h>
30973ad627SThomas Zimmermann #include <drm/drm_modeset_helper_vtables.h>
31fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h>
32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h>
33d38ceaf9SAlex Deucher #include "amdgpu.h"
34d38ceaf9SAlex Deucher #include "atom.h"
35d38ceaf9SAlex Deucher #include "atombios_encoders.h"
36d38ceaf9SAlex Deucher #include "atombios_dp.h"
37d38ceaf9SAlex Deucher #include "amdgpu_connectors.h"
38d38ceaf9SAlex Deucher #include "amdgpu_i2c.h"
395df58525SHuang Rui #include "amdgpu_display.h"
40d38ceaf9SAlex Deucher
41d38ceaf9SAlex Deucher #include <linux/pm_runtime.h>
42d38ceaf9SAlex Deucher
amdgpu_connector_hotplug(struct drm_connector * connector)43d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector)
44d38ceaf9SAlex Deucher {
45d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
461348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
47d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
48d38ceaf9SAlex Deucher
49d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g.,
50d38ceaf9SAlex Deucher * VGA, TV, etc.
51d38ceaf9SAlex Deucher */
52d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
53d38ceaf9SAlex Deucher return;
54d38ceaf9SAlex Deucher
55d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
56d38ceaf9SAlex Deucher
57d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */
58d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON)
59d38ceaf9SAlex Deucher return;
60d38ceaf9SAlex Deucher
61d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */
62d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
63d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector =
64d38ceaf9SAlex Deucher amdgpu_connector->con_priv;
65d38ceaf9SAlex Deucher
66d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */
67d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
68d38ceaf9SAlex Deucher return;
69d38ceaf9SAlex Deucher
70d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */
71d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
72d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e.,
73d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor
74d38ceaf9SAlex Deucher */
75daf88096SMichel Dänzer if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
76daf88096SMichel Dänzer amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
77daf88096SMichel Dänzer amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
78daf88096SMichel Dänzer /* Don't start link training before we have the DPCD */
790b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
80a887adadSAlex Deucher return;
81a887adadSAlex Deucher
82daf88096SMichel Dänzer /* Turn the connector off and back on immediately, which
83daf88096SMichel Dänzer * will trigger link training
84d38ceaf9SAlex Deucher */
85daf88096SMichel Dänzer drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
86d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
87d38ceaf9SAlex Deucher }
88d38ceaf9SAlex Deucher }
89d38ceaf9SAlex Deucher }
90d38ceaf9SAlex Deucher
amdgpu_connector_property_change_mode(struct drm_encoder * encoder)91d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
92d38ceaf9SAlex Deucher {
93d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc;
94d38ceaf9SAlex Deucher
95d38ceaf9SAlex Deucher if (crtc && crtc->enabled) {
96d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode,
97d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb);
98d38ceaf9SAlex Deucher }
99d38ceaf9SAlex Deucher }
100d38ceaf9SAlex Deucher
amdgpu_connector_get_monitor_bpc(struct drm_connector * connector)101d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
102d38ceaf9SAlex Deucher {
103d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
104d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector;
105d38ceaf9SAlex Deucher int bpc = 8;
106d38ceaf9SAlex Deucher unsigned mode_clock, max_tmds_clock;
107d38ceaf9SAlex Deucher
108d38ceaf9SAlex Deucher switch (connector->connector_type) {
109d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII:
110d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB:
111d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) {
1123c021931SClaudio Suarez if (connector->display_info.is_hdmi) {
113d38ceaf9SAlex Deucher if (connector->display_info.bpc)
114d38ceaf9SAlex Deucher bpc = connector->display_info.bpc;
115d38ceaf9SAlex Deucher }
116d38ceaf9SAlex Deucher }
117d38ceaf9SAlex Deucher break;
118d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID:
119d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA:
1203c021931SClaudio Suarez if (connector->display_info.is_hdmi) {
121d38ceaf9SAlex Deucher if (connector->display_info.bpc)
122d38ceaf9SAlex Deucher bpc = connector->display_info.bpc;
123d38ceaf9SAlex Deucher }
124d38ceaf9SAlex Deucher break;
125d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort:
126d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv;
127d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
128d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
1293c021931SClaudio Suarez connector->display_info.is_hdmi) {
130d38ceaf9SAlex Deucher if (connector->display_info.bpc)
131d38ceaf9SAlex Deucher bpc = connector->display_info.bpc;
132d38ceaf9SAlex Deucher }
133d38ceaf9SAlex Deucher break;
134d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP:
135d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS:
136d38ceaf9SAlex Deucher if (connector->display_info.bpc)
137d38ceaf9SAlex Deucher bpc = connector->display_info.bpc;
138d38ceaf9SAlex Deucher else {
13917b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs =
140d38ceaf9SAlex Deucher connector->helper_private;
141d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
142d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
143d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
144d38ceaf9SAlex Deucher
145d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
146d38ceaf9SAlex Deucher bpc = 6;
147d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
148d38ceaf9SAlex Deucher bpc = 8;
149d38ceaf9SAlex Deucher }
150d38ceaf9SAlex Deucher break;
151d38ceaf9SAlex Deucher }
152d38ceaf9SAlex Deucher
1533c021931SClaudio Suarez if (connector->display_info.is_hdmi) {
154d38ceaf9SAlex Deucher /*
155d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
156d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
157d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is
158d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
159d38ceaf9SAlex Deucher */
160d38ceaf9SAlex Deucher if (bpc > 12) {
161d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
162d38ceaf9SAlex Deucher connector->name, bpc);
163d38ceaf9SAlex Deucher bpc = 12;
164d38ceaf9SAlex Deucher }
165d38ceaf9SAlex Deucher
166d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */
1672a272ca9SVille Syrjälä if (connector->display_info.max_tmds_clock > 0) {
168d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */
169d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset;
170d38ceaf9SAlex Deucher
171d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */
1722a272ca9SVille Syrjälä max_tmds_clock = connector->display_info.max_tmds_clock;
173d38ceaf9SAlex Deucher
174d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
175d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock);
176d38ceaf9SAlex Deucher
177d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
178d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
1794adc33f3SMaxime Ripard if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
180d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock))
181d38ceaf9SAlex Deucher bpc = 10;
182d38ceaf9SAlex Deucher else
183d38ceaf9SAlex Deucher bpc = 8;
184d38ceaf9SAlex Deucher
185d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
186d38ceaf9SAlex Deucher connector->name, bpc);
187d38ceaf9SAlex Deucher }
188d38ceaf9SAlex Deucher
189d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
190d38ceaf9SAlex Deucher bpc = 8;
191d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
192d38ceaf9SAlex Deucher connector->name, bpc);
1939d746ab6SMario Kleiner }
194d38ceaf9SAlex Deucher } else if (bpc > 8) {
195d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
196d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
197d38ceaf9SAlex Deucher connector->name);
198d38ceaf9SAlex Deucher bpc = 8;
199d38ceaf9SAlex Deucher }
200d38ceaf9SAlex Deucher }
201d38ceaf9SAlex Deucher
202d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) {
203d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
204d38ceaf9SAlex Deucher connector->name);
205d38ceaf9SAlex Deucher bpc = 8;
206d38ceaf9SAlex Deucher }
207d38ceaf9SAlex Deucher
208d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
209d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc);
210d38ceaf9SAlex Deucher
211d38ceaf9SAlex Deucher return bpc;
212d38ceaf9SAlex Deucher }
213d38ceaf9SAlex Deucher
214d38ceaf9SAlex Deucher static void
amdgpu_connector_update_scratch_regs(struct drm_connector * connector,enum drm_connector_status status)215d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
216d38ceaf9SAlex Deucher enum drm_connector_status status)
217d38ceaf9SAlex Deucher {
21898c0e348SVille Syrjälä struct drm_encoder *best_encoder;
21998c0e348SVille Syrjälä struct drm_encoder *encoder;
22017b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
221d38ceaf9SAlex Deucher bool connected;
222d38ceaf9SAlex Deucher
223d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector);
224d38ceaf9SAlex Deucher
22562afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) {
226d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected))
227d38ceaf9SAlex Deucher connected = true;
228d38ceaf9SAlex Deucher else
229d38ceaf9SAlex Deucher connected = false;
230d38ceaf9SAlex Deucher
231d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
232d38ceaf9SAlex Deucher }
233d38ceaf9SAlex Deucher }
234d38ceaf9SAlex Deucher
235d38ceaf9SAlex Deucher static struct drm_encoder *
amdgpu_connector_find_encoder(struct drm_connector * connector,int encoder_type)236d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector,
237d38ceaf9SAlex Deucher int encoder_type)
238d38ceaf9SAlex Deucher {
239d38ceaf9SAlex Deucher struct drm_encoder *encoder;
240d38ceaf9SAlex Deucher
24162afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) {
242d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type)
243d38ceaf9SAlex Deucher return encoder;
244d38ceaf9SAlex Deucher }
24598c0e348SVille Syrjälä
246d38ceaf9SAlex Deucher return NULL;
247d38ceaf9SAlex Deucher }
248d38ceaf9SAlex Deucher
amdgpu_connector_edid(struct drm_connector * connector)249d38ceaf9SAlex Deucher struct edid *amdgpu_connector_edid(struct drm_connector *connector)
250d38ceaf9SAlex Deucher {
251d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
252d38ceaf9SAlex Deucher struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
253d38ceaf9SAlex Deucher
254d38ceaf9SAlex Deucher if (amdgpu_connector->edid) {
255d38ceaf9SAlex Deucher return amdgpu_connector->edid;
256d38ceaf9SAlex Deucher } else if (edid_blob) {
257d38ceaf9SAlex Deucher struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
258d38ceaf9SAlex Deucher if (edid)
259d38ceaf9SAlex Deucher amdgpu_connector->edid = edid;
260d38ceaf9SAlex Deucher }
261d38ceaf9SAlex Deucher return amdgpu_connector->edid;
262d38ceaf9SAlex Deucher }
263d38ceaf9SAlex Deucher
264d38ceaf9SAlex Deucher static struct edid *
amdgpu_connector_get_hardcoded_edid(struct amdgpu_device * adev)265d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
266d38ceaf9SAlex Deucher {
267d38ceaf9SAlex Deucher struct edid *edid;
268d38ceaf9SAlex Deucher
269d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) {
270d38ceaf9SAlex Deucher edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
271d38ceaf9SAlex Deucher if (edid) {
272d38ceaf9SAlex Deucher memcpy((unsigned char *)edid,
273d38ceaf9SAlex Deucher (unsigned char *)adev->mode_info.bios_hardcoded_edid,
274d38ceaf9SAlex Deucher adev->mode_info.bios_hardcoded_edid_size);
275d38ceaf9SAlex Deucher return edid;
276d38ceaf9SAlex Deucher }
277d38ceaf9SAlex Deucher }
278d38ceaf9SAlex Deucher return NULL;
279d38ceaf9SAlex Deucher }
280d38ceaf9SAlex Deucher
amdgpu_connector_get_edid(struct drm_connector * connector)281d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector)
282d38ceaf9SAlex Deucher {
283d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
2841348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
285d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
286d38ceaf9SAlex Deucher
287d38ceaf9SAlex Deucher if (amdgpu_connector->edid)
288d38ceaf9SAlex Deucher return;
289d38ceaf9SAlex Deucher
290d38ceaf9SAlex Deucher /* on hw with routers, select right port */
291d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid)
292d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
293d38ceaf9SAlex Deucher
294d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
295d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) &&
296d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) {
297d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector,
298d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc);
299d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
300d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
301d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
302d38ceaf9SAlex Deucher
303d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
304d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
305d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux)
306d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector,
307d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc);
308d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus)
309d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector,
310d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter);
311d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) {
312d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector,
313d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter);
314d38ceaf9SAlex Deucher }
315d38ceaf9SAlex Deucher
316d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) {
317d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */
318d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
31920543be9SClaudio Suarez (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
320d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
32120543be9SClaudio Suarez drm_connector_update_edid_property(connector, amdgpu_connector->edid);
32220543be9SClaudio Suarez }
323d38ceaf9SAlex Deucher }
324d38ceaf9SAlex Deucher }
325d38ceaf9SAlex Deucher
amdgpu_connector_free_edid(struct drm_connector * connector)326d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector)
327d38ceaf9SAlex Deucher {
328d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
329d38ceaf9SAlex Deucher
330d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid);
331d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL;
332d38ceaf9SAlex Deucher }
333d38ceaf9SAlex Deucher
amdgpu_connector_ddc_get_modes(struct drm_connector * connector)334d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
335d38ceaf9SAlex Deucher {
336d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
337d38ceaf9SAlex Deucher int ret;
338d38ceaf9SAlex Deucher
339d38ceaf9SAlex Deucher if (amdgpu_connector->edid) {
340c555f023SDaniel Vetter drm_connector_update_edid_property(connector, amdgpu_connector->edid);
341d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
342d38ceaf9SAlex Deucher return ret;
343d38ceaf9SAlex Deucher }
344c555f023SDaniel Vetter drm_connector_update_edid_property(connector, NULL);
345d38ceaf9SAlex Deucher return 0;
346d38ceaf9SAlex Deucher }
347d38ceaf9SAlex Deucher
348d38ceaf9SAlex Deucher static struct drm_encoder *
amdgpu_connector_best_single_encoder(struct drm_connector * connector)349d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector)
350d38ceaf9SAlex Deucher {
35198c0e348SVille Syrjälä struct drm_encoder *encoder;
352d38ceaf9SAlex Deucher
35398c0e348SVille Syrjälä /* pick the first one */
35462afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder)
35598c0e348SVille Syrjälä return encoder;
35698c0e348SVille Syrjälä
357d38ceaf9SAlex Deucher return NULL;
358d38ceaf9SAlex Deucher }
359d38ceaf9SAlex Deucher
amdgpu_get_native_mode(struct drm_connector * connector)360d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector)
361d38ceaf9SAlex Deucher {
362d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
363d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
364d38ceaf9SAlex Deucher
365d38ceaf9SAlex Deucher if (encoder == NULL)
366d38ceaf9SAlex Deucher return;
367d38ceaf9SAlex Deucher
368d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
369d38ceaf9SAlex Deucher
370d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) {
371d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode =
372d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes,
373d38ceaf9SAlex Deucher struct drm_display_mode, head);
374d38ceaf9SAlex Deucher
375d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode;
376d38ceaf9SAlex Deucher } else {
377d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0;
378d38ceaf9SAlex Deucher }
379d38ceaf9SAlex Deucher }
380d38ceaf9SAlex Deucher
381d38ceaf9SAlex Deucher static struct drm_display_mode *
amdgpu_connector_lcd_native_mode(struct drm_encoder * encoder)382d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
383d38ceaf9SAlex Deucher {
384d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev;
385d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
386d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL;
387d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
388d38ceaf9SAlex Deucher
389d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 &&
390d38ceaf9SAlex Deucher native_mode->vdisplay != 0 &&
391d38ceaf9SAlex Deucher native_mode->clock != 0) {
392d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode);
393b220110eSZhou Qingyang if (!mode)
394b220110eSZhou Qingyang return NULL;
395b220110eSZhou Qingyang
396d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
397d38ceaf9SAlex Deucher drm_mode_set_name(mode);
398d38ceaf9SAlex Deucher
399d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
400d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 &&
401d38ceaf9SAlex Deucher native_mode->vdisplay != 0) {
402d38ceaf9SAlex Deucher /* mac laptops without an edid */
403d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode,
404d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these
405d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the
406d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much
407d38ceaf9SAlex Deucher * simpler.
408d38ceaf9SAlex Deucher */
409d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
410b220110eSZhou Qingyang if (!mode)
411b220110eSZhou Qingyang return NULL;
412b220110eSZhou Qingyang
413d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
414d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
415d38ceaf9SAlex Deucher }
416d38ceaf9SAlex Deucher return mode;
417d38ceaf9SAlex Deucher }
418d38ceaf9SAlex Deucher
amdgpu_connector_add_common_modes(struct drm_encoder * encoder,struct drm_connector * connector)419d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
420d38ceaf9SAlex Deucher struct drm_connector *connector)
421d38ceaf9SAlex Deucher {
422d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev;
423d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
424d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL;
425d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
426d38ceaf9SAlex Deucher int i;
427aeba709aSNils Wallménius static const struct mode_size {
428d38ceaf9SAlex Deucher int w;
429d38ceaf9SAlex Deucher int h;
430d38ceaf9SAlex Deucher } common_modes[17] = {
431d38ceaf9SAlex Deucher { 640, 480},
432d38ceaf9SAlex Deucher { 720, 480},
433d38ceaf9SAlex Deucher { 800, 600},
434d38ceaf9SAlex Deucher { 848, 480},
435d38ceaf9SAlex Deucher {1024, 768},
436d38ceaf9SAlex Deucher {1152, 768},
437d38ceaf9SAlex Deucher {1280, 720},
438d38ceaf9SAlex Deucher {1280, 800},
439d38ceaf9SAlex Deucher {1280, 854},
440d38ceaf9SAlex Deucher {1280, 960},
441d38ceaf9SAlex Deucher {1280, 1024},
442d38ceaf9SAlex Deucher {1440, 900},
443d38ceaf9SAlex Deucher {1400, 1050},
444d38ceaf9SAlex Deucher {1680, 1050},
445d38ceaf9SAlex Deucher {1600, 1200},
446d38ceaf9SAlex Deucher {1920, 1080},
447d38ceaf9SAlex Deucher {1920, 1200}
448d38ceaf9SAlex Deucher };
449d38ceaf9SAlex Deucher
450d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) {
451d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
452d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 ||
453d38ceaf9SAlex Deucher common_modes[i].h > 768)
454d38ceaf9SAlex Deucher continue;
455d38ceaf9SAlex Deucher }
456d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
457d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay ||
458d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay ||
459d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay &&
460d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay))
461d38ceaf9SAlex Deucher continue;
462d38ceaf9SAlex Deucher }
463d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200)
464d38ceaf9SAlex Deucher continue;
465d38ceaf9SAlex Deucher
466d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
467d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode);
468d38ceaf9SAlex Deucher }
469d38ceaf9SAlex Deucher }
470d38ceaf9SAlex Deucher
amdgpu_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)471d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector,
472d38ceaf9SAlex Deucher struct drm_property *property,
473d38ceaf9SAlex Deucher uint64_t val)
474d38ceaf9SAlex Deucher {
475d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
4761348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
477d38ceaf9SAlex Deucher struct drm_encoder *encoder;
478d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
479d38ceaf9SAlex Deucher
480d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) {
481d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig;
482d38ceaf9SAlex Deucher bool new_coherent_mode;
483d38ceaf9SAlex Deucher
484d38ceaf9SAlex Deucher /* need to find digital encoder on connector */
485d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
486d38ceaf9SAlex Deucher if (!encoder)
487d38ceaf9SAlex Deucher return 0;
488d38ceaf9SAlex Deucher
489d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
490d38ceaf9SAlex Deucher
491d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv)
492d38ceaf9SAlex Deucher return 0;
493d38ceaf9SAlex Deucher
494d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv;
495d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false;
496d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) {
497d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode;
498d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
499d38ceaf9SAlex Deucher }
500d38ceaf9SAlex Deucher }
501d38ceaf9SAlex Deucher
502d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) {
503d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
504d38ceaf9SAlex Deucher /* need to find digital encoder on connector */
505d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
506d38ceaf9SAlex Deucher if (!encoder)
507d38ceaf9SAlex Deucher return 0;
508d38ceaf9SAlex Deucher
509d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
510d38ceaf9SAlex Deucher
511d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) {
512d38ceaf9SAlex Deucher amdgpu_connector->audio = val;
513d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
514d38ceaf9SAlex Deucher }
515d38ceaf9SAlex Deucher }
516d38ceaf9SAlex Deucher
517d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) {
518d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
519d38ceaf9SAlex Deucher /* need to find digital encoder on connector */
520d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
521d38ceaf9SAlex Deucher if (!encoder)
522d38ceaf9SAlex Deucher return 0;
523d38ceaf9SAlex Deucher
524d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
525d38ceaf9SAlex Deucher
526d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) {
527d38ceaf9SAlex Deucher amdgpu_connector->dither = val;
528d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
529d38ceaf9SAlex Deucher }
530d38ceaf9SAlex Deucher }
531d38ceaf9SAlex Deucher
532d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) {
533d38ceaf9SAlex Deucher /* need to find digital encoder on connector */
534d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
535d38ceaf9SAlex Deucher if (!encoder)
536d38ceaf9SAlex Deucher return 0;
537d38ceaf9SAlex Deucher
538d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
539d38ceaf9SAlex Deucher
540d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) {
541d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val;
542d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
543d38ceaf9SAlex Deucher }
544d38ceaf9SAlex Deucher }
545d38ceaf9SAlex Deucher
546d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) {
547d38ceaf9SAlex Deucher /* need to find digital encoder on connector */
548d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
549d38ceaf9SAlex Deucher if (!encoder)
550d38ceaf9SAlex Deucher return 0;
551d38ceaf9SAlex Deucher
552d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
553d38ceaf9SAlex Deucher
554d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) {
555d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val;
556d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
557d38ceaf9SAlex Deucher }
558d38ceaf9SAlex Deucher }
559d38ceaf9SAlex Deucher
560d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) {
561d38ceaf9SAlex Deucher /* need to find digital encoder on connector */
562d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
563d38ceaf9SAlex Deucher if (!encoder)
564d38ceaf9SAlex Deucher return 0;
565d38ceaf9SAlex Deucher
566d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
567d38ceaf9SAlex Deucher
568d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) {
569d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val;
570d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
571d38ceaf9SAlex Deucher }
572d38ceaf9SAlex Deucher }
573d38ceaf9SAlex Deucher
574d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) {
575d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector =
576d38ceaf9SAlex Deucher to_amdgpu_connector(connector);
577d38ceaf9SAlex Deucher
578d38ceaf9SAlex Deucher if (val == 0)
579d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false;
580d38ceaf9SAlex Deucher else
581d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true;
582d38ceaf9SAlex Deucher }
583d38ceaf9SAlex Deucher
584d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) {
585d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type;
586d38ceaf9SAlex Deucher
587d38ceaf9SAlex Deucher if (connector->encoder) {
588d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
589d38ceaf9SAlex Deucher } else {
59017b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
591d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
592d38ceaf9SAlex Deucher }
593d38ceaf9SAlex Deucher
594d38ceaf9SAlex Deucher switch (val) {
595d38ceaf9SAlex Deucher default:
596*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_NONE:
597*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_OFF;
598*a6f7baa3SSrinivasan Shanmugam break;
599*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_CENTER:
600*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_CENTER;
601*a6f7baa3SSrinivasan Shanmugam break;
602*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_ASPECT:
603*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_ASPECT;
604*a6f7baa3SSrinivasan Shanmugam break;
605*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_FULLSCREEN:
606*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_FULL;
607*a6f7baa3SSrinivasan Shanmugam break;
608d38ceaf9SAlex Deucher }
609*a6f7baa3SSrinivasan Shanmugam
610d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type)
611d38ceaf9SAlex Deucher return 0;
612d38ceaf9SAlex Deucher
613d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) &&
614d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0))
615d38ceaf9SAlex Deucher return 0;
616d38ceaf9SAlex Deucher
617d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type;
618d38ceaf9SAlex Deucher
619d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
620d38ceaf9SAlex Deucher }
621d38ceaf9SAlex Deucher
622d38ceaf9SAlex Deucher return 0;
623d38ceaf9SAlex Deucher }
624d38ceaf9SAlex Deucher
625d38ceaf9SAlex Deucher static void
amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder * encoder,struct drm_connector * connector)626d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
627d38ceaf9SAlex Deucher struct drm_connector *connector)
628d38ceaf9SAlex Deucher {
629d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
630d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
631d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode;
632d38ceaf9SAlex Deucher
633d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */
634d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
635d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) {
636d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay ||
637d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay)
638426c89aaSVille Syrjälä drm_mode_copy(native_mode, mode);
639d38ceaf9SAlex Deucher }
640d38ceaf9SAlex Deucher }
641d38ceaf9SAlex Deucher
642d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */
643d38ceaf9SAlex Deucher if (!native_mode->clock) {
644d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
645d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay &&
646d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) {
647426c89aaSVille Syrjälä drm_mode_copy(native_mode, mode);
648d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
649d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
650d38ceaf9SAlex Deucher break;
651d38ceaf9SAlex Deucher }
652d38ceaf9SAlex Deucher }
653d38ceaf9SAlex Deucher }
654d38ceaf9SAlex Deucher
655d38ceaf9SAlex Deucher if (!native_mode->clock) {
656d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
657d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF;
658d38ceaf9SAlex Deucher }
659d38ceaf9SAlex Deucher }
660d38ceaf9SAlex Deucher
amdgpu_connector_lvds_get_modes(struct drm_connector * connector)661d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
662d38ceaf9SAlex Deucher {
663d38ceaf9SAlex Deucher struct drm_encoder *encoder;
664d38ceaf9SAlex Deucher int ret = 0;
665d38ceaf9SAlex Deucher struct drm_display_mode *mode;
666d38ceaf9SAlex Deucher
667d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
668d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector);
669d38ceaf9SAlex Deucher if (ret > 0) {
670d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector);
671d38ceaf9SAlex Deucher if (encoder) {
672d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
673d38ceaf9SAlex Deucher /* add scaled modes */
674d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector);
675d38ceaf9SAlex Deucher }
676d38ceaf9SAlex Deucher return ret;
677d38ceaf9SAlex Deucher }
678d38ceaf9SAlex Deucher
679d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector);
680d38ceaf9SAlex Deucher if (!encoder)
681d38ceaf9SAlex Deucher return 0;
682d38ceaf9SAlex Deucher
683d38ceaf9SAlex Deucher /* we have no EDID modes */
684d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder);
685d38ceaf9SAlex Deucher if (mode) {
686d38ceaf9SAlex Deucher ret = 1;
687d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode);
688d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */
689d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm;
690d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm;
691d38ceaf9SAlex Deucher /* add scaled modes */
692d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector);
693d38ceaf9SAlex Deucher }
694d38ceaf9SAlex Deucher
695d38ceaf9SAlex Deucher return ret;
696d38ceaf9SAlex Deucher }
697d38ceaf9SAlex Deucher
amdgpu_connector_lvds_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)698ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
699d38ceaf9SAlex Deucher struct drm_display_mode *mode)
700d38ceaf9SAlex Deucher {
701d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
702d38ceaf9SAlex Deucher
703d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
704d38ceaf9SAlex Deucher return MODE_PANEL;
705d38ceaf9SAlex Deucher
706d38ceaf9SAlex Deucher if (encoder) {
707d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
708d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
709d38ceaf9SAlex Deucher
710d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel
711d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable.
712d38ceaf9SAlex Deucher */
713d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) ||
714d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay))
715d38ceaf9SAlex Deucher return MODE_PANEL;
716d38ceaf9SAlex Deucher
717d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */
718d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) {
719d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) ||
720d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay))
721d38ceaf9SAlex Deucher return MODE_PANEL;
722d38ceaf9SAlex Deucher }
723d38ceaf9SAlex Deucher }
724d38ceaf9SAlex Deucher
725d38ceaf9SAlex Deucher return MODE_OK;
726d38ceaf9SAlex Deucher }
727d38ceaf9SAlex Deucher
728d38ceaf9SAlex Deucher static enum drm_connector_status
amdgpu_connector_lvds_detect(struct drm_connector * connector,bool force)729d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
730d38ceaf9SAlex Deucher {
731d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
732d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
733d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected;
734d38ceaf9SAlex Deucher int r;
735d38ceaf9SAlex Deucher
736aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
737d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev);
738f79f9476SNavid Emamdoost if (r < 0) {
739f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev);
740d38ceaf9SAlex Deucher return connector_status_disconnected;
741aa0aad57SLukas Wunner }
742f79f9476SNavid Emamdoost }
743d38ceaf9SAlex Deucher
744d38ceaf9SAlex Deucher if (encoder) {
745d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
746d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
747d38ceaf9SAlex Deucher
748d38ceaf9SAlex Deucher /* check if panel is valid */
749d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
750d38ceaf9SAlex Deucher ret = connector_status_connected;
751d38ceaf9SAlex Deucher
752d38ceaf9SAlex Deucher }
753d38ceaf9SAlex Deucher
754d38ceaf9SAlex Deucher /* check for edid as well */
755d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
756d38ceaf9SAlex Deucher if (amdgpu_connector->edid)
757d38ceaf9SAlex Deucher ret = connector_status_connected;
758d38ceaf9SAlex Deucher /* check acpi lid status ??? */
759d38ceaf9SAlex Deucher
760d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret);
761aa0aad57SLukas Wunner
762aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
763d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev);
764d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev);
765aa0aad57SLukas Wunner }
766aa0aad57SLukas Wunner
767d38ceaf9SAlex Deucher return ret;
768d38ceaf9SAlex Deucher }
769d38ceaf9SAlex Deucher
amdgpu_connector_unregister(struct drm_connector * connector)77040492f60SGrazvydas Ignotas static void amdgpu_connector_unregister(struct drm_connector *connector)
771d38ceaf9SAlex Deucher {
772d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
773d38ceaf9SAlex Deucher
774eef2b411SAlex Deucher if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
775d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
7762f9ba199SGrazvydas Ignotas amdgpu_connector->ddc_bus->has_aux = false;
7772f9ba199SGrazvydas Ignotas }
77840492f60SGrazvydas Ignotas }
77940492f60SGrazvydas Ignotas
amdgpu_connector_destroy(struct drm_connector * connector)78040492f60SGrazvydas Ignotas static void amdgpu_connector_destroy(struct drm_connector *connector)
78140492f60SGrazvydas Ignotas {
78240492f60SGrazvydas Ignotas struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
78340492f60SGrazvydas Ignotas
784d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
785d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv);
786d38ceaf9SAlex Deucher drm_connector_unregister(connector);
787d38ceaf9SAlex Deucher drm_connector_cleanup(connector);
788d38ceaf9SAlex Deucher kfree(connector);
789d38ceaf9SAlex Deucher }
790d38ceaf9SAlex Deucher
amdgpu_connector_set_lcd_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)791d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
792d38ceaf9SAlex Deucher struct drm_property *property,
793d38ceaf9SAlex Deucher uint64_t value)
794d38ceaf9SAlex Deucher {
795d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
796d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
797d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type;
798d38ceaf9SAlex Deucher
799d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n");
800d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property)
801d38ceaf9SAlex Deucher return 0;
802d38ceaf9SAlex Deucher
803d38ceaf9SAlex Deucher if (connector->encoder)
804d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
805d38ceaf9SAlex Deucher else {
80617b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
807d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
808d38ceaf9SAlex Deucher }
809d38ceaf9SAlex Deucher
810d38ceaf9SAlex Deucher switch (value) {
811*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_NONE:
812*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_OFF;
813*a6f7baa3SSrinivasan Shanmugam break;
814*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_CENTER:
815*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_CENTER;
816*a6f7baa3SSrinivasan Shanmugam break;
817*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_ASPECT:
818*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_ASPECT;
819*a6f7baa3SSrinivasan Shanmugam break;
820d38ceaf9SAlex Deucher default:
821*a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_FULLSCREEN:
822*a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_FULL;
823*a6f7baa3SSrinivasan Shanmugam break;
824d38ceaf9SAlex Deucher }
825*a6f7baa3SSrinivasan Shanmugam
826d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type)
827d38ceaf9SAlex Deucher return 0;
828d38ceaf9SAlex Deucher
829d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type;
830d38ceaf9SAlex Deucher
831d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
832d38ceaf9SAlex Deucher return 0;
833d38ceaf9SAlex Deucher }
834d38ceaf9SAlex Deucher
835d38ceaf9SAlex Deucher
836d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
837d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes,
838d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid,
839d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder,
840d38ceaf9SAlex Deucher };
841d38ceaf9SAlex Deucher
842d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
843d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms,
844d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect,
845d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes,
84640492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister,
847d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy,
848d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property,
849d38ceaf9SAlex Deucher };
850d38ceaf9SAlex Deucher
amdgpu_connector_vga_get_modes(struct drm_connector * connector)851d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
852d38ceaf9SAlex Deucher {
853d38ceaf9SAlex Deucher int ret;
854d38ceaf9SAlex Deucher
855d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
856d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector);
8576c5af7d2Shongao amdgpu_get_native_mode(connector);
858d38ceaf9SAlex Deucher
859d38ceaf9SAlex Deucher return ret;
860d38ceaf9SAlex Deucher }
861d38ceaf9SAlex Deucher
amdgpu_connector_vga_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)862ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
863d38ceaf9SAlex Deucher struct drm_display_mode *mode)
864d38ceaf9SAlex Deucher {
865d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
8661348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
867d38ceaf9SAlex Deucher
868d38ceaf9SAlex Deucher /* XXX check mode bandwidth */
869d38ceaf9SAlex Deucher
870d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock)
871d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH;
872d38ceaf9SAlex Deucher
873d38ceaf9SAlex Deucher return MODE_OK;
874d38ceaf9SAlex Deucher }
875d38ceaf9SAlex Deucher
876d38ceaf9SAlex Deucher static enum drm_connector_status
amdgpu_connector_vga_detect(struct drm_connector * connector,bool force)877d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
878d38ceaf9SAlex Deucher {
879d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
880d38ceaf9SAlex Deucher struct drm_encoder *encoder;
88117b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs;
882d38ceaf9SAlex Deucher bool dret = false;
883d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected;
884d38ceaf9SAlex Deucher int r;
885d38ceaf9SAlex Deucher
886aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
887d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev);
888f79f9476SNavid Emamdoost if (r < 0) {
889f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev);
890d38ceaf9SAlex Deucher return connector_status_disconnected;
891aa0aad57SLukas Wunner }
892f79f9476SNavid Emamdoost }
893d38ceaf9SAlex Deucher
894d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector);
895d38ceaf9SAlex Deucher if (!encoder)
896d38ceaf9SAlex Deucher ret = connector_status_disconnected;
897d38ceaf9SAlex Deucher
898d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus)
899e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
900d38ceaf9SAlex Deucher if (dret) {
901d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false;
902d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
903d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
904d38ceaf9SAlex Deucher
905d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) {
906d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
907d38ceaf9SAlex Deucher connector->name);
908d38ceaf9SAlex Deucher ret = connector_status_connected;
909d38ceaf9SAlex Deucher } else {
910d38ceaf9SAlex Deucher amdgpu_connector->use_digital =
911d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
912d38ceaf9SAlex Deucher
913d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors
914d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi)
915d38ceaf9SAlex Deucher */
916d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
917d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
918d38ceaf9SAlex Deucher ret = connector_status_disconnected;
919d38ceaf9SAlex Deucher } else {
920d38ceaf9SAlex Deucher ret = connector_status_connected;
921d38ceaf9SAlex Deucher }
922d38ceaf9SAlex Deucher }
923d38ceaf9SAlex Deucher } else {
924d38ceaf9SAlex Deucher
925d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */
926d38ceaf9SAlex Deucher if (!force) {
927d38ceaf9SAlex Deucher /* only return the previous status if we last
928d38ceaf9SAlex Deucher * detected a monitor via load.
929d38ceaf9SAlex Deucher */
930d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load)
931d38ceaf9SAlex Deucher ret = connector->status;
932d38ceaf9SAlex Deucher goto out;
933d38ceaf9SAlex Deucher }
934d38ceaf9SAlex Deucher
935d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) {
936d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private;
937d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector);
938d38ceaf9SAlex Deucher if (ret != connector_status_disconnected)
939d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true;
940d38ceaf9SAlex Deucher }
941d38ceaf9SAlex Deucher }
942d38ceaf9SAlex Deucher
943d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret);
944d38ceaf9SAlex Deucher
945d38ceaf9SAlex Deucher out:
946aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
947d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev);
948d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev);
949aa0aad57SLukas Wunner }
950d38ceaf9SAlex Deucher
951d38ceaf9SAlex Deucher return ret;
952d38ceaf9SAlex Deucher }
953d38ceaf9SAlex Deucher
954d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
955d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes,
956d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid,
957d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder,
958d38ceaf9SAlex Deucher };
959d38ceaf9SAlex Deucher
960d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
961d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms,
962d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect,
963d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes,
96440492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister,
965d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy,
966d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property,
967d38ceaf9SAlex Deucher };
968d38ceaf9SAlex Deucher
969d38ceaf9SAlex Deucher static bool
amdgpu_connector_check_hpd_status_unchanged(struct drm_connector * connector)970d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
971d38ceaf9SAlex Deucher {
972d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
9731348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
974d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
975d38ceaf9SAlex Deucher enum drm_connector_status status;
976d38ceaf9SAlex Deucher
977d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
978d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
979d38ceaf9SAlex Deucher status = connector_status_connected;
980d38ceaf9SAlex Deucher else
981d38ceaf9SAlex Deucher status = connector_status_disconnected;
982d38ceaf9SAlex Deucher if (connector->status == status)
983d38ceaf9SAlex Deucher return true;
984d38ceaf9SAlex Deucher }
985d38ceaf9SAlex Deucher
986d38ceaf9SAlex Deucher return false;
987d38ceaf9SAlex Deucher }
988d38ceaf9SAlex Deucher
989d38ceaf9SAlex Deucher /*
990d38ceaf9SAlex Deucher * DVI is complicated
991d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so
992d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point.
993d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC,
994d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector.
995d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object.
996d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder
997d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV)
998d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected.
999d38ceaf9SAlex Deucher */
1000d38ceaf9SAlex Deucher static enum drm_connector_status
amdgpu_connector_dvi_detect(struct drm_connector * connector,bool force)1001d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
1002d38ceaf9SAlex Deucher {
1003d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
10041348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
1005d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
100617b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs;
100798c0e348SVille Syrjälä int r;
1008d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected;
1009d38ceaf9SAlex Deucher bool dret = false, broken_edid = false;
1010d38ceaf9SAlex Deucher
1011aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
1012d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev);
1013f79f9476SNavid Emamdoost if (r < 0) {
1014f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev);
1015d38ceaf9SAlex Deucher return connector_status_disconnected;
1016aa0aad57SLukas Wunner }
1017f79f9476SNavid Emamdoost }
1018d38ceaf9SAlex Deucher
101990f56611Sxurui if (amdgpu_connector->detected_hpd_without_ddc) {
102090f56611Sxurui force = true;
102190f56611Sxurui amdgpu_connector->detected_hpd_without_ddc = false;
102290f56611Sxurui }
102390f56611Sxurui
1024d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1025d38ceaf9SAlex Deucher ret = connector->status;
1026d38ceaf9SAlex Deucher goto exit;
1027d38ceaf9SAlex Deucher }
1028d38ceaf9SAlex Deucher
102990f56611Sxurui if (amdgpu_connector->ddc_bus) {
1030e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
103190f56611Sxurui
103290f56611Sxurui /* Sometimes the pins required for the DDC probe on DVI
103390f56611Sxurui * connectors don't make contact at the same time that the ones
103490f56611Sxurui * for HPD do. If the DDC probe fails even though we had an HPD
103590f56611Sxurui * signal, try again later
103690f56611Sxurui */
103790f56611Sxurui if (!dret && !force &&
103890f56611Sxurui amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
103990f56611Sxurui DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
104090f56611Sxurui amdgpu_connector->detected_hpd_without_ddc = true;
104190f56611Sxurui schedule_delayed_work(&adev->hotplug_work,
104290f56611Sxurui msecs_to_jiffies(1000));
104390f56611Sxurui goto exit;
104490f56611Sxurui }
104590f56611Sxurui }
1046d38ceaf9SAlex Deucher if (dret) {
1047d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false;
1048d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
1049d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
1050d38ceaf9SAlex Deucher
1051d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) {
1052d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1053d38ceaf9SAlex Deucher connector->name);
1054d38ceaf9SAlex Deucher ret = connector_status_connected;
1055d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */
1056d38ceaf9SAlex Deucher } else {
1057d38ceaf9SAlex Deucher amdgpu_connector->use_digital =
1058d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1059d38ceaf9SAlex Deucher
1060d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors
1061d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi)
1062d38ceaf9SAlex Deucher */
1063d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1064d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
1065d38ceaf9SAlex Deucher ret = connector_status_disconnected;
1066d38ceaf9SAlex Deucher } else {
1067d38ceaf9SAlex Deucher ret = connector_status_connected;
1068d38ceaf9SAlex Deucher }
1069d38ceaf9SAlex Deucher
1070d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a
1071d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared
1072d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters
1073d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital.
1074d38ceaf9SAlex Deucher */
1075d38ceaf9SAlex Deucher if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1076d38ceaf9SAlex Deucher struct drm_connector *list_connector;
1077f8d2d39eSLyude Paul struct drm_connector_list_iter iter;
1078d38ceaf9SAlex Deucher struct amdgpu_connector *list_amdgpu_connector;
1079f8d2d39eSLyude Paul
1080f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter);
1081f8d2d39eSLyude Paul drm_for_each_connector_iter(list_connector,
1082f8d2d39eSLyude Paul &iter) {
1083d38ceaf9SAlex Deucher if (connector == list_connector)
1084d38ceaf9SAlex Deucher continue;
1085d38ceaf9SAlex Deucher list_amdgpu_connector = to_amdgpu_connector(list_connector);
1086d38ceaf9SAlex Deucher if (list_amdgpu_connector->shared_ddc &&
1087d38ceaf9SAlex Deucher (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1088d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->rec.i2c_id)) {
1089d38ceaf9SAlex Deucher /* cases where both connectors are digital */
1090d38ceaf9SAlex Deucher if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1091d38ceaf9SAlex Deucher /* hpd is our only option in this case */
1092d38ceaf9SAlex Deucher if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1093d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
1094d38ceaf9SAlex Deucher ret = connector_status_disconnected;
1095d38ceaf9SAlex Deucher }
1096d38ceaf9SAlex Deucher }
1097d38ceaf9SAlex Deucher }
1098d38ceaf9SAlex Deucher }
1099f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter);
1100d38ceaf9SAlex Deucher }
1101d38ceaf9SAlex Deucher }
1102d38ceaf9SAlex Deucher }
1103d38ceaf9SAlex Deucher
1104d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1105d38ceaf9SAlex Deucher goto out;
1106d38ceaf9SAlex Deucher
1107d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */
1108d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1109d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1110d38ceaf9SAlex Deucher goto out;
1111d38ceaf9SAlex Deucher
1112d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */
1113d38ceaf9SAlex Deucher if (!force) {
1114d38ceaf9SAlex Deucher /* only return the previous status if we last
1115d38ceaf9SAlex Deucher * detected a monitor via load.
1116d38ceaf9SAlex Deucher */
1117d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load)
1118d38ceaf9SAlex Deucher ret = connector->status;
1119d38ceaf9SAlex Deucher goto out;
1120d38ceaf9SAlex Deucher }
1121d38ceaf9SAlex Deucher
1122d38ceaf9SAlex Deucher /* find analog encoder */
1123d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) {
112498c0e348SVille Syrjälä struct drm_encoder *encoder;
1125d38ceaf9SAlex Deucher
112662afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) {
1127d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1128d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1129d38ceaf9SAlex Deucher continue;
1130d38ceaf9SAlex Deucher
1131d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private;
1132d38ceaf9SAlex Deucher if (encoder_funcs->detect) {
1133d38ceaf9SAlex Deucher if (!broken_edid) {
1134d38ceaf9SAlex Deucher if (ret != connector_status_connected) {
1135d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */
1136d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector);
1137d38ceaf9SAlex Deucher if (ret == connector_status_connected) {
1138d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false;
1139d38ceaf9SAlex Deucher }
1140d38ceaf9SAlex Deucher if (ret != connector_status_disconnected)
1141d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true;
1142d38ceaf9SAlex Deucher }
1143d38ceaf9SAlex Deucher } else {
1144d38ceaf9SAlex Deucher enum drm_connector_status lret;
1145d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */
1146d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true;
1147d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector);
1148*a6f7baa3SSrinivasan Shanmugam DRM_DEBUG_KMS("load_detect %x returned: %x\n",
1149*a6f7baa3SSrinivasan Shanmugam encoder->encoder_type, lret);
1150d38ceaf9SAlex Deucher if (lret == connector_status_connected)
1151d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false;
1152d38ceaf9SAlex Deucher }
1153d38ceaf9SAlex Deucher break;
1154d38ceaf9SAlex Deucher }
1155d38ceaf9SAlex Deucher }
1156d38ceaf9SAlex Deucher }
1157d38ceaf9SAlex Deucher
1158d38ceaf9SAlex Deucher out:
1159d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */
1160d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret);
1161d38ceaf9SAlex Deucher
1162d38ceaf9SAlex Deucher exit:
1163aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
1164d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev);
1165d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev);
1166aa0aad57SLukas Wunner }
1167d38ceaf9SAlex Deucher
1168d38ceaf9SAlex Deucher return ret;
1169d38ceaf9SAlex Deucher }
1170d38ceaf9SAlex Deucher
1171d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */
1172d38ceaf9SAlex Deucher static struct drm_encoder *
amdgpu_connector_dvi_encoder(struct drm_connector * connector)1173d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1174d38ceaf9SAlex Deucher {
1175d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1176d38ceaf9SAlex Deucher struct drm_encoder *encoder;
1177d38ceaf9SAlex Deucher
117862afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) {
1179d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) {
1180d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1181d38ceaf9SAlex Deucher return encoder;
1182d38ceaf9SAlex Deucher } else {
1183d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1184d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1185d38ceaf9SAlex Deucher return encoder;
1186d38ceaf9SAlex Deucher }
1187d38ceaf9SAlex Deucher }
1188d38ceaf9SAlex Deucher
1189d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */
1190d38ceaf9SAlex Deucher
1191d38ceaf9SAlex Deucher /* then check use digitial */
1192d38ceaf9SAlex Deucher /* pick the first one */
119362afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder)
119498c0e348SVille Syrjälä return encoder;
119598c0e348SVille Syrjälä
1196d38ceaf9SAlex Deucher return NULL;
1197d38ceaf9SAlex Deucher }
1198d38ceaf9SAlex Deucher
amdgpu_connector_dvi_force(struct drm_connector * connector)1199d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1200d38ceaf9SAlex Deucher {
1201d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1202d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON)
1203d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false;
1204d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL)
1205d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true;
1206d38ceaf9SAlex Deucher }
1207d38ceaf9SAlex Deucher
amdgpu_connector_dvi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1208ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1209d38ceaf9SAlex Deucher struct drm_display_mode *mode)
1210d38ceaf9SAlex Deucher {
1211d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
12121348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
1213d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1214d38ceaf9SAlex Deucher
1215d38ceaf9SAlex Deucher /* XXX check mode bandwidth */
1216d38ceaf9SAlex Deucher
1217d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1218d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1219d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1220d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1221d38ceaf9SAlex Deucher return MODE_OK;
12223c021931SClaudio Suarez } else if (connector->display_info.is_hdmi) {
1223d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */
1224d38ceaf9SAlex Deucher if (mode->clock > 340000)
1225d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH;
1226d38ceaf9SAlex Deucher else
1227d38ceaf9SAlex Deucher return MODE_OK;
1228d38ceaf9SAlex Deucher } else {
1229d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH;
1230d38ceaf9SAlex Deucher }
1231d38ceaf9SAlex Deucher }
1232d38ceaf9SAlex Deucher
1233d38ceaf9SAlex Deucher /* check against the max pixel clock */
1234d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1235d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH;
1236d38ceaf9SAlex Deucher
1237d38ceaf9SAlex Deucher return MODE_OK;
1238d38ceaf9SAlex Deucher }
1239d38ceaf9SAlex Deucher
1240d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1241d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes,
1242d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid,
1243d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder,
1244d38ceaf9SAlex Deucher };
1245d38ceaf9SAlex Deucher
1246d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1247d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms,
1248d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect,
1249d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes,
1250d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property,
125140492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister,
1252d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy,
1253d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force,
1254d38ceaf9SAlex Deucher };
1255d38ceaf9SAlex Deucher
amdgpu_connector_dp_get_modes(struct drm_connector * connector)1256d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1257d38ceaf9SAlex Deucher {
1258d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1259d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1260d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1261d38ceaf9SAlex Deucher int ret;
1262d38ceaf9SAlex Deucher
1263d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1264d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1265d38ceaf9SAlex Deucher struct drm_display_mode *mode;
1266d38ceaf9SAlex Deucher
1267d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1268d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on)
1269d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector,
1270d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON);
1271d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
1272d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector);
1273d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on)
1274d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector,
1275d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF);
1276d38ceaf9SAlex Deucher } else {
1277d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */
1278d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1279d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) {
1280d38ceaf9SAlex Deucher if (encoder)
1281d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1282d38ceaf9SAlex Deucher }
1283d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
1284d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector);
1285d38ceaf9SAlex Deucher }
1286d38ceaf9SAlex Deucher
1287d38ceaf9SAlex Deucher if (ret > 0) {
1288d38ceaf9SAlex Deucher if (encoder) {
1289d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1290d38ceaf9SAlex Deucher /* add scaled modes */
1291d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector);
1292d38ceaf9SAlex Deucher }
1293d38ceaf9SAlex Deucher return ret;
1294d38ceaf9SAlex Deucher }
1295d38ceaf9SAlex Deucher
1296d38ceaf9SAlex Deucher if (!encoder)
1297d38ceaf9SAlex Deucher return 0;
1298d38ceaf9SAlex Deucher
1299d38ceaf9SAlex Deucher /* we have no EDID modes */
1300d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder);
1301d38ceaf9SAlex Deucher if (mode) {
1302d38ceaf9SAlex Deucher ret = 1;
1303d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode);
1304d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */
1305d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm;
1306d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm;
1307d38ceaf9SAlex Deucher /* add scaled modes */
1308d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector);
1309d38ceaf9SAlex Deucher }
1310d38ceaf9SAlex Deucher } else {
1311d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */
1312d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1313d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) {
1314d38ceaf9SAlex Deucher if (encoder)
1315d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1316d38ceaf9SAlex Deucher }
1317d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector);
1318d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector);
1319d38ceaf9SAlex Deucher
1320d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector);
1321d38ceaf9SAlex Deucher }
1322d38ceaf9SAlex Deucher
1323d38ceaf9SAlex Deucher return ret;
1324d38ceaf9SAlex Deucher }
1325d38ceaf9SAlex Deucher
amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector * connector)1326d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1327d38ceaf9SAlex Deucher {
1328d38ceaf9SAlex Deucher struct drm_encoder *encoder;
1329d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
1330d38ceaf9SAlex Deucher
133162afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) {
1332d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
1333d38ceaf9SAlex Deucher
1334d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) {
1335d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS:
1336d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG:
1337d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id;
1338d38ceaf9SAlex Deucher default:
1339d38ceaf9SAlex Deucher break;
1340d38ceaf9SAlex Deucher }
1341d38ceaf9SAlex Deucher }
1342d38ceaf9SAlex Deucher
1343d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE;
1344d38ceaf9SAlex Deucher }
1345d38ceaf9SAlex Deucher
amdgpu_connector_encoder_is_hbr2(struct drm_connector * connector)1346d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1347d38ceaf9SAlex Deucher {
1348d38ceaf9SAlex Deucher struct drm_encoder *encoder;
1349d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
1350d38ceaf9SAlex Deucher bool found = false;
1351d38ceaf9SAlex Deucher
135262afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) {
1353d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
1354d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1355d38ceaf9SAlex Deucher found = true;
1356d38ceaf9SAlex Deucher }
1357d38ceaf9SAlex Deucher
1358d38ceaf9SAlex Deucher return found;
1359d38ceaf9SAlex Deucher }
1360d38ceaf9SAlex Deucher
amdgpu_connector_is_dp12_capable(struct drm_connector * connector)1361d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1362d38ceaf9SAlex Deucher {
1363d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
13641348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
1365d38ceaf9SAlex Deucher
1366d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) &&
1367d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) {
1368d38ceaf9SAlex Deucher return true;
1369d38ceaf9SAlex Deucher }
1370d38ceaf9SAlex Deucher
1371d38ceaf9SAlex Deucher return false;
1372d38ceaf9SAlex Deucher }
1373d38ceaf9SAlex Deucher
1374d38ceaf9SAlex Deucher static enum drm_connector_status
amdgpu_connector_dp_detect(struct drm_connector * connector,bool force)1375d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1376d38ceaf9SAlex Deucher {
1377d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev;
13781348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev);
1379d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1380d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected;
1381d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1382d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1383d38ceaf9SAlex Deucher int r;
1384d38ceaf9SAlex Deucher
1385aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
1386d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev);
1387f79f9476SNavid Emamdoost if (r < 0) {
1388f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev);
1389d38ceaf9SAlex Deucher return connector_status_disconnected;
1390aa0aad57SLukas Wunner }
1391f79f9476SNavid Emamdoost }
1392d38ceaf9SAlex Deucher
1393d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1394d38ceaf9SAlex Deucher ret = connector->status;
1395d38ceaf9SAlex Deucher goto out;
1396d38ceaf9SAlex Deucher }
1397d38ceaf9SAlex Deucher
1398d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector);
1399d38ceaf9SAlex Deucher
1400d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1401d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1402d38ceaf9SAlex Deucher if (encoder) {
1403d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1404d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1405d38ceaf9SAlex Deucher
1406d38ceaf9SAlex Deucher /* check if panel is valid */
1407d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1408d38ceaf9SAlex Deucher ret = connector_status_connected;
1409d38ceaf9SAlex Deucher }
1410d38ceaf9SAlex Deucher /* eDP is always DP */
1411d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1412d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on)
1413d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector,
1414d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON);
1415d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1416d38ceaf9SAlex Deucher ret = connector_status_connected;
1417d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on)
1418d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector,
1419d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF);
1420d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1421d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) {
1422d38ceaf9SAlex Deucher /* DP bridges are always DP */
1423d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1424d38ceaf9SAlex Deucher /* get the DPCD from the bridge */
1425d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1426d38ceaf9SAlex Deucher
1427d38ceaf9SAlex Deucher if (encoder) {
1428d38ceaf9SAlex Deucher /* setup ddc on the bridge */
1429d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1430d38ceaf9SAlex Deucher /* bridge chips are always aux */
1431e0b5b5ecSSamuel Li /* try DDC */
1432e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1433d38ceaf9SAlex Deucher ret = connector_status_connected;
1434d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */
143517b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1436d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector);
1437d38ceaf9SAlex Deucher }
1438d38ceaf9SAlex Deucher }
1439d38ceaf9SAlex Deucher } else {
1440d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type =
1441d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1442d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1443d38ceaf9SAlex Deucher ret = connector_status_connected;
1444d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1445d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1446d38ceaf9SAlex Deucher } else {
1447d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1448d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1449d38ceaf9SAlex Deucher ret = connector_status_connected;
1450d38ceaf9SAlex Deucher } else {
1451d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1452e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector,
1453e0b5b5ecSSamuel Li false))
1454d38ceaf9SAlex Deucher ret = connector_status_connected;
1455d38ceaf9SAlex Deucher }
1456d38ceaf9SAlex Deucher }
1457d38ceaf9SAlex Deucher }
1458d38ceaf9SAlex Deucher
1459d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret);
1460d38ceaf9SAlex Deucher out:
1461aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) {
1462d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev);
1463d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev);
1464aa0aad57SLukas Wunner }
1465d38ceaf9SAlex Deucher
146605211e7fSAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
146705211e7fSAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_eDP)
146865bf2cf9SOleg Vasilev drm_dp_set_subconnector_property(&amdgpu_connector->base,
146965bf2cf9SOleg Vasilev ret,
147065bf2cf9SOleg Vasilev amdgpu_dig_connector->dpcd,
147165bf2cf9SOleg Vasilev amdgpu_dig_connector->downstream_ports);
1472d38ceaf9SAlex Deucher return ret;
1473d38ceaf9SAlex Deucher }
1474d38ceaf9SAlex Deucher
amdgpu_connector_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1475ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1476d38ceaf9SAlex Deucher struct drm_display_mode *mode)
1477d38ceaf9SAlex Deucher {
1478d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1479d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1480d38ceaf9SAlex Deucher
1481d38ceaf9SAlex Deucher /* XXX check mode bandwidth */
1482d38ceaf9SAlex Deucher
1483d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1484d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1485d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1486d38ceaf9SAlex Deucher
1487d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1488d38ceaf9SAlex Deucher return MODE_PANEL;
1489d38ceaf9SAlex Deucher
1490d38ceaf9SAlex Deucher if (encoder) {
1491d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1492d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1493d38ceaf9SAlex Deucher
1494d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel
1495d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable.
1496d38ceaf9SAlex Deucher */
1497d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) ||
1498d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay))
1499d38ceaf9SAlex Deucher return MODE_PANEL;
1500d38ceaf9SAlex Deucher
1501d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */
1502d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) {
1503d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) ||
1504d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay))
1505d38ceaf9SAlex Deucher return MODE_PANEL;
1506d38ceaf9SAlex Deucher }
1507d38ceaf9SAlex Deucher }
1508d38ceaf9SAlex Deucher return MODE_OK;
1509d38ceaf9SAlex Deucher } else {
1510d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1511d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1512d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1513d38ceaf9SAlex Deucher } else {
15143c021931SClaudio Suarez if (connector->display_info.is_hdmi) {
1515d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */
1516d38ceaf9SAlex Deucher if (mode->clock > 340000)
1517d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH;
1518d38ceaf9SAlex Deucher } else {
1519d38ceaf9SAlex Deucher if (mode->clock > 165000)
1520d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH;
1521d38ceaf9SAlex Deucher }
1522d38ceaf9SAlex Deucher }
1523d38ceaf9SAlex Deucher }
1524d38ceaf9SAlex Deucher
1525d38ceaf9SAlex Deucher return MODE_OK;
1526d38ceaf9SAlex Deucher }
1527d38ceaf9SAlex Deucher
1528405a1f90SAlex Deucher static int
amdgpu_connector_late_register(struct drm_connector * connector)1529405a1f90SAlex Deucher amdgpu_connector_late_register(struct drm_connector *connector)
1530405a1f90SAlex Deucher {
1531405a1f90SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1532405a1f90SAlex Deucher int r = 0;
1533405a1f90SAlex Deucher
1534405a1f90SAlex Deucher if (amdgpu_connector->ddc_bus->has_aux) {
1535405a1f90SAlex Deucher amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1536405a1f90SAlex Deucher r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1537405a1f90SAlex Deucher }
1538405a1f90SAlex Deucher
1539405a1f90SAlex Deucher return r;
1540405a1f90SAlex Deucher }
1541405a1f90SAlex Deucher
1542d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1543d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes,
1544d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid,
1545d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder,
1546d38ceaf9SAlex Deucher };
1547d38ceaf9SAlex Deucher
1548d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1549d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms,
1550d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect,
1551d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes,
1552d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property,
155340492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister,
1554d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy,
1555d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force,
1556405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register,
1557d38ceaf9SAlex Deucher };
1558d38ceaf9SAlex Deucher
1559d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1560d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms,
1561d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect,
1562d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes,
1563d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property,
156440492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister,
1565d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy,
1566d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force,
1567405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register,
1568d38ceaf9SAlex Deucher };
1569d38ceaf9SAlex Deucher
1570d38ceaf9SAlex Deucher void
amdgpu_connector_add(struct amdgpu_device * adev,uint32_t connector_id,uint32_t supported_device,int connector_type,struct amdgpu_i2c_bus_rec * i2c_bus,uint16_t connector_object_id,struct amdgpu_hpd * hpd,struct amdgpu_router * router)1571d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev,
1572d38ceaf9SAlex Deucher uint32_t connector_id,
1573d38ceaf9SAlex Deucher uint32_t supported_device,
1574d38ceaf9SAlex Deucher int connector_type,
1575d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus,
1576d38ceaf9SAlex Deucher uint16_t connector_object_id,
1577d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd,
1578d38ceaf9SAlex Deucher struct amdgpu_router *router)
1579d38ceaf9SAlex Deucher {
15804a580877SLuben Tuikov struct drm_device *dev = adev_to_drm(adev);
1581d38ceaf9SAlex Deucher struct drm_connector *connector;
1582f8d2d39eSLyude Paul struct drm_connector_list_iter iter;
1583d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector;
1584d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1585d38ceaf9SAlex Deucher struct drm_encoder *encoder;
1586d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder;
15875b50fa2bSAndrzej Pietrasiewicz struct i2c_adapter *ddc = NULL;
1588d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone;
1589d38ceaf9SAlex Deucher bool shared_ddc = false;
1590d38ceaf9SAlex Deucher bool is_dp_bridge = false;
1591d38ceaf9SAlex Deucher bool has_aux = false;
1592d38ceaf9SAlex Deucher
1593d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1594d38ceaf9SAlex Deucher return;
1595d38ceaf9SAlex Deucher
1596d38ceaf9SAlex Deucher /* see if we already added it */
1597f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter);
1598f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) {
1599d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector);
1600d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) {
1601d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device;
1602f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter);
1603d38ceaf9SAlex Deucher return;
1604d38ceaf9SAlex Deucher }
1605d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1606d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1607d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true;
1608d38ceaf9SAlex Deucher shared_ddc = true;
1609d38ceaf9SAlex Deucher }
1610d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid &&
1611d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) {
1612d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false;
1613d38ceaf9SAlex Deucher shared_ddc = false;
1614d38ceaf9SAlex Deucher }
1615d38ceaf9SAlex Deucher }
1616d38ceaf9SAlex Deucher }
1617f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter);
1618d38ceaf9SAlex Deucher
1619d38ceaf9SAlex Deucher /* check if it's a dp bridge */
1620d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1621d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder);
1622d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) {
1623d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) {
1624d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS:
1625d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG:
1626d38ceaf9SAlex Deucher is_dp_bridge = true;
1627d38ceaf9SAlex Deucher break;
1628d38ceaf9SAlex Deucher default:
1629d38ceaf9SAlex Deucher break;
1630d38ceaf9SAlex Deucher }
1631d38ceaf9SAlex Deucher }
1632d38ceaf9SAlex Deucher }
1633d38ceaf9SAlex Deucher
1634d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1635d38ceaf9SAlex Deucher if (!amdgpu_connector)
1636d38ceaf9SAlex Deucher return;
1637d38ceaf9SAlex Deucher
1638d38ceaf9SAlex Deucher connector = &amdgpu_connector->base;
1639d38ceaf9SAlex Deucher
1640d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id;
1641d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device;
1642d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc;
1643d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id;
1644d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd;
1645d38ceaf9SAlex Deucher
1646d38ceaf9SAlex Deucher amdgpu_connector->router = *router;
1647d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) {
1648d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1649d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus)
1650d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1651d38ceaf9SAlex Deucher }
1652d38ceaf9SAlex Deucher
1653d38ceaf9SAlex Deucher if (is_dp_bridge) {
1654d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1655d38ceaf9SAlex Deucher if (!amdgpu_dig_connector)
1656d38ceaf9SAlex Deucher goto failed;
1657d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector;
1658d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1659d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
16605b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) {
1661d38ceaf9SAlex Deucher has_aux = true;
16625b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
16635b50fa2bSAndrzej Pietrasiewicz } else {
1664d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1665d38ceaf9SAlex Deucher }
16665b50fa2bSAndrzej Pietrasiewicz }
1667d38ceaf9SAlex Deucher switch (connector_type) {
1668d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA:
1669d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA:
1670d38ceaf9SAlex Deucher default:
16715b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
16725b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs,
16735b50fa2bSAndrzej Pietrasiewicz connector_type,
16745b50fa2bSAndrzej Pietrasiewicz ddc);
1675d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base,
1676d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs);
1677d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1678d38ceaf9SAlex Deucher connector->doublescan_allowed = true;
1679d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true;
1680d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1681d38ceaf9SAlex Deucher adev->mode_info.load_detect_property,
1682d38ceaf9SAlex Deucher 1);
1683d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1684d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1685d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1686d38ceaf9SAlex Deucher break;
1687d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII:
1688d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID:
1689d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA:
1690d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB:
1691d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort:
16925b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
16935b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs,
16945b50fa2bSAndrzej Pietrasiewicz connector_type,
16955b50fa2bSAndrzej Pietrasiewicz ddc);
1696d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base,
1697d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs);
1698d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1699d38ceaf9SAlex Deucher adev->mode_info.underscan_property,
1700d38ceaf9SAlex Deucher UNDERSCAN_OFF);
1701d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1702d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property,
1703d38ceaf9SAlex Deucher 0);
1704d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1705d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property,
1706d38ceaf9SAlex Deucher 0);
1707d38ceaf9SAlex Deucher
1708d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1709d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1710d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1711d38ceaf9SAlex Deucher
1712d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1713d38ceaf9SAlex Deucher adev->mode_info.dither_property,
1714d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE);
1715d38ceaf9SAlex Deucher
17164bb71fceShongao if (amdgpu_audio != 0) {
1717d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1718d38ceaf9SAlex Deucher adev->mode_info.audio_property,
1719d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO);
17204bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
17214bb71fceShongao }
1722d38ceaf9SAlex Deucher
1723d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
1724d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1725d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1726d38ceaf9SAlex Deucher connector->doublescan_allowed = true;
1727d38ceaf9SAlex Deucher else
1728d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
1729d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1730d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true;
1731d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1732d38ceaf9SAlex Deucher adev->mode_info.load_detect_property,
1733d38ceaf9SAlex Deucher 1);
1734d38ceaf9SAlex Deucher }
1735d38ceaf9SAlex Deucher break;
1736d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS:
1737d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP:
17385b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
17395b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs,
17405b50fa2bSAndrzej Pietrasiewicz connector_type,
17415b50fa2bSAndrzej Pietrasiewicz ddc);
1742d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base,
1743d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs);
1744d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1745d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1746d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN);
1747d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
1748d38ceaf9SAlex Deucher connector->interlace_allowed = false;
1749d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
1750d38ceaf9SAlex Deucher break;
1751d38ceaf9SAlex Deucher }
1752d38ceaf9SAlex Deucher } else {
1753d38ceaf9SAlex Deucher switch (connector_type) {
1754d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA:
1755d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1756d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1757d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus)
1758d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
17595b50fa2bSAndrzej Pietrasiewicz else
17605b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
1761d38ceaf9SAlex Deucher }
17625b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
17635b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs,
17645b50fa2bSAndrzej Pietrasiewicz connector_type,
17655b50fa2bSAndrzej Pietrasiewicz ddc);
17665b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1767d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true;
1768d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1769d38ceaf9SAlex Deucher adev->mode_info.load_detect_property,
1770d38ceaf9SAlex Deucher 1);
1771d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1772d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1773d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1774d38ceaf9SAlex Deucher /* no HPD on analog connectors */
1775d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1776d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1777d38ceaf9SAlex Deucher connector->doublescan_allowed = true;
1778d38ceaf9SAlex Deucher break;
1779d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA:
1780d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1781d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1782d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus)
1783d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
17845b50fa2bSAndrzej Pietrasiewicz else
17855b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
1786d38ceaf9SAlex Deucher }
17875b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
17885b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs,
17895b50fa2bSAndrzej Pietrasiewicz connector_type,
17905b50fa2bSAndrzej Pietrasiewicz ddc);
17915b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1792d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true;
1793d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1794d38ceaf9SAlex Deucher adev->mode_info.load_detect_property,
1795d38ceaf9SAlex Deucher 1);
1796d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1797d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1798d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1799d38ceaf9SAlex Deucher /* no HPD on analog connectors */
1800d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1801d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1802d38ceaf9SAlex Deucher connector->doublescan_allowed = true;
1803d38ceaf9SAlex Deucher break;
1804d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII:
1805d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID:
1806d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1807d38ceaf9SAlex Deucher if (!amdgpu_dig_connector)
1808d38ceaf9SAlex Deucher goto failed;
1809d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector;
1810d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1811d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1812d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus)
1813d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
18145b50fa2bSAndrzej Pietrasiewicz else
18155b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
1816d38ceaf9SAlex Deucher }
18175b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
18185b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs,
18195b50fa2bSAndrzej Pietrasiewicz connector_type,
18205b50fa2bSAndrzej Pietrasiewicz ddc);
18215b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1822d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
1823d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1824d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property,
1825d38ceaf9SAlex Deucher 1);
1826d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1827d38ceaf9SAlex Deucher adev->mode_info.underscan_property,
1828d38ceaf9SAlex Deucher UNDERSCAN_OFF);
1829d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1830d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property,
1831d38ceaf9SAlex Deucher 0);
1832d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1833d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property,
1834d38ceaf9SAlex Deucher 0);
1835d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1836d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1837d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1838d38ceaf9SAlex Deucher
1839d38ceaf9SAlex Deucher if (amdgpu_audio != 0) {
1840d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1841d38ceaf9SAlex Deucher adev->mode_info.audio_property,
1842d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO);
18434bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1844d38ceaf9SAlex Deucher }
1845d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1846d38ceaf9SAlex Deucher adev->mode_info.dither_property,
1847d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE);
1848d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1849d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true;
1850d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1851d38ceaf9SAlex Deucher adev->mode_info.load_detect_property,
1852d38ceaf9SAlex Deucher 1);
1853d38ceaf9SAlex Deucher }
1854d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1855d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII)
1856d38ceaf9SAlex Deucher connector->doublescan_allowed = true;
1857d38ceaf9SAlex Deucher else
1858d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
1859d38ceaf9SAlex Deucher break;
1860d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA:
1861d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB:
1862d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1863d38ceaf9SAlex Deucher if (!amdgpu_dig_connector)
1864d38ceaf9SAlex Deucher goto failed;
1865d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector;
1866d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1867d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1868d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus)
1869d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
18705b50fa2bSAndrzej Pietrasiewicz else
18715b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
1872d38ceaf9SAlex Deucher }
18735b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
18745b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs,
18755b50fa2bSAndrzej Pietrasiewicz connector_type,
18765b50fa2bSAndrzej Pietrasiewicz ddc);
18775b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1878d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1879d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property,
1880d38ceaf9SAlex Deucher 1);
1881d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1882d38ceaf9SAlex Deucher adev->mode_info.underscan_property,
1883d38ceaf9SAlex Deucher UNDERSCAN_OFF);
1884d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1885d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property,
1886d38ceaf9SAlex Deucher 0);
1887d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1888d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property,
1889d38ceaf9SAlex Deucher 0);
1890d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1891d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1892d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1893d38ceaf9SAlex Deucher if (amdgpu_audio != 0) {
1894d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1895d38ceaf9SAlex Deucher adev->mode_info.audio_property,
1896d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO);
18974bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1898d38ceaf9SAlex Deucher }
1899d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1900d38ceaf9SAlex Deucher adev->mode_info.dither_property,
1901d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE);
1902d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
1903d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1904d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1905d38ceaf9SAlex Deucher connector->doublescan_allowed = true;
1906d38ceaf9SAlex Deucher else
1907d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
1908d38ceaf9SAlex Deucher break;
1909d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort:
1910d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1911d38ceaf9SAlex Deucher if (!amdgpu_dig_connector)
1912d38ceaf9SAlex Deucher goto failed;
1913d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector;
1914d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1915d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
19165b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) {
1917d38ceaf9SAlex Deucher has_aux = true;
19185b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
19195b50fa2bSAndrzej Pietrasiewicz } else {
1920d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1921d38ceaf9SAlex Deucher }
19225b50fa2bSAndrzej Pietrasiewicz }
19235b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
19245b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs,
19255b50fa2bSAndrzej Pietrasiewicz connector_type,
19265b50fa2bSAndrzej Pietrasiewicz ddc);
19275b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1928d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
1929d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1930d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property,
1931d38ceaf9SAlex Deucher 1);
1932d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1933d38ceaf9SAlex Deucher adev->mode_info.underscan_property,
1934d38ceaf9SAlex Deucher UNDERSCAN_OFF);
1935d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1936d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property,
1937d38ceaf9SAlex Deucher 0);
1938d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1939d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property,
1940d38ceaf9SAlex Deucher 0);
1941d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1942d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1943d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE);
1944d38ceaf9SAlex Deucher if (amdgpu_audio != 0) {
1945d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1946d38ceaf9SAlex Deucher adev->mode_info.audio_property,
1947d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO);
19484bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1949d38ceaf9SAlex Deucher }
1950d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1951d38ceaf9SAlex Deucher adev->mode_info.dither_property,
1952d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE);
1953d38ceaf9SAlex Deucher connector->interlace_allowed = true;
1954d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */
1955d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
1956d38ceaf9SAlex Deucher break;
1957d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP:
1958d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1959d38ceaf9SAlex Deucher if (!amdgpu_dig_connector)
1960d38ceaf9SAlex Deucher goto failed;
1961d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector;
1962d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1963d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
19645b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) {
1965d38ceaf9SAlex Deucher has_aux = true;
19665b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
19675b50fa2bSAndrzej Pietrasiewicz } else {
1968d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1969d38ceaf9SAlex Deucher }
19705b50fa2bSAndrzej Pietrasiewicz }
19715b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
19725b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs,
19735b50fa2bSAndrzej Pietrasiewicz connector_type,
19745b50fa2bSAndrzej Pietrasiewicz ddc);
19755b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1976d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
1977d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
1978d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN);
1979d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
1980d38ceaf9SAlex Deucher connector->interlace_allowed = false;
1981d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
1982d38ceaf9SAlex Deucher break;
1983d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS:
1984d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1985d38ceaf9SAlex Deucher if (!amdgpu_dig_connector)
1986d38ceaf9SAlex Deucher goto failed;
1987d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector;
1988d38ceaf9SAlex Deucher if (i2c_bus->valid) {
1989d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1990d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus)
1991d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
19925b50fa2bSAndrzej Pietrasiewicz else
19935b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter;
1994d38ceaf9SAlex Deucher }
19955b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
19965b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_lvds_funcs,
19975b50fa2bSAndrzej Pietrasiewicz connector_type,
19985b50fa2bSAndrzej Pietrasiewicz ddc);
19995b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
2000d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base,
2001d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property,
2002d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN);
2003d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB;
2004d38ceaf9SAlex Deucher connector->interlace_allowed = false;
2005d38ceaf9SAlex Deucher connector->doublescan_allowed = false;
2006d38ceaf9SAlex Deucher break;
2007d38ceaf9SAlex Deucher }
2008d38ceaf9SAlex Deucher }
2009d38ceaf9SAlex Deucher
2010d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2011b636a1b3SLyude if (i2c_bus->valid) {
2012b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2013b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT;
2014b636a1b3SLyude }
2015d38ceaf9SAlex Deucher } else
2016d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD;
2017d38ceaf9SAlex Deucher
2018d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order;
2019d38ceaf9SAlex Deucher
2020d38ceaf9SAlex Deucher if (has_aux)
2021d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector);
2022d38ceaf9SAlex Deucher
202365bf2cf9SOleg Vasilev if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
202465bf2cf9SOleg Vasilev connector_type == DRM_MODE_CONNECTOR_eDP) {
202565bf2cf9SOleg Vasilev drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
202665bf2cf9SOleg Vasilev }
202765bf2cf9SOleg Vasilev
2028d38ceaf9SAlex Deucher return;
2029d38ceaf9SAlex Deucher
2030d38ceaf9SAlex Deucher failed:
2031d38ceaf9SAlex Deucher drm_connector_cleanup(connector);
2032d38ceaf9SAlex Deucher kfree(connector);
2033d38ceaf9SAlex Deucher }
2034