1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include <linux/slab.h> 26 #include <linux/pci.h> 27 #include <drm/drmP.h> 28 #include <linux/firmware.h> 29 #include <drm/amdgpu_drm.h> 30 #include "amdgpu.h" 31 #include "cgs_linux.h" 32 #include "atom.h" 33 #include "amdgpu_ucode.h" 34 35 36 struct amdgpu_cgs_device { 37 struct cgs_device base; 38 struct amdgpu_device *adev; 39 }; 40 41 #define CGS_FUNC_ADEV \ 42 struct amdgpu_device *adev = \ 43 ((struct amdgpu_cgs_device *)cgs_device)->adev 44 45 static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, 46 uint64_t *mc_start, uint64_t *mc_size, 47 uint64_t *mem_size) 48 { 49 CGS_FUNC_ADEV; 50 switch(type) { 51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB: 52 case CGS_GPU_MEM_TYPE__VISIBLE_FB: 53 *mc_start = 0; 54 *mc_size = adev->mc.visible_vram_size; 55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size; 56 break; 57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: 58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB: 59 *mc_start = adev->mc.visible_vram_size; 60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size; 61 *mem_size = *mc_size; 62 break; 63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE: 64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE: 65 *mc_start = adev->mc.gtt_start; 66 *mc_size = adev->mc.gtt_size; 67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size; 68 break; 69 default: 70 return -EINVAL; 71 } 72 73 return 0; 74 } 75 76 static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, 77 uint64_t size, 78 uint64_t min_offset, uint64_t max_offset, 79 cgs_handle_t *kmem_handle, uint64_t *mcaddr) 80 { 81 CGS_FUNC_ADEV; 82 int ret; 83 struct amdgpu_bo *bo; 84 struct page *kmem_page = vmalloc_to_page(kmem); 85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT; 86 87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages); 88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false, 89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo); 90 if (ret) 91 return ret; 92 ret = amdgpu_bo_reserve(bo, false); 93 if (unlikely(ret != 0)) 94 return ret; 95 96 /* pin buffer into GTT */ 97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT, 98 min_offset, max_offset, mcaddr); 99 amdgpu_bo_unreserve(bo); 100 101 *kmem_handle = (cgs_handle_t)bo; 102 return ret; 103 } 104 105 static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) 106 { 107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle; 108 109 if (obj) { 110 int r = amdgpu_bo_reserve(obj, false); 111 if (likely(r == 0)) { 112 amdgpu_bo_unpin(obj); 113 amdgpu_bo_unreserve(obj); 114 } 115 amdgpu_bo_unref(&obj); 116 117 } 118 return 0; 119 } 120 121 static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, 122 enum cgs_gpu_mem_type type, 123 uint64_t size, uint64_t align, 124 uint64_t min_offset, uint64_t max_offset, 125 cgs_handle_t *handle) 126 { 127 CGS_FUNC_ADEV; 128 uint16_t flags = 0; 129 int ret = 0; 130 uint32_t domain = 0; 131 struct amdgpu_bo *obj; 132 struct ttm_placement placement; 133 struct ttm_place place; 134 135 if (min_offset > max_offset) { 136 BUG_ON(1); 137 return -EINVAL; 138 } 139 140 /* fail if the alignment is not a power of 2 */ 141 if (((align != 1) && (align & (align - 1))) 142 || size == 0 || align == 0) 143 return -EINVAL; 144 145 146 switch(type) { 147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB: 148 case CGS_GPU_MEM_TYPE__VISIBLE_FB: 149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 150 domain = AMDGPU_GEM_DOMAIN_VRAM; 151 if (max_offset > adev->mc.real_vram_size) 152 return -EINVAL; 153 place.fpfn = min_offset >> PAGE_SHIFT; 154 place.lpfn = max_offset >> PAGE_SHIFT; 155 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 156 TTM_PL_FLAG_VRAM; 157 break; 158 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: 159 case CGS_GPU_MEM_TYPE__INVISIBLE_FB: 160 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 161 domain = AMDGPU_GEM_DOMAIN_VRAM; 162 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { 163 place.fpfn = 164 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT; 165 place.lpfn = 166 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT; 167 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 168 TTM_PL_FLAG_VRAM; 169 } 170 171 break; 172 case CGS_GPU_MEM_TYPE__GART_CACHEABLE: 173 domain = AMDGPU_GEM_DOMAIN_GTT; 174 place.fpfn = min_offset >> PAGE_SHIFT; 175 place.lpfn = max_offset >> PAGE_SHIFT; 176 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 177 break; 178 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE: 179 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 180 domain = AMDGPU_GEM_DOMAIN_GTT; 181 place.fpfn = min_offset >> PAGE_SHIFT; 182 place.lpfn = max_offset >> PAGE_SHIFT; 183 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | 184 TTM_PL_FLAG_UNCACHED; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 191 *handle = 0; 192 193 placement.placement = &place; 194 placement.num_placement = 1; 195 placement.busy_placement = &place; 196 placement.num_busy_placement = 1; 197 198 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE, 199 true, domain, flags, 200 NULL, &placement, NULL, 201 &obj); 202 if (ret) { 203 DRM_ERROR("(%d) bo create failed\n", ret); 204 return ret; 205 } 206 *handle = (cgs_handle_t)obj; 207 208 return ret; 209 } 210 211 static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd, 212 cgs_handle_t *handle) 213 { 214 CGS_FUNC_ADEV; 215 int r; 216 uint32_t dma_handle; 217 struct drm_gem_object *obj; 218 struct amdgpu_bo *bo; 219 struct drm_device *dev = adev->ddev; 220 struct drm_file *file_priv = NULL, *priv; 221 222 mutex_lock(&dev->struct_mutex); 223 list_for_each_entry(priv, &dev->filelist, lhead) { 224 rcu_read_lock(); 225 if (priv->pid == get_pid(task_pid(current))) 226 file_priv = priv; 227 rcu_read_unlock(); 228 if (file_priv) 229 break; 230 } 231 mutex_unlock(&dev->struct_mutex); 232 r = dev->driver->prime_fd_to_handle(dev, 233 file_priv, dmabuf_fd, 234 &dma_handle); 235 spin_lock(&file_priv->table_lock); 236 237 /* Check if we currently have a reference on the object */ 238 obj = idr_find(&file_priv->object_idr, dma_handle); 239 if (obj == NULL) { 240 spin_unlock(&file_priv->table_lock); 241 return -EINVAL; 242 } 243 spin_unlock(&file_priv->table_lock); 244 bo = gem_to_amdgpu_bo(obj); 245 *handle = (cgs_handle_t)bo; 246 return 0; 247 } 248 249 static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) 250 { 251 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 252 253 if (obj) { 254 int r = amdgpu_bo_reserve(obj, false); 255 if (likely(r == 0)) { 256 amdgpu_bo_kunmap(obj); 257 amdgpu_bo_unpin(obj); 258 amdgpu_bo_unreserve(obj); 259 } 260 amdgpu_bo_unref(&obj); 261 262 } 263 return 0; 264 } 265 266 static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, 267 uint64_t *mcaddr) 268 { 269 int r; 270 u64 min_offset, max_offset; 271 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 272 273 WARN_ON_ONCE(obj->placement.num_placement > 1); 274 275 min_offset = obj->placements[0].fpfn << PAGE_SHIFT; 276 max_offset = obj->placements[0].lpfn << PAGE_SHIFT; 277 278 r = amdgpu_bo_reserve(obj, false); 279 if (unlikely(r != 0)) 280 return r; 281 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT, 282 min_offset, max_offset, mcaddr); 283 amdgpu_bo_unreserve(obj); 284 return r; 285 } 286 287 static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) 288 { 289 int r; 290 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 291 r = amdgpu_bo_reserve(obj, false); 292 if (unlikely(r != 0)) 293 return r; 294 r = amdgpu_bo_unpin(obj); 295 amdgpu_bo_unreserve(obj); 296 return r; 297 } 298 299 static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, 300 void **map) 301 { 302 int r; 303 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 304 r = amdgpu_bo_reserve(obj, false); 305 if (unlikely(r != 0)) 306 return r; 307 r = amdgpu_bo_kmap(obj, map); 308 amdgpu_bo_unreserve(obj); 309 return r; 310 } 311 312 static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) 313 { 314 int r; 315 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 316 r = amdgpu_bo_reserve(obj, false); 317 if (unlikely(r != 0)) 318 return r; 319 amdgpu_bo_kunmap(obj); 320 amdgpu_bo_unreserve(obj); 321 return r; 322 } 323 324 static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset) 325 { 326 CGS_FUNC_ADEV; 327 return RREG32(offset); 328 } 329 330 static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset, 331 uint32_t value) 332 { 333 CGS_FUNC_ADEV; 334 WREG32(offset, value); 335 } 336 337 static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, 338 enum cgs_ind_reg space, 339 unsigned index) 340 { 341 CGS_FUNC_ADEV; 342 switch (space) { 343 case CGS_IND_REG__MMIO: 344 return RREG32_IDX(index); 345 case CGS_IND_REG__PCIE: 346 return RREG32_PCIE(index); 347 case CGS_IND_REG__SMC: 348 return RREG32_SMC(index); 349 case CGS_IND_REG__UVD_CTX: 350 return RREG32_UVD_CTX(index); 351 case CGS_IND_REG__DIDT: 352 return RREG32_DIDT(index); 353 case CGS_IND_REG__AUDIO_ENDPT: 354 DRM_ERROR("audio endpt register access not implemented.\n"); 355 return 0; 356 } 357 WARN(1, "Invalid indirect register space"); 358 return 0; 359 } 360 361 static void amdgpu_cgs_write_ind_register(void *cgs_device, 362 enum cgs_ind_reg space, 363 unsigned index, uint32_t value) 364 { 365 CGS_FUNC_ADEV; 366 switch (space) { 367 case CGS_IND_REG__MMIO: 368 return WREG32_IDX(index, value); 369 case CGS_IND_REG__PCIE: 370 return WREG32_PCIE(index, value); 371 case CGS_IND_REG__SMC: 372 return WREG32_SMC(index, value); 373 case CGS_IND_REG__UVD_CTX: 374 return WREG32_UVD_CTX(index, value); 375 case CGS_IND_REG__DIDT: 376 return WREG32_DIDT(index, value); 377 case CGS_IND_REG__AUDIO_ENDPT: 378 DRM_ERROR("audio endpt register access not implemented.\n"); 379 return; 380 } 381 WARN(1, "Invalid indirect register space"); 382 } 383 384 static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) 385 { 386 CGS_FUNC_ADEV; 387 uint8_t val; 388 int ret = pci_read_config_byte(adev->pdev, addr, &val); 389 if (WARN(ret, "pci_read_config_byte error")) 390 return 0; 391 return val; 392 } 393 394 static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) 395 { 396 CGS_FUNC_ADEV; 397 uint16_t val; 398 int ret = pci_read_config_word(adev->pdev, addr, &val); 399 if (WARN(ret, "pci_read_config_word error")) 400 return 0; 401 return val; 402 } 403 404 static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, 405 unsigned addr) 406 { 407 CGS_FUNC_ADEV; 408 uint32_t val; 409 int ret = pci_read_config_dword(adev->pdev, addr, &val); 410 if (WARN(ret, "pci_read_config_dword error")) 411 return 0; 412 return val; 413 } 414 415 static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, 416 uint8_t value) 417 { 418 CGS_FUNC_ADEV; 419 int ret = pci_write_config_byte(adev->pdev, addr, value); 420 WARN(ret, "pci_write_config_byte error"); 421 } 422 423 static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, 424 uint16_t value) 425 { 426 CGS_FUNC_ADEV; 427 int ret = pci_write_config_word(adev->pdev, addr, value); 428 WARN(ret, "pci_write_config_word error"); 429 } 430 431 static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, 432 uint32_t value) 433 { 434 CGS_FUNC_ADEV; 435 int ret = pci_write_config_dword(adev->pdev, addr, value); 436 WARN(ret, "pci_write_config_dword error"); 437 } 438 439 static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, 440 unsigned table, uint16_t *size, 441 uint8_t *frev, uint8_t *crev) 442 { 443 CGS_FUNC_ADEV; 444 uint16_t data_start; 445 446 if (amdgpu_atom_parse_data_header( 447 adev->mode_info.atom_context, table, size, 448 frev, crev, &data_start)) 449 return (uint8_t*)adev->mode_info.atom_context->bios + 450 data_start; 451 452 return NULL; 453 } 454 455 static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, 456 uint8_t *frev, uint8_t *crev) 457 { 458 CGS_FUNC_ADEV; 459 460 if (amdgpu_atom_parse_cmd_header( 461 adev->mode_info.atom_context, table, 462 frev, crev)) 463 return 0; 464 465 return -EINVAL; 466 } 467 468 static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, 469 void *args) 470 { 471 CGS_FUNC_ADEV; 472 473 return amdgpu_atom_execute_table( 474 adev->mode_info.atom_context, table, args); 475 } 476 477 static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request) 478 { 479 /* TODO */ 480 return 0; 481 } 482 483 static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request) 484 { 485 /* TODO */ 486 return 0; 487 } 488 489 static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request, 490 int active) 491 { 492 /* TODO */ 493 return 0; 494 } 495 496 static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request, 497 enum cgs_clock clock, unsigned freq) 498 { 499 /* TODO */ 500 return 0; 501 } 502 503 static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, 504 enum cgs_engine engine, int powered) 505 { 506 /* TODO */ 507 return 0; 508 } 509 510 511 512 static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, 513 enum cgs_clock clock, 514 struct cgs_clock_limits *limits) 515 { 516 /* TODO */ 517 return 0; 518 } 519 520 static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask, 521 const uint32_t *voltages) 522 { 523 DRM_ERROR("not implemented"); 524 return -EPERM; 525 } 526 527 struct cgs_irq_params { 528 unsigned src_id; 529 cgs_irq_source_set_func_t set; 530 cgs_irq_handler_func_t handler; 531 void *private_data; 532 }; 533 534 static int cgs_set_irq_state(struct amdgpu_device *adev, 535 struct amdgpu_irq_src *src, 536 unsigned type, 537 enum amdgpu_interrupt_state state) 538 { 539 struct cgs_irq_params *irq_params = 540 (struct cgs_irq_params *)src->data; 541 if (!irq_params) 542 return -EINVAL; 543 if (!irq_params->set) 544 return -EINVAL; 545 return irq_params->set(irq_params->private_data, 546 irq_params->src_id, 547 type, 548 (int)state); 549 } 550 551 static int cgs_process_irq(struct amdgpu_device *adev, 552 struct amdgpu_irq_src *source, 553 struct amdgpu_iv_entry *entry) 554 { 555 struct cgs_irq_params *irq_params = 556 (struct cgs_irq_params *)source->data; 557 if (!irq_params) 558 return -EINVAL; 559 if (!irq_params->handler) 560 return -EINVAL; 561 return irq_params->handler(irq_params->private_data, 562 irq_params->src_id, 563 entry->iv_entry); 564 } 565 566 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = { 567 .set = cgs_set_irq_state, 568 .process = cgs_process_irq, 569 }; 570 571 static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, 572 unsigned num_types, 573 cgs_irq_source_set_func_t set, 574 cgs_irq_handler_func_t handler, 575 void *private_data) 576 { 577 CGS_FUNC_ADEV; 578 int ret = 0; 579 struct cgs_irq_params *irq_params; 580 struct amdgpu_irq_src *source = 581 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); 582 if (!source) 583 return -ENOMEM; 584 irq_params = 585 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL); 586 if (!irq_params) { 587 kfree(source); 588 return -ENOMEM; 589 } 590 source->num_types = num_types; 591 source->funcs = &cgs_irq_funcs; 592 irq_params->src_id = src_id; 593 irq_params->set = set; 594 irq_params->handler = handler; 595 irq_params->private_data = private_data; 596 source->data = (void *)irq_params; 597 ret = amdgpu_irq_add_id(adev, src_id, source); 598 if (ret) { 599 kfree(irq_params); 600 kfree(source); 601 } 602 603 return ret; 604 } 605 606 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type) 607 { 608 CGS_FUNC_ADEV; 609 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type); 610 } 611 612 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type) 613 { 614 CGS_FUNC_ADEV; 615 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type); 616 } 617 618 int amdgpu_cgs_set_clockgating_state(void *cgs_device, 619 enum amd_ip_block_type block_type, 620 enum amd_clockgating_state state) 621 { 622 CGS_FUNC_ADEV; 623 int i, r = -1; 624 625 for (i = 0; i < adev->num_ip_blocks; i++) { 626 if (!adev->ip_block_status[i].valid) 627 continue; 628 629 if (adev->ip_blocks[i].type == block_type) { 630 r = adev->ip_blocks[i].funcs->set_clockgating_state( 631 (void *)adev, 632 state); 633 break; 634 } 635 } 636 return r; 637 } 638 639 int amdgpu_cgs_set_powergating_state(void *cgs_device, 640 enum amd_ip_block_type block_type, 641 enum amd_powergating_state state) 642 { 643 CGS_FUNC_ADEV; 644 int i, r = -1; 645 646 for (i = 0; i < adev->num_ip_blocks; i++) { 647 if (!adev->ip_block_status[i].valid) 648 continue; 649 650 if (adev->ip_blocks[i].type == block_type) { 651 r = adev->ip_blocks[i].funcs->set_powergating_state( 652 (void *)adev, 653 state); 654 break; 655 } 656 } 657 return r; 658 } 659 660 661 static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) 662 { 663 CGS_FUNC_ADEV; 664 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM; 665 666 switch (fw_type) { 667 case CGS_UCODE_ID_SDMA0: 668 result = AMDGPU_UCODE_ID_SDMA0; 669 break; 670 case CGS_UCODE_ID_SDMA1: 671 result = AMDGPU_UCODE_ID_SDMA1; 672 break; 673 case CGS_UCODE_ID_CP_CE: 674 result = AMDGPU_UCODE_ID_CP_CE; 675 break; 676 case CGS_UCODE_ID_CP_PFP: 677 result = AMDGPU_UCODE_ID_CP_PFP; 678 break; 679 case CGS_UCODE_ID_CP_ME: 680 result = AMDGPU_UCODE_ID_CP_ME; 681 break; 682 case CGS_UCODE_ID_CP_MEC: 683 case CGS_UCODE_ID_CP_MEC_JT1: 684 result = AMDGPU_UCODE_ID_CP_MEC1; 685 break; 686 case CGS_UCODE_ID_CP_MEC_JT2: 687 if (adev->asic_type == CHIP_TONGA) 688 result = AMDGPU_UCODE_ID_CP_MEC2; 689 else if (adev->asic_type == CHIP_CARRIZO) 690 result = AMDGPU_UCODE_ID_CP_MEC1; 691 break; 692 case CGS_UCODE_ID_RLC_G: 693 result = AMDGPU_UCODE_ID_RLC_G; 694 break; 695 default: 696 DRM_ERROR("Firmware type not supported\n"); 697 } 698 return result; 699 } 700 701 static int amdgpu_cgs_get_firmware_info(void *cgs_device, 702 enum cgs_ucode_id type, 703 struct cgs_firmware_info *info) 704 { 705 CGS_FUNC_ADEV; 706 707 if (CGS_UCODE_ID_SMU != type) { 708 uint64_t gpu_addr; 709 uint32_t data_size; 710 const struct gfx_firmware_header_v1_0 *header; 711 enum AMDGPU_UCODE_ID id; 712 struct amdgpu_firmware_info *ucode; 713 714 id = fw_type_convert(cgs_device, type); 715 ucode = &adev->firmware.ucode[id]; 716 if (ucode->fw == NULL) 717 return -EINVAL; 718 719 gpu_addr = ucode->mc_addr; 720 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 721 data_size = le32_to_cpu(header->header.ucode_size_bytes); 722 723 if ((type == CGS_UCODE_ID_CP_MEC_JT1) || 724 (type == CGS_UCODE_ID_CP_MEC_JT2)) { 725 gpu_addr += le32_to_cpu(header->jt_offset) << 2; 726 data_size = le32_to_cpu(header->jt_size) << 2; 727 } 728 info->mc_addr = gpu_addr; 729 info->image_size = data_size; 730 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version); 731 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version); 732 } else { 733 char fw_name[30] = {0}; 734 int err = 0; 735 uint32_t ucode_size; 736 uint32_t ucode_start_address; 737 const uint8_t *src; 738 const struct smc_firmware_header_v1_0 *hdr; 739 740 switch (adev->asic_type) { 741 case CHIP_TONGA: 742 strcpy(fw_name, "amdgpu/tonga_smc.bin"); 743 break; 744 default: 745 DRM_ERROR("SMC firmware not supported\n"); 746 return -EINVAL; 747 } 748 749 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 750 if (err) { 751 DRM_ERROR("Failed to request firmware\n"); 752 return err; 753 } 754 755 err = amdgpu_ucode_validate(adev->pm.fw); 756 if (err) { 757 DRM_ERROR("Failed to load firmware \"%s\"", fw_name); 758 release_firmware(adev->pm.fw); 759 adev->pm.fw = NULL; 760 return err; 761 } 762 763 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 764 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 765 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 766 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); 767 src = (const uint8_t *)(adev->pm.fw->data + 768 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 769 770 info->version = adev->pm.fw_version; 771 info->image_size = ucode_size; 772 info->kptr = (void *)src; 773 } 774 return 0; 775 } 776 777 static const struct cgs_ops amdgpu_cgs_ops = { 778 amdgpu_cgs_gpu_mem_info, 779 amdgpu_cgs_gmap_kmem, 780 amdgpu_cgs_gunmap_kmem, 781 amdgpu_cgs_alloc_gpu_mem, 782 amdgpu_cgs_free_gpu_mem, 783 amdgpu_cgs_gmap_gpu_mem, 784 amdgpu_cgs_gunmap_gpu_mem, 785 amdgpu_cgs_kmap_gpu_mem, 786 amdgpu_cgs_kunmap_gpu_mem, 787 amdgpu_cgs_read_register, 788 amdgpu_cgs_write_register, 789 amdgpu_cgs_read_ind_register, 790 amdgpu_cgs_write_ind_register, 791 amdgpu_cgs_read_pci_config_byte, 792 amdgpu_cgs_read_pci_config_word, 793 amdgpu_cgs_read_pci_config_dword, 794 amdgpu_cgs_write_pci_config_byte, 795 amdgpu_cgs_write_pci_config_word, 796 amdgpu_cgs_write_pci_config_dword, 797 amdgpu_cgs_atom_get_data_table, 798 amdgpu_cgs_atom_get_cmd_table_revs, 799 amdgpu_cgs_atom_exec_cmd_table, 800 amdgpu_cgs_create_pm_request, 801 amdgpu_cgs_destroy_pm_request, 802 amdgpu_cgs_set_pm_request, 803 amdgpu_cgs_pm_request_clock, 804 amdgpu_cgs_pm_request_engine, 805 amdgpu_cgs_pm_query_clock_limits, 806 amdgpu_cgs_set_camera_voltages, 807 amdgpu_cgs_get_firmware_info, 808 amdgpu_cgs_set_powergating_state, 809 amdgpu_cgs_set_clockgating_state 810 }; 811 812 static const struct cgs_os_ops amdgpu_cgs_os_ops = { 813 amdgpu_cgs_import_gpu_mem, 814 amdgpu_cgs_add_irq_source, 815 amdgpu_cgs_irq_get, 816 amdgpu_cgs_irq_put 817 }; 818 819 void *amdgpu_cgs_create_device(struct amdgpu_device *adev) 820 { 821 struct amdgpu_cgs_device *cgs_device = 822 kmalloc(sizeof(*cgs_device), GFP_KERNEL); 823 824 if (!cgs_device) { 825 DRM_ERROR("Couldn't allocate CGS device structure\n"); 826 return NULL; 827 } 828 829 cgs_device->base.ops = &amdgpu_cgs_ops; 830 cgs_device->base.os_ops = &amdgpu_cgs_os_ops; 831 cgs_device->adev = adev; 832 833 return cgs_device; 834 } 835 836 void amdgpu_cgs_destroy_device(void *cgs_device) 837 { 838 kfree(cgs_device); 839 } 840