1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include <linux/slab.h> 26 #include <linux/pci.h> 27 #include <linux/acpi.h> 28 #include <drm/drmP.h> 29 #include <linux/firmware.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "cgs_linux.h" 33 #include "atom.h" 34 #include "amdgpu_ucode.h" 35 36 struct amdgpu_cgs_device { 37 struct cgs_device base; 38 struct amdgpu_device *adev; 39 }; 40 41 #define CGS_FUNC_ADEV \ 42 struct amdgpu_device *adev = \ 43 ((struct amdgpu_cgs_device *)cgs_device)->adev 44 45 static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, 46 uint64_t *mc_start, uint64_t *mc_size, 47 uint64_t *mem_size) 48 { 49 CGS_FUNC_ADEV; 50 switch(type) { 51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB: 52 case CGS_GPU_MEM_TYPE__VISIBLE_FB: 53 *mc_start = 0; 54 *mc_size = adev->mc.visible_vram_size; 55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size; 56 break; 57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: 58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB: 59 *mc_start = adev->mc.visible_vram_size; 60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size; 61 *mem_size = *mc_size; 62 break; 63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE: 64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE: 65 *mc_start = adev->mc.gtt_start; 66 *mc_size = adev->mc.gtt_size; 67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size; 68 break; 69 default: 70 return -EINVAL; 71 } 72 73 return 0; 74 } 75 76 static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, 77 uint64_t size, 78 uint64_t min_offset, uint64_t max_offset, 79 cgs_handle_t *kmem_handle, uint64_t *mcaddr) 80 { 81 CGS_FUNC_ADEV; 82 int ret; 83 struct amdgpu_bo *bo; 84 struct page *kmem_page = vmalloc_to_page(kmem); 85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT; 86 87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages); 88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false, 89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo); 90 if (ret) 91 return ret; 92 ret = amdgpu_bo_reserve(bo, false); 93 if (unlikely(ret != 0)) 94 return ret; 95 96 /* pin buffer into GTT */ 97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT, 98 min_offset, max_offset, mcaddr); 99 amdgpu_bo_unreserve(bo); 100 101 *kmem_handle = (cgs_handle_t)bo; 102 return ret; 103 } 104 105 static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) 106 { 107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle; 108 109 if (obj) { 110 int r = amdgpu_bo_reserve(obj, false); 111 if (likely(r == 0)) { 112 amdgpu_bo_unpin(obj); 113 amdgpu_bo_unreserve(obj); 114 } 115 amdgpu_bo_unref(&obj); 116 117 } 118 return 0; 119 } 120 121 static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, 122 enum cgs_gpu_mem_type type, 123 uint64_t size, uint64_t align, 124 uint64_t min_offset, uint64_t max_offset, 125 cgs_handle_t *handle) 126 { 127 CGS_FUNC_ADEV; 128 uint16_t flags = 0; 129 int ret = 0; 130 uint32_t domain = 0; 131 struct amdgpu_bo *obj; 132 struct ttm_placement placement; 133 struct ttm_place place; 134 135 if (min_offset > max_offset) { 136 BUG_ON(1); 137 return -EINVAL; 138 } 139 140 /* fail if the alignment is not a power of 2 */ 141 if (((align != 1) && (align & (align - 1))) 142 || size == 0 || align == 0) 143 return -EINVAL; 144 145 146 switch(type) { 147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB: 148 case CGS_GPU_MEM_TYPE__VISIBLE_FB: 149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 150 domain = AMDGPU_GEM_DOMAIN_VRAM; 151 if (max_offset > adev->mc.real_vram_size) 152 return -EINVAL; 153 place.fpfn = min_offset >> PAGE_SHIFT; 154 place.lpfn = max_offset >> PAGE_SHIFT; 155 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 156 TTM_PL_FLAG_VRAM; 157 break; 158 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: 159 case CGS_GPU_MEM_TYPE__INVISIBLE_FB: 160 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 161 domain = AMDGPU_GEM_DOMAIN_VRAM; 162 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { 163 place.fpfn = 164 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT; 165 place.lpfn = 166 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT; 167 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 168 TTM_PL_FLAG_VRAM; 169 } 170 171 break; 172 case CGS_GPU_MEM_TYPE__GART_CACHEABLE: 173 domain = AMDGPU_GEM_DOMAIN_GTT; 174 place.fpfn = min_offset >> PAGE_SHIFT; 175 place.lpfn = max_offset >> PAGE_SHIFT; 176 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 177 break; 178 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE: 179 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 180 domain = AMDGPU_GEM_DOMAIN_GTT; 181 place.fpfn = min_offset >> PAGE_SHIFT; 182 place.lpfn = max_offset >> PAGE_SHIFT; 183 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | 184 TTM_PL_FLAG_UNCACHED; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 191 *handle = 0; 192 193 placement.placement = &place; 194 placement.num_placement = 1; 195 placement.busy_placement = &place; 196 placement.num_busy_placement = 1; 197 198 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE, 199 true, domain, flags, 200 NULL, &placement, NULL, 201 &obj); 202 if (ret) { 203 DRM_ERROR("(%d) bo create failed\n", ret); 204 return ret; 205 } 206 *handle = (cgs_handle_t)obj; 207 208 return ret; 209 } 210 211 static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) 212 { 213 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 214 215 if (obj) { 216 int r = amdgpu_bo_reserve(obj, false); 217 if (likely(r == 0)) { 218 amdgpu_bo_kunmap(obj); 219 amdgpu_bo_unpin(obj); 220 amdgpu_bo_unreserve(obj); 221 } 222 amdgpu_bo_unref(&obj); 223 224 } 225 return 0; 226 } 227 228 static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, 229 uint64_t *mcaddr) 230 { 231 int r; 232 u64 min_offset, max_offset; 233 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 234 235 WARN_ON_ONCE(obj->placement.num_placement > 1); 236 237 min_offset = obj->placements[0].fpfn << PAGE_SHIFT; 238 max_offset = obj->placements[0].lpfn << PAGE_SHIFT; 239 240 r = amdgpu_bo_reserve(obj, false); 241 if (unlikely(r != 0)) 242 return r; 243 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT, 244 min_offset, max_offset, mcaddr); 245 amdgpu_bo_unreserve(obj); 246 return r; 247 } 248 249 static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) 250 { 251 int r; 252 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 253 r = amdgpu_bo_reserve(obj, false); 254 if (unlikely(r != 0)) 255 return r; 256 r = amdgpu_bo_unpin(obj); 257 amdgpu_bo_unreserve(obj); 258 return r; 259 } 260 261 static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, 262 void **map) 263 { 264 int r; 265 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 266 r = amdgpu_bo_reserve(obj, false); 267 if (unlikely(r != 0)) 268 return r; 269 r = amdgpu_bo_kmap(obj, map); 270 amdgpu_bo_unreserve(obj); 271 return r; 272 } 273 274 static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) 275 { 276 int r; 277 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; 278 r = amdgpu_bo_reserve(obj, false); 279 if (unlikely(r != 0)) 280 return r; 281 amdgpu_bo_kunmap(obj); 282 amdgpu_bo_unreserve(obj); 283 return r; 284 } 285 286 static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset) 287 { 288 CGS_FUNC_ADEV; 289 return RREG32(offset); 290 } 291 292 static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset, 293 uint32_t value) 294 { 295 CGS_FUNC_ADEV; 296 WREG32(offset, value); 297 } 298 299 static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, 300 enum cgs_ind_reg space, 301 unsigned index) 302 { 303 CGS_FUNC_ADEV; 304 switch (space) { 305 case CGS_IND_REG__MMIO: 306 return RREG32_IDX(index); 307 case CGS_IND_REG__PCIE: 308 return RREG32_PCIE(index); 309 case CGS_IND_REG__SMC: 310 return RREG32_SMC(index); 311 case CGS_IND_REG__UVD_CTX: 312 return RREG32_UVD_CTX(index); 313 case CGS_IND_REG__DIDT: 314 return RREG32_DIDT(index); 315 case CGS_IND_REG__AUDIO_ENDPT: 316 DRM_ERROR("audio endpt register access not implemented.\n"); 317 return 0; 318 } 319 WARN(1, "Invalid indirect register space"); 320 return 0; 321 } 322 323 static void amdgpu_cgs_write_ind_register(void *cgs_device, 324 enum cgs_ind_reg space, 325 unsigned index, uint32_t value) 326 { 327 CGS_FUNC_ADEV; 328 switch (space) { 329 case CGS_IND_REG__MMIO: 330 return WREG32_IDX(index, value); 331 case CGS_IND_REG__PCIE: 332 return WREG32_PCIE(index, value); 333 case CGS_IND_REG__SMC: 334 return WREG32_SMC(index, value); 335 case CGS_IND_REG__UVD_CTX: 336 return WREG32_UVD_CTX(index, value); 337 case CGS_IND_REG__DIDT: 338 return WREG32_DIDT(index, value); 339 case CGS_IND_REG__AUDIO_ENDPT: 340 DRM_ERROR("audio endpt register access not implemented.\n"); 341 return; 342 } 343 WARN(1, "Invalid indirect register space"); 344 } 345 346 static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) 347 { 348 CGS_FUNC_ADEV; 349 uint8_t val; 350 int ret = pci_read_config_byte(adev->pdev, addr, &val); 351 if (WARN(ret, "pci_read_config_byte error")) 352 return 0; 353 return val; 354 } 355 356 static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) 357 { 358 CGS_FUNC_ADEV; 359 uint16_t val; 360 int ret = pci_read_config_word(adev->pdev, addr, &val); 361 if (WARN(ret, "pci_read_config_word error")) 362 return 0; 363 return val; 364 } 365 366 static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, 367 unsigned addr) 368 { 369 CGS_FUNC_ADEV; 370 uint32_t val; 371 int ret = pci_read_config_dword(adev->pdev, addr, &val); 372 if (WARN(ret, "pci_read_config_dword error")) 373 return 0; 374 return val; 375 } 376 377 static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, 378 uint8_t value) 379 { 380 CGS_FUNC_ADEV; 381 int ret = pci_write_config_byte(adev->pdev, addr, value); 382 WARN(ret, "pci_write_config_byte error"); 383 } 384 385 static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, 386 uint16_t value) 387 { 388 CGS_FUNC_ADEV; 389 int ret = pci_write_config_word(adev->pdev, addr, value); 390 WARN(ret, "pci_write_config_word error"); 391 } 392 393 static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, 394 uint32_t value) 395 { 396 CGS_FUNC_ADEV; 397 int ret = pci_write_config_dword(adev->pdev, addr, value); 398 WARN(ret, "pci_write_config_dword error"); 399 } 400 401 402 static int amdgpu_cgs_get_pci_resource(void *cgs_device, 403 enum cgs_resource_type resource_type, 404 uint64_t size, 405 uint64_t offset, 406 uint64_t *resource_base) 407 { 408 CGS_FUNC_ADEV; 409 410 if (resource_base == NULL) 411 return -EINVAL; 412 413 switch (resource_type) { 414 case CGS_RESOURCE_TYPE_MMIO: 415 if (adev->rmmio_size == 0) 416 return -ENOENT; 417 if ((offset + size) > adev->rmmio_size) 418 return -EINVAL; 419 *resource_base = adev->rmmio_base; 420 return 0; 421 case CGS_RESOURCE_TYPE_DOORBELL: 422 if (adev->doorbell.size == 0) 423 return -ENOENT; 424 if ((offset + size) > adev->doorbell.size) 425 return -EINVAL; 426 *resource_base = adev->doorbell.base; 427 return 0; 428 case CGS_RESOURCE_TYPE_FB: 429 case CGS_RESOURCE_TYPE_IO: 430 case CGS_RESOURCE_TYPE_ROM: 431 default: 432 return -EINVAL; 433 } 434 } 435 436 static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, 437 unsigned table, uint16_t *size, 438 uint8_t *frev, uint8_t *crev) 439 { 440 CGS_FUNC_ADEV; 441 uint16_t data_start; 442 443 if (amdgpu_atom_parse_data_header( 444 adev->mode_info.atom_context, table, size, 445 frev, crev, &data_start)) 446 return (uint8_t*)adev->mode_info.atom_context->bios + 447 data_start; 448 449 return NULL; 450 } 451 452 static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, 453 uint8_t *frev, uint8_t *crev) 454 { 455 CGS_FUNC_ADEV; 456 457 if (amdgpu_atom_parse_cmd_header( 458 adev->mode_info.atom_context, table, 459 frev, crev)) 460 return 0; 461 462 return -EINVAL; 463 } 464 465 static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, 466 void *args) 467 { 468 CGS_FUNC_ADEV; 469 470 return amdgpu_atom_execute_table( 471 adev->mode_info.atom_context, table, args); 472 } 473 474 static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request) 475 { 476 /* TODO */ 477 return 0; 478 } 479 480 static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request) 481 { 482 /* TODO */ 483 return 0; 484 } 485 486 static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request, 487 int active) 488 { 489 /* TODO */ 490 return 0; 491 } 492 493 static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request, 494 enum cgs_clock clock, unsigned freq) 495 { 496 /* TODO */ 497 return 0; 498 } 499 500 static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, 501 enum cgs_engine engine, int powered) 502 { 503 /* TODO */ 504 return 0; 505 } 506 507 508 509 static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, 510 enum cgs_clock clock, 511 struct cgs_clock_limits *limits) 512 { 513 /* TODO */ 514 return 0; 515 } 516 517 static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask, 518 const uint32_t *voltages) 519 { 520 DRM_ERROR("not implemented"); 521 return -EPERM; 522 } 523 524 struct cgs_irq_params { 525 unsigned src_id; 526 cgs_irq_source_set_func_t set; 527 cgs_irq_handler_func_t handler; 528 void *private_data; 529 }; 530 531 static int cgs_set_irq_state(struct amdgpu_device *adev, 532 struct amdgpu_irq_src *src, 533 unsigned type, 534 enum amdgpu_interrupt_state state) 535 { 536 struct cgs_irq_params *irq_params = 537 (struct cgs_irq_params *)src->data; 538 if (!irq_params) 539 return -EINVAL; 540 if (!irq_params->set) 541 return -EINVAL; 542 return irq_params->set(irq_params->private_data, 543 irq_params->src_id, 544 type, 545 (int)state); 546 } 547 548 static int cgs_process_irq(struct amdgpu_device *adev, 549 struct amdgpu_irq_src *source, 550 struct amdgpu_iv_entry *entry) 551 { 552 struct cgs_irq_params *irq_params = 553 (struct cgs_irq_params *)source->data; 554 if (!irq_params) 555 return -EINVAL; 556 if (!irq_params->handler) 557 return -EINVAL; 558 return irq_params->handler(irq_params->private_data, 559 irq_params->src_id, 560 entry->iv_entry); 561 } 562 563 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = { 564 .set = cgs_set_irq_state, 565 .process = cgs_process_irq, 566 }; 567 568 static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, 569 unsigned num_types, 570 cgs_irq_source_set_func_t set, 571 cgs_irq_handler_func_t handler, 572 void *private_data) 573 { 574 CGS_FUNC_ADEV; 575 int ret = 0; 576 struct cgs_irq_params *irq_params; 577 struct amdgpu_irq_src *source = 578 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); 579 if (!source) 580 return -ENOMEM; 581 irq_params = 582 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL); 583 if (!irq_params) { 584 kfree(source); 585 return -ENOMEM; 586 } 587 source->num_types = num_types; 588 source->funcs = &cgs_irq_funcs; 589 irq_params->src_id = src_id; 590 irq_params->set = set; 591 irq_params->handler = handler; 592 irq_params->private_data = private_data; 593 source->data = (void *)irq_params; 594 ret = amdgpu_irq_add_id(adev, src_id, source); 595 if (ret) { 596 kfree(irq_params); 597 kfree(source); 598 } 599 600 return ret; 601 } 602 603 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type) 604 { 605 CGS_FUNC_ADEV; 606 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type); 607 } 608 609 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type) 610 { 611 CGS_FUNC_ADEV; 612 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type); 613 } 614 615 int amdgpu_cgs_set_clockgating_state(void *cgs_device, 616 enum amd_ip_block_type block_type, 617 enum amd_clockgating_state state) 618 { 619 CGS_FUNC_ADEV; 620 int i, r = -1; 621 622 for (i = 0; i < adev->num_ip_blocks; i++) { 623 if (!adev->ip_block_status[i].valid) 624 continue; 625 626 if (adev->ip_blocks[i].type == block_type) { 627 r = adev->ip_blocks[i].funcs->set_clockgating_state( 628 (void *)adev, 629 state); 630 break; 631 } 632 } 633 return r; 634 } 635 636 int amdgpu_cgs_set_powergating_state(void *cgs_device, 637 enum amd_ip_block_type block_type, 638 enum amd_powergating_state state) 639 { 640 CGS_FUNC_ADEV; 641 int i, r = -1; 642 643 for (i = 0; i < adev->num_ip_blocks; i++) { 644 if (!adev->ip_block_status[i].valid) 645 continue; 646 647 if (adev->ip_blocks[i].type == block_type) { 648 r = adev->ip_blocks[i].funcs->set_powergating_state( 649 (void *)adev, 650 state); 651 break; 652 } 653 } 654 return r; 655 } 656 657 658 static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) 659 { 660 CGS_FUNC_ADEV; 661 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM; 662 663 switch (fw_type) { 664 case CGS_UCODE_ID_SDMA0: 665 result = AMDGPU_UCODE_ID_SDMA0; 666 break; 667 case CGS_UCODE_ID_SDMA1: 668 result = AMDGPU_UCODE_ID_SDMA1; 669 break; 670 case CGS_UCODE_ID_CP_CE: 671 result = AMDGPU_UCODE_ID_CP_CE; 672 break; 673 case CGS_UCODE_ID_CP_PFP: 674 result = AMDGPU_UCODE_ID_CP_PFP; 675 break; 676 case CGS_UCODE_ID_CP_ME: 677 result = AMDGPU_UCODE_ID_CP_ME; 678 break; 679 case CGS_UCODE_ID_CP_MEC: 680 case CGS_UCODE_ID_CP_MEC_JT1: 681 result = AMDGPU_UCODE_ID_CP_MEC1; 682 break; 683 case CGS_UCODE_ID_CP_MEC_JT2: 684 if (adev->asic_type == CHIP_TONGA) 685 result = AMDGPU_UCODE_ID_CP_MEC2; 686 else if (adev->asic_type == CHIP_CARRIZO) 687 result = AMDGPU_UCODE_ID_CP_MEC1; 688 break; 689 case CGS_UCODE_ID_RLC_G: 690 result = AMDGPU_UCODE_ID_RLC_G; 691 break; 692 default: 693 DRM_ERROR("Firmware type not supported\n"); 694 } 695 return result; 696 } 697 698 static int amdgpu_cgs_get_firmware_info(void *cgs_device, 699 enum cgs_ucode_id type, 700 struct cgs_firmware_info *info) 701 { 702 CGS_FUNC_ADEV; 703 704 if (CGS_UCODE_ID_SMU != type) { 705 uint64_t gpu_addr; 706 uint32_t data_size; 707 const struct gfx_firmware_header_v1_0 *header; 708 enum AMDGPU_UCODE_ID id; 709 struct amdgpu_firmware_info *ucode; 710 711 id = fw_type_convert(cgs_device, type); 712 ucode = &adev->firmware.ucode[id]; 713 if (ucode->fw == NULL) 714 return -EINVAL; 715 716 gpu_addr = ucode->mc_addr; 717 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 718 data_size = le32_to_cpu(header->header.ucode_size_bytes); 719 720 if ((type == CGS_UCODE_ID_CP_MEC_JT1) || 721 (type == CGS_UCODE_ID_CP_MEC_JT2)) { 722 gpu_addr += le32_to_cpu(header->jt_offset) << 2; 723 data_size = le32_to_cpu(header->jt_size) << 2; 724 } 725 info->mc_addr = gpu_addr; 726 info->image_size = data_size; 727 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version); 728 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version); 729 } else { 730 char fw_name[30] = {0}; 731 int err = 0; 732 uint32_t ucode_size; 733 uint32_t ucode_start_address; 734 const uint8_t *src; 735 const struct smc_firmware_header_v1_0 *hdr; 736 737 switch (adev->asic_type) { 738 case CHIP_TONGA: 739 strcpy(fw_name, "amdgpu/tonga_smc.bin"); 740 break; 741 case CHIP_FIJI: 742 strcpy(fw_name, "amdgpu/fiji_smc.bin"); 743 break; 744 default: 745 DRM_ERROR("SMC firmware not supported\n"); 746 return -EINVAL; 747 } 748 749 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 750 if (err) { 751 DRM_ERROR("Failed to request firmware\n"); 752 return err; 753 } 754 755 err = amdgpu_ucode_validate(adev->pm.fw); 756 if (err) { 757 DRM_ERROR("Failed to load firmware \"%s\"", fw_name); 758 release_firmware(adev->pm.fw); 759 adev->pm.fw = NULL; 760 return err; 761 } 762 763 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 764 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 765 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 766 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); 767 src = (const uint8_t *)(adev->pm.fw->data + 768 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 769 770 info->version = adev->pm.fw_version; 771 info->image_size = ucode_size; 772 info->kptr = (void *)src; 773 } 774 return 0; 775 } 776 777 static int amdgpu_cgs_query_system_info(void *cgs_device, 778 struct cgs_system_info *sys_info) 779 { 780 CGS_FUNC_ADEV; 781 782 if (NULL == sys_info) 783 return -ENODEV; 784 785 if (sizeof(struct cgs_system_info) != sys_info->size) 786 return -ENODEV; 787 788 switch (sys_info->info_id) { 789 case CGS_SYSTEM_INFO_ADAPTER_BDF_ID: 790 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8); 791 break; 792 case CGS_SYSTEM_INFO_PCIE_GEN_INFO: 793 sys_info->value = adev->pm.pcie_gen_mask; 794 break; 795 case CGS_SYSTEM_INFO_PCIE_MLW: 796 sys_info->value = adev->pm.pcie_mlw_mask; 797 break; 798 default: 799 return -ENODEV; 800 } 801 802 return 0; 803 } 804 805 static int amdgpu_cgs_get_active_displays_info(void *cgs_device, 806 struct cgs_display_info *info) 807 { 808 CGS_FUNC_ADEV; 809 struct amdgpu_crtc *amdgpu_crtc; 810 struct drm_device *ddev = adev->ddev; 811 struct drm_crtc *crtc; 812 uint32_t line_time_us, vblank_lines; 813 814 if (info == NULL) 815 return -EINVAL; 816 817 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { 818 list_for_each_entry(crtc, 819 &ddev->mode_config.crtc_list, head) { 820 amdgpu_crtc = to_amdgpu_crtc(crtc); 821 if (crtc->enabled) { 822 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); 823 info->display_count++; 824 } 825 if (info->mode_info != NULL && 826 crtc->enabled && amdgpu_crtc->enabled && 827 amdgpu_crtc->hw_mode.clock) { 828 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / 829 amdgpu_crtc->hw_mode.clock; 830 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - 831 amdgpu_crtc->hw_mode.crtc_vdisplay + 832 (amdgpu_crtc->v_border * 2); 833 info->mode_info->vblank_time_us = vblank_lines * line_time_us; 834 info->mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); 835 info->mode_info->ref_clock = adev->clock.spll.reference_freq; 836 info->mode_info++; 837 } 838 } 839 } 840 841 return 0; 842 } 843 844 /** \brief evaluate acpi namespace object, handle or pathname must be valid 845 * \param cgs_device 846 * \param info input/output arguments for the control method 847 * \return status 848 */ 849 850 #if defined(CONFIG_ACPI) 851 static int amdgpu_cgs_acpi_eval_object(void *cgs_device, 852 struct cgs_acpi_method_info *info) 853 { 854 CGS_FUNC_ADEV; 855 acpi_handle handle; 856 struct acpi_object_list input; 857 struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL }; 858 union acpi_object *params = NULL; 859 union acpi_object *obj = NULL; 860 uint8_t name[5] = {'\0'}; 861 struct cgs_acpi_method_argument *argument = NULL; 862 uint32_t i, count; 863 acpi_status status; 864 int result; 865 uint32_t func_no = 0xFFFFFFFF; 866 867 handle = ACPI_HANDLE(&adev->pdev->dev); 868 if (!handle) 869 return -ENODEV; 870 871 memset(&input, 0, sizeof(struct acpi_object_list)); 872 873 /* validate input info */ 874 if (info->size != sizeof(struct cgs_acpi_method_info)) 875 return -EINVAL; 876 877 input.count = info->input_count; 878 if (info->input_count > 0) { 879 if (info->pinput_argument == NULL) 880 return -EINVAL; 881 argument = info->pinput_argument; 882 func_no = argument->value; 883 for (i = 0; i < info->input_count; i++) { 884 if (((argument->type == ACPI_TYPE_STRING) || 885 (argument->type == ACPI_TYPE_BUFFER)) && 886 (argument->pointer == NULL)) 887 return -EINVAL; 888 argument++; 889 } 890 } 891 892 if (info->output_count > 0) { 893 if (info->poutput_argument == NULL) 894 return -EINVAL; 895 argument = info->poutput_argument; 896 for (i = 0; i < info->output_count; i++) { 897 if (((argument->type == ACPI_TYPE_STRING) || 898 (argument->type == ACPI_TYPE_BUFFER)) 899 && (argument->pointer == NULL)) 900 return -EINVAL; 901 argument++; 902 } 903 } 904 905 /* The path name passed to acpi_evaluate_object should be null terminated */ 906 if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) { 907 strncpy(name, (char *)&(info->name), sizeof(uint32_t)); 908 name[4] = '\0'; 909 } 910 911 /* parse input parameters */ 912 if (input.count > 0) { 913 input.pointer = params = 914 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL); 915 if (params == NULL) 916 return -EINVAL; 917 918 argument = info->pinput_argument; 919 920 for (i = 0; i < input.count; i++) { 921 params->type = argument->type; 922 switch (params->type) { 923 case ACPI_TYPE_INTEGER: 924 params->integer.value = argument->value; 925 break; 926 case ACPI_TYPE_STRING: 927 params->string.length = argument->method_length; 928 params->string.pointer = argument->pointer; 929 break; 930 case ACPI_TYPE_BUFFER: 931 params->buffer.length = argument->method_length; 932 params->buffer.pointer = argument->pointer; 933 break; 934 default: 935 break; 936 } 937 params++; 938 argument++; 939 } 940 } 941 942 /* parse output info */ 943 count = info->output_count; 944 argument = info->poutput_argument; 945 946 /* evaluate the acpi method */ 947 status = acpi_evaluate_object(handle, name, &input, &output); 948 949 if (ACPI_FAILURE(status)) { 950 result = -EIO; 951 goto error; 952 } 953 954 /* return the output info */ 955 obj = output.pointer; 956 957 if (count > 1) { 958 if ((obj->type != ACPI_TYPE_PACKAGE) || 959 (obj->package.count != count)) { 960 result = -EIO; 961 goto error; 962 } 963 params = obj->package.elements; 964 } else 965 params = obj; 966 967 if (params == NULL) { 968 result = -EIO; 969 goto error; 970 } 971 972 for (i = 0; i < count; i++) { 973 if (argument->type != params->type) { 974 result = -EIO; 975 goto error; 976 } 977 switch (params->type) { 978 case ACPI_TYPE_INTEGER: 979 argument->value = params->integer.value; 980 break; 981 case ACPI_TYPE_STRING: 982 if ((params->string.length != argument->data_length) || 983 (params->string.pointer == NULL)) { 984 result = -EIO; 985 goto error; 986 } 987 strncpy(argument->pointer, 988 params->string.pointer, 989 params->string.length); 990 break; 991 case ACPI_TYPE_BUFFER: 992 if (params->buffer.pointer == NULL) { 993 result = -EIO; 994 goto error; 995 } 996 memcpy(argument->pointer, 997 params->buffer.pointer, 998 argument->data_length); 999 break; 1000 default: 1001 break; 1002 } 1003 argument++; 1004 params++; 1005 } 1006 1007 error: 1008 if (obj != NULL) 1009 kfree(obj); 1010 kfree((void *)input.pointer); 1011 return result; 1012 } 1013 #else 1014 static int amdgpu_cgs_acpi_eval_object(void *cgs_device, 1015 struct cgs_acpi_method_info *info) 1016 { 1017 return -EIO; 1018 } 1019 #endif 1020 1021 int amdgpu_cgs_call_acpi_method(void *cgs_device, 1022 uint32_t acpi_method, 1023 uint32_t acpi_function, 1024 void *pinput, void *poutput, 1025 uint32_t output_count, 1026 uint32_t input_size, 1027 uint32_t output_size) 1028 { 1029 struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} }; 1030 struct cgs_acpi_method_argument acpi_output = {0}; 1031 struct cgs_acpi_method_info info = {0}; 1032 1033 acpi_input[0].type = CGS_ACPI_TYPE_INTEGER; 1034 acpi_input[0].method_length = sizeof(uint32_t); 1035 acpi_input[0].data_length = sizeof(uint32_t); 1036 acpi_input[0].value = acpi_function; 1037 1038 acpi_input[1].type = CGS_ACPI_TYPE_BUFFER; 1039 acpi_input[1].method_length = CGS_ACPI_MAX_BUFFER_SIZE; 1040 acpi_input[1].data_length = input_size; 1041 acpi_input[1].pointer = pinput; 1042 1043 acpi_output.type = CGS_ACPI_TYPE_BUFFER; 1044 acpi_output.method_length = CGS_ACPI_MAX_BUFFER_SIZE; 1045 acpi_output.data_length = output_size; 1046 acpi_output.pointer = poutput; 1047 1048 info.size = sizeof(struct cgs_acpi_method_info); 1049 info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT; 1050 info.input_count = 2; 1051 info.name = acpi_method; 1052 info.pinput_argument = acpi_input; 1053 info.output_count = output_count; 1054 info.poutput_argument = &acpi_output; 1055 1056 return amdgpu_cgs_acpi_eval_object(cgs_device, &info); 1057 } 1058 1059 static const struct cgs_ops amdgpu_cgs_ops = { 1060 amdgpu_cgs_gpu_mem_info, 1061 amdgpu_cgs_gmap_kmem, 1062 amdgpu_cgs_gunmap_kmem, 1063 amdgpu_cgs_alloc_gpu_mem, 1064 amdgpu_cgs_free_gpu_mem, 1065 amdgpu_cgs_gmap_gpu_mem, 1066 amdgpu_cgs_gunmap_gpu_mem, 1067 amdgpu_cgs_kmap_gpu_mem, 1068 amdgpu_cgs_kunmap_gpu_mem, 1069 amdgpu_cgs_read_register, 1070 amdgpu_cgs_write_register, 1071 amdgpu_cgs_read_ind_register, 1072 amdgpu_cgs_write_ind_register, 1073 amdgpu_cgs_read_pci_config_byte, 1074 amdgpu_cgs_read_pci_config_word, 1075 amdgpu_cgs_read_pci_config_dword, 1076 amdgpu_cgs_write_pci_config_byte, 1077 amdgpu_cgs_write_pci_config_word, 1078 amdgpu_cgs_write_pci_config_dword, 1079 amdgpu_cgs_get_pci_resource, 1080 amdgpu_cgs_atom_get_data_table, 1081 amdgpu_cgs_atom_get_cmd_table_revs, 1082 amdgpu_cgs_atom_exec_cmd_table, 1083 amdgpu_cgs_create_pm_request, 1084 amdgpu_cgs_destroy_pm_request, 1085 amdgpu_cgs_set_pm_request, 1086 amdgpu_cgs_pm_request_clock, 1087 amdgpu_cgs_pm_request_engine, 1088 amdgpu_cgs_pm_query_clock_limits, 1089 amdgpu_cgs_set_camera_voltages, 1090 amdgpu_cgs_get_firmware_info, 1091 amdgpu_cgs_set_powergating_state, 1092 amdgpu_cgs_set_clockgating_state, 1093 amdgpu_cgs_get_active_displays_info, 1094 amdgpu_cgs_call_acpi_method, 1095 amdgpu_cgs_query_system_info, 1096 }; 1097 1098 static const struct cgs_os_ops amdgpu_cgs_os_ops = { 1099 amdgpu_cgs_add_irq_source, 1100 amdgpu_cgs_irq_get, 1101 amdgpu_cgs_irq_put 1102 }; 1103 1104 void *amdgpu_cgs_create_device(struct amdgpu_device *adev) 1105 { 1106 struct amdgpu_cgs_device *cgs_device = 1107 kmalloc(sizeof(*cgs_device), GFP_KERNEL); 1108 1109 if (!cgs_device) { 1110 DRM_ERROR("Couldn't allocate CGS device structure\n"); 1111 return NULL; 1112 } 1113 1114 cgs_device->base.ops = &amdgpu_cgs_ops; 1115 cgs_device->base.os_ops = &amdgpu_cgs_os_ops; 1116 cgs_device->adev = adev; 1117 1118 return cgs_device; 1119 } 1120 1121 void amdgpu_cgs_destroy_device(void *cgs_device) 1122 { 1123 kfree(cgs_device); 1124 } 1125