1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_BO_LIST_H__ 24 #define __AMDGPU_BO_LIST_H__ 25 26 #include <drm/ttm/ttm_execbuf_util.h> 27 #include <drm/amdgpu_drm.h> 28 29 struct hmm_range; 30 31 struct amdgpu_device; 32 struct amdgpu_bo; 33 struct amdgpu_bo_va; 34 struct amdgpu_fpriv; 35 36 struct amdgpu_bo_list_entry { 37 struct ttm_validate_buffer tv; 38 struct amdgpu_bo_va *bo_va; 39 uint32_t priority; 40 struct page **user_pages; 41 struct hmm_range *range; 42 bool user_invalidated; 43 }; 44 45 struct amdgpu_bo_list { 46 struct rcu_head rhead; 47 struct kref refcount; 48 struct amdgpu_bo *gds_obj; 49 struct amdgpu_bo *gws_obj; 50 struct amdgpu_bo *oa_obj; 51 unsigned first_userptr; 52 unsigned num_entries; 53 54 /* Protect access during command submission. 55 */ 56 struct mutex bo_list_mutex; 57 }; 58 59 int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, 60 struct amdgpu_bo_list **result); 61 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 62 struct list_head *validated); 63 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 64 int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in, 65 struct drm_amdgpu_bo_list_entry **info_param); 66 67 int amdgpu_bo_list_create(struct amdgpu_device *adev, 68 struct drm_file *filp, 69 struct drm_amdgpu_bo_list_entry *info, 70 size_t num_entries, 71 struct amdgpu_bo_list **list); 72 73 static inline struct amdgpu_bo_list_entry * 74 amdgpu_bo_list_array_entry(struct amdgpu_bo_list *list, unsigned index) 75 { 76 struct amdgpu_bo_list_entry *array = (void *)&list[1]; 77 78 return &array[index]; 79 } 80 81 #define amdgpu_bo_list_for_each_entry(e, list) \ 82 for (e = amdgpu_bo_list_array_entry(list, 0); \ 83 e != amdgpu_bo_list_array_entry(list, (list)->num_entries); \ 84 ++e) 85 86 #define amdgpu_bo_list_for_each_userptr_entry(e, list) \ 87 for (e = amdgpu_bo_list_array_entry(list, (list)->first_userptr); \ 88 e != amdgpu_bo_list_array_entry(list, (list)->num_entries); \ 89 ++e) 90 91 #endif 92