1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/amdgpu_drm.h> 25 #include "amdgpu.h" 26 #include "atomfirmware.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "atom.h" 29 #include "atombios.h" 30 #include "soc15_hw_ip.h" 31 32 union firmware_info { 33 struct atom_firmware_info_v3_1 v31; 34 struct atom_firmware_info_v3_2 v32; 35 struct atom_firmware_info_v3_3 v33; 36 struct atom_firmware_info_v3_4 v34; 37 }; 38 39 /* 40 * Helper function to query firmware capability 41 * 42 * @adev: amdgpu_device pointer 43 * 44 * Return firmware_capability in firmwareinfo table on success or 0 if not 45 */ 46 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev) 47 { 48 struct amdgpu_mode_info *mode_info = &adev->mode_info; 49 int index; 50 u16 data_offset, size; 51 union firmware_info *firmware_info; 52 u8 frev, crev; 53 u32 fw_cap = 0; 54 55 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 56 firmwareinfo); 57 58 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 59 index, &size, &frev, &crev, &data_offset)) { 60 /* support firmware_info 3.1 + */ 61 if ((frev == 3 && crev >=1) || (frev > 3)) { 62 firmware_info = (union firmware_info *) 63 (mode_info->atom_context->bios + data_offset); 64 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); 65 } 66 } 67 68 return fw_cap; 69 } 70 71 /* 72 * Helper function to query gpu virtualizaiton capability 73 * 74 * @adev: amdgpu_device pointer 75 * 76 * Return true if gpu virtualization is supported or false if not 77 */ 78 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev) 79 { 80 u32 fw_cap; 81 82 fw_cap = adev->mode_info.firmware_flags; 83 84 return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false; 85 } 86 87 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) 88 { 89 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 90 firmwareinfo); 91 uint16_t data_offset; 92 93 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, 94 NULL, NULL, &data_offset)) { 95 struct atom_firmware_info_v3_1 *firmware_info = 96 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + 97 data_offset); 98 99 adev->bios_scratch_reg_offset = 100 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); 101 } 102 } 103 104 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) 105 { 106 struct atom_context *ctx = adev->mode_info.atom_context; 107 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 108 vram_usagebyfirmware); 109 struct vram_usagebyfirmware_v2_1 *firmware_usage; 110 uint32_t start_addr, size; 111 uint16_t data_offset; 112 int usage_bytes = 0; 113 114 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 115 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); 116 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n", 117 le32_to_cpu(firmware_usage->start_address_in_kb), 118 le16_to_cpu(firmware_usage->used_by_firmware_in_kb), 119 le16_to_cpu(firmware_usage->used_by_driver_in_kb)); 120 121 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb); 122 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb); 123 124 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == 125 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 126 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 127 /* Firmware request VRAM reservation for SR-IOV */ 128 adev->mman.fw_vram_usage_start_offset = (start_addr & 129 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 130 adev->mman.fw_vram_usage_size = size << 10; 131 /* Use the default scratch size */ 132 usage_bytes = 0; 133 } else { 134 usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10; 135 } 136 } 137 ctx->scratch_size_bytes = 0; 138 if (usage_bytes == 0) 139 usage_bytes = 20 * 1024; 140 /* allocate some scratch memory */ 141 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 142 if (!ctx->scratch) 143 return -ENOMEM; 144 ctx->scratch_size_bytes = usage_bytes; 145 return 0; 146 } 147 148 union igp_info { 149 struct atom_integrated_system_info_v1_11 v11; 150 struct atom_integrated_system_info_v1_12 v12; 151 struct atom_integrated_system_info_v2_1 v21; 152 }; 153 154 union umc_info { 155 struct atom_umc_info_v3_1 v31; 156 struct atom_umc_info_v3_2 v32; 157 struct atom_umc_info_v3_3 v33; 158 }; 159 160 union vram_info { 161 struct atom_vram_info_header_v2_3 v23; 162 struct atom_vram_info_header_v2_4 v24; 163 struct atom_vram_info_header_v2_5 v25; 164 struct atom_vram_info_header_v2_6 v26; 165 struct atom_vram_info_header_v3_0 v30; 166 }; 167 168 union vram_module { 169 struct atom_vram_module_v9 v9; 170 struct atom_vram_module_v10 v10; 171 struct atom_vram_module_v11 v11; 172 struct atom_vram_module_v3_0 v30; 173 }; 174 175 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, 176 int atom_mem_type) 177 { 178 int vram_type; 179 180 if (adev->flags & AMD_IS_APU) { 181 switch (atom_mem_type) { 182 case Ddr2MemType: 183 case LpDdr2MemType: 184 vram_type = AMDGPU_VRAM_TYPE_DDR2; 185 break; 186 case Ddr3MemType: 187 case LpDdr3MemType: 188 vram_type = AMDGPU_VRAM_TYPE_DDR3; 189 break; 190 case Ddr4MemType: 191 case LpDdr4MemType: 192 vram_type = AMDGPU_VRAM_TYPE_DDR4; 193 break; 194 case Ddr5MemType: 195 case LpDdr5MemType: 196 vram_type = AMDGPU_VRAM_TYPE_DDR5; 197 break; 198 default: 199 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 200 break; 201 } 202 } else { 203 switch (atom_mem_type) { 204 case ATOM_DGPU_VRAM_TYPE_GDDR5: 205 vram_type = AMDGPU_VRAM_TYPE_GDDR5; 206 break; 207 case ATOM_DGPU_VRAM_TYPE_HBM2: 208 case ATOM_DGPU_VRAM_TYPE_HBM2E: 209 vram_type = AMDGPU_VRAM_TYPE_HBM; 210 break; 211 case ATOM_DGPU_VRAM_TYPE_GDDR6: 212 vram_type = AMDGPU_VRAM_TYPE_GDDR6; 213 break; 214 default: 215 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 216 break; 217 } 218 } 219 220 return vram_type; 221 } 222 223 224 int 225 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 226 int *vram_width, int *vram_type, 227 int *vram_vendor) 228 { 229 struct amdgpu_mode_info *mode_info = &adev->mode_info; 230 int index, i = 0; 231 u16 data_offset, size; 232 union igp_info *igp_info; 233 union vram_info *vram_info; 234 union vram_module *vram_module; 235 u8 frev, crev; 236 u8 mem_type; 237 u8 mem_vendor; 238 u32 mem_channel_number; 239 u32 mem_channel_width; 240 u32 module_id; 241 242 if (adev->flags & AMD_IS_APU) 243 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 244 integratedsysteminfo); 245 else 246 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 247 vram_info); 248 249 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 250 index, &size, 251 &frev, &crev, &data_offset)) { 252 if (adev->flags & AMD_IS_APU) { 253 igp_info = (union igp_info *) 254 (mode_info->atom_context->bios + data_offset); 255 switch (frev) { 256 case 1: 257 switch (crev) { 258 case 11: 259 case 12: 260 mem_channel_number = igp_info->v11.umachannelnumber; 261 if (!mem_channel_number) 262 mem_channel_number = 1; 263 /* channel width is 64 */ 264 if (vram_width) 265 *vram_width = mem_channel_number * 64; 266 mem_type = igp_info->v11.memorytype; 267 if (vram_type) 268 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 269 break; 270 default: 271 return -EINVAL; 272 } 273 break; 274 case 2: 275 switch (crev) { 276 case 1: 277 case 2: 278 mem_channel_number = igp_info->v21.umachannelnumber; 279 if (!mem_channel_number) 280 mem_channel_number = 1; 281 /* channel width is 64 */ 282 if (vram_width) 283 *vram_width = mem_channel_number * 64; 284 mem_type = igp_info->v21.memorytype; 285 if (vram_type) 286 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 287 break; 288 default: 289 return -EINVAL; 290 } 291 break; 292 default: 293 return -EINVAL; 294 } 295 } else { 296 vram_info = (union vram_info *) 297 (mode_info->atom_context->bios + data_offset); 298 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; 299 if (frev == 3) { 300 switch (crev) { 301 /* v30 */ 302 case 0: 303 vram_module = (union vram_module *)vram_info->v30.vram_module; 304 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; 305 if (vram_vendor) 306 *vram_vendor = mem_vendor; 307 mem_type = vram_info->v30.memory_type; 308 if (vram_type) 309 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 310 mem_channel_number = vram_info->v30.channel_num; 311 mem_channel_width = vram_info->v30.channel_width; 312 if (vram_width) 313 *vram_width = mem_channel_number * mem_channel_width; 314 break; 315 default: 316 return -EINVAL; 317 } 318 } else if (frev == 2) { 319 switch (crev) { 320 /* v23 */ 321 case 3: 322 if (module_id > vram_info->v23.vram_module_num) 323 module_id = 0; 324 vram_module = (union vram_module *)vram_info->v23.vram_module; 325 while (i < module_id) { 326 vram_module = (union vram_module *) 327 ((u8 *)vram_module + vram_module->v9.vram_module_size); 328 i++; 329 } 330 mem_type = vram_module->v9.memory_type; 331 if (vram_type) 332 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 333 mem_channel_number = vram_module->v9.channel_num; 334 mem_channel_width = vram_module->v9.channel_width; 335 if (vram_width) 336 *vram_width = mem_channel_number * (1 << mem_channel_width); 337 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 338 if (vram_vendor) 339 *vram_vendor = mem_vendor; 340 break; 341 /* v24 */ 342 case 4: 343 if (module_id > vram_info->v24.vram_module_num) 344 module_id = 0; 345 vram_module = (union vram_module *)vram_info->v24.vram_module; 346 while (i < module_id) { 347 vram_module = (union vram_module *) 348 ((u8 *)vram_module + vram_module->v10.vram_module_size); 349 i++; 350 } 351 mem_type = vram_module->v10.memory_type; 352 if (vram_type) 353 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 354 mem_channel_number = vram_module->v10.channel_num; 355 mem_channel_width = vram_module->v10.channel_width; 356 if (vram_width) 357 *vram_width = mem_channel_number * (1 << mem_channel_width); 358 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; 359 if (vram_vendor) 360 *vram_vendor = mem_vendor; 361 break; 362 /* v25 */ 363 case 5: 364 if (module_id > vram_info->v25.vram_module_num) 365 module_id = 0; 366 vram_module = (union vram_module *)vram_info->v25.vram_module; 367 while (i < module_id) { 368 vram_module = (union vram_module *) 369 ((u8 *)vram_module + vram_module->v11.vram_module_size); 370 i++; 371 } 372 mem_type = vram_module->v11.memory_type; 373 if (vram_type) 374 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 375 mem_channel_number = vram_module->v11.channel_num; 376 mem_channel_width = vram_module->v11.channel_width; 377 if (vram_width) 378 *vram_width = mem_channel_number * (1 << mem_channel_width); 379 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; 380 if (vram_vendor) 381 *vram_vendor = mem_vendor; 382 break; 383 /* v26 */ 384 case 6: 385 if (module_id > vram_info->v26.vram_module_num) 386 module_id = 0; 387 vram_module = (union vram_module *)vram_info->v26.vram_module; 388 while (i < module_id) { 389 vram_module = (union vram_module *) 390 ((u8 *)vram_module + vram_module->v9.vram_module_size); 391 i++; 392 } 393 mem_type = vram_module->v9.memory_type; 394 if (vram_type) 395 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 396 mem_channel_number = vram_module->v9.channel_num; 397 mem_channel_width = vram_module->v9.channel_width; 398 if (vram_width) 399 *vram_width = mem_channel_number * (1 << mem_channel_width); 400 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 401 if (vram_vendor) 402 *vram_vendor = mem_vendor; 403 break; 404 default: 405 return -EINVAL; 406 } 407 } else { 408 /* invalid frev */ 409 return -EINVAL; 410 } 411 } 412 413 } 414 415 return 0; 416 } 417 418 /* 419 * Return true if vbios enabled ecc by default, if umc info table is available 420 * or false if ecc is not enabled or umc info table is not available 421 */ 422 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) 423 { 424 struct amdgpu_mode_info *mode_info = &adev->mode_info; 425 int index; 426 u16 data_offset, size; 427 union umc_info *umc_info; 428 u8 frev, crev; 429 bool ecc_default_enabled = false; 430 u8 umc_config; 431 u32 umc_config1; 432 433 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 434 umc_info); 435 436 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 437 index, &size, &frev, &crev, &data_offset)) { 438 if (frev == 3) { 439 umc_info = (union umc_info *) 440 (mode_info->atom_context->bios + data_offset); 441 switch (crev) { 442 case 1: 443 umc_config = le32_to_cpu(umc_info->v31.umc_config); 444 ecc_default_enabled = 445 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 446 break; 447 case 2: 448 umc_config = le32_to_cpu(umc_info->v32.umc_config); 449 ecc_default_enabled = 450 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 451 break; 452 case 3: 453 umc_config = le32_to_cpu(umc_info->v33.umc_config); 454 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1); 455 ecc_default_enabled = 456 ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) || 457 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false; 458 break; 459 default: 460 /* unsupported crev */ 461 return false; 462 } 463 } 464 } 465 466 return ecc_default_enabled; 467 } 468 469 /* 470 * Helper function to query sram ecc capablity 471 * 472 * @adev: amdgpu_device pointer 473 * 474 * Return true if vbios supports sram ecc or false if not 475 */ 476 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev) 477 { 478 u32 fw_cap; 479 480 fw_cap = adev->mode_info.firmware_flags; 481 482 return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false; 483 } 484 485 /* 486 * Helper function to query dynamic boot config capability 487 * 488 * @adev: amdgpu_device pointer 489 * 490 * Return true if vbios supports dynamic boot config or false if not 491 */ 492 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev) 493 { 494 u32 fw_cap; 495 496 fw_cap = adev->mode_info.firmware_flags; 497 498 return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false; 499 } 500 501 /** 502 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS 503 * @adev: amdgpu_device pointer 504 * @i2c_address: pointer to u8; if not NULL, will contain 505 * the RAS EEPROM address if the function returns true 506 * 507 * Return true if VBIOS supports RAS EEPROM address reporting, 508 * else return false. If true and @i2c_address is not NULL, 509 * will contain the RAS ROM address. 510 */ 511 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, 512 u8 *i2c_address) 513 { 514 struct amdgpu_mode_info *mode_info = &adev->mode_info; 515 int index; 516 u16 data_offset, size; 517 union firmware_info *firmware_info; 518 u8 frev, crev; 519 520 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 521 firmwareinfo); 522 523 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 524 index, &size, &frev, &crev, 525 &data_offset)) { 526 /* support firmware_info 3.4 + */ 527 if ((frev == 3 && crev >=4) || (frev > 3)) { 528 firmware_info = (union firmware_info *) 529 (mode_info->atom_context->bios + data_offset); 530 /* The ras_rom_i2c_slave_addr should ideally 531 * be a 19-bit EEPROM address, which would be 532 * used as is by the driver; see top of 533 * amdgpu_eeprom.c. 534 * 535 * When this is the case, 0 is of course a 536 * valid RAS EEPROM address, in which case, 537 * we'll drop the first "if (firm...)" and only 538 * leave the check for the pointer. 539 * 540 * The reason this works right now is because 541 * ras_rom_i2c_slave_addr contains the EEPROM 542 * device type qualifier 1010b in the top 4 543 * bits. 544 */ 545 if (firmware_info->v34.ras_rom_i2c_slave_addr) { 546 if (i2c_address) 547 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr; 548 return true; 549 } 550 } 551 } 552 553 return false; 554 } 555 556 557 union smu_info { 558 struct atom_smu_info_v3_1 v31; 559 }; 560 561 union gfx_info { 562 struct atom_gfx_info_v2_2 v22; 563 struct atom_gfx_info_v2_4 v24; 564 struct atom_gfx_info_v2_7 v27; 565 struct atom_gfx_info_v3_0 v30; 566 }; 567 568 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) 569 { 570 struct amdgpu_mode_info *mode_info = &adev->mode_info; 571 struct amdgpu_pll *spll = &adev->clock.spll; 572 struct amdgpu_pll *mpll = &adev->clock.mpll; 573 uint8_t frev, crev; 574 uint16_t data_offset; 575 int ret = -EINVAL, index; 576 577 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 578 firmwareinfo); 579 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 580 &frev, &crev, &data_offset)) { 581 union firmware_info *firmware_info = 582 (union firmware_info *)(mode_info->atom_context->bios + 583 data_offset); 584 585 adev->clock.default_sclk = 586 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 587 adev->clock.default_mclk = 588 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 589 590 adev->pm.current_sclk = adev->clock.default_sclk; 591 adev->pm.current_mclk = adev->clock.default_mclk; 592 593 ret = 0; 594 } 595 596 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 597 smu_info); 598 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 599 &frev, &crev, &data_offset)) { 600 union smu_info *smu_info = 601 (union smu_info *)(mode_info->atom_context->bios + 602 data_offset); 603 604 /* system clock */ 605 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); 606 607 spll->reference_div = 0; 608 spll->min_post_div = 1; 609 spll->max_post_div = 1; 610 spll->min_ref_div = 2; 611 spll->max_ref_div = 0xff; 612 spll->min_feedback_div = 4; 613 spll->max_feedback_div = 0xff; 614 spll->best_vco = 0; 615 616 ret = 0; 617 } 618 619 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 620 umc_info); 621 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 622 &frev, &crev, &data_offset)) { 623 union umc_info *umc_info = 624 (union umc_info *)(mode_info->atom_context->bios + 625 data_offset); 626 627 /* memory clock */ 628 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); 629 630 mpll->reference_div = 0; 631 mpll->min_post_div = 1; 632 mpll->max_post_div = 1; 633 mpll->min_ref_div = 2; 634 mpll->max_ref_div = 0xff; 635 mpll->min_feedback_div = 4; 636 mpll->max_feedback_div = 0xff; 637 mpll->best_vco = 0; 638 639 ret = 0; 640 } 641 642 /* if asic is Navi+, the rlc reference clock is used for system clock 643 * from vbios gfx_info table */ 644 if (adev->asic_type >= CHIP_NAVI10) { 645 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 646 gfx_info); 647 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 648 &frev, &crev, &data_offset)) { 649 union gfx_info *gfx_info = (union gfx_info *) 650 (mode_info->atom_context->bios + data_offset); 651 if ((frev == 3) || 652 (frev == 2 && crev == 6)) { 653 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk); 654 ret = 0; 655 } else if ((frev == 2) && 656 (crev >= 2) && 657 (crev != 6)) { 658 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk); 659 ret = 0; 660 } else { 661 BUG(); 662 } 663 } 664 } 665 666 return ret; 667 } 668 669 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) 670 { 671 struct amdgpu_mode_info *mode_info = &adev->mode_info; 672 int index; 673 uint8_t frev, crev; 674 uint16_t data_offset; 675 676 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 677 gfx_info); 678 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 679 &frev, &crev, &data_offset)) { 680 union gfx_info *gfx_info = (union gfx_info *) 681 (mode_info->atom_context->bios + data_offset); 682 if (frev == 2) { 683 switch (crev) { 684 case 4: 685 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; 686 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; 687 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; 688 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; 689 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; 690 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); 691 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; 692 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; 693 adev->gfx.config.gs_prim_buffer_depth = 694 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth); 695 adev->gfx.config.double_offchip_lds_buf = 696 gfx_info->v24.gc_double_offchip_lds_buffer; 697 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size); 698 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd); 699 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu; 700 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); 701 return 0; 702 case 7: 703 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines; 704 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; 705 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; 706 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se; 707 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches; 708 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs); 709 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds; 710 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth; 711 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth); 712 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer; 713 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size); 714 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd); 715 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu; 716 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size); 717 return 0; 718 default: 719 return -EINVAL; 720 } 721 } else if (frev == 3) { 722 switch (crev) { 723 case 0: 724 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines; 725 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh; 726 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; 727 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se; 728 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches; 729 return 0; 730 default: 731 return -EINVAL; 732 } 733 } else { 734 return -EINVAL; 735 } 736 737 } 738 return -EINVAL; 739 } 740 741 /* 742 * Helper function to query two stage mem training capability 743 * 744 * @adev: amdgpu_device pointer 745 * 746 * Return true if two stage mem training is supported or false if not 747 */ 748 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev) 749 { 750 u32 fw_cap; 751 752 fw_cap = adev->mode_info.firmware_flags; 753 754 return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false; 755 } 756 757 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev) 758 { 759 struct atom_context *ctx = adev->mode_info.atom_context; 760 union firmware_info *firmware_info; 761 int index; 762 u16 data_offset, size; 763 u8 frev, crev; 764 int fw_reserved_fb_size; 765 766 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 767 firmwareinfo); 768 769 if (!amdgpu_atom_parse_data_header(ctx, index, &size, 770 &frev, &crev, &data_offset)) 771 /* fail to parse data_header */ 772 return 0; 773 774 firmware_info = (union firmware_info *)(ctx->bios + data_offset); 775 776 if (frev !=3) 777 return -EINVAL; 778 779 switch (crev) { 780 case 4: 781 fw_reserved_fb_size = 782 (firmware_info->v34.fw_reserved_size_in_kb << 10); 783 break; 784 default: 785 fw_reserved_fb_size = 0; 786 break; 787 } 788 789 return fw_reserved_fb_size; 790 } 791 792 /* 793 * Helper function to execute asic_init table 794 * 795 * @adev: amdgpu_device pointer 796 * @fb_reset: flag to indicate whether fb is reset or not 797 * 798 * Return 0 if succeed, otherwise failed 799 */ 800 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset) 801 { 802 struct amdgpu_mode_info *mode_info = &adev->mode_info; 803 struct atom_context *ctx; 804 uint8_t frev, crev; 805 uint16_t data_offset; 806 uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz; 807 struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1; 808 int index; 809 810 if (!mode_info) 811 return -EINVAL; 812 813 ctx = mode_info->atom_context; 814 if (!ctx) 815 return -EINVAL; 816 817 /* query bootup sclk/mclk from firmware_info table */ 818 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 819 firmwareinfo); 820 if (amdgpu_atom_parse_data_header(ctx, index, NULL, 821 &frev, &crev, &data_offset)) { 822 union firmware_info *firmware_info = 823 (union firmware_info *)(ctx->bios + 824 data_offset); 825 826 bootup_sclk_in10khz = 827 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 828 bootup_mclk_in10khz = 829 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 830 } else { 831 return -EINVAL; 832 } 833 834 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 835 asic_init); 836 if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) { 837 if (frev == 2 && crev >= 1) { 838 memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1)); 839 asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz; 840 asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz; 841 asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT; 842 if (!fb_reset) 843 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT; 844 else 845 asic_init_ps_v2_1.param.memparam.memflag = 0; 846 } else { 847 return -EINVAL; 848 } 849 } else { 850 return -EINVAL; 851 } 852 853 return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1); 854 } 855