1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/amdgpu_drm.h> 25 #include "amdgpu.h" 26 #include "atomfirmware.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "atom.h" 29 #include "atombios.h" 30 #include "soc15_hw_ip.h" 31 32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev) 33 { 34 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 35 firmwareinfo); 36 uint16_t data_offset; 37 38 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, 39 NULL, NULL, &data_offset)) { 40 struct atom_firmware_info_v3_1 *firmware_info = 41 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + 42 data_offset); 43 44 if (le32_to_cpu(firmware_info->firmware_capability) & 45 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) 46 return true; 47 } 48 return false; 49 } 50 51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) 52 { 53 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 54 firmwareinfo); 55 uint16_t data_offset; 56 57 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, 58 NULL, NULL, &data_offset)) { 59 struct atom_firmware_info_v3_1 *firmware_info = 60 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + 61 data_offset); 62 63 adev->bios_scratch_reg_offset = 64 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); 65 } 66 } 67 68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) 69 { 70 struct atom_context *ctx = adev->mode_info.atom_context; 71 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 72 vram_usagebyfirmware); 73 struct vram_usagebyfirmware_v2_1 * firmware_usage; 74 uint32_t start_addr, size; 75 uint16_t data_offset; 76 int usage_bytes = 0; 77 78 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 79 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); 80 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n", 81 le32_to_cpu(firmware_usage->start_address_in_kb), 82 le16_to_cpu(firmware_usage->used_by_firmware_in_kb), 83 le16_to_cpu(firmware_usage->used_by_driver_in_kb)); 84 85 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb); 86 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb); 87 88 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == 89 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 90 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 91 /* Firmware request VRAM reservation for SR-IOV */ 92 adev->mman.fw_vram_usage_start_offset = (start_addr & 93 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 94 adev->mman.fw_vram_usage_size = size << 10; 95 /* Use the default scratch size */ 96 usage_bytes = 0; 97 } else { 98 usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10; 99 } 100 } 101 ctx->scratch_size_bytes = 0; 102 if (usage_bytes == 0) 103 usage_bytes = 20 * 1024; 104 /* allocate some scratch memory */ 105 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 106 if (!ctx->scratch) 107 return -ENOMEM; 108 ctx->scratch_size_bytes = usage_bytes; 109 return 0; 110 } 111 112 union igp_info { 113 struct atom_integrated_system_info_v1_11 v11; 114 struct atom_integrated_system_info_v1_12 v12; 115 }; 116 117 union umc_info { 118 struct atom_umc_info_v3_1 v31; 119 }; 120 121 union vram_info { 122 struct atom_vram_info_header_v2_3 v23; 123 struct atom_vram_info_header_v2_4 v24; 124 struct atom_vram_info_header_v2_5 v25; 125 }; 126 127 union vram_module { 128 struct atom_vram_module_v9 v9; 129 struct atom_vram_module_v10 v10; 130 struct atom_vram_module_v11 v11; 131 }; 132 133 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, 134 int atom_mem_type) 135 { 136 int vram_type; 137 138 if (adev->flags & AMD_IS_APU) { 139 switch (atom_mem_type) { 140 case Ddr2MemType: 141 case LpDdr2MemType: 142 vram_type = AMDGPU_VRAM_TYPE_DDR2; 143 break; 144 case Ddr3MemType: 145 case LpDdr3MemType: 146 vram_type = AMDGPU_VRAM_TYPE_DDR3; 147 break; 148 case Ddr4MemType: 149 case LpDdr4MemType: 150 vram_type = AMDGPU_VRAM_TYPE_DDR4; 151 break; 152 default: 153 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 154 break; 155 } 156 } else { 157 switch (atom_mem_type) { 158 case ATOM_DGPU_VRAM_TYPE_GDDR5: 159 vram_type = AMDGPU_VRAM_TYPE_GDDR5; 160 break; 161 case ATOM_DGPU_VRAM_TYPE_HBM2: 162 vram_type = AMDGPU_VRAM_TYPE_HBM; 163 break; 164 case ATOM_DGPU_VRAM_TYPE_GDDR6: 165 vram_type = AMDGPU_VRAM_TYPE_GDDR6; 166 break; 167 default: 168 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 169 break; 170 } 171 } 172 173 return vram_type; 174 } 175 176 177 int 178 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 179 int *vram_width, int *vram_type, 180 int *vram_vendor) 181 { 182 struct amdgpu_mode_info *mode_info = &adev->mode_info; 183 int index, i = 0; 184 u16 data_offset, size; 185 union igp_info *igp_info; 186 union vram_info *vram_info; 187 union vram_module *vram_module; 188 u8 frev, crev; 189 u8 mem_type; 190 u8 mem_vendor; 191 u32 mem_channel_number; 192 u32 mem_channel_width; 193 u32 module_id; 194 195 if (adev->flags & AMD_IS_APU) 196 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 197 integratedsysteminfo); 198 else 199 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 200 vram_info); 201 202 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 203 index, &size, 204 &frev, &crev, &data_offset)) { 205 if (adev->flags & AMD_IS_APU) { 206 igp_info = (union igp_info *) 207 (mode_info->atom_context->bios + data_offset); 208 switch (crev) { 209 case 11: 210 mem_channel_number = igp_info->v11.umachannelnumber; 211 /* channel width is 64 */ 212 if (vram_width) 213 *vram_width = mem_channel_number * 64; 214 mem_type = igp_info->v11.memorytype; 215 if (vram_type) 216 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 217 break; 218 case 12: 219 mem_channel_number = igp_info->v12.umachannelnumber; 220 /* channel width is 64 */ 221 if (vram_width) 222 *vram_width = mem_channel_number * 64; 223 mem_type = igp_info->v12.memorytype; 224 if (vram_type) 225 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 226 break; 227 default: 228 return -EINVAL; 229 } 230 } else { 231 vram_info = (union vram_info *) 232 (mode_info->atom_context->bios + data_offset); 233 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; 234 switch (crev) { 235 case 3: 236 if (module_id > vram_info->v23.vram_module_num) 237 module_id = 0; 238 vram_module = (union vram_module *)vram_info->v23.vram_module; 239 while (i < module_id) { 240 vram_module = (union vram_module *) 241 ((u8 *)vram_module + vram_module->v9.vram_module_size); 242 i++; 243 } 244 mem_type = vram_module->v9.memory_type; 245 if (vram_type) 246 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 247 mem_channel_number = vram_module->v9.channel_num; 248 mem_channel_width = vram_module->v9.channel_width; 249 if (vram_width) 250 *vram_width = mem_channel_number * (1 << mem_channel_width); 251 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; 252 if (vram_vendor) 253 *vram_vendor = mem_vendor; 254 break; 255 case 4: 256 if (module_id > vram_info->v24.vram_module_num) 257 module_id = 0; 258 vram_module = (union vram_module *)vram_info->v24.vram_module; 259 while (i < module_id) { 260 vram_module = (union vram_module *) 261 ((u8 *)vram_module + vram_module->v10.vram_module_size); 262 i++; 263 } 264 mem_type = vram_module->v10.memory_type; 265 if (vram_type) 266 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 267 mem_channel_number = vram_module->v10.channel_num; 268 mem_channel_width = vram_module->v10.channel_width; 269 if (vram_width) 270 *vram_width = mem_channel_number * (1 << mem_channel_width); 271 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; 272 if (vram_vendor) 273 *vram_vendor = mem_vendor; 274 break; 275 case 5: 276 if (module_id > vram_info->v25.vram_module_num) 277 module_id = 0; 278 vram_module = (union vram_module *)vram_info->v25.vram_module; 279 while (i < module_id) { 280 vram_module = (union vram_module *) 281 ((u8 *)vram_module + vram_module->v11.vram_module_size); 282 i++; 283 } 284 mem_type = vram_module->v11.memory_type; 285 if (vram_type) 286 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); 287 mem_channel_number = vram_module->v11.channel_num; 288 mem_channel_width = vram_module->v11.channel_width; 289 if (vram_width) 290 *vram_width = mem_channel_number * (1 << mem_channel_width); 291 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; 292 if (vram_vendor) 293 *vram_vendor = mem_vendor; 294 break; 295 default: 296 return -EINVAL; 297 } 298 } 299 300 } 301 302 return 0; 303 } 304 305 /* 306 * Return true if vbios enabled ecc by default, if umc info table is available 307 * or false if ecc is not enabled or umc info table is not available 308 */ 309 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) 310 { 311 struct amdgpu_mode_info *mode_info = &adev->mode_info; 312 int index; 313 u16 data_offset, size; 314 union umc_info *umc_info; 315 u8 frev, crev; 316 bool ecc_default_enabled = false; 317 318 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 319 umc_info); 320 321 if (amdgpu_atom_parse_data_header(mode_info->atom_context, 322 index, &size, &frev, &crev, &data_offset)) { 323 /* support umc_info 3.1+ */ 324 if ((frev == 3 && crev >= 1) || (frev > 3)) { 325 umc_info = (union umc_info *) 326 (mode_info->atom_context->bios + data_offset); 327 ecc_default_enabled = 328 (le32_to_cpu(umc_info->v31.umc_config) & 329 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; 330 } 331 } 332 333 return ecc_default_enabled; 334 } 335 336 union firmware_info { 337 struct atom_firmware_info_v3_1 v31; 338 struct atom_firmware_info_v3_2 v32; 339 struct atom_firmware_info_v3_3 v33; 340 struct atom_firmware_info_v3_4 v34; 341 }; 342 343 /* 344 * Return true if vbios supports sram ecc or false if not 345 */ 346 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev) 347 { 348 struct amdgpu_mode_info *mode_info = &adev->mode_info; 349 int index; 350 u16 data_offset, size; 351 union firmware_info *firmware_info; 352 u8 frev, crev; 353 bool sram_ecc_supported = false; 354 355 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 356 firmwareinfo); 357 358 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, 359 index, &size, &frev, &crev, &data_offset)) { 360 /* support firmware_info 3.1 + */ 361 if ((frev == 3 && crev >=1) || (frev > 3)) { 362 firmware_info = (union firmware_info *) 363 (mode_info->atom_context->bios + data_offset); 364 sram_ecc_supported = 365 (le32_to_cpu(firmware_info->v31.firmware_capability) & 366 ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false; 367 } 368 } 369 370 return sram_ecc_supported; 371 } 372 373 union smu_info { 374 struct atom_smu_info_v3_1 v31; 375 }; 376 377 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) 378 { 379 struct amdgpu_mode_info *mode_info = &adev->mode_info; 380 struct amdgpu_pll *spll = &adev->clock.spll; 381 struct amdgpu_pll *mpll = &adev->clock.mpll; 382 uint8_t frev, crev; 383 uint16_t data_offset; 384 int ret = -EINVAL, index; 385 386 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 387 firmwareinfo); 388 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 389 &frev, &crev, &data_offset)) { 390 union firmware_info *firmware_info = 391 (union firmware_info *)(mode_info->atom_context->bios + 392 data_offset); 393 394 adev->clock.default_sclk = 395 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); 396 adev->clock.default_mclk = 397 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); 398 399 adev->pm.current_sclk = adev->clock.default_sclk; 400 adev->pm.current_mclk = adev->clock.default_mclk; 401 402 /* not technically a clock, but... */ 403 adev->mode_info.firmware_flags = 404 le32_to_cpu(firmware_info->v31.firmware_capability); 405 406 ret = 0; 407 } 408 409 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 410 smu_info); 411 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 412 &frev, &crev, &data_offset)) { 413 union smu_info *smu_info = 414 (union smu_info *)(mode_info->atom_context->bios + 415 data_offset); 416 417 /* system clock */ 418 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); 419 420 spll->reference_div = 0; 421 spll->min_post_div = 1; 422 spll->max_post_div = 1; 423 spll->min_ref_div = 2; 424 spll->max_ref_div = 0xff; 425 spll->min_feedback_div = 4; 426 spll->max_feedback_div = 0xff; 427 spll->best_vco = 0; 428 429 ret = 0; 430 } 431 432 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 433 umc_info); 434 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 435 &frev, &crev, &data_offset)) { 436 union umc_info *umc_info = 437 (union umc_info *)(mode_info->atom_context->bios + 438 data_offset); 439 440 /* memory clock */ 441 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); 442 443 mpll->reference_div = 0; 444 mpll->min_post_div = 1; 445 mpll->max_post_div = 1; 446 mpll->min_ref_div = 2; 447 mpll->max_ref_div = 0xff; 448 mpll->min_feedback_div = 4; 449 mpll->max_feedback_div = 0xff; 450 mpll->best_vco = 0; 451 452 ret = 0; 453 } 454 455 return ret; 456 } 457 458 union gfx_info { 459 struct atom_gfx_info_v2_4 v24; 460 }; 461 462 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev) 463 { 464 struct amdgpu_mode_info *mode_info = &adev->mode_info; 465 int index; 466 uint8_t frev, crev; 467 uint16_t data_offset; 468 469 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 470 gfx_info); 471 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 472 &frev, &crev, &data_offset)) { 473 union gfx_info *gfx_info = (union gfx_info *) 474 (mode_info->atom_context->bios + data_offset); 475 switch (crev) { 476 case 4: 477 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; 478 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; 479 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; 480 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; 481 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; 482 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); 483 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; 484 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; 485 adev->gfx.config.gs_prim_buffer_depth = 486 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth); 487 adev->gfx.config.double_offchip_lds_buf = 488 gfx_info->v24.gc_double_offchip_lds_buffer; 489 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size); 490 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd); 491 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu; 492 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); 493 return 0; 494 default: 495 return -EINVAL; 496 } 497 498 } 499 return -EINVAL; 500 } 501 502 /* 503 * Check if VBIOS supports GDDR6 training data save/restore 504 */ 505 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev) 506 { 507 uint16_t data_offset; 508 int index; 509 510 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 511 firmwareinfo); 512 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, 513 NULL, NULL, &data_offset)) { 514 struct atom_firmware_info_v3_1 *firmware_info = 515 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + 516 data_offset); 517 518 DRM_DEBUG("atom firmware capability:0x%08x.\n", 519 le32_to_cpu(firmware_info->firmware_capability)); 520 521 if (le32_to_cpu(firmware_info->firmware_capability) & 522 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) 523 return true; 524 } 525 526 return false; 527 } 528 529 int amdgpu_mem_train_support(struct amdgpu_device *adev) 530 { 531 int ret; 532 uint32_t major, minor, revision, hw_v; 533 534 if (gddr6_mem_train_vbios_support(adev)) { 535 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision); 536 hw_v = HW_REV(major, minor, revision); 537 /* 538 * treat 0 revision as a special case since register for MP0 and MMHUB is missing 539 * for some Navi10 A0, preventing driver from discovering the hwip information since 540 * none of the functions will be initialized, it should not cause any problems 541 */ 542 switch (hw_v) { 543 case HW_REV(11, 0, 0): 544 case HW_REV(11, 0, 5): 545 case HW_REV(11, 0, 7): 546 case HW_REV(11, 0, 11): 547 ret = 1; 548 break; 549 default: 550 DRM_ERROR("memory training vbios supports but psp hw(%08x)" 551 " doesn't support!\n", hw_v); 552 ret = -1; 553 break; 554 } 555 } else { 556 ret = 0; 557 hw_v = -1; 558 } 559 560 561 DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret); 562 return ret; 563 } 564 565 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev) 566 { 567 struct atom_context *ctx = adev->mode_info.atom_context; 568 union firmware_info *firmware_info; 569 int index; 570 u16 data_offset, size; 571 u8 frev, crev; 572 int fw_reserved_fb_size; 573 574 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 575 firmwareinfo); 576 577 if (!amdgpu_atom_parse_data_header(ctx, index, &size, 578 &frev, &crev, &data_offset)) 579 /* fail to parse data_header */ 580 return 0; 581 582 firmware_info = (union firmware_info *)(ctx->bios + data_offset); 583 584 if (frev !=3) 585 return -EINVAL; 586 587 switch (crev) { 588 case 4: 589 fw_reserved_fb_size = 590 (firmware_info->v34.fw_reserved_size_in_kb << 10); 591 break; 592 default: 593 fw_reserved_fb_size = 0; 594 break; 595 } 596 597 return fw_reserved_fb_size; 598 } 599